@ PHILIPS
DATA SHEET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT563
Octal D-type transparent latch;
3-state; inverting
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990 2
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state;
inverting 74HC/HCT563
FEATURES
•3-state inverting outputs for bus
oriented applications
•Inputs and outputs on opposite
sides of package allowing easy
interface with microprocessor
•Common 3-state output enable
input
•Output capability: bus driver
•ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT563 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard no.
7A.
The 74HC/HCT563 are octal D-type
transparent latches featuring
separate D-type inputs for each latch
and inverting 3-state outputs for bus
oriented applications.
A latch enable (LE) input and an
output enable (OE) input are common
to all latches.
The “563” is functionally identical to
the “573”, but has inverted outputs.
The “563” consists of eight D-type
transparent latches with 3-state
inverting outputs. The LE and OE are
common to all latches.
When LE is HIGH, data at the Dn
inputs enter the latches. In this
condition the latches are transparent,
i.e. a latch output will change state
each time its corresponding D-input
changes.
When LE is LOW the latches store the
information that was present at the
D-inputs a set-up time preceding the
HIGH-to-LOW transition of LE.
When OE is LOW, the contents of the
8 latches are available at the outputs.
When OE is HIGH, the outputs go to
the high impedance OFF-state.
Operation of the OE input does not
affect the state of the latches.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25°C; tr=t
f= 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD=C
PD × VCC2× fi+ ∑ (CL× VCC2 × fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× VCC2× fo) = sum of outputs
CL= output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI= GND to VCC
for HCT the condition is VI= GND to VCC − 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
HC HCT
tPHL/ tPLH propagation delay Dn, LE to QnCL= 15 pF; VCC =5 V 14 16 ns
C
Iinput capacitance 3.5 3.5 pF
CPD power dissipation capacitance per latch notes 1 and 2 19 19 pF
53 u U Ev“
not: I-Jfiu
”IE I-JE
DIE Elfii
‘- a,
“E so: g3.
D5E E65
o. [I Ea.
o, E £13,
("In In I! LE
muux
December 1990 3
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state;
inverting 74HC/HCT563
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
2, 3, 4, 5, 6, 7, 8, 9 D0 to D7data inputs
11 LE latch enable input (active HIGH)
1OE 3-state output enable input (active LOW)
10 GND ground (0 V)
19, 18, 17, 16, 15, 14, 13, 12 Q0 to Q73-state latch outputs
20 VCC positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
December 1990 4
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state;
inverting 74HC/HCT563
Fig.4 Functional diagram.
FUNCTION TABLE
Notes
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the
HIGH-to-LOW LE transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the
HIGH-to-LOW LE transition
Z = high impedance OFF-state
OPERATING
MODES
INPUTS INTER-
NAL
LATCHES
OUT-
PUTS
OE LE DnQ0to Q7
enable and
read register
L
L
H
H
L
H
L
H
H
L
latch and read
register
L
L
L
L
l
h
L
H
H
L
latch register
and disable
outputs
H
H
L
L
l
h
L
H
Z
Z
Fig.5 Logic diagram.
December 1990 5
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state;
inverting 74HC/HCT563
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: bus driver
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr=t
f= 6 ns; CL= 50 pF
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC VCC
(V) WAVEFORMS+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
Dn to Qn
47
17
14
145
29
25
180
36
31
220
44
38
ns 2.0
4.5
6.0
Fig.6
tPHL/ tPLH propagation delay
LE to Qn
47
17
14
145
29
25
180
36
31
220
44
38
ns 2.0
4.5
6.0
Fig.7
tPZH/ tPZL 3-state output enable
time
OE to Qn
47
17
14
150
30
26
190
38
33
225
45
38
ns 2.0
4.5
6.0
Fig.8
tPHZ/ tPLZ 3-state output disable
time
OE to Qn
50
18
14
150
30
26
190
38
33
225
45
38
ns 2.0
4.5
6.0
Fig.8
tTHL/ tTLH output transition time 14
5
4
60
12
10
75
15
13
90
18
15
ns 2.0
4.5
6.0
Fig.6
tWenable pulse width
HIGH
80
16
14
14
5
4
100
20
17
120
24
20
ns 2.0
4.5
6.0
Fig.7
tsu set-up time
Dn to LE
50
10
9
11
4
3
65
13
11
75
15
13
ns 2.0
4.5
6.0
Fig.9
thhold time
Dn to LE
4
4
4
−6
−2
−2
4
4
4
4
4
4
ns 2.0
4.5
6.0
Fig.9
December 1990 6
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state;
inverting 74HC/HCT563
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: bus driver
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr=t
f= 6 ns; CL= 50 pF
INPUT UNIT LOAD COEFFICIENT
Dn
LE
OE
0.35
0.65
1.25
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT VCC
(V) WAVEFORMS+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
Dn to Qn
18 30 38 45 ns 4.5 Fig.6
tPHL/ tPLH propagation delay
LE to Qn
19 35 44 53 ns 4.5 Fig.7
tPZH/ tPZL 3-state output enable
time OE to Qn
20 35 44 53 ns 4.5 Fig.8
tPHZ/ tPLZ 3-state output disable
time OE to Qn
22 35 44 53 ns 4.5 Fig.8
tTHL/ tTLH output transition time 5 12 15 18 ns 4.5 Fig.6
tWenable pulse width
HIGH
16 5 20 24 ns 4.5 Fig.7
tsu set-up time
Dn to LE
10 3 13 15 ns 4.5 Fig.9
thhold time
Dn to LE
5−1 5 5 ns 4.5 Fig.9
n" mrur LE mm
in mirror 5,. uurruT
7mm Wm. *‘TLN mm: “rm
WZ/////
In 9.
°_5 "“7 Lsmwr Vum
m
6,, mm
LUW-m-OFF
“Purim
a“ cum
KlGNdmOFF
OFF-«mink
mum
December 1990 7
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state;
inverting 74HC/HCT563
AC WAVEFORMS
Fig.6 Waveforms showing the data input (Dn) to
output (Qn) propagation delays and the
output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
Fig.7 Waveforms showing the latch enable input
(LE) pulse width, the latch enable input to
output (Qn) propagation delays and the
output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
Fig.8 Waveforms showing the 3-state enable and
disable times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
Fig.9 Waveforms showing the data set-up and
hold times for Dn input to LE input
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
Products related to this Datasheet
IC LATCH OCTAL D 3STATE 20DIP
IC OCTAL D TRANSP LATCH 20-SSOP
IC LATCH TRANSP OCT D 3ST 20SOIC
IC LATCH TRANSP OCT D 3ST 20SOIC
IC OCT D TRANSP LATCH INV 20SOIC
IC OCT D TRANSP LATCH INV 20SSOP
IC OCT D TRANSP LATCH INV 20SOIC
IC OCT D TRANSP LATCH INV 20DIP