74AHC(T)164 Datasheet by Nexperia USA Inc.

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1. General description
The 74AHC164; 74AHCT164 shift register is a high-speed Si-gate CMOS device and is
pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with
JEDEC standard No. 7A.
The 74AHC164; 74AHCT164 input signals are 8-bit serial through one of two inputs (DSA
or DSB); either input can be used as an active HIGH enable for data entry through the
other input. Both inputs must be connected together or an unused input must be tied
HIGH.
Data shifts one place to the right on each LOW-to-HIGH transition of the clock input (CP)
and enters into output Q0, which is a logical AND of the two data inputs (DSA and DSB)
that existed one set-up time prior to the rising clock edge.
A LOW-level on the master reset (MR) input overrides all other inputs and clears the
register asynchronously, forcing all outputs LOW.
2. Features
nBalanced propagation delays
nAll inputs have Schmitt-trigger actions
nInputs accept voltages higher than VCC
nInput levels:
uFor 74AHC164: CMOS level
uFor 74AHCT164: TTL level
nESD protection:
uHBM EIA/JESD22-A114E exceeds 2000 V
uMM EIA/JESD22-A115-A exceeds 200 V
uCDM EIA/JESD22-C101C exceeds 1000 V
nMultiple package options
nSpecified from 40 °C to +85 °C and from 40 °C to +125 °C
74AHC164; 74AHCT164
8-bit serial-in/parallel-out shift register
Rev. 03 — 24 April 2008 Product data sheet
74AHC_AHCT164_3
Product data sheet Rev. 03 — 24 April 2008 2 of 18
Nexperia 74AHC164; 74AHCT164
8-bit serial-in/parallel-out shift register
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74AHC164
74AHC164D 40 °C to +125 °C SO14 plastic small outline package; 14 leads;
body width 3.9 mm SOT108-1
74AHC164PW 40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm SOT402-1
74AHC164BQ 40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals; body
2.5 × 3 ×0.85 mm
SOT762-1
74AHCT164
74AHCT164D 40 °C to +125 °C SO14 plastic small outline package; 14 leads;
body width 3.9 mm SOT108-1
74AHCT164PW 40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm SOT402-1
74AHCT164BQ 40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals; body
2.5 × 3 × 0.85 mm
SOT762-1
Fig 1. Functional diagram
001aac425
1
2
310136412511
8
9
Q0 Q1 Q2
8-BIT SERIALIN/PARALLELOUT
SHIFT REGISTER
Q3 Q4 Q5 Q6 Q7
DSB
CP
MR
DSA
© Nexperia B.V. 2017. All rights reserved
5 J, \ *5 xfi V
74AHC_AHCT164_3
Product data sheet Rev. 03 — 24 April 2008 3 of 18
Nexperia 74AHC164; 74AHCT164
8-bit serial-in/parallel-out shift register
Fig 2. Logic symbol Fig 3. IEC logic symbol
001aac423
3
1
24
5
6
10
11
12
13
8
9
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CP
DSB
DSA
MR
001aac424
9
8
&3
1
2
4
5
6
10
11
13
12
R
C1/
1D
SRG8
Fig 4. Logic diagram
001aac616
Q0
D
FF1
Q
CP
RD
CP
DSB
DSA
MR
Q1
D
FF2
Q
CP
RD
Q2
D
FF3
Q
CP
RD
Q3
D
FF4
Q
CP
RD
Q4
D
FF5
Q
CP
RD
Q5
D
FF6
Q
CP
RD
Q6
D
FF7
Q
CP
RD
Q7
D
FF8
Q
CP
RD
© Nexperia B.V. 2017. All rights reserved
CCCCC UH flfl 33333 3 3333333 EEEEEEE
74AHC_AHCT164_3
Product data sheet Rev. 03 — 24 April 2008 4 of 18
Nexperia 74AHC164; 74AHCT164
8-bit serial-in/parallel-out shift register
5. Pinning information
5.1 Pinning
5.2 Pin description
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as a
supply pin or input.
Fig 5. Pin configuration SO14 and TSSOP14 Fig 6. Pin configuration DHVQFN14
164
DSA VCC
DSB Q7
Q0 Q6
Q1 Q5
Q2 Q4
Q3 MR
GND CP
001aac422
1
2
3
4
5
6
78
10
9
12
11
14
13
001aac828
164
GND(1)
Transparent top view
Q3 MR
Q2 Q4
Q1 Q5
Q0 Q6
DSB Q7
GND
CP
DSA
VCC
6 9
5 10
4 11
3 12
2 13
7
8
1
14
terminal 1
index area
Table 2. Pin description
Symbol Pin Description
DSA 1 serial data input A
DSB 2 serial data input B
Q0 3 output 0
Q1 4 output 1
Q2 5 output 2
Q3 6 output 3
GND 7 ground (0 V)
CP 8 clock input (LOW-to-HIGH edge-triggered)
MR 9 master reset input (active LOW)
Q4 10 output 4
Q5 11 output 5
Q6 12 output 6
Q7 13 output 7
VCC 14 supply voltage
© Nexperia B.V. 2017. All rights reserved
74AHC_AHCT164_3
Product data sheet Rev. 03 — 24 April 2008 5 of 18
Nexperia 74AHC164; 74AHCT164
8-bit serial-in/parallel-out shift register
6. Functional description
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
= LOW-to-HIGH transition;
X = don’t care;
q = lower case letter indicates the state of the referenced input one set-up time prior to the LOW-to-HIGH transition.
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO14 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K.
For TSSOP14 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K.
For DHVQFN14 packages: above 60 °C the value of Ptot derates linearly at 4.5 mW/K.
Table 3. Function table[1]
Operating mode Control Input Output
MR CP DSA DSB Q0 Q1 to Q7
Reset (clear) L X X X L L to L
Shift H l l L q0 to q6
l h L q0 to q6
h l L q0 to q6
h h H q0 to q6
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7.0 V
VIinput voltage 0.5 +7.0 V
IIK input clamping current VI < 0.5 V [1] 20 - mA
IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V [1] 20 +20 mA
IOoutput current VO = 0.5 V to (VCC + 0.5 V) 25 +25 mA
ICC supply current - +75 mA
IGND ground current 75 - mA
Tstg storage temperature 65 +150 °C
Ptot total power dissipation Tamb = 40 °C to +125 °C[2] - 500 mW
© Nexperia B.V. 2017. All rights reserved
74AHC_AHCT164_3
Product data sheet Rev. 03 — 24 April 2008 6 of 18
Nexperia 74AHC164; 74AHCT164
8-bit serial-in/parallel-out shift register
8. Recommended operating conditions
9. Static characteristics
Table 5. Operating conditions
Symbol Parameter Conditions Min Typ Max Unit
74AHC164
VCC supply voltage 2.0 5.0 5.5 V
VIinput voltage 0 - 5.5 V
VOoutput voltage 0 - VCC V
Tamb ambient temperature 40 +25 +125 °C
t/V input transition rise and fall rate VCC = 3.0 V to 3.6 V - - 100 ns/V
VCC = 4.5 V to 5.5 V - - 20 ns/V
74AHCT164
VCC supply voltage 4.5 5.0 5.5 V
VIinput voltage 0 - 5.5 V
VOoutput voltage 0 - VCC V
Tamb ambient temperature 40 +25 +125 °C
t/V input transition rise and fall rate VCC = 4.5 V to 5.5 V - - 20 ns/V
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 °C40 °C to +85 °C40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
74AHC164
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V
VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V
VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V
VIL LOW-level
input voltage VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V
VCC = 3.0 V - - 0.9 - 0.9 - 0.9 V
VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V
VOH HIGH-level
output voltage VI= VIH or VIL
IO=50 µA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO=50 µA; VCC = 3.0 V 2.9 3.0 - 2.9 - 2.9 - V
IO=50 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO=4.0 mA; VCC = 3.0 V 2.58 - - 2.48 - 2.40 - V
IO=8.0 mA; VCC = 4.5 V 3.94 - - 3.80 - 3.70 - V
VOL LOW-level
output voltage VI= VIH or VIL
IO= 50 µA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO= 50 µA; VCC = 3.0 V - 0 0.1 - 0.1 - 0.1 V
IO= 50 µA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO= 4.0 mA; VCC = 3.0 V - - 0.36 - 0.44 - 0.55 V
IO= 8.0 mA; VCC = 4.5 V - - 0.36 - 0.44 - 0.55 V
© Nexperia B.V. 2017. All rights reserved
74AHC_AHCT164_3
Product data sheet Rev. 03 — 24 April 2008 7 of 18
Nexperia 74AHC164; 74AHCT164
8-bit serial-in/parallel-out shift register
IIinput leakage
current VI= 5.5 V or GND;
VCC =0Vto5.5V - - 0.1 - 1.0 - 2.0 µA
ICC supply current VI=V
CC or GND; IO = 0 A;
VCC = 5.5 V - - 4.0 - 40 - 80 µA
CIinput
capacitance - 3 10 - - - - pF
74AHCT164
VIH HIGH-level
input voltage VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V
VIL LOW-level
input voltage VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage VI= VIH or VIL; VCC = 4.5 V
IO=50 µA 4.4 4.5 - 4.4 - 4.4 - V
IO=8.0 mA 3.94 - - 3.80 - 3.70 - V
VOL LOW-level
output voltage VI= VIH or VIL; VCC = 4.5 V
IO= 50 µA - 0 0.1 - 0.1 - 0.1 V
IO= 8.0 mA - - 0.36 - 0.44 - 0.55 V
IIinput leakage
current VI= 5.5 V or GND;
VCC =0Vto5.5V - - 0.1 - 1.0 - 2.0 µA
ICC supply current VI=V
CC or GND; IO = 0 A;
VCC = 5.5 V - - 4.0 - 40 - 80 µA
ICC additional
supply current per input pin;
VI=V
CC 2.1 V; IO= 0 A;
other pins at VCC or GND;
VCC = 4.5 V to 5.5 V
- - 1.35 - 1.5 - 1.5 mA
CIinput
capacitance - 3 10 - - - - pF
Table 6. Static characteristics
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 °C40 °C to +85 °C40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
© Nexperia B.V. 2017. All rights reserved
74AHC_AHCT164_3
Product data sheet Rev. 03 — 24 April 2008 8 of 18
Nexperia 74AHC164; 74AHCT164
8-bit serial-in/parallel-out shift register
10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10.
Symbol Parameter Conditions 25 °C40 °C to +85 °C40 °C to +125 °C Unit
Min Typ[1] Max Min Max Min Max
74AHC164
tpd propagation
delay CP to Qn; see Figure 7 [2]
VCC = 3.0 V to 3.6 V
CL= 15 pF - 6.5 12.8 1.0 15.0 1.0 16.0 ns
CL= 50 pF - 9.3 16.3 1.0 18.5 1.0 20.5 ns
VCC = 4.5 V to 5.5 V
CL= 15 pF - 4.5 9.0 1.0 10.5 1.0 11.5 ns
CL= 50 pF - 6.4 11.0 1.0 12.5 1.0 14.0 ns
MR to Qn; see Figure 8 [3]
VCC = 3.0 V to 3.6 V
CL= 15 pF - 5.3 12.8 1.0 15.0 1.0 16.0 ns
CL= 50 pF - 7.6 16.3 1.0 18.5 1.0 20.5 ns
VCC = 4.5 V to 5.5 V
CL= 15 pF - 4.0 8.6 1.0 10.0 1.0 11.0 ns
CL= 50 pF - 5.8 10.6 1.0 12.0 1.0 13.5 ns
fmax maximum
frequency see Figure 7
VCC = 3.0 V to 3.6 V
CL= 15 pF 80 125 - 65 - 50 - MHz
CL= 50 pF 50 75 - 45 - 35 - MHz
VCC = 4.5 V to 5.5 V
CL= 15 pF 125 175 - 105 - 85 - MHz
CL= 50 pF 85 115 - 75 - 65 - MHz
tWpulse width CP HIGH or LOW;
see Figure 7
VCC = 3.0 V to 3.6 V 5.0 - - 5.0 - 5.0 - ns
VCC = 4.5 V to 5.5 V 5.0 - - 5.0 - 5.0 - ns
tWL pulse width
LOW MR; see Figure 8
VCC = 3.0 V to 3.6 V 5.0 - - 5.0 - 5.0 - ns
VCC = 4.5 V to 5.5 V 5.0 - - 5.0 - 5.0 - ns
tsu set-up time DSA, DSB to CP;
see Figure 9
VCC = 3.0 V to 3.6 V 5.0 - - 6.0 - 6.0 - ns
VCC = 4.5 V to 5.5 V 4.5 - - 4.5 - 4.5 - ns
thhold time DSA, DSB to CP;
see Figure 9
VCC = 3.0 V to 3.6 V 1.5 - - 1.5 - 1.5 - ns
VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - ns
© Nexperia B.V. 2017. All rights reserved
\va \
74AHC_AHCT164_3
Product data sheet Rev. 03 — 24 April 2008 9 of 18
Nexperia 74AHC164; 74AHCT164
8-bit serial-in/parallel-out shift register
[1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[2] tpd is the same as tPLH and tPHL.
[3] tpd is the same as tPHL only.
[4] CPD is used to determine the dynamic power dissipation (PDin µW).
PD=C
PD ×VCC2×fi×N+Σ(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL×VCC2×fo) = sum of the outputs.
trec recovery
time MR to CP; see Figure 8
VCC = 3.0 V to 3.6 V 2.5 - - 2.5 - 2.5 - ns
VCC = 4.5 V to 5.5 V 2.5 - - 2.5 - 2.5 - ns
CPD power
dissipation
capacitance
fi = 1 MHz; VI= GND to VCC [4] -48- - - - -pF
74AHCT164; VCC = 4.5 V to 5.5 V
tpd propagation
delay CP to Qn; see Figure 7 [2]
CL= 15 pF - 3.4 9.0 1.0 10.5 1.0 11.5 ns
CL= 50 pF - 4.9 11.0 1.0 12.5 1.0 14.0 ns
MR to Qn; see Figure 8 [3]
CL= 15 pF - 3.5 8.6 1.0 10.0 1.0 11.0 ns
CL= 50 pF - 5.0 10.6 1.0 12.0 1.0 13.5 ns
fmax maximum
frequency see Figure 7
CL= 15 pF 125 175 - 105 - 85 - MHz
CL= 50 pF 85 115 - 75 - 65 - MHz
tWpulse width CP HIGH or LOW;
see Figure 7 5.0 - - 5.0 - 5.0 - ns
tWL pulse width
LOW MR; see Figure 8 5.0 - - 5.0 - 5.0 - ns
tsu set-up time DSA, DSB to CP;
see Figure 9 4.5 - - 4.5 - 4.5 - ns
thhold time DSA, DSB to CP;
see Figure 9 2.0 - - 2.0 - 2.0 - ns
trec recovery
time MR to CP; see Figure 8 2.5 - - 2.5 - 2.5 - ns
CPD power
dissipation
capacitance
fi = 1 MHz; VI= GND to VCC [4] -51- - - - -pF
Table 7. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10.
Symbol Parameter Conditions 25 °C40 °C to +85 °C40 °C to +125 °C Unit
Min Typ[1] Max Min Max Min Max
© Nexperia B.V. 2017. All rights reserved
3 + 7 _
74AHC_AHCT164_3
Product data sheet Rev. 03 — 24 April 2008 10 of 18
Nexperia 74AHC164; 74AHCT164
8-bit serial-in/parallel-out shift register
11. Waveforms
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Clock pulse width, maximum frequency and input to output propagation delays
001aac426
CP input
Qn output
tPHL tPLH
tW
VOH
VI
GND
VOL
VM
VM
1/fmax
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8. Master reset pulse width, recovery time and propagation delays
001aac446
MR input
CP input
Qn output
tPHL
tWL trec
VM
VI
GND
VI
VOH
VOL
GND
VM
VM
© Nexperia B.V. 2017. All rights reserved
74AHC_AHCT164_3
Product data sheet Rev. 03 — 24 April 2008 11 of 18
Nexperia 74AHC164; 74AHCT164
8-bit serial-in/parallel-out shift register
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 9. Data set-up and hold times
001aaf612
GND
GND
th
tsu
th
tsu
VM
VM
VM
VI
VOH
VOL
VI
Qn output
CP input
DSA, DSB input
Table 8. Measurement points
Type Input Output
VMVM
74AHC164 0.5 ×VCC 0.5 ×VCC
74AHCT164 1.5 V 0.5 ×VCC
© Nexperia B.V. 2017. All rights reserved
E | MI
74AHC_AHCT164_3
Product data sheet Rev. 03 — 24 April 2008 12 of 18
Nexperia 74AHC164; 74AHCT164
8-bit serial-in/parallel-out shift register
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator
CL = Load capacitance including jig and probe capacitance
Fig 10. Load circuitry for measuring switching times
001aah768
tW
tW
tr
tr
tf
VM
VI
negative
pulse
GND
VI
positive
pulse
GND
10 %
90 %
90 %
10 %
VMVM
VM
tf
VCC
DUT
RT
VIVO
CL
G
Table 9. Test data
Type Input Load Test
VItr, tfCL
74AHC164 VCC 3.0 ns 15 pF, 50 pF tPLH, tPHL
74AHCT164 3.0 V 3.0 ns 15 pF, 50 pF tPLH, tPHL
© Nexperia B.V. 2017. All rights reserved
74AHC_AHCT164_3
Product data sheet Rev. 03 — 24 April 2008 13 of 18
Nexperia 74AHC164; 74AHCT164
8-bit serial-in/parallel-out shift register
12. Package outline
Fig 11. Package outline SOT108-1 (SO14)
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 8.75
8.55 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT108-1
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
7
8
1
14
y
076E06 MS-012
pin 1 index
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.35
0.34 0.16
0.15 0.05
1.05
0.041
0.244
0.228 0.028
0.024 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
99-12-27
03-02-19
0 2.5 5 mm
scale
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
© Nexperia B.V. 2017. All rights reserved
74AHC_AHCT164_3
Product data sheet Rev. 03 — 24 April 2008 14 of 18
Nexperia 74AHC164; 74AHCT164
8-bit serial-in/parallel-out shift register
Fig 12. Package outline SOT402-1 (TSSOP14)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.72
0.38 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT402-1 MO-153 99-12-27
03-02-18
wM
bp
D
Z
e
0.25
17
14 8
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
A
max.
1.1
pin 1 index
© Nexperia B.V. 2017. All rights reserved
E© W A \ /fi 7/ x, P // \ P Ea ,i mu 5: n ‘w‘ pim‘ + U i H mm W H ;
74AHC_AHCT164_3
Product data sheet Rev. 03 — 24 April 2008 15 of 18
Nexperia 74AHC164; 74AHCT164
8-bit serial-in/parallel-out shift register
Fig 13. Package outline SOT762-1 (DHVQFN14)
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 3.1
2.9
Dh
1.65
1.35
y1
2.6
2.4 1.15
0.85
e1
2
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT762-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT762-1
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
A(1)
max.
AA1
c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
26
13 9
8
7
1
14
X
D
E
C
BA
02-10-17
03-01-27
terminal 1
index area
AC
C
B
vM
wM
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
© Nexperia B.V. 2017. All rights reserved
74AHC_AHCT164_3
Product data sheet Rev. 03 — 24 April 2008 16 of 18
Nexperia 74AHC164; 74AHCT164
8-bit serial-in/parallel-out shift register
13. Abbreviations
14. Revision history
Table 10. Abbreviations
Acronym Description
CDM Charged Device Model
CMOS Complementary Metal-Oxide Semiconductor
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74AHC_AHCT164_3 20080424 Product data sheet - 74AHC_AHCT164_2
Modifications: Table 6: the conditions for input leakage current have been changed.
74AHC_AHCT164_2 20061129 Product data sheet - 74AHC_AHCT164_1
74AHC_AHCT164_1
(9397 750 07332) 20000815 Product specification - -
© Nexperia B.V. 2017. All rights reserved
w
74AHC_AHCT164_3
Product data sheet Rev. 03 — 24 April 2008 17 of 18
Nexperia 74AHC164; 74AHCT164
8-bit serial-in/parallel-out shift register
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nexperia.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable.However, Nexperiadoesnotgiveanyrepresentationsor
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — Nexperiareserves therighttomake
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — Nexperia products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a Nexperia product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. Nexperia accepts no liability for inclusion and/or use of
Nexperia products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — Nexperia products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nexperia.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by Nexperia. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
© Nexperia B.V. 2017. All rights reserved
Nexperia 74AHC164; 74AHCT164
8-bit serial-in/parallel-out shift register
17. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional description . . . . . . . . . . . . . . . . . . . 5
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Recommended operating conditions. . . . . . . . 6
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
16 Contact information. . . . . . . . . . . . . . . . . . . . . 17
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
© Nexperia B.V. 2017. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release:
24 April 2008

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