AD9634 Datasheet by Analog Devices Inc.

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ANALOG t, 170 MSPS/ZIU MSPS/250 MSPS, DEVICES 1.8 V Analog-to-Digital Converter A09634
12-Bit, 170 MSPS/210 MSPS/250 MSPS,
1.8 V Analog-to-Digital Converter
Data Sheet
AD9634
FEATURES
SNR = 69.7 dBFS at 185 MHz AIN and 250 MSPS
SFDR = 87 dBc at 185 MHz AIN and 250 MSPS
−150.6 dBFS/Hz input noise at 185 MHz, −1 dBFS AIN and
250 MSPS
Total power consumption: 360 mW at 250 MSPS
1.8 V supply voltages
LVDS (ANSI-644 levels) outputs
Integer 1-to-8 input clock divider (625 MHz maximum input)
Sample rates of up to 250 MSPS
Internal ADC voltage reference
Flexible analog input range
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
ADC clock duty cycle stabilizer
Serial port control
Energy-saving power-down modes
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Ultrasound equipment
Broadband data applications
FUNCTIONAL BLOCK DIAGRAM
12
REFERENCE
SERIAL PORT
SCLK SDIO CSB CLK+ CLK–
1-TO-8
CLOCK DIVIDER
AD9634
VIN+ D0±/D1±
D10±/D11±
DCO±
OR±
VIN–
VCM
AVDD AGND DRVDD
.
.
.
PARALLEL
DDR LVDS
AND
DRIVERS
PIPELINE
12-BIT
ADC
09996-001
Figure 1.
GENERAL DESCRIPTION
The AD9634 is a 12-bit, analog-to-digital converter (ADC) with
sampling speeds of up to 250 MSPS. The AD9634 is designed to
support communications applications where low cost, small size,
wide bandwidth, and versatility are desired.
The ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. The
ADC features wide bandwidth inputs that can support a variety
of user-selectable input ranges. An integrated voltage reference
eases design considerations. A duty cycle stabilizer (DCS) is
provided to compensate for variations in the ADC clock duty cycle,
allowing the converter to maintain excellent performance.
The ADC output data are routed directly to the external 12-bit
LVDS output port.
Flexible power-down options allow significant power savings,
when desired.
Programming for setup and control is accomplished using a
3-wire, SPI-compatible serial interface.
The AD9634 is available in a 32-lead LFCSP and is specified over
the industrial temperature range of −40°C to +85°C. This product
is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1. Integrated 12-bit, 170 MSPS/210 MSPS/250 MSPS ADC.
2. Fast overrange and threshold detect.
3. Proprietary differential input maintains excellent SNR
performance for input frequencies of up to 350 MHz.
4. 3-pin, 1.8 V SPI port for register programming and readback.
5. Pin compatibility with the AD9642, allowing a simple
migration up to 14 bits, and with the AD6672.
Rev. B Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2011–2014 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
AD9634 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
ADC DC Specifications ................................................................. 3
ADC AC Specifications ................................................................. 4
Digital Specifications ................................................................... 6
Switching Specifications ................................................................ 7
Timing Specifications .................................................................. 8
Absolute Maximum Ratings ............................................................ 9
Thermal Characteristics .............................................................. 9
ESD Caution .................................................................................. 9
Pin Configuration and Function Descriptions ........................... 10
Typical Performance Characteristics ........................................... 12
Equivalent Circuits ......................................................................... 18
Theory of Operation ...................................................................... 19
ADC Architecture ...................................................................... 19
Analog Input Considerations ................................................... 19
Voltage Reference ....................................................................... 21
Clock Input Considerations ...................................................... 21
Power Dissipation and Standby Mode .................................... 23
Digital Outputs ........................................................................... 23
ADC Overrange (OR) ................................................................ 23
Serial Port Interface (SPI) .............................................................. 24
Configuration Using the SPI ..................................................... 24
Hardware Interface ..................................................................... 24
SPI Accessible Features .............................................................. 25
Memory Map .................................................................................. 26
Reading the Memory Map Register Table ............................... 26
Memory Map Register Table ..................................................... 27
Applications Information .............................................................. 29
Design Guidelines ...................................................................... 29
Outline Dimensions ....................................................................... 30
Ordering Guide .......................................................................... 30
REVISION HISTORY
12/14—Rev. A to Rev. B
Changes to Features Section............................................................ 1
Changes to Reading the Memory Map Register Table
Section .............................................................................................. 26
Changes to Table 13 ........................................................................ 28
7/14—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Changes to Full Power Bandwidth Parameter, Table 2 ................ 5
Deleted Noise Bandwidth Parameter, Table 2............................... 5
7/11—Revision 0: Initial Version
Rev. B | Page 2 of 30
Table L
Data Sheet AD9634
SPECIFICATIONS
ADC DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full scale input range,
DCS enabled, unless otherwise noted.
Table 1.
Parameter Temperature
AD9634-170 AD9634-210 AD9634-250
Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION Full 12 12 12 Bits
ACCURACY
No Missing Codes Full Guaranteed Guaranteed Guaranteed
Offset Error Full ±11 ±11 ±11 mV
Gain Error Full +2/−11 +1/−8 +3/−7 %FSR
Differential Nonlinearity (DNL) Full ±0.4 ±0.4 ±0.4 LSB
25°C
±0.22
±0.22
±0.22
LSB
Integral Nonlinearity (INL)1 Full ±0.4 ±0.4 ±0.6 LSB
25°C ±0.2 ±0.2 ±0.27 LSB
TEMPERATURE DRIFT
Offset Error Full ±7 ±7 ±7 ppm/°C
Gain Error Full ±55 ±58 ±75 ppm/°C
INPUT REFERRED NOISE
VREF = 1.0 V 25°C 0.531 0.391 0.407 LSB rms
ANALOG INPUT
Input Span Full 1.75 1.75 1.75 V p-p
Input Capacitance2 Full 2.5 2.5 2.5 pF
Input Resistance3 Full 20 20 20 kΩ
Input Common-Mode Voltage Full 0.9 0.9 0.9 V
POWER SUPPLIES
Supply Voltage
AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
Supply Current
IAVDD1 Full 123 134 129 139 136 145 mA
IDRVDD1 Full 50 54 56 60 64 68 mA
POWER CONSUMPTION
Sine Wave Input (DRVDD = 1.8 V) Full 311 340 333 360 360 385 mW
Standby Power4 Full 50 50 50 mW
Power-Down Power Full 5 5 5 mW
1 Measured with a low input frequency, full-scale sine wave.
2 Input capacitance refers to the effective capacitance between one differential input pin and its complement.
3 Input resistance refers to the effective resistance between one differential input pin and its complement.
4 Standby power is measured with a dc input and the CLK pin inactive (that is, set to AVDD or AGND).
Rev. B | Page 3 of 30
Table 2‘
AD9634 Data Sheet
ADC AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, unless
otherwise noted.
Table 2.
AD9634-170 AD9634-210 AD9634-250
Parameter1 Temperature Min Typ Max Min Typ Max Min Typ Max Unit
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 30 MHz 25°C 70.3 70.2 70.1 dBFS
fIN = 90 MHz 25°C 70.1 70.1 70.0 dBFS
Full 69.1 68.8 dBFS
fIN = 140 MHz 25°C 69.9 70.0 69.9 dBFS
fIN = 185 MHz 25°C 69.5 69.6 69.7 dBFS
Full 67.8 dBFS
fIN = 220 MHz 25°C 69.2 69.2 69.3 dBFS
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 30 MHz 25°C 69.4 69.2 69.2 dBFS
fIN = 90 MHz 25°C 69.2 69.1 69.0 dBFS
Full 68.1 67.8 dBFS
fIN = 140 MHz 25°C 68.9 69.1 69.0 dBFS
fIN = 185 MHz 25°C 68.5 68.7 68.7 dBFS
Full 66.7 dBFS
fIN = 220 MHz 25°C 68.3 68.3 68.4 dBFS
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 30 MHz 25°C 11.2 11.2 11.2 Bits
fIN = 90 MHz 25°C 11.2 11.2 11.2 Bits
f
IN
= 140 MHz
25°C
11.1
11.2
11.2
Bits
fIN = 185 MHz 25°C 11.1 11.1 11.1 Bits
fIN = 220 MHz 25°C 11.0 11.0 11.1 Bits
WORST SECOND OR THIRD HARMONIC
fIN = 30 MHz 25°C −96 −96 −90 dBc
fIN = 90 MHz 25°C −95 −92 −89 dBc
Full −83 −80 dBc
fIN = 140 MHz 25°C −97 −94 −91 dBc
fIN = 185 MHz 25°C −86 −95 −87 dBc
Full −80 dBc
fIN = 220 MHz 25°C −84 −84 −93 dBc
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 30 MHz 25°C 96 96 90 dBc
fIN = 90 MHz 25°C 95 92 89 dBc
Full 83 80 dBc
fIN = 140 MHz 25°C 97 94 91 dBc
f
IN
= 185 MHz
25°C
86
95
87
dBc
Full 80 dBc
fIN = 220 MHz 25°C 84 84 93 dBc
WORST OTHER (HARMONIC OR SPUR)
fIN = 30 MHz 25°C −98 −96 −95 dBc
fIN = 90 MHz 25°C −97 −95 −95 dBc
Full −87 −83 dBc
fIN = 140 MHz 25°C −98 −97 −96 dBc
fIN = 185 MHz 25°C −95 −95 −94 dBc
Full −81 dBc
fIN = 220 MHz 25°C −96 −95 −94 dBc
Rev. B | Page 4 of 30
Data Sheet AD9634
AD9634-170 AD9634-210 AD9634-250
Parameter1 Temperature Min Typ Max Min Typ Max Min Typ Max Unit
TWO-TONE SFDR
fIN = 184.1 MHz, 187.1 MHz (−7 dBFS) 25°C 87 89 88 dBc
FULL POWER BANDWIDTH 25°C 1000 1000 1000 MHz
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
Rev. B | Page 5 of 30
Table 3‘ mpm CommonrMode Range
AD9634 Data Sheet
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless
otherwise noted.
Table 3.
Parameter Temperature Min Typ Max Unit
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
CMOS/LVDS/LVPECL
Internal Common-Mode Bias Full 0.9 V
Differential Input Voltage Full 0.3 3.6 V p-p
Input Voltage Range Full AGND AVDD V
Input Common-Mode Range
Full 0.9 1.4 V
High Level Input Current Full 10 22 µA
Low Level Input Current Full −22 −10 µA
Input Capacitance Full 4 pF
Input Resistance Full 12 15 18 kΩ
LOGIC INPUT (CSB)1
High Level Input Voltage Full 1.22 2.1 V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current Full 50 71 µA
Low Level Input Current Full −5 +5 µA
Input Resistance Full 26 kΩ
Input Capacitance Full 2 pF
LOGIC INPUT (SCLK)2
High Level Input Voltage Full 1.22 2.1 V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current Full 45 70 µA
Low Level Input Current
Full
−5
+5
µA
Input Resistance Full 26 kΩ
Input Capacitance Full 2 pF
LOGIC INPUTS (SDIO)1
High Level Input Voltage Full 1.22 2.1 V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current Full 45 70 µA
Low Level Input Current Full −5 +5 µA
Input Resistance Full 26 kΩ
Input Capacitance Full 5 pF
DIGITAL OUTPUTS
LVDS Data and OR Outputs (OR+, OR−)
Differential Output Voltage (VOD), ANSI Mode Full 250 350 450 mV
Output Offset Voltage (VOS), ANSI Mode Full 1.15 1.25 1.35 V
Differential Output Voltage (VOD), Reduced Swing Mode Full 150 200 280 mV
Output Offset Voltage (VOS), Reduced Swing Mode Full 1.15 1.25 1.35 V
1 Pull-up.
2 Pull-down.
Rev. B | Page 6 of 30
+ \/\ \j\/\/\/\/ \/\/\/\/\ TEXXXXXXXX) xxxxxxxx>
Data Sheet AD9634
SWITCHING SPECIFICATIONS
Table 4.
AD9634-170 AD9634-210 AD9634-250
Parameter Temperature Min Typ Max Min Typ Max Min Typ Max Unit
CLOCK INPUT PARAMETERS1
Input Clock Rate Full 625 625 625 MHz
Conversion Rate2
DCS Enabled Full 40 170 40 210 40 250 MSPS
DCS Disabled
Full
10
170
10
210
10
250
MSPS
CLK Period, Divide-by-1 Mode (tCLK) Full 5.8 4.8 4 ns
CLK Pulse Width High (tCH)
Divide-by-1 Mode, DCS Enabled Full 2.61 2.9 3.19 2.16 2.4 2.64 1.8 2.0 2.2 ns
Divide-by-1 Mode, DCS Disabled Full 2.76 2.9 3.05 2.28 2.4 2.52 1.9 2.0 2.1 ns
Divide-by-2 Mode Through
Divide-by-8 Mode
Full 0.8 0.8 0.8 ns
Aperture Delay (tA) Full 1.0 1.0 1.0 ns
Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 0.1 ps rms
DATA OUTPUT PARAMETERS1
Data Propagation Delay (tPD) Full 4.1 4.7 5.2 4.1 4.7 5.2 4.1 4.7 5.2 ns
DCO Propagation Delay (tDCO) Full 4.7 5.3 5.8 4.7 5.3 5.8 4.7 5.3 5.8 ns
DCO to Data Skew (tSKEW) Full 0.3 0.5 0.7 0.3 0.5 0.7 0.3 0.5 0.7 ns
Pipeline Delay (Latency) Full 10 10 10 Cycles
Wake-Up Time (from Standby) Full 10 10 10 µs
Wake-Up Time (from Power-Down) Full 100 100 100 µs
Out-of-Range Recovery Time Full 3 3 3 Cycles
1 See Figure 2.
2 Conversion rate is the clock rate after the divider.
Timing Diagram
VIN
CLK+
CLK–
DCO–
DCO+
D0±/D1±
(LSB)
EVEN/ODD
D10±/D11±
(MSB)
D0
N – 10 D1
N – 10 D0
N – 9 D1
N – 9 D0
N – 8 D1
N – 8 D0
N – 7 D1
N – 7 D0
N – 6
D10
N – 10 D11
N – 10 D10
N – 9 D11
N – 9 D10
N – 8 D11
N – 8 D10
N – 7 D11
N – 7 D10
N – 6
N – 1
N
N + 1 N + 2
N + 3
N + 4
N + 5
t
A
t
CH
t
PD
t
SKEW
t
DCO
t
CLK
09996-002
Figure 2. Even/Odd LVDS Mode Data Output Timing
Rev. B | Page 7 of 30
AD9634 Data Sheet
Rev. B | Page 8 of 30
TIMING SPECIFICATIONS
Table 5.
Parameter Test Conditions/Comments Min Typ Max Unit
SPI TIMING REQUIREMENTS See Figure 58 for the SPI timing diagram
tDS Setup time between the data and the rising edge of SCLK 2 ns
tDH Hold time between the data and the rising edge of SCLK 2 ns
tCLK Period of the SCLK 40 ns
tS Setup time between CSB and SCLK 2 ns
tH Hold time between CSB and SCLK 2 ns
tHIGH Minimum period that SCLK should be in a logic high state 10 ns
tLOW Minimum period that SCLK should be in a logic low state 10 ns
tEN_SDIO Time required for the SDIO pin to switch from an input to an output
relative to the SCLK falling edge (not shown in Figure 58)
10 ns
tDIS_SDIO Time required for the SDIO pin to switch from an output to an input
relative to the SCLK rising edge (not shown in Figure 58)
10 ns
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Data Sheet AD9634
Rev. B | Page 9 of 30
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Rating
Electrical
AVDD to AGND −0.3 V to +2.0 V
DRVDD to AGND −0.3 V to +2.0 V
VIN+, VIN− to AGND −0.3 V to AVDD + 0.2 V
CLK+, CLK− to AGND −0.3 V to AVDD + 0.2V
VCM to AGND −0.3 V to AVDD + 0.2 V
CSB to AGND −0.3 V to DRVDD + 0.3 V
SCLK to AGND −0.3 V to DRVDD + 0.3 V
SDIO to AGND −0.3 V to DRVDD + 0.3 V
D0±/D1± through D10±/D11±
to AGND
−0.3 V to DRVDD + 0.3 V
DCO+/DCO− to AGND −0.3 V to DRVDD + 0.3 V
OR+/OR− to AGND −0.3 V to DRVDD + 0.3 V
Environmental
Operating Temperature Range
(Ambient)
−40°C to +85°C
Maximum Junction Temperature
Under Bias
150°C
Storage Temperature Range
(Ambient)
−65°C to +125°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL CHARACTERISTICS
The exposed paddle must be soldered to the ground plane for the
LFCSP package. Soldering the exposed paddle to the customer
board increases the reliability of the solder joints, maximizing
the thermal capability of the package.
Table 7. Thermal Resistance
Package
Type
Airflow
Velocity
(m/sec) θJA1, 2 θJC1, 3 θJB1, 4 Unit
32-Lead LFCSP
5 mm × 5 mm
(CP-32-12)
0 37.1 3.1 20.7 °C/W
1.0 32.4 °C/W
2.0 29.1 °C/W
1 Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.
2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3 Per MIL-Std 883, Method 1012.1.
4 Per JEDEC JESD51-8 (still air).
Typical θJA is specified for a 4-layer PCB with solid ground plane.
As shown in Table 7, airflow increases heat dissipation, which
reduces θJA. In addition, metal in direct contact with the package
leads from metal traces, through holes, ground, and power
planes reduces the θJA.
ESD CAUTION
AD9634 Data Sheet
Rev. B | Page 10 of 30
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
24 CSB
23 SCLK
22 SDIO
21 DCO+
20 DCO–
19 D10+/D11+ (MSB)
18 D10–/D11– (MSB)
17 DRVDD
1
2
3
4
5
6
7
8
CLK+
CLK–
AVDD
OR–
OR+
D0–/D1– (LSB)
D0+/D1+ (LSB)
DRVDD
9
10
11
12
13
14
15
16
D2–/D3–
D2+/D3+
D4–/D5–
D4+/D5+
D6–/D7–
D6+/D7+
D8–/D9–
D8+/D9+
32
31
30
29
28
27
26
25
AVDD
AVDD
VIN+
VIN–
AVDD
AVDD
VCM
DNC
AD9634
TOP VIEW
(Not to Scale)
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE
PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED
PADDLE MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
09996-003
Figure 3. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic Type Description
ADC Power Supplies
8, 17 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal).
3, 27, 28, 31, 32 AVDD Supply Analog Power Supply (1.8 V Nominal).
0 AGND, Exposed
Paddle
Ground Analog Ground. The exposed thermal paddle on the bottom of the
package provides the analog ground for the part. This exposed paddle
must be connected to ground for proper operation.
25 DNC Do No Connect. Do not connect to this pin.
ADC Analog
30 VIN+ Input Differential Analog Input Pin (+).
29 VIN− Input Differential Analog Input Pin (−).
26 VCM Output
Common-Mode Level Bias Output for Analog Inputs. This pin should be
decoupled to ground using a 0.1 μF capacitor.
1 CLK+ Input ADC Clock Input—True.
2 CLK− Input ADC Clock Input—Complement.
Digital Outputs
5 OR+ Output Overrange—True.
4 OR− Output Overrange—Complement.
7 D0+/D1+ (LSB) Output DDR LVDS Output Data 0/Data 1—True (LSB).
6 D0−/D1− (LSB) Output DDR LVDS Output Data 0/Data 1—Complement (LSB).
10 D2+/D3+ Output DDR LVDS Output Data 2/Data 3—True.
9 D2−/D3− Output DDR LVDS Output Data 2/Data 3—Complement.
12 D4+/D5+ Output DDR LVDS Output Data 4/Data 5—True.
11 D4−/D5− Output DDR LVDS Output Data 4/Data 5—Complement.
14 D6+/D7+ Output DDR LVDS Output Data 6/Data 7—True.
13 D6−/D7− Output DDR LVDS Output Data 6/Data 7—Complement.
16 D8+/D9+ Output DDR LVDS Output Data 8/Data 9—True.
15 D8−/D9− Output DDR LVDS Output Data 8/Data 9—Complement.
19 D10+/D11+ (MSB) Output DDR LVDS Output Data 10/Data 11—True (MSB).
18 D10−/ D11− (MSB) Output DDR LVDS Output Data 10/Data 11—Complement (MSB).
21 DCO+ Output LVDS Data Clock Output—True.
20 DCO− Output LVDS Data Clock Output—Complement.
Data Sheet AD9634
Rev. B | Page 11 of 30
Pin No. Mnemonic Type Description
SPI Control
23 SCLK Input SPI Serial Clock.
22 SDIO Input/Output SPI Serial Data I/O.
24 CSB Input SPI Chip Select (Active Low).
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AD9634 Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = maximum sample rate per speed grade, DCS enabled, 1.75 V p-p differential input,
VIN = −1.0 dBFS, 32k sample, TA = 25°C, unless otherwise noted.
0
–140
–120
–100
–80
–60
–40
–20
08070605040302010
SECOND
HARMONIC THIRD
HARMONIC
AMPLITUDE (dBFS)
FREQUENCY (MHz)
170MSPS
90.1MHz @ –1.0dBFS
SNR = 69.1dB (70.1dBFS)
SFDR = 93dBc
09996-004
Figure 4. AD9634-170 Single-Tone FFT with fIN = 90.1 MHz
0
–140
–120
–100
–80
–60
–40
–20
08070605040302010
SECOND
HARMONIC THIRD
HARMONIC
AMPLITUDE (dBFS)
FREQUENCY (MHz)
170MSPS
185.1MHz @ –1.0dBFS
SNR = 68.5dB (69.5dBFS)
SFDR = 86dBc
09996-005
Figure 5. AD9634-170 Single-Tone FFT with fIN = 185.1 MHz
0
–140
–120
–100
–80
–60
–40
–20
08070605040302010
SECOND
HARMONIC
THIRD
HARMONIC
AMPLITUDE (dBFS)
FREQUENCY (MHz)
170MSPS
220.1MHz @ –1.0dBFS
SNR = 68.2dB (69.2dBFS)
SFDR = 84dBc
09996-006
Figure 6. AD9634-170 Single-Tone FFT with fIN = 220.1 MHz
0
–140
–120
–100
–80
–60
–40
–20
08070605040302010
SECOND
HARMONIC
THIRD
HARMONIC
AMPLITUDE (dBFS)
FREQUENCY (MHz)
09996-107
170MSPS
305.1MHz @ –1.0dBFS
SNR = 67.2dB (68.2dBFS)
SFDR = 86dBc
Figure 7. AD9634-170 Single-Tone FFT with fIN = 305.1 MHz
120
0
20
40
60
80
100
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0
SNR/SFDR (dBc and dBFS)
INPUT AMPLITUDE (dBFS)
SNR (dBFS)
SFDR (dBc)
SNR (dBc)
SFDR (dBFS)
09996-007
Figure 8. AD9634-170 Single-Tone SNR/SFDR vs.
Input Amplitude (AIN) with fIN = 90.1 MHz, fS = 170 MSPS
100
95
90
85
80
75
70
65
6060 90 120 150 180 210 240 270 300 330
SNR/SFDR (dBc and dBFS)
INPUT FREQUENCY (MHz)
SNR (dBFS)
SFDR (dBc)
09996-008
Figure 9. AD9634-170 Single-Tone SNR/SFDR vs. Input Frequency (fIN),
fS = 170 MSPS
Rev. B | Page 12 of 30
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Data Sheet AD9634
0
–20
–40
–60
–80
–100
–120
SFDR/IMD3 (dBc and dBFS)
INPUT AMPLITUDE (dBFS)
SFDR (dBc)
SFDR (dBFS)
IMD3 (dBc)
IMD3 (dBFS)
09996-009
–90.0 –81.7 –73.4 –65.1 –56.8 –48.5 –40.2 –31.9 –23.6 –15.3 –7.0
Figure 10. AD9634-170 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with
fIN1 = 89.12 MHz, fIN2 = 92.12 MHz, fS = 170 MSPS
–90.0 –81.7 –73.4 –65.1 –56.8 –48.5 –40.2 –31.9 –23.6 –15.3 –7.0
0
–20
–40
–60
–80
–100
–120
SFDR/IMD3 (dBc and dBFS)
INPUT AMPLITUDE (dBFS)
SFDR (dBc)
SFDR (dBFS)
IMD3 (dBc)
IMD3 (dBFS)
09996-010
Figure 11. AD9634-170 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)
with fIN1 = 184.12 MHz, fIN2 = 187.12 MHz, fS = 170 MSPS
0
–140
–120
–100
–80
–60
–40
–20
08070605040302010
AMPLITUDE (dBFS)
FREQUENCY (MHz)
170MSPS
89.12MHz @ –7.0dBFS
92.12MHz @ –7.0dBFS
SFDR = 89dBc (96dBFS)
09996-011
Figure 12. AD9634-170 Two-Tone FFT with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz
0
–140
–120
–100
–80
–60
–40
–20
08070605040302010
AMPLITUDE (dBFS)
FREQUENCY (MHz)
170MSPS
184.12MHz @ –7.0dBFS
187.12MHz @ –7.0dBFS
SFDR = 85dBc (92dBFS)
09996-012
Figure 13. AD9634-170 Two Tone FFT with fIN1 = 184.12 MHz, fIN2 = 187.12 MHz
100
95
90
85
80
75
70
6540 50 60 70 80 90 100 110 120 130 140 150 160 170
SNR/SFDR (dBFS and dBc)
SAMPLE RATE (MSPS)
SNR
SFDR
09996-013
Figure 14. AD9634-170 Single-Tone SNR/SFDR vs. Sample Rate (fS)
with fIN = 90 MHz
14000
12000
10000
8000
6000
4000
2000
0
NUMBER OF HITS
OUTPUT CODE
0.531 LSB rms
16,384 TOTAL HITS
09996-014
N – 1 NN + 1
Figure 15. AD9634-170 Grounded Input Histogram, fS = 170 MSPS
Rev. B | Page 13 of 30
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AD9634 Data Sheet
0
–140
–120
–100
–80
–60
–40
–20
0105
907560453015
SECOND
HARMONIC THIRD
HARMONIC
AMPLITUDE (dBFS)
FREQUENCY (MHz)
210MSPS
90.1MHz @ –1.0dBFS
SNR = 69.1dB (70.1dBFS)
SFDR = 92dBc
09996-015
Figure 16. AD9634-210 Single-Tone FFT with fIN = 90.1 MHz
0
–140
–120
–100
–80
–60
–40
–20
0105907560453015
SECOND
HARMONIC THIRD
HARMONIC
AMPLITUDE (dBFS)
FREQUENCY (MHz)
210MSPS
185.1MHz @ –1.0dBFS
SNR = 68.6dB (69.6dBFS)
SFDR = 93dBc
09996-016
Figure 17. AD9634-210 Single-Tone FFT with fIN = 185.1 MHz
0
–140
–120
–100
–80
–60
–40
–20
0105907560453015
SECOND
HARMONIC
THIRD
HARMONIC
AMPLITUDE (dBFS)
210MSPS
220.1MHz @ –1.0dBFS
SNR = 68.3dB (69.3dBFS)
SFDR = 84dBc
09996-017
FREQUENCY (MHz)
Figure 18. AD9634-210 Single-Tone FFT with fIN = 220.1 MHz
0
–140
–120
–100
–80
–60
–40
–20
0105907560453015
SECOND
HARMONIC THIRD
HARMONIC
AMPLITUDE (dBFS)
210MSPS
305.1MHz @ –1.0dBFS
SNR = 67.6dB (68.6dBFS)
SFDR = 83dBc
09996-100
FREQUENCY (MHz)
Figure 19. AD9634-210 Single-Tone FFT with fIN = 305.1 MHz
120
0
20
40
60
80
100
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0
SNR/SFDR (dBc and dBFS)
SNR (dBFS)
SFDR (dBc)
SNR (dBc)
SFDR (dBFS)
09996-018
INPUT AMPLITUDE (dBFS)
Figure 20. AD9634-210 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with
fIN = 90.1 MHz, fS = 210 MSPS
100
95
90
85
80
75
70
65
6060 90 120 150 180 210 240 270 300 330
SNR/SFDR (dBc and dBFS)
SNR (dBFS)
SFDR (dBc)
09996-019
INPUT FREQUENCY (MHz)
Figure 21. AD9634-210 Single-Tone SNR/SFDR vs. Input Frequency (fIN),
fS = 210 MSPS
Rev. B | Page 14 of 30
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Data Sheet AD9634
–90.0 –81.7 –73.4 –65.1 –56.8 –48.5 –40.2 –31.9 –23.6 –15.3 –7.0
0
–20
–40
–60
–80
–100
–120
SFDR/IMD3 (dBc and dBFS)
SFDR (dBc)
SFDR (dBFS)
IMD3 (dBc)
IMD3 (dBFS)
09996-020
INPUT AMPLITUDE (dBFS)
Figure 22. AD9634-210 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with
fIN1 = 89.12 MHz, fIN2 = 92.12 MHz, fS = 210 MSPS
–90.0 –81.7 –73.4 –65.1 –56.8 –48.5 –40.2 –31.9 –23.6 –15.3 –7.0
0
–20
–40
–60
–80
–100
–120
SFDR/IMD3 (dBc and dBFS)
INPUT AMPLITUDE (dBFS)
SFDR (dBc)
SFDR (dBFS)
IMD3 (dBc)
IMD3 (dBFS)
09996-021
Figure 23. AD9634-210 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with
fIN1 = 184.12 MHz, fIN2 = 187.12 MHz, fS = 210 MSPS
0
–140
–120
–100
–80
–60
–40
–20
0105907560453015
AMPLITUDE (dBFS)
FREQUENCY (MHz)
210MSPS
89.12MHz @ –7.0dBFS
92.12MHz @ –7.0dBFS
SFDR = 88dBc (95dBFS)
09996-022
Figure 24. AD9634-210 Two-Tone FFT with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz
0
–140
–120
–100
–80
–60
–40
–20
AMPLITUDE (dBFS)
FREQUENCY (MHz)
09996-023
210MSPS
184.12MHz @ –7.0dBFS
187.12MHz @ –7.0dBFS
SFDR = 89dBc (96dBFS)
0105907560453015
Figure 25. AD9634-210 Two Tone FFT with fIN1 = 184.12 MHz, fIN2 = 187.12 MHz
100
95
90
85
80
75
70
65
40 50 60 70 80 90 100 110 120 130 150 170 190 210
140 160 180 200
SNR/SFDR (dBFS and dBc)
SAMPLE RATE (MSPS)
SNR
SFDR
09996-024
Figure 26. AD9634-210 Single-Tone SNR/SFDR vs. Sample Rate (fS) with
fIN = 90 MHz
16000
14000
12000
10000
8000
6000
4000
2000
0
NUMBER OF HITS
OUTPUT CODE
0.391 LSB rms
16,384 TOTAL HITS
09996-025
N – 1 NN + 1
Figure 27. AD9634-210 Grounded Input Histogram, fS = 210 MSPS
Rev. B | Page 15 of 30
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AD9634 Data Sheet
0
–140
–120
–100
–80
–60
–40
–20
0125100755025
SECOND
HARMONIC
THIRD
HARMONIC
AMPLITUDE (dBFS)
FREQUENCY (MHz)
250MSPS
90.1MHz @ –1.0dBFS
SNR = 69.0dB (70.0dBFS)
SFDR = 89dBc
09996-026
Figure 28. AD9634-250 Single-Tone FFT with fIN = 90.1 MHz
0
–140
–120
–100
–80
–60
–40
–20
0125100755025
SECOND
HARMONIC
THIRD
HARMONIC
AMPLITUDE (dBFS)
FREQUENCY (MHz)
250MSPS
185.1MHz @ –1.0dBFS
SNR = 68.7dB (69.7dBFS)
SFDR = 87dBc
09996-027
Figure 29. AD9634-250 Single-Tone FFT with fIN = 185.1 MHz
0
–20
–40
–60
–80
–100
–120
–140 025 50 75 100 125
AMPLITUDE (dBFS)
FREQUENCY (MHz)
250MSPS
220.1MHz @ –1.0dBFS
SNR = 68.3dB (69.3dBFS)
SFDR = 91dBc
SECOND
HARMONIC THIRD
HARMONIC
09996-028
Figure 30. AD9634-250 Single-Tone FFT with fIN = 220.1 MHz
0
–20
–40
–60
–80
–100
–120
–140 025 50 75 100 125
AMPLITUDE (dBFS)
FREQUENCY (MHz)
250MSPS
305.1MHz @ –1.0dBFS
SNR = 67.4dB (68.4dBFS)
SFDR = 82dBc
SECOND
HARMONIC
THIRD
HARMONIC
09996-101
Figure 31. AD9634-250 Single-Tone FFT with fIN = 305.1 MHz
120
0
20
40
60
80
100
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0
SNR/SFDR (dBc and dBFS)
INPUT AMPLITUDE (dBFS)
SNR (dBFS)
SFDR (dBc)
SNR (dBc)
SFDR (dBFS)
09996-029
Figure 32. AD9634-250 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with
fIN = 90.1 MHz, fS = 250 MSPS
100
95
90
85
80
75
70
65
6060 90 120 150 180 210 240 270 300 330
SNR/SFDR (dBc and dBFS)
INPUT FREQUENCY (MHz)
SNR (dBFS)
SFDR (dBc)
09996-030
Figure 33. AD9634-250 Single-Tone SNR/SFDR vs. Input Frequency (fIN),
fS = 250 MSPS
Rev. B | Page 16 of 30
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Data Sheet AD9634
–90.0 –81.7 –73.4 –65.1 –56.8 –48.5 –40.2 –31.9 –23.6 –15.3 –7.0
0
–20
–40
–60
–80
–100
–120
SFDR/IMD3 (dBc and dBFS)
INPUT AMPLITUDE (dBFS)
SFDR (dBc)
SFDR (dBFS)
IMD3 (dBc)
IMD3 (dBFS)
09996-031
Figure 34. AD9634-250 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with
fIN1 = 89.12 MHz, fIN2 = 92.12 MHz, fS = 250 MSPS
–90.0 –81.7 –73.4 –65.1 –56.8 –48.5 –40.2 –31.9 –23.6 –15.3 –7.0
0
–20
–40
–60
–80
–100
–120
SFDR/IMD3 (dBc and dBFS)
INPUT AMPLITUDE (dBFS)
SFDR (dBc)
SFDR (dBFS)
IMD3 (dBc)
IMD3 (dBFS)
09996-032
Figure 35. AD9634-250 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)
with fIN1 = 184.12 MHz, fIN2 = 187.12 MHz, fS = 250 MSPS
0
–140
–120
–100
–80
–60
–40
–20
0125100755025
AMPLITUDE (dBFS)
FREQUENCY (MHz)
09996-033
250MSPS
89.12MHz @ –7.0dBFS
92.12MHz @ –7.0dBFS
SFDR = 88dBc (95dBFS)
Figure 36. AD9634-250 Two-Tone FFT with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz
09996-034
0
–140
–120
–100
–80
–60
–40
–20
0125100755025
AMPLITUDE (dBFS)
FREQUENCY (MHz)
250MSPS
184.12MHz @ –7.0dBFS
187.12MHz @ –7.0dBFS
SFDR = 88dBc (95dBFS)
Figure 37. AD9634-250 Two Tone FFT with fIN1 = 184.12 MHz, fIN2 = 187.12 MHz
100
95
90
85
80
75
70
6540 60 80 100 120 140 160 180 200 220 240 260
SNR/SFDR (dBFS and dBc)
SAMPLE RATE (MSPS)
SNR
SFDR
09996-035
Figure 38. AD9634-250 Single-Tone SNR/SFDR vs. Sample Rate (fS)
with fIN = 90 MHz
16000
14000
12000
10000
8000
6000
4000
2000
0
NUMBER OF HITS
OUTPUT CODE
0.407 LSB rms
16,384 TOTAL HITS
09996-036
N – 1 NN + 1
Figure 39. AD9634-250 Grounded Input Histogram, fS = 250 MSPS
Rev. B | Page 17 of 30
mm DRVDD 35m E 3500 E Avon
AD9634 Data Sheet
EQUIVALENT CIRCUITS
VIN
AVDD
09996-037
Figure 40. Equivalent Analog Input Circuit
0.9V
15kΩ 15kΩ
CLK+ CLK–
AVDD
AVDD AVDD
09996-038
Figure 41. Equivalent Clock lnput Circuit
DRVDD
DATAOUT+
V–
V+
DATAOUT–
V+
V–
09996-039
Figure 42. Equivalent LVDS Output Circuit
SDIO 350Ω
26kΩ
DRVDD
09996-040
Figure 43. Equivalent SDIO Circuit
SCLK 350Ω
26kΩ
09996-041
Figure 44. Equivalent SCLK Input Circuit
CSB 350Ω
26kΩ
AVDD
09996-042
Figure 45. Equivalent CSB Input Circuit
Rev. B | Page 18 of 30
Data Sheet AD9634
THEORY OF OPERATION
The AD9634 can sample any fS/2 frequency segment from dc to
250 MHz using appropriate low-pass or band-pass filtering at
the ADC inputs with little loss in ADC performance.
Programming and control of the AD9634 are accomplished
using a 3-pin, SPI-compatible serial interface.
ADC ARCHITECTURE
The AD9634 architecture consists of a front-end sample-and-
hold circuit, followed by a pipelined, switched-capacitor ADC.
The quantized outputs from each stage are combined into a
final 12-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate on a new input
sample and the remaining stages to operate on the preceding
samples. Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor digital-
to-analog converter (DAC) and an interstage residue amplifier
(MDAC). The MDAC magnifies the difference between the
reconstructed DAC output and the flash input for the next stage
in the pipeline. One bit of redundancy is used in each stage to
facilitate digital correction of flash errors. The last stage simply
consists of a flash ADC.
The input stage contains a differential sampling circuit that can
be ac- or dc-coupled in differential or single-ended modes. The
output staging block aligns the data, corrects errors, and passes the
data to the output buffers. The output buffers are powered from a
separate supply, allowing digital output noise to be separated from
the analog core. During power-down, the output buffers go into
a high impedance state.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9634 is a differential switched-capacitor
circuit that has been designed to attain optimum performance
when processing a differential input signal.
The clock signal alternatively switches the input between sample
mode and hold mode (see the configuration shown in Figure 46).
When the input is switched into sample mode, the signal source
must be capable of charging the sampling capacitors and settling
within ½ clock cycle.
A small resistor in series with each input can help reduce the
peak transient current required from the output stage of the
driving source. A shunt capacitor can be placed across the
inputs to provide dynamic charging currents. This passive
network creates a low-pass filter at the ADC input; therefore,
the precise values are dependent on the application.
In intermediate frequency (IF) undersampling applications, reduce
the shunt capacitors. In combination with the driving source
impedance, the shunt capacitors limit the input bandwidth.
Refer to the AN-742 Application Note, Frequency Domain
Response of Switched-Capacitor ADCs; the AN-827 Application
Note, A Resonant Approach to Interfacing Amplifiers to Switched-
Capacitor ADCs; and the Analog Dialogue article, “Transformer-
Coupled Front-End for Wideband A/D Converters” for more
information on this subject.
C
PAR1
C
PAR1
C
PAR2
C
PAR2
S
S
S
S
S
S
C
FB
C
FB
C
S
C
S
BIAS
BIAS
VIN+
H
VIN–
09996-043
Figure 46. Switched-Capacitor Input
For best dynamic performance, match the source impedances
driving VIN+ and VIN− and differentially balance the inputs.
Input Common Mode
The analog inputs of the AD9634 are not internally dc biased. In
ac-coupled applications, the user must provide this bias externally.
Setting the device so that VCM = 0.5 × AVDD (or 0.9 V) is
recommended for optimum performance. An on-board common-
mode voltage reference is included in the design and is available
from the VCM pin. Using the VCM output to set the input
common mode is recommended. Optimum performance is
achieved when the common-mode voltage of the analog input
is set by the VCM pin voltage (typically 0.5 × AVDD). The
VCM pin must be decoupled to ground by a 0.1 µF capacitor,
as described in the Applications Information section. Place this
decoupling capacitor close to the pin to minimize the series
resistance and inductance between the part and this capacitor.
Rev. B | Page 19 of 30
”15 WFQ 4+» 4—4
AD9634 Data Sheet
Rev. B | Page 20 of 30
Differential Input Configurations
Optimum performance can be achieved when driving the
AD9634 in a differential input configuration. For baseband
applications, the AD8138, ADA4937-1, and ADA4930-1
differential drivers provide excellent performance and a flexible
interface to the ADC.
The output common-mode voltage of the ADA4930-1 is easily
set with the VCM pin of the AD9634 (see Figure 47), and the
driver can be configured in a Sallen-Key filter topology to
provide band limiting of the input signal.
V
IN 76.8Ω
120Ω
0.1µF
200Ω
200Ω
90ΩAVDD
33Ω
33Ω
15Ω
15Ω
5pF
15pF
15pF
ADC
VIN–
VIN+ VCM
ADA4930-1
0.1µF
09996-044
Figure 47. Differential Input Configuration Using the ADA4930-1
For baseband applications where SNR is a key parameter,
differential transformer coupling is the recommended input
configuration. An example is shown in Figure 48. To bias the
analog input, connect the VCM voltage to the center tap of the
secondary winding of the transformer.
2V p-p 49.9Ω
0.1µF
R1
R1
C1 ADC
VIN+
VIN– VCM
C2
R2
R3
R2
C2
R3 0.1µF
09996-045
Figure 48. Differential Transformer-Coupled Configuration
The signal characteristics must be considered when selecting
a transformer. Most RF transformers saturate at frequencies
below a few megahertz. Excessive signal power can also cause
core saturation, which leads to distortion.
At input frequencies in the second Nyquist zone and above, the
noise performance of most amplifiers is not adequate to achieve
the true SNR performance of the AD9634. For applications where
SNR is a key parameter, differential double balun coupling is
the recommended input configuration (see Figure 49). In this
configuration, the input is ac-coupled and the VCM voltage is
provided to each input through a 33 Ω resistor. These resistors
compensate for losses in the input baluns to provide a 50 Ω
impedance to the driver.
In the double balun and transformer configurations, the value
of the input capacitors and resistors is dependent on the input
frequency and source impedance. Based on these parameters
the value of the input resistors and capacitors may need to be
adjusted, or some components may need to be removed. Table 9
displays recommended values to set the RC network for different
input frequency ranges. However, these values are dependent on
the input signal and bandwidth and should be used only as a
starting guide. Note that the values given in Table 9 are for the
R1, R2, R3, C1, and C2 components shown in Figure 49.
Table 9. Example RC Network
Frequency Range (MHz) R1 Series (Ω) C1 Differential (pF) R2 Series (Ω) C2 Shunt (pF) R3 Shunt (Ω)
0 to 100 33 8.2 0 15 49.9
100 to 300 15 3.9 0 8.2 49.9
ADC
R1
0.1µF
0.1µF
2V p-p VIN+
VIN– VCM
C1
C2
R1
R2
R2
0.1µF
S
0.1µF
C2
33Ω
33Ω
SP
A
P
R3
R3 0.1µF
09996-046
Figure 49. Differential Double Balun Input Configuration
Data Sheet AD9634
Rev. B | Page 21 of 30
AD8375
AD9634
1µH
1µH 1nF
1nF
VPOS
VCM
15pF
68nH
2.5kΩ║2pF
301Ω
165Ω
165Ω
5.1pF 3.9pF
180nH1000pF
1000pF 180nH
220nH
220nH
NOTES
1. ALL INDUCTORS ARE COILCRAFT 0603CS COMPONENTS
WITH THE EXCEPTION OF THE 1µH CHOKE INDUCTORS (0603LS).
2. FILTER VALUES SHOWN ARE FOR A 20MHz BANDWIDTH FILTER CENTERED AT 140MHz.
09996-047
Figure 50. Differential Input Configuration Using the AD8375
An alternative to using a transformer-coupled input at
frequencies in the second Nyquist zone is to use an amplifier
with variable gain. The AD8375 digital variable gain amplifier
(DVGA) provides good performance for driving the AD9634.
Figure 50 shows an example of the AD8375 driving the AD9634
through a band-pass antialiasing filter.
VOLTAGE REFERENCE
A stable and accurate voltage reference is built into the AD9634.
The full-scale input range can be adjusted by varying the reference
voltage via SPI. The input span of the ADC tracks reference
voltage changes linearly.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9634 sample clock inputs,
CLK+ and CLK−, should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK− pins by
means of a transformer or a passive component configuration.
These pins are biased internally (see Figure 51) and require no
external bias. If the inputs are floated, the CLK− pin is pulled low
to prevent spurious clocking.
AVDD
CLK+
4pF4pF
CLK–
0.9V
09996-048
Figure 51. Equivalent Clock Input Circuit
Clock Input Options
The AD9634 has a very flexible clock input structure. Clock input
can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless
of the type of signal being used, clock source jitter is of the most
concern, as described in the Jitter Considerations section.
Figure 52 and Figure 53 show two preferable methods for clocking
the AD9634 (at clock rates of up to 625 MHz). A low jitter clock
source is converted from a single-ended signal to a differential
signal using an RF balun or RF transformer.
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 625 MHz, and the RF transformer is
recommended for clock frequencies from 10 MHz to 200 MHz.
The back-to-back Schottky diodes across the secondary windings
of the transformer limit clock excursions into the AD9634 to
approximately 0.8 V p-p differential. This limit helps prevent the
large voltage swings of the clock from feeding through to other
portions of the AD9634, while preserving the fast rise and fall times
of the signal, which are critical for low jitter performance.
390pF
390pF390pF
SCHOTTKY
DIODES:
HSMS2822
CLOCK
INPUT 50Ω100Ω
CLK–
CLK+
ADC
Mini-Circuits
®
ADT1-1WT, 1:1Z
XFMR
09996-056
Figure 52. Transformer Coupled Differential Clock (Up to 200 MHz)
390pF 390pF
390pF
CLOCK
INPUT
1nF
25Ω
25Ω
CLK–
CLK+
SCHOTTKY
DIODES:
HSMS2822
ADC
09996-057
Figure 53. Balun-Coupled Differential Clock (Up to 625 MHz)
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input pins
as shown in Figure 54. The AD9510, AD9511, AD9512, AD9513,
AD9514, AD9515, AD9516, AD9517, AD9518, AD9520, AD9522,
AD9523, AD9524, ADCLK905, ADCLK907, and ADCLK925
clock drivers offer excellent jitter performance.
100Ω
0.1µF
0.1µF0.1µF
0.1µF
240Ω240Ω
PECL DRIVER
50kΩ50kΩ
CLK–
CLK+
CLOCK
INPUT
CLOCK
INPUT
AD95xx,
ADCLKxxx ADC
09996-051
Figure 54. Differential PECL Sample Clock (Up to 625 MHz)
I WP 973
AD9634 Data Sheet
Rev. B | Page 22 of 30
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 55. The AD9510,
AD9511, AD9512, AD9513, AD9514, AD9515, AD9516, AD9517,
AD9518, AD9520, AD9522, AD9523, AD9524 clock drivers offer
excellent jitter performance.
100Ω
0.1µF
0.1µF
0.1µF
0.1µF
50kΩ50kΩ
CLK–
CLK+
CLOCK
INPUT
CLOCK
INPUT
AD95xx
LVDS DRIVER
ADC
09996-052
Figure 55. Differential LVDS Sample Clock (Up to 625 MHz)
Input Clock Divider
The AD9634 contains an input clock divider with the ability to
divide the input clock by integer values between 1 and 8. For
divide ratios other than 1, the DCS is enabled by default on
power-up.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be sensitive to
clock duty cycle. Commonly, a ±5% tolerance is required on the
clock duty cycle to maintain dynamic performance characteristics.
The AD9634 contains a DCS that retimes the nonsampling
(falling) edge, providing an internal clock signal with a nominal
50% duty cycle. This allows the user to provide a wide range of
clock input duty cycles without affecting the performance of the
AD9634.
Jitter on the rising edge of the input clock is still of paramount
concern and is not reduced by the duty cycle stabilizer. The duty
cycle control loop does not function for clock rates less than
40 MHz nominally. The loop has a time constant associated
with it that must be considered when the clock rate may change
dynamically. A wait time of 1.5 μs to 5 μs is required after a
dynamic clock frequency increase or decrease before the DCS loop
is relocked to the input signal. During the time that the loop is
not locked, the DCS loop is bypassed, and internal device timing
is dependent on the duty cycle of the input clock signal. In such
applications, it may be appropriate to disable the duty cycle
stabilizer. In all other applications, enabling the DCS circuit is
recommended to maximize ac performance.
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR at a given input
frequency (fIN) due to jitter (tJ) can be calculated by
SNRHF = −10 log[(2π × fIN × tJRMS)2 + 10 )10/( LF
SNR]
In the equation, the rms aperture jitter represents the root-
mean-square of all jitter sources, which include the clock input,
the analog input signal, and the ADC aperture jitter specification.
IF undersampling applications are particularly sensitive to jitter,
as shown in Figure 56.
80
75
70
65
60
55
50
1 10 100 1000
SNR (dBFS)
INPUT FREQUENCY (MHz)
0.05ps
0.2ps
0.5ps
1ps
1.5ps
MEASURED
09996-054
Figure 56. AD9634-250 SNR vs. Input Frequency and Jitter
In cases where aperture jitter may affect the dynamic range of the
AD9634, treat the clock input as an analog signal. In addition,
use separate power supplies for the clock drivers and the ADC
output driver to avoid modulating the clock signal with digital
noise. Low jitter, crystal controlled oscillators provide the best clock
sources. If the clock is generated from another type of source (by
gating, dividing, or another method), it should be retimed by the
original clock during the last step.
Refer to AN-501 Application Note, Aperture Uncertainty and ADC
System Performance, and AN-756 Application Note, Sampled
Systems and the Effects of Clock Phase Noise and Jitter, for more
information about jitter performance as it relates to ADCs.
\ \\ \ \ \ \ Table 10. Output Data Emma:
Data Sheet AD9634
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 57, the power dissipated by the AD9634 is
proportional to its sample rate. The data in Figure 57 was taken
using the same operating conditions as those used for the Typical
Performance Characteristics section.
0.4
0.3
0.2
0.1
0
0.25
0.20
0.15
0.10
0.05
0
40 55 70 85 100 115 130 145 160 175 190 205 220 235 250
TOTAL POWER (W)
SUPPLY CURRENT (A)
ENCODE FREQUENCY (MSPS)
TOTAL POWER
I
AVDD
I
DRVDD
09996-053
Figure 57. AD9634-250 Power and Current vs. Sample Rate
By setting the internal power-down mode bits (Bits[1:0]) in the
power modes register (Address 0x08) to 01, the AD9634 is placed
in power-down mode. In this state, the ADC typically dissipates
5 mW. During power-down, the output drivers are placed in a
high impedance state.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering power-
down mode and then must be recharged when returning to
normal operation. As a result, wake-up time is related to the
time spent in power-down mode, and shorter power-down
cycles result in proportionally shorter wake-up times.
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. To put the part into standby
mode, set the internal power-down mode bits (Bits[1:0]) in the
power modes register (Address 0x08) to 10. See the Memory
Map section and AN-877 Application Note, Interfacing to High
Speed ADCs via SPI for additional details.
DIGITAL OUTPUTS
The AD9634 output drivers can be configured for either ANSI
LVDS or reduced swing LVDS using a 1.8 V DRVDD supply.
As detailed in the AN-877 Application Note, Interfacing to High
Speed ADCs via SPI, the data format can be selected for offset
binary, twos complement, or gray code when using the SPI
control.
Digital Output Enable Function (OEB)
The AD9634 has a flexible three-state ability for the digital output
pins. The three-state mode is enabled using the SPI interface.
The data outputs can be three-stated by using the output enable
bar bit (Bit 4) in Register 0x14. This OEB function is not intended
for rapid access to the data bus.
Timing
The AD9634 provides latched data with a pipeline delay of 10 input
sample clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of the clock signal.
Minimize the length of the output data lines as well as the loads
placed on these lines to reduce transients within the AD9634.
These transients may degrade converter dynamic performance.
The lowest typical conversion rate of the AD9634 is 40 MSPS. At
clock rates below 40 MSPS, dynamic performance can degrade.
Data Clock Output (DCO)
The AD9634 also provides the data clock output (DCO) intended
for capturing the data in an external register. Figure 2 shows
timing diagram of the AD9634 output modes.
ADC OVERRANGE (OR)
The ADC overrange indicator is asserted when an overrange is
detected on the input of the ADC. The overrange condition is
determined at the output of the ADC pipeline and, therefore, is
subject to a latency of 10 ADC clock cycles. An overrange at the
input is indicated by this bit 10 clock cycles after it occurs.
Table 10. Output Data Format
Input (V) VIN+ − VIN−, Input Span = 1.75 V p-p (V) Offset Binary Output Mode Twos Complement Mode (Default) OR
VIN+ − VIN− < −0.875 0000 0000 0000 1000 0000 0000 1
VIN+ − VIN− = −0.875 0000 0000 0000 1000 0000 0000 0
VIN+ − VIN− = 0 1000 0000 0000 0000 0000 0000 0
VIN+ − VIN− = +0.875 1111 1111 1111 0111 1111 1111 0
VIN+ − VIN− > +0.875 1111 1111 1111 0111 1111 1111 1
Rev. B | Page 23 of 30
Table 11. Serial Port Interface Pins
AD9634 Data Sheet
SERIAL PORT INTERFACE (SPI)
The AD9634 serial port interface (SPI) allows the user to configure
the converter for specific functions or operations through a
structured register space provided inside the ADC. The SPI offers
added flexibility and customization, depending on the application.
Addresses are accessed via the serial port and can be written to
or read from via the port. Memory is organized into bytes that can
be further divided into fields. These fields are documented in the
Memory Map section. For detailed operational information, see
the AN-877 Application Note, Interfacing to High Speed ADCs
via SPI.
CONFIGURATION USING THE SPI
Three pins define the SPI of this ADC: the SCLK pin, the SDIO
pin, and the CSB pin (see Table 11). The SCLK (serial clock) pin
is used to synchronize the read and write data presented from
and to the ADC. The SDIO (serial data input/output) pin is a
dual-purpose pin that allows data to be sent and read from the
internal ADC memory map registers. The CSB (chip select bar)
pin is an active-low control that enables or disables the read and
write cycles.
Table 11. Serial Port Interface Pins
Pin
Function
SCLK Serial clock. The serial shift clock input, which is used to
synchronize serial interface reads and writes.
SDIO
Serial data input/output. A dual-purpose pin that
typically serves as an input or an output, depending on
the instruction being sent and the relative position in the
timing frame.
CSB Chip select bar. An active-low control that gates the read
and write cycles.
The falling edge of CSB, in conjunction with the rising edge of
SCLK, determines the start of the framing. An example of the serial
timing and its definitions can be found in Figure 58 and Table 5.
Other modes involving the CSB are available. The CSB can be
held low indefinitely, which permanently enables the device;
this is called streaming. The CSB can stall high between bytes to
allow for additional external timing. When CSB is tied high, SPI
functions are placed in a high impedance mode. This mode turns
on any SPI pin secondary functions.
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase, and its length is determined
by the W0 and W1 bits.
All data is composed of 8-bit words. The first bit of each individual
byte of serial data indicates whether a read or write command is
issued. This allows the serial data input/output (SDIO) pin to
change direction from an input to an output.
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used both to program the chip and to read
the contents of the on-chip memory. If the instruction is a readback
operation, performing a readback causes the serial data input/
output (SDIO) pin to change direction from an input to an output
at the appropriate point in the serial frame.
Data can be sent in MSB-first mode or in LSB-first mode. MSB-
first mode is the default on power-up and can be changed via
the SPI port configuration register. For more information about
this and other features, see the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
HARDWARE INTERFACE
The pins described in Table 11 comprise the physical interface
between the user programming device and the serial port of the
AD9634. The SCLK pin and the CSB pin function as inputs when
using the SPI interface. The SDIO pin is bidirectional, functioning
as an input during write phases and as an output during readback.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in the AN-812 Application Note,
Microcontroller-Based Serial Port Interface (SPI) Boot Circuit.
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is used for
other devices, it may be necessary to provide buffers between
this bus and the AD9634 to prevent these signals from transi-
tioning at the converter inputs during critical sampling periods.
Rev. B | Page 24 of 30
Table 12. Feamres Accessible Using the SP1
Data Sheet AD9634
SPI ACCESSIBLE FEATURES
Table 12 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail in
AN-877 Application Note, Interfacing to High Speed ADCs via SPI.
Table 12. Features Accessible Using the SPI
Feature Name Description
Mode Allows the user to set either power-down mode
or standby mode
Clock Allows the user to access the DCS via the SPI
Offset Allows the user to digitally adjust the
converter offset
Test I/O Allows the user to set test modes to have
known data on output bits
Output Mode Allows the user to set up outputs
Output Phase Allows the user to set the output clock polarity
Output Delay Allows the user to vary the DCO delay
VREF Allows the user to set the reference voltage
Digital
Processing
Allows the user to enable the synchronization
features
DON’T CARE
DON’T CAREDON’T CARE
DON’T CARE
SDIO
SCLK
CSB
t
S
t
DH
t
CLK
t
DS
t
H
R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0
t
LOW
t
HIGH
09996-055
Figure 58. Serial Port Interface Timing Diagram
Rev. B | Page 25 of 30
AD9634 Data Sheet
MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
Each row in the memory map register table has eight bit
locations. The memory map is roughly divided into three
sections: the chip configuration registers (Address 0x00 to
Address 0x02), the transfer register (Address 0xFF), and the
ADC functions registers (Address 0x08 to Address 0x20),
including setup, control, and test.
The memory map register table (Table 13) documents the
default hexadecimal value for each hexadecimal address shown.
The Bit 7 (MSB) column is the start of the default hexadecimal
value given. For example, Address 0x14, the output mode register,
has a hexadecimal default value of 0x01. This means that Bit 0 = 1
and the remaining bits are 0s. This setting is the default output
format value, which is twos complement. For more information
on this function and others, see the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI. This document details
the functions controlled by Register 0x00 to Register 0x20.
Open Locations
All address and bit locations that are not included in Table 13
are not currently supported for this device. Write 0s to unused
bits of a valid address location. Writing to these locations is
required only when part of an address location is open (for
example, Address 0x18). If the entire address location is open
(for example, Address 0x13), do not write to this address location.
Default Values
After the AD9634 is reset, critical registers are loaded with
default values. The default values for the registers are given in
the memory map register table (see Table 13).
Logic Levels
An explanation of logic level terminology follows:
• “Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
• “Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
Transfer Register Map
Address 0x08 to Address 0x20 are shadowed. Writes to these
addresses do not affect part operation until a transfer command is
issued by writing 0x01 to Address 0xFF, setting the transfer bit. This
allows these registers to be updated internally and simultaneously
when the transfer bit is set. The internal update takes place
when the transfer bit is set, and then the bit autoclears.
Rev. B | Page 26 of 30
Table 13. Memory Map Registers
Data Sheet AD9634
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 13 are not currently supported for this device.
Table 13. Memory Map Registers
Addr
(Hex)
Register
Name
Bit 7
(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Default
Notes/
Comments
Chip Configuration Registers
0x00 SPI port
configuration
0 LSB first Soft reset 1 1 Soft reset LSB first 0 0x18 Nibbles are
mirrored so
that LSB-
first mode
or MSB-first
mode is set
correctly,
regardless
of shift
mode.
0x01
Chip ID
8-bit chip ID[7:0], AD9634 = 0x87 (default)
0x87
Read only.
0x02 Chip grade Open Open Speed grade ID;
00 = 250 MSPS
01 = 210 MSPS
11 = 170 MSPS
Open Open Open Open Speed
grade ID
used to
differentiate
devices;
read only.
Transfer Register
0xFF Transfer Open Open Open Open Open Open Open Transfer 0x00 Synchro-
nously
transfers
data from
the master
shift
register to
the slave.
ADC Function Registers
0x08 Power modes Open Open Open Open Open Open Internal power-down mode
00 = normal operation
01 = full power-down
10 = standby
11 = reserved
0x00 Determines
various
generic
modes of
chip
operation.
0x09
Global clock
Open
Open
Open
Open
Open
Open
Open
Duty cycle
stabilizer
(default)
0x01
0x0B Clock divide Open Open Input clock divider phase adjust
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
0x00 Clock divide
values other
than 000
auto-
matically
cause the
duty cycle
stabilizer to
become
active.
0x0D Test mode Test mode
0 = contin-
uous/
repeat
pattern
1 = single
pattern
then zeros
Open Reset PN
long gen
Reset PN
short gen
Output test mode
0000 = off (default)
0001 = midscale short
0010 = positive FS
0011 = negative FS
0100 = alternating checkerboard
0101 = PN long sequence
0110 = PN short sequence
0111 = one/zero word toggle
1000 = user test mode
1001 to 1110 = unused
1111 = ramp output
0x00 When this
register is
set, the test
data is
placed on
the output
pins in
place of
normal
data.
0x10 Offset adjust Open Open Offset adjust in LSBs from +31 to −32
(twos complement format)
0x00
Rev. B | Page 27 of 30
AD9634 Data Sheet
Addr
(Hex)
Register
Name
Bit 7
(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Default
Notes/
Comments
0x14 Output mode Open Open Open Output
enable bar
0 = on
(default)
1 = off
Open Output
invert
0 = normal
(default)
1 =
inverted
Output format
00 = offset binary
01 = twos complement
(default)
10 = gray code
11 = reserved
0x01 Configures
the outputs
and the
format of
the data.
0x15 Output adjust Open Open Open Open LVDS output drive current adjust
0000 = 3.72 mA output drive current
0001 = 3.5 mA output drive current (default)
0010 = 3.30 mA output drive current
0011 = 2.96 mA output drive current
0100 = 2.82 mA output drive current
0101 = 2.57 mA output drive current
0110 = 2.27 mA output drive current
0111 = 2.0 mA output drive current (reduced range)
1000 to 1111 = reserved
0x01
0x16 Clock phase
control
Invert
DCO clock
Open Open Open Open Open Open Open 0x00
0x17 DCO output
delay
Enable
DCO
clock
delay
Open Open DCO clock delay
[delay = (3100 ps × register value/31 + 100)]
00000 = 100 ps
00001 = 200 ps
00010 = 300 ps
…
11110 = 3100 ps
11111 = 3200 ps
0x00
0x18 Input span
select
Open Open Open Full-scale input voltage selection
01111 = 2.087 V p-p
…
00001 = 1.772 V p-p
00000 = 1.75 V p-p (default)
11111 = 1.727 V p-p
…
10000 = 1.383 V p-p
0x00 Full-scale
input
adjustment
in 0.022 V
steps.
0x19 User Test
Pattern 1 LSB
User Test Pattern 1[7:0] 0x00
0x1A User Test
Pattern 1 MSB
User Test Pattern 1[15:8] 0x00
0x1B
User Test
Pattern 2 LSB
User Test Pattern 2[7:0]
0x00
0x1C User Test
Pattern 2 MSB
User Test Pattern 2[15:8] 0x00
0x1D
User Test
Pattern 3 LSB
User Test Pattern 3[7:0]
0x00
0x1E User Test
Pattern 3 MSB
User Test Pattern 3[15:8] 0x00
0x1F User Test
Pattern 4 LSB
User Test Pattern 4[7:0] 0x00
0x20 User Test
Pattern 4 MSB
User Test Pattern 4[15:8] 0x00
Rev. B | Page 28 of 30
Data Sheet AD9634
APPLICATIONS INFORMATION
DESIGN GUIDELINES
Before starting system-level design and layout of the AD9634, it
is recommended that the designer become familiar with these
guidelines, which describe the special circuit connections and
layout requirements needed for certain pins.
Power and Ground Recommendations
When connecting power to the AD9634, it is recommended that
two separate 1.8 V supplies be used: use one supply for analog
(AVDD) and a separate supply for digital outputs (DRVDD).
The designer can employ several different decoupling capacitors
to cover both high and low frequencies. Locate these capacitors
close to the point of entry at the PC board level and close to the
pins of the part with minimal trace length.
A single PCB ground plane should be sufficient when using the
AD9634. With proper decoupling and smart partitioning of the
PCB analog, digital, and clock sections, optimum performance
can be easily achieved.
Exposed Paddle Thermal Heat Slug Recommendations
It is mandatory that the exposed paddle on the underside of the
ADC be connected to analog ground (AGND) to achieve the
best electrical and thermal performance. A continuous, exposed
(no solder mask) copper plane on the PCB should be connected
to the AD9634 exposed paddle, Pin 0.
The copper plane should have several vias to achieve the lowest
possible resistive thermal path for heat dissipation to flow through
the bottom of the PCB. These vias should be filled or plugged with
nonconductive epoxy.
To maximize the coverage and adhesion between the ADC and
the PCB, overlay a silkscreen to partition the continuous plane on
the PCB into several uniform sections. This provides several tie
points between the ADC and the PCB during the reflow process.
Using one continuous plane with no partitions guarantees only one
tie point between the ADC and the PCB. See the evaluation
board for a PCB layout example. For detailed information about
the packaging and PCB layout of chip scale packages, refer to
the AN-772 Application Note, A Design and Manufacturing
Guide for the Lead Frame Chip Scale Package (LFCSP).
VCM
Decouple the VCM pin to ground with a 0.1 µF capacitor, as
shown in Figure 48.
SPI Port
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK, CSB, and SDIO signals are typically asynchronous to the
ADC clock, noise from these signals can degrade converter
performance. If the on-board SPI bus is used for other devices,
it may be necessary to provide buffers between this bus and the
AD9634 to keep these signals from transitioning at the converter
input pins during critical sampling periods.
Rev. B | Page 29 of 30
UUUUUUUU 3 3 z 3 3 c 3 c 3 c 3 c , 3 g , nnnnnnnn‘ -‘ ‘4 "‘L ‘ ‘ fl 57 Tr mm 1 71m 4 Analug Devkes, um. All lights vexevvedv Tvidtmavks and
AD9634 Data Sheet
OUTLINE DIMENSIONS
08-16-2010-B
1
0.50
BSC
BOTTOM VIEWTOP VIEW
PIN 1
INDICATOR 32
9
16
17
24
25
8
EXPOSED
PAD
PIN 1
INDICATOR
SEATING
PLANE
0.05 MAX
0.02 NOM
0.20 REF
COPLANARITY
0.08
0.30
0.25
0.18
5.10
5.00 SQ
4.90
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.50
0.40
0.30
0.25 MIN
*3.75
3.60 SQ
3.55
*COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5
WITH THE EXCEPTION OF THE EXPOSED PAD DIMENSION.
Figure 59. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
5 mm × 5 mm Body, Very Very Thin Quad
(CP-32-12)
Dimensions shown in millimeters
ORDERING GUIDE
Model
1
Temperature Range
Package Description
Package Option
AD9634BCPZ-250 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12
AD9634BCPZRL7-250 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12
AD9634BCPZ-210 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12
AD9634BCPZRL7-210 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12
AD9634BCPZ-170 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12
AD9634BCPZRL7-170 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12
AD9634-170EBZ Evaluation Board with AD9634 and Software
AD9634-210EBZ
Evaluation Board with AD9634 and Software
AD9634-250EBZ Evaluation Board with AD9634 and Software
1 Z = RoHS Compliant Part.
©2011–2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09996-0-12/14(B)
Rev. B | Page 30 of 30

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