MT41K_512M4,256M8,128M16 Datasheet by Micron Technology Inc.
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1.35V DDR3L SDRAM Addendum
MT41K512M4 – 64 Meg x 4 x 8 banks
MT41K256M8 – 32 Meg x 8 x 8 banks
MT41K128M16 – 16 Meg x 16 x 8 banks
Description
DDR3L SDRAM (1.35V) is a low voltage version of the
DDR3 SDRAM (1.5V). Unless stated otherwise, DDR3L
SDRAM meet the functional and timing specifications
listed in the equivalent density DDR3 SDRAM data
sheet located on www.micron.com.
Features
•VDD = VDDQ = +1.35V (1.283V to 1.45V)
•Backward-compatible to VDD = VDDQ = +1.5V ±0.075V
•Differential bidirectional data strobe
•8n-bit prefetch architecture
•Differential clock inputs (CK, CK#)
•8 internal banks
•Nominal and dynamic on-die termination (ODT)
for data, strobe, and mask signals
•Programmable CAS (READ) latency (CL)
•Programmable posted CAS additive latency (AL)
•Programmable CAS (WRITE) latency (CWL)
•Fixed burst length (BL) of 8 and burst chop (BC) of 4
(via the mode register set [MRS])
•Selectable BC4 or BL8 on-the-fly (OTF)
•Self refresh mode
•TC of 0°C to +95°C
–64ms, 8192-cycle refresh at 0°C to +85°C
–32ms at +85°C to +95°C
•Self refresh temperature (SRT)
•Automatic self refresh (ASR)
•Write leveling
•Multipurpose register
•Output driver calibration
Options Marking
•Configuration
–512 Meg x 4 512M4
–256 Meg x 8 256M8
–128 Meg x 16 128M16
•FBGA package (Pb-free) – x4, x8
–78-ball (8mm x 10.5mm) Rev. H, M DA
–78-ball FBGA (9mm x 11.5mm) Rev. D HX
•FBGA package (Pb-free) – x16
–96-ball FBGA (9mm x 14mm) Rev. D HA
•Timing – cycle time
–1.25ns @ CL = 11 (DDR3-1600) -125
–1.5ns @ CL = 9 (DDR3-1333) -15E
–1.875ns @ CL = 7 (DDR3-1066) -187E
•Revision :D/ :H/ :M
Table 1: Key Timing Parameters
Speed Grade Data Rate (MT/s) Target tRCD-tRP-CL tRCD (ns) tRP (ns) CL (ns)
-1251, 2 1600 11-11-11 13.75 13.75 13.75
-15E11333 9-9-9 13.5 13.5 13.5
-187E 1066 7-7-7 13.1 13.1 13.1
Notes: 1. Backward compatible to 1066, CL = 7 (-187E).
2. Backward compatible to 1333, CL = 9 (-15E).
2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Description
PDF: 09005aef83ed2952
2Gb_1_35V_DDR3L.pdf - Rev. E 1/11 EN 1Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
Table 2: Addressing
Parameter 512 Meg x 4 256 Meg x 8 128 Meg x 16
Configuration 64 Meg x 4 x 8 banks 32 Meg x 8 x 8 banks 16 Meg x 16 x 8 banks
Refresh count 8K 8K 8K
Row address 32K A[14:0] 32K A[14:0] 16K A[13:0]
Bank address 8 BA[2:0] 8 BA[2:0] 8 BA[2:0]
Column address 2K A[11, 9:0] 1K A[9:0] 1K A[9:0]
2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Description
PDF: 09005aef83ed2952
2Gb_1_35V_DDR3L.pdf - Rev. E 1/11 EN 2Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
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Ball Assignments and Descriptions
Figure 1: 78-Ball FBGA – x4, x8 Ball Assignments (Top View)
1 2 3 4 6 7 8 95
VSS
VSS
VDDQ
VSSQ
VREFDQ
NC
ODT
NC
VSS
VDD
VSS
VDD
VSS
VDD
VSSQ
DQ2
NF, DQ6
VDDQ
VSS
VDD
CS#
BA0
A3
A5
A7
RESET#
NC
DQ0
DQS
DQS#
NF, DQ4
RAS#
CAS#
WE#
BA2
A0
A2
A9
A13
NF, NF/TDQS#
DM, DM/TDQS
DQ1
VDD
NF, DQ7
CK
CK#
A10/AP
NC
A12/BC#
A1
A11
A14
VDD
VDDQ
VSSQ
VSSQ
VDDQ
NC
CKE
NC
VSS
VDD
VSS
VDD
VSS
VSS
VSSQ
DQ3
VSS
NF, DQ5
VSS
VDD
ZQ
VREFCA
BA1
A4
A6
A8
A
B
C
D
E
F
G
H
J
K
L
M
N
Notes: 1. Ball descriptions listed in Table 3 (page 5) are listed as “x4, x8” if unique; otherwise,
x4 and x8 are the same.
2. A comma separates the configuration; a slash defines a selectable function.
Example: D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies
to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are de-
fined in Table 3).
2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Ball Assignments and Descriptions
PDF: 09005aef83ed2952
2Gb_1_35V_DDR3L.pdf - Rev. E 1/11 EN 3Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
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Figure 2: 96-Ball FBGA – x16 Ball Assignments (Top View)
1 2 3 4 6 7 8 95
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
VDDQ
VSSQ
VDDQ
VSSQ
VSS
VDDQ
VSSQ
VREFDQ
NC
ODT
NC
VSS
VDD
VSS
VDD
VSS
DQ13
VDD
DQ11
VDDQ
VSSQ
DQ2
DQ6
VDDQ
VSS
VDD
CS#
BA0
A3
A5
A7
RESET#
DQ15
VSS
DQ9
UDM
DQ0
LDQS
LDQS#
DQ4
RAS#
CAS#
WE#
BA2
A0
A2
A9
A13
DQ12
UDQS#
UDQS
DQ8
LDM
DQ1
VDD
DQ7
CK
CK#
A10/AP
NC
A12/BC#
A1
A11
NC
VDDQ
DQ14
DQ10
VSSQ
VSSQ
DQ3
VSS
DQ5
VSS
VDD
ZQ
VREFCA
BA1
A4
A6
A8
VSS
VSSQ
VDDQ
VDD
VDDQ
VSSQ
VSSQ
VDDQ
NC
CKE
NC
VSS
VDD
VSS
VDD
VSS
Notes: 1. Ball descriptions listed in Table 4 (page 7) are listed as “x16.”
2. A comma separates the configuration; a slash defines a selectable function.
2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Ball Assignments and Descriptions
PDF: 09005aef83ed2952
2Gb_1_35V_DDR3L.pdf - Rev. E 1/11 EN 4Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions
Symbol Type Description
A[9:0], A10/AP,
A11, A12/BC#,
A[14:13]
Input Address inputs: Provide the row address for ACTIVATE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 sampled during a PRECHARGE com-
mand determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected
by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a
LOAD MODE command. Address inputs are referenced to VREFCA. A12/BC#: When enabled
in the mode register (MR), A12 is sampled during READ and WRITE commands to deter-
mine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop,
LOW = BC4 burst chop).
BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or
PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1,
MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to
VREFCA.
CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#. Out-
put data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.
CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal cir-
cuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is depend-
ent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW
provides PRECHARGE power-down and SELF REFRESH operations (all banks idle) or active
power-down (row active in any bank). CKE is synchronous for power-down entry and exit
and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (exclud-
ing CK, CK#, CKE, RESET#, and ODT) are disabled during power-down. Input buffers
(excluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to
VREFCA.
CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when CS# is registered HIGH. CS# provides for exter-
nal rank selection on systems with multiple ranks. CS# is considered part of the command
code. CS# is referenced to VREFCA.
DM Input Input data mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH along with the input data during a write access. Although the DM
ball is input-only, the DM loading is designed to match that of the DQ and DQS balls. DM
is referenced to VREFDQ. DM has an optional use as TDQS on the x8 device.
ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW) ter-
mination resistance internal to the DDR3 SDRAM. When enabled in normal operation,
ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM for the
x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the
LOAD MODE command. ODT is referenced to VREFCA.
RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being
entered and are referenced to VREFCA.
RESET# Input Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input
receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDDQ and DC
LOW ≤ 0.2 × VDDQ. RESET# assertion and deassertion are asynchronous.
DQ[3:0] I/O Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:0] are refer-
enced to VREFDQ.
2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Ball Assignments and Descriptions
PDF: 09005aef83ed2952
2Gb_1_35V_DDR3L.pdf - Rev. E 1/11 EN 5Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions (Continued)
Symbol Type Description
DQ[7:0] I/O Data input/output: Bidirectional data bus for the x8 configuration. DQ[7:0] are refer-
enced to VREFDQ.
DQS, DQS# I/O Data strobe: Output with read data. Edge-aligned with read data. Input with write da-
ta. Center-aligned to write data.
TDQS, TDQS# I/O Termination data strobe: Applies to the x8 configuration only. When TDQS is enabled,
DM is disabled, and the TDQS and TDQS# balls provide termination resistance.
VDD Supply Power supply: 1.35V, 1.283V to 1.45V operational; compatible to 1.5V operation.
VDDQ Supply DQ power supply: 1.35V, 1.283V to 1.45V operational; compatible with 1.5V operation.
VREFCA Supply Reference voltage for control, command, and address: VREFCA must be maintained
at all times (including self refresh) for proper device operation.
VREFDQ Supply Reference voltage for data: VREFDQ must be maintained at all times (including self re-
fresh) for proper device operation.
VSS Supply Ground.
VSSQ Supply DQ ground: Isolated on the device for improved noise immunity.
ZQ Reference External reference ball for output drive calibration: This ball is tied to an external
240Ω resistor (RZQ), which is tied to VSSQ.
NC –No connect: These balls should be left unconnected (the ball has no connection to the
DRAM or to other balls).
NF –No function: When configured as a x4 device, these balls are NF. When configured as a
x8 device, these balls are defined as TDQS#, DQ[7:4].
2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Ball Assignments and Descriptions
PDF: 09005aef83ed2952
2Gb_1_35V_DDR3L.pdf - Rev. E 1/11 EN 6Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
Table 4: 96-Ball FBGA – x16 Ball Descriptions
Symbol Type Description
A[9:0], A10/AP,
A11, A12/BC#, A13
Input Address inputs: Provide the row address for ACTIVATE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 sampled during a PRECHARGE com-
mand determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected
by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a
LOAD MODE command. Address inputs are referenced to VREFCA. A12/BC#: When enabled
in the mode register (MR), A12 is sampled during READ and WRITE commands to deter-
mine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop,
LOW = BC4 burst chop).
BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or
PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1,
MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to
VREFCA.
CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#. Out-
put data strobe (LDQS, LDQS#, UDQS, UDQS#) is referenced to the crossings of CK and CK#.
CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal cir-
cuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is depend-
ent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW
provides PRECHARGE power-down and SELF REFRESH operations (all banks idle) or active
power-down (row active in any bank). CKE is synchronous for power-down entry and exit
and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (exclud-
ing CK, CK#, CKE, RESET#, and ODT) are disabled during power-down. Input buffers
(excluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to
VREFCA.
CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when CS# is registered HIGH. CS# provides for exter-
nal rank selection on systems with multiple ranks. CS# is considered part of the command
code. CS# is referenced to VREFCA.
LDM Input Input data mask: LDM is a lower-byte, input mask signal for write data. Lower-byte in-
put data is masked when LDM is sampled HIGH along with the input data during a write
access. Although the LDM ball is input-only, the LDM loading is designed to match that
of the DQ and LDQS balls. LDM is referenced to VREFDQ.
ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW) ter-
mination resistance internal to the DDR3 SDRAM. When enabled in normal operation,
ODT is only applied to each of the following balls: DQ[15:0], LDQS, LDQS#, UDQS,
UDQS#, LDM, and UDM for the x16. The ODT input is ignored if disabled via the LOAD
MODE command. ODT is referenced to VREFCA.
RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being
entered and are referenced to VREFCA.
RESET# Input Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input
receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDDQ and DC
LOW ≤ 0.2 × VDDQ. RESET# assertion and deassertion are asynchronous.
2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Ball Assignments and Descriptions
PDF: 09005aef83ed2952
2Gb_1_35V_DDR3L.pdf - Rev. E 1/11 EN 7Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
Table 4: 96-Ball FBGA – x16 Ball Descriptions (Continued)
Symbol Type Description
UDM Input Input data mask: UDM is an upper-byte, input mask signal for write data. Upper-byte
input data is masked when UDM is sampled HIGH along with the input data during a
write access. Although the UDM ball is input-only, the UDM loading is designed to match
that of the DQ and UDQS balls. UDM is referenced to VREFDQ.
DQ[7:0] I/O Data input/output: Lower byte of bidirectional data bus for the x16 configuration.
DQ[7:0] are referenced to VREFDQ.
DQ[15:8] I/O Data input/output: Upper byte of bidirectional data bus for the x16 configuration.
DQ[15:8] are referenced to VREFDQ.
LDQS, LDQS# I/O Lower byte data strobe: Output with read data. Edge-aligned with read data. Input
with write data. LDQS is center-aligned to write data.
UDQS, UDQS# I/O Upper byte data strobe: Output with read data. Edge-aligned with read data. Input
with write data. UDQS is center-aligned to write data.
VDD Supply Power supply: 1.35V, 1.283V to 1.45V operational; compatible to 1.5V operation.
VDDQ Supply DQ power supply: 1.35V, 1.283V to 1.45V operational; compatible with 1.5V operation.
VREFCA Supply Reference voltage for control, command, and address: VREFCA must be maintained
at all times (including self refresh) for proper device operation.
VREFDQ Supply Reference voltage for data: VREFDQ must be maintained at all times (including self re-
fresh) for proper device operation.
VSS Supply Ground.
VSSQ Supply DQ ground: Isolated on the device for improved noise immunity.
ZQ Reference External reference ball for output drive calibration: This ball is tied to an external
240Ω resistor (RZQ), which is tied to VSSQ.
NC –No connect: These balls should be left unconnected (the ball has no connection to the
DRAM or to other balls).
2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Ball Assignments and Descriptions
PDF: 09005aef83ed2952
2Gb_1_35V_DDR3L.pdf - Rev. E 1/11 EN 8Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
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<.7 a4-="" «447="" 44»="">Package Dimensions
Figure 3: 78-Ball FBGA – x4, x8 (DA)
Ball A1 ID
1.2 MAX
0.25 MIN
8 ±0.1
Ball A1 ID
78X Ø0.45
Solder ball material:
SAC305 (96.5% Sn,
3% Ag, 0.5% Cu).
Dimensions apply to
solder balls post-reflow
on Ø0.35 SMD ball
pads.
0.8 TYP
0.8 TYP
9.6 CTR 10.5 ±0.1
0.8 ±0.05
0.155
1.8 CTR
Nonconductive overmold
0.12 A A
Seating
Plane
6.4 CTR
9 8 7 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
Note: 1. All dimensions are in millimeters.
2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Package Dimensions
PDF: 09005aef83ed2952
2Gb_1_35V_DDR3L.pdf - Rev. E 1/11 EN 9Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
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Figure 4: 78-Ball FBGA – x4, x8; Die Rev. D (HX)
0.8 TYP
9.6 CTR
11.5 ±0.1
0.8 TYP
6.4 CTR
9 ±0.1
Ball A1 ID
Ball A1 ID
A
B
C
D
E
F
G
H
J
K
L
M
N
123789
78X Ø0.45
Dimensions
apply to solder
balls post-reflow
on Ø0.35 SMD
ball pads.
A 0.12 A
Seating plane
1.1 ±0.1
0.25 MIN
1.8 CTR
Nonconductive
overmold
0.155
Notes: 1. All dimensions are in millimeters.
2. Solder ball material: SAC305 (96.5% SN, 3% Ag, 0.5% Cu).
2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Package Dimensions
PDF: 09005aef83ed2952
2Gb_1_35V_DDR3L.pdf - Rev. E 1/11 EN 10 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
V H
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Figure 5: 96-Ball FBGA – x16; Die Rev. D (HA)
Ball A1 ID
Seating
plane
0.8 ±0.1
Solder ball
material: SAC305.
Dimensions
apply to solder
balls post-reflow
on Ø0.35 SMD
ball pads.
0.12 AA
14 ±0.15
0.8 TYP
1.2 MAX
12 CTR
Ball A1 ID
0.8 TYP
9 ±0.15
0.25 MIN6.4 CTR
96X Ø0.45
9 8 7 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Note: 1. All dimensions are in millimeters.
2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Package Dimensions
PDF: 09005aef83ed2952
2Gb_1_35V_DDR3L.pdf - Rev. E 1/11 EN 11 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
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Electrical Characteristics – IDD Specifications
Table 5: IDD Maximum Limits – Rev. D
Speed Bin
DDR3L-800 DDR3L-1066 DDR3L-1333 UnitsIDD Width
IDD0 x4, 8 70 75 85 mA
x16 85 90 100 mA
IDD1 x4, 8 92 95 100 mA
x16 122 125 130 mA
IDD2P0 All 12 12 12 mA
IDD2P1 x4, 8 22 25 30 mA
x16 27 30 35 mA
IDD2Q All 27 30 35 mA
IDD2N All 28 32 37 mA
IDD2NT x4, 8 37 40 45 mA
x16 52 55 60 mA
IDD3P x4, 8 27 30 35 mA
x16 32 35 40 mA
IDD3N All 32 35 40 mA
IDD4R x4 110 125 145 mA
x8 125 140 160 mA
x16 160 200 245 mA
IDD4W x4 120 135 155 mA
x8 130 145 165 mA
x16 170 210 255 mA
IDD5B All 185 190 200 mA
IDD6 All 12 12 12 mA
IDD6ET All 15 15 15 mA
IDD7 x4, 8 290 335 385 mA
x16 330 375 425 mA
IDD8 All IDD2P0 + 2mA IDD2P0 + 2mA IDD2P0 + 2mA mA
2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Electrical Characteristics – IDD Specifications
PDF: 09005aef83ed2952
2Gb_1_35V_DDR3L.pdf - Rev. E 1/11 EN 12 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
flcron' LSD D
Table 6: IDD Maximum Limits – Die Rev H
Speed Bin
DDR3L-1066 DDR3L-1333 DDR3L-1600 UnitIDD Width
IDD0 x4, 8 65 70 75 mA
IDD1 x4, 8 85 90 95 mA
IDD2P0 (Slow) x4, 8 12 12 12 mA
IDD2P1 (Fast) x4, 8 27 32 37 mA
IDD2Q x4, 8 32 37 42 mA
IDD2N x4, 8 34 38 43 mA
IDD2NT x4, 8 42 47 52 mA
IDD3P x4, 8 37 42 47 mA
IDD3N x4, 8 42 47 52 mA
IDD4R x4 110 125 140 mA
x8 125 140 155 mA
IDD4W x4 110 125 140 mA
x8 125 140 155 mA
IDD5B x4, 8 180 185 190 mA
IDD6 x4, 8 12 12 12 mA
IDD6ET x4, 8 15 15 15 mA
IDD7 x4, 8 225 240 255 mA
IDD8 x4, 8 IDD2P0 + 2mA IDD2P0 + 2mA IDD2P0 + 2mA mA
2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Electrical Characteristics – IDD Specifications
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flcron' LSD D
Table 7: IDD Maximum Limits – Die Rev M
Speed Bin
DDR3L-1066 DDR3L-1333 DDR3L-1600 UnitIDD Width
IDD0 x4, 8 50 55 60 mA
IDD1 x4, 8 65 70 75 mA
IDD2P0 (Slow) x4, 8 12 12 12 mA
IDD2P1 (Fast) x4, 8 23 28 33 mA
IDD2Q x4, 8 23 28 33 mA
IDD2N x4, 8 25 30 35 mA
IDD2NT x4, 8 30 35 40 mA
IDD3P x4, 8 37 42 47 mA
IDD3N x4, 8 42 47 52 mA
IDD4R x4 95 110 125 mA
x8 110 125 140 mA
IDD4W x4 85 100 115 mA
x8 95 110 125 mA
IDD5B x4, 8 180 185 190 mA
IDD6 x4, 8 12 12 12 mA
IDD6ET x4, 8 15 15 15 mA
IDD7 x4, 8 190 205 220 mA
IDD8 x4, 8 IDD2P0 + 2mA IDD2P0 + 2mA IDD2P0 + 2mA mA
2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Electrical Characteristics – IDD Specifications
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A}? cron‘
Gray-shaded (eHs have the same va‘ues as those m the 1.5V DDR3 data sheet
AH voueges are referented m vSS
AH voueges are referented m vSS
Electrical Specifications
Table 8: Input/Output Capacitance
Gray-shaded cells have the same values as those in the 1.5V DDR3 data sheet
Capacitance Parame-
ters Symbol
DDR3L-800 DDR3L-1066 DDR3L-1333 DDR3L-1600 Unit
sMin Max Min Max Min Max Min Max
Single-end I/O: DQ, DM CIO 1.5 2.5 1.5 2.5 1.5 2.3 1.5 2.3 pF
Differential I/O: DQS,
DQS#, TDQS, TDQS#
CIO 1.5 2.5 1.5 2.5 1.5 2.3 1.5 2.3 pF
Inputs (CTRL,
CMD,ADDR)
CI0.75 1.3 0.75 1.3 0.75 1.3 0.75 1.3 pF
Table 9: DC Electrical Characteristics and Operating Conditions – 1.35V Operation
All voltages are referenced to VSS
Parameter/Condition Symbol Min Nom Max Units Notes
Supply voltage VDD 1.283 1.35 1.45 V 1, 2, 3, 4
I/O supply voltage VDDQ 1.283 1.35 1.45 V 1, 2, 3, 4
Notes: 1. Maximum DC value may not be greater than 1.425V. The DC value is the linear average
of VDD/VDDQ(t) over a very long period of time (e.g., 1 sec).
2. If the maximum limit is exceeded, input levels shall be governed by DDR3 specifications.
3. Under these supply voltages, the device operates to this DDR3L specification.
4. Once initialized for DDR3L operation, DDR3 operation may only be used if the device is
in reset while VDD and VDDQ are changed for DDR3 operation (see Figure 6 (page 23)).
Table 10: DC Electrical Characteristics and Operating Conditions – 1.5V Operation
All voltages are referenced to VSS
Parameter/Condition Symbol Min Nom Max Units Notes
Supply voltage VDD 1.425 1.5 1.575 V 1, 2, 3
I/O supply voltage VDDQ 1.425 1.5 1.575 V 1, 2, 3
Notes: 1. If the minimum limit is exceeded, input levels shall be governed by DDR3L specifications.
2. Under 1.5V operation, this DDR3L device operates in accordance with the DDR3 specifica-
tions under the same speed timings as defined for this device.
3. Once initialized for DDR3 operation, DDR3L operation may only be used if the device is
in reset while VDD and VDDQ are changed for DDR3L operation (see Figure 6 (page 23)).
Table 11: Input Switching Conditions – Command and Address
Parameter/Condition Symbol DDR3L-800/1066 DDR3L-1333/1600 Units
Input high AC voltage: Logic 1 VIH(AC160)min 160 160 mV
Input high AC voltage: Logic 1 VIH(AC135)min 135 135 mV
Input high DC voltage: Logic 1 VIH(DC90)min 90 90 mV
Input low AC voltage: Logic 0 VIL(AC160)min –160 –160 mV
Input low AC voltage: Logic 0 VIL(AC135)min –135 –135 mV
2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Electrical Specifications
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Table 11: Input Switching Conditions – Command and Address (Continued)
Parameter/Condition Symbol DDR3L-800/1066 DDR3L-1333/1600 Units
Input low DC voltage: Logic 0 VIL(DC90)min –90 –90 mV
Table 12: Input Switching Conditions – DQ and DM
Parameter/Condition Symbol DDR3L-800/1066 DDR3L-1333/1600 Units
Input high AC voltage: Logic 1 VIH(AC160)min 160 –mV
Input high AC voltage: Logic 1 VIH(AC135)min 135 135 mV
Input high DC voltage: Logic 1 VIH(DC90)min 90 90 mV
Input low AC voltage: Logic 0 VIL(AC160)min –160 –mV
Input low AC voltage: Logic 0 VIL(AC135)min –135 –135 mV
Input low DC voltage: Logic 0 VIL(DC90)min –90 –90 mV
Table 13: Differential Input Operating Conditions (CK, CK# and DQS, DQS#)
Parameter/Condition Symbol Min Max Units
Differential input logic high – slew VIH,diff(AC)slew 180 N/A mV
Differential input logic low – slew VIL,diff(AC)slew N/A –180 mV
Differential input logic high VIH,diff(AC) 2 × (VIH(AC) - VREF) VDD/VDDQ mV
Differential input logic low VIL,diff(AC) VSS/VSSQ 2 × (VREF - VIL(AC)) mV
Single-ended high level for strobes VSEH VDDQ/2 + 160 VDDQ mV
Single-ended high level for CK, CK# VDD/2 + 160 VDD mV
Single-ended low level for strobes VSEL VSSQ VDDQ/2 - 160 mV
Single-ended low level for CK, CK# VSS VDD/2 - 160 mV
Table 14: Required Time tDVAC for CK/CK#, DQS/DQS# Differential for AC Ringback
Slew Rate (V/ns) tDVAC at 320mV (ps) tDVAC at 270mV (ps)
>4.0 70 209
4.0 53 198
3.0 47 194
2.0 35 186
1.8 31 184
1.6 26 181
1.4 20 177
1.2 12 171
1.0 0 164
<1.0 0 164
2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Electrical Specifications
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(9’ crew
Gra -shaded (eHs have the same va‘ues as those m the 1.5V DDR3 data sheet
Table 15: RTT Effective Impedance
Gray-shaded cells have the same values as those in the 1.5V DDR3 data sheet
MR1
[9, 6, 2] RTT Resistor VOUT Min Nom Max Units
0, 1, 0 120Ω RTT,120PD240 0.2 × VDDQ 0.6 1.0 1.15 RZQ/1
0.5 × VDDQ 0.9 1.0 1.15 RZQ/1
0.8 × VDDQ 0.9 1.0 1.45 RZQ/1
RTT,120PU240 0.2 × VDDQ 0.9 1.0 1.45 RZQ/1
0.5 × VDDQ 0.9 1.0 1.15 RZQ/1
0.8 × VDDQ 0.6 1.0 1.15 RZQ/1
120Ω VIL(AC) to VIH(AC) 0.9 1.0 1.65 RZQ/2
0, 0, 1 60Ω RTT,60PD120 0.2 × VDDQ 0.6 1.0 1.15 RZQ/2
0.5 × VDDQ 0.9 1.0 1.15 RZQ/2
0.8 × VDDQ 0.9 1.0 1.45 RZQ/2
RTT,60PU120 0.2 × VDDQ 0.9 1.0 1.45 RZQ/2
0.5 × VDDQ 0.9 1.0 1.15 RZQ/2
0.8 × VDDQ 0.6 1.0 1.15 RZQ/2
60Ω VIL(AC) to VIH(AC) 0.9 1.0 1.65 RZQ/4
0, 1, 1 40Ω RTT,40PD80 0.2 × VDDQ 0.6 1.0 1.15 RZQ/3
0.5 × VDDQ 0.9 1.0 1.15 RZQ/3
0.8 × VDDQ 0.9 1.0 1.45 RZQ/3
RTT,40PU80 0.2 × VDDQ 0.9 1.0 1.45 RZQ/3
0.5 × VDDQ 0.9 1.0 1.15 RZQ/3
0.8 × VDDQ 0.6 1.0 1.15 RZQ/3
40Ω VIL(AC) to VIH(AC) 0.9 1.0 1.65 RZQ/6
1, 0, 1 30Ω RTT,30PD60 0.2 × VDDQ 0.6 1.0 1.15 RZQ/4
0.5 × VDDQ 0.9 1.0 1.15 RZQ/4
0.8 × VDDQ 0.9 1.0 1.45 RZQ/4
RTT,30PU60 0.2 × VDDQ 0.9 1.0 1.45 RZQ/4
0.5 × VDDQ 0.9 1.0 1.15 RZQ/4
0.8 × VDDQ 0.6 1.0 1.15 RZQ/4
30Ω VIL(AC) to VIH(AC) 0.9 1.0 1.65 RZQ/8
1, 0, 0 20Ω RTT,20PD40 0.2 × VDDQ 0.6 1.0 1.15 RZQ/6
0.5 × VDDQ 0.9 1.0 1.15 RZQ/6
0.8 × VDDQ 0.9 1.0 1.45 RZQ/6
RTT,20PU40 0.2 × VDDQ 0.9 1.0 1.45 RZQ/6
0.5 × VDDQ 0.9 1.0 1.15 RZQ/6
0.8 × VDDQ 0.6 1.0 1.15 RZQ/6
20Ω VIL(AC) to VIH(AC) 0.9 1.0 1.65 RZQ/12
2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Electrical Specifications
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(y cron'
Gra -shaded (eHs have the same va‘ues as those m the 1.5V DDR3 data sheet
Gra -shaded (eHs have the same va‘ues as those m the 1.5V DDR3 data sheet
Gra -shaded (eHs have the same va‘ues as those m the 1.5V DDR3 data sheet
Table 16: Reference Settings for ODT Timing Measurements
Gray-shaded cells have the same values as those in the 1.5V DDR3 data sheet
Measured
Parameter RTT,nom Setting RTT(WR) Setting VSW1 VSW2
tAON RZQ/4 (60Ω) N/A 50mV 100mv
RZQ/12 (20Ω) N/A 100mV 200mV
tAOF RZQ/4 (60Ω) N/A 50mV 100mv
RZQ/12 (20Ω) N/A 100mV 200mV
tAONPD RZQ/4 (60Ω) N/A 50mV 100mv
RZQ/12 (20Ω) N/A 100mV 200mV
tAOFPD RZQ/4 (60Ω) N/A 50mV 100mv
RZQ/12 (20Ω) N/A 100mV 200mV
tADC RZQ/12 (20Ω) RZQ/2 (20Ω) 200mV 250mV
Table 17: 34Ω Driver Impedance Characteristics
Gray-shaded cells have the same values as those in the 1.5V DDR3 data sheet
MR1
[5, 1] RON Resistor VOUT Min Nom Max1Units
0, 1 34.3Ω RON,34PD 0.2 × VDDQ 0.6 1.0 1.15 RZQ/7
0.5 × VDDQ 0.9 1.0 1.15 RZQ/7
0.8 × VDDQ 0.9 1.0 1.45 RZQ/7
RON,34PU 0.2 × VDDQ 0.9 1.0 1.45 RZQ/7
0.5 × VDDQ 0.9 1.0 1.15 RZQ/7
0.8 × VDDQ 0.6 1.0 1.15 RZQ/7
Pull-up/pull-down mismatch (MMPUPD) VIL(AC) to VIH(AC) –10 N/A 10 %
Note: 1. A larger maximum limit will result in slightly lower minimum currents.
Table 18: 40Ω Driver Impedance Characteristics
Gray-shaded cells have the same values as those in the 1.5V DDR3 data sheet
MR1
[5, 1] RON Resistor VOUT Min Nom Max1Units
0, 0 40Ω RON,40PD 0.2 × VDDQ 0.6 1.0 1.15 RZQ/6
0.5 × VDDQ 0.9 1.0 1.15 RZQ/6
0.8 × VDDQ 0.9 1.0 1.45 RZQ/6
RON,40PU 0.2 × VDDQ 0.9 1.0 1.45 RZQ/6
0.5 × VDDQ 0.9 1.0 1.15 RZQ/6
0.8 × VDDQ 0.6 1.0 1.15 RZQ/6
Pull-up/pull-down mismatch (MMPUPD) VIL(AC) to VIH(AC) –10 N/A 10 %
Note: 1. A larger maximum limit will result in slightly lower minimum currents.
2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Electrical Specifications
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A}? cron‘
Gray-shaded (eHs have the same va‘ues as those m the 1.5V DDR3 data sheet
Gray-shaded (eHs have the same va‘ues as those m the 1.5V DDR3 data sheet
Table 19: Single-Ended Output Driver Characteristics
Gray-shaded cells have the same values as those in the 1.5V DDR3 data sheet
Parameter/Condition Symbol Min Max Units
Output slew rate: Single-ended; For rising and falling
edges, measure between VOL(AC) = VREF - 0.09 × VDDQ
and VOH(AC) = VREF +0.09 × VDDQ
SRQse 1.75 6 V/ns
Table 20: Differential Output Driver Characteristics
Gray-shaded cells have the same values as those in the 1.5V DDR3 data sheet
Parameter/Condition Symbol Min Max Units
Output slew rate: Differential; For rising and falling
edges, measure between VOL,diff(AC) = –0.18 × VDDQ and
VOH,diff(AC) = +0.18 × VDDQ
SRQdiff 3.5 12 V/ns
Output differential crosspoint voltage VOX(AC) VREF - 135 VREF + 135 mV
Table 21: Electrical Characteristics and AC Operating Conditions
Parameter Symbol
DDR3L-800 DDR3L-1066 DDR3L-1333 DDR3L-1600
UnitsMin Max Min Max Min Max Min Max
DQ Input Timing
Data setup time
to DQS, DQS#
Base
(specification)
tDS
(AC160)
90 –40 –N/A –N/A –ps
VREF @ 1 V/ns 250 –200 –N/A –N/A –ps
Data setup time
to DQS, DQS#
Base
(specification)
tDS
(AC135)
140 –90 –45 –25 –ps
VREF @ 1 V/ns 275 –225 –180 –160 –ps
Data hold time
from DQS, DQS#
Base
(specification)
tDH
(DC90)
160 –110 –75 –55 –ps
VREF @ 1 V/ns 250 –200 –165 –145 –ps
Command and Address Timing
CTRL, CMD,
ADDR setup to
CK, CK#
Base
(specification)
tIS
(AC160)
215 –140 –80 –60 –ps
VREF @ 1 V/ns 375 –300 –240 –220 –ps
CTRL, CMD,
ADDR setup to
CK, CK#
Base
(specification)
tIS
(AC135)
365 –290 –205 –185 –ps
VREF @ 1 V/ns 500 –425 –340 –320 –ps
CTRL, CMD,
ADDR hold from
CK, CK#
Base
(specification)
tIH
(DC90)
285 –210 –150 –130 –ps
VREF @ 1 V/ns 375 –300 –240 –220 –ps
2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Electrical Specifications
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flcron'
Table 22: Derating Values for tIS/tIH – AC160/DC90-Based
ΔtIS, ΔtIH Derating (ps) – AC/DC-Based
CMD/ADDR
Slew Rate
V/ns
CK, CK# Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH
2.0 80 45 80 45 80 45 88 53 96 61 104 69 112 79 120 95
1.5 53 30 53 30 53 30 61 38 69 46 77 54 85 64 93 80
1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50
0.9 –1 –3 –1 –3 –1 –3 7 5 15 13 23 21 31 31 39 47
0.8 –3 –8 –3 –8 –3 –8 5 1 13 9 21 17 29 27 37 43
0.7 –5 –13 –5 –13 –5 –13 3 –5 11 3 19 11 27 21 35 37
0.6 –8 –20 –8 –20 –8 –20 0 –12 8 –4 16 4 24 14 32 30
0.5 –20 –30 –20 –30 –20 –30 –12 –22 –4 –14 4 –6 12 4 20 20
0.4 –40 –45 –40 –45 –40 –45 –32 –37 –24 –29 –16 –21 –8 –11 0 5
Table 23: Derating Values for tIS/tIH – AC135/DC90-Based
ΔtIS, ΔtIH Derating (ps) – AC/DC-Based
CMD/ADDR
Slew Rate
V/ns
CK, CK# Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH
2.0 68 45 68 45 45 45 76 53 84 61 92 69 100 79 108 95
1.5 45 30 45 30 30 30 53 38 61 46 69 54 77 64 85 80
1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50
0.9 2 –3 2 –3 2 –3 10 5 18 13 26 21 34 31 42 47
0.8 3 –8 3 –8 3 –8 11 1 19 9 27 17 35 27 43 43
0.7 6 –13 6 –13 6 –13 14 –5 22 3 30 11 38 21 46 37
0.6 9 –20 9 –20 9 –20 17 –12 25 –4 33 4 41 14 49 30
0.5 5 –30 5 –30 5 –30 13 –22 21 –14 29 –6 37 4 45 20
0.4 –3 –45 –3 –45 –3 –45 6 –37 14 –29 22 –21 30 –11 38 5
Table 24: Required Time tVAC Above VIH(AC) (Below VIL[AC]) for Valid ADD/CMD Transition
Slew Rate (V/ns) tVAC at 160mV (ps) tVAC at 135mV (ps)
>2.0 70 209
2.0 53 198
1.5 47 194
1.0 35 186
0.9 31 184
0.8 26 181
2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Electrical Specifications
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flcron'
Table 24: Required Time tVAC Above VIH(AC) (Below VIL[AC]) for Valid ADD/CMD Transition (Contin-
ued)
Slew Rate (V/ns) tVAC at 160mV (ps) tVAC at 135mV (ps)
0.7 20 177
0.6 12 171
0.5 0 164
<0.5 0 164
Table 25: Derating Values for tDS/tDH – AC160/DC90-Based
ΔtDS, ΔtDH Derating (ps) – AC/DC-Based
DQ Slew
Rate V/ns
DQS, DQS# Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH
2.0 80 45 80 45 80 45
1.5 53 30 53 30 53 30 61 38
1.0 0 0 0 0 0 0 8 8 16 16
0.9 –1 –3 –1 –3 7 5 15 13 23 21
0.8 –3 –8 5 1 13 9 21 17 29 27
0.7 –3 –5 11 3 19 11 27 21 35 37
0.6 8 –4 16 4 24 14 32 30
0.5 4 6 12 4 20 20
0.4 –8 –11 0 5
Table 26: Derating Values for tDS/tDH – AC135/DC90-Based
ΔtDS, ΔtDH Derating (ps) – AC/DC-Based
DQ Slew
Rate V/ns
DQS, DQS# Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH
2.0 68 45 68 45 68 45
1.5 45 30 45 30 45 30 53 38
1.0 0 0 0 0 0 0 8 8 16 16
0.9 2 –3 2 –3 10 5 18 13 26 21
0.8 3 –8 11 1 19 9 27 17 35 27
0.7 14 –5 22 3 30 11 38 21 46 37
0.6 25 –4 33 4 41 14 49 30
0.5 39 –6 37 4 45 20
0.4 30 –11 38 5
2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Electrical Specifications
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Table 27: Required Time tVAC Above VIH(AC) (Below VIL(AC)) for Valid DQTransition
Slew Rate (V/ns) tVAC at 160mV (ps) tVAC at 135mV (ps)
>2.0 70 109
2.0 53 98
1.5 47 94
1.0 35 86
0.9 31 84
0.8 26 81
0.7 20 77
0.6 12 71
0.5 0 64
<0.5 0 64
Initialization
If the SDRAM is powered up and initialized for the 1.35V operating voltage range, volt-
age can be increased to the 1.5V operating range provided that:
•Just prior to increasing the 1.35V operating voltages, no further commands are issued,
other than NOPs or COMMAND INHIBITs, and all banks are in the precharge state.
•The 1.5V operating voltages are stable prior to issuing new commands, other than
NOPs or COMMAND INHIBITs.
•The DLL is reset and relocked after the 1.5V operating voltages are stable and prior to
any READ command.
•The ZQ calibration is performed. tZQinit must be satisfied after the 1.5V operating vol-
tages are stable and prior to any READ command.
If the SDRAM is powered up and initialized for the 1.5V operating voltage range, voltage
can be reduced to the 1.35V operation range provided that:
•Just prior to reducing the 1.5V operating voltages, no further commands are issued,
other than NOPs or COMMAND INHIBITs, and all banks are in the precharge state.
•The 1.35V operating voltages are stable prior to issuing new commands, other than
NOPs or COMMAND INHIBITs.
•The DLL is reset and relocked after the 1.35V operating voltages are stable and prior
to any READ command.
•The ZQ calibration is performed. tZQinit must be satisfied after the 1.35V operating
voltages are stable and prior to any READ command.
2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Initialization
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a ; MW >4 m m m fibfifl
I, I, u .I .I m 2; “
VD
VDD Voltage Switching
After the DDR3L DRAM is powered up and initialized, the power supply can be altered
between the DDR3L and DDR3 levels, provided the sequence in Figure 6 is maintained.
Figure 6: VDD Voltage Switching
(
)(
)
(
)(
)
CKE
RTT
BA
(
)(
)
(
)(
)
CK, CK#
Command Note 1 Note 1
(
)(
)
(
)(
)
TdTc Tg
Don’t Care
(
)(
)
(
)(
)
(
)(
)
tIS
ODT
(
)(
)
(
)(
)
Th
tMRD tMOD
(
)(
)
(
)(
)
MRSMRS
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
tMRD tMRD
(
)(
)
(
)(
)
(
)(
)
(
)(
)
MRS
MR0MR1
MR3
MRS
MR2
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
Ti Tj Tk
(
)(
)
(
)(
)
RESET#
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
T = 500µs
(
)(
)
(
)(
)
(
)(
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Te
Ta Tb Tf
(
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(
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ZQCL
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(
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(
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tIS
Static LOW in case RTT,nom is enabled at time Tg, otherwise static HIGH or LOW
(
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(
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(
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)
(
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tIS tIS
tXPR
(
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(
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(
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)
(
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)
(
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)
(
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)
Time break
TMIN = 10ns
TMIN = 10ns
TMIN = 10ns
TMIN = 200µs
tCKSRX
VDD, VDDQ (DDR3)
(
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)
(
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)
tDLLK
(
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)
(
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)
(
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)
(
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)
tZQinit
(
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(
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)
(
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(
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(
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(
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(
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(
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(
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(
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(
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(
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(
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(
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(
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(
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(
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(
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(
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VDD, VDDQ (DDR3L)
(
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)
(
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(
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(
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(
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(
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(
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(
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(
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(
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(
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(
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(
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(
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(
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(
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(
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(
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Valid
Valid
Valid
Valid
(
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(
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(
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(
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(
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)
Note: 1. From time point Td until Tk, NOP or DES commands must be applied between MRS and
ZQCL commands.
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www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.
2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Initialization
PDF: 09005aef83ed2952
2Gb_1_35V_DDR3L.pdf - Rev. E 1/11 EN 23 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
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