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IEER Rectifier _
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IR2103(S)PBF
1
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© 2013 International Rectifier
April 18, 2013
Half-Bridge Driver
Features
Floating channel designed for bootstrap operation
Fully operational to +600V
Tolerant to negative transient voltage
dV/dt immune
Gate drive supply range from 10 to 20V
Undervoltage lockout
3.3V, 5V and 15V logic compatible
Cross-conduction prevention logic
Matched propagation delay for both channels
Internal set deadtime
High side output in phase with HIN input
Low side output out of phase with LIN input
Description
The IR2103(S) are high voltage, high speed power MOSFET and
IGBT drivers with dependent high and low side referenced output
channels. Proprietary HVIC and latch immune CMOS technologies
enable ruggedized monolithic construction. The logic input is
compatible with standard CMOS or LSTTL output, down to 3.3V
logic. The output drivers feature a high pulse current buffer stage
designed for minimum driver cross-conduction. The floating channel
can be used to drive an N-channel power MOSFET or IGBT in the
high side configuration which operates up to 600 volts.
Ordering Information
Product Summary
VOFFSET (max)
600V
IO+/-
130mA / 270mA
VOUT
10V – 20V
ton/off (typ.)
680 & 150 ns
Deadtime (typ.)
520 ns
Package Options
8 Lead SOIC 8 Lead PDIP
Base Part Number
Package Type
Standard Pack
Orderable Part Number
Form
Quantity
IR2103SPBF
SO8N
Tube
95
IR2103SPBF
IR2103SPBF
SO8N
Tape and Reel
2500
IR2103STRPBF
IR2103PBF
PDIP8
Tube
50
IR2103PBF
IEBR
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April 18, 2013
Table of Contents
Page
Description
1
Ordering Information
1
Typical Connection Diagram
3
Absolute Maximum Ratings
4
Recommended Operating Conditions
4
Dynamic Electrical Characteristics
5
Static Electrical Characteristics
5
Functional Block Diagrams
6
Lead Definitions
7
Lead Assignments
7
Application Information and Additional Details
8
Package Details: PDIP8, SO8N
15
Tape and Reel Details: SO8N
16
Part Marking Information
17
Qualification Information
18
TO
,, VCC VB ’
H'N - HIN HO
W H m Vs fl LOAD
COM Lo ,
\
[Reler In Lean Assignments for omen comgurallon) ThIsznese diagrams) snnw elecmca‘ connections only
Please refer lo our Apullmnon Notes and Deslgn'fius lorpvouer urcun board lax/0m
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Typical Connection Diagram
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Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are
measured under board mounted and still air conditions.
Symbol
Definition
Min.
Max.
Units
VB
High side floating absolute voltage
-0.3
625
V
VS
High side floating supply offset voltage
VB - 25
VB + 0.3
VHO
High side floating output voltage
VS - 0.3
VB + 0.3
VCC
Low side and logic fixed supply voltage
-0.3
25
VLO
Low side output voltage
-0.3
VCC + 0.3
VIN
Logic input voltage (HIN & LIN ¯¯¯)
-0.3
VCC + 0.3
dVS/dt
Allowable offset supply voltage transient
—
50
V/ns
PD
Package power dissipation
@ TA ≤ +25°C
8 lead PDIP
—
1
W
8 lead SOIC
—
0.625
RthJA
Thermal resistance, junction to
ambient
8 lead PDIP
—
125
°C/W
8 lead SOIC
—
200
TJ
Junction temperature
—
150
°C
TS
Storage temperature
-55
150
TL
Lead temperature (soldering, 10 seconds)
—
300
Recommended Operating Conditions
The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within
the recommended conditions. The VS offset rating is tested with all supplies biased at 15V differential.
Symbol
Definition
Min.
Max.
Units
VB
High side floating absolute voltage
VS + 10
VS + 20
V
VS
High side floating supply offset voltage
†
600
VHO
High side floating output voltage
VS
VB
VCC
Low side and logic fixed supply voltage
10
20
VLO
Low side output voltage
0
VCC
VIN
Logic input voltage (HIN & LIN)
0
VCC
TA
Ambient temperature
-40
125
°C
†
Logic operational for VS of -5 to +600V. Logic state held for VS of -5V to -VBS. (Please refer to the Design Tip DT97-3 for
more details).
VOH BIAS V0 lo
VOL 0 lo
ILK Va Vs
loss Vas VIN
loco Vcc VIN
hm W
IN N
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Dynamic Electrical Characteristics
VBIAS (VCC, VBS) = 15V, CL = 1000 pF and TA = 25°C unless otherwise specified.
Symbol
Definition
Min.
Typ.
Max.
Units
Test Conditions
ton
Turn-on propagation delay
—
680
820
ns
VS = 0V
toff
Turn-off propagation delay
—
150
220
VS = 600V
tr
Turn-on rise time
—
100
170
tf
Turn-off fall time
—
50
60
DT
Deadtime, LS turn-off to HS turn-on
& HS turn-on to LS turn-off
400
520
650
MT
Delay matching, HS & LS turn on/off
—
—
60
Static Electrical Characteristics
VBIAS (VCC, VBS) = 15V and TA = 25°C unless otherwise specified. The VIN, VTH, and IIN parameters are
referenced to COM. The VO and IO parameters are referenced to COM and are applicable to the respective
output leads: HO or LO.
Symbol
Definition
Min.
Typ.
Max.
Units
Test Conditions
VIH
Logic ―1‖ (HIN) & Logic ―0‖ ( LIN ¯¯¯)
input voltage
3
—
—
V
VCC = 10V to 20V
VIL
Logic ―0‖ (HIN) & Logic ―1‖ ( LIN ¯¯¯)
input voltage
—
—
0.8
VCC = 10V to 20V
VOH
High level output voltage VBIAS - VO
—
—
100
mV
IO = 0A
VOL
Low level output voltage, VO
—
—
100
IO = 0A
ILK
Offset supply leakage current
—
—
50
μA
VB = VS = 600V
IQBS
Quiescent VBS supply current
—
30
55
VIN = 0V or 5V
IQCC
Quiescent VCC supply current
150
270
VIN = 0V or 5V
IIN+
Logic ―1‖ input bias current
—
3
10
HIN = 5V, LIN ¯¯¯ =0V
IIN-
Logic ―0‖ input bias current
—
—
1
HIN = 0V, LIN ¯¯¯ =5V
VCCUV+
VCC supply undervoltage positive
going threshold
8
8.9
9.8
V
VCCUV-
VCC supply undervoltage negative
going threshold
7.4
8.2
9
IO+
Output high short circuit pulsed
current
130
210
—
mA
VO = 0V, VIN = VIH
PW ≤ 10 μs
IO-
Output low short circuit pulsed
current
270
360
—
VO = 15V , VIN = VIL
PW ≤ 10 μs
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6
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April 18, 2013
Functional Block Diagram
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7
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April 18, 2013
Lead Definitions
Symbol
Description
HIN
Logic input for high side gate driver output (HO), in phase
LIN ¯¯¯
Logic input for low side gate driver output (LO), out of phase
VB
High side floating supply
HO
High side gate drive output
VS
High side floating supply return
VCC
Low side and logic fixed supply
LO
Low side gate drive output
COM
Low side return
Lead Assignments
8
7
6
5
VCC VB
HIN
1
2
3
4
VS
HO
LO
LIN
COM
ISER _
W
HIN
90%
HO I I I LO
LO l'l
HIN
90%
HIN 50% 50%
m HO
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April 18, 2013
Application Information and Additional Details
Figure 1. Input/Output Timing Diagram
Figure 2. Switching Time Waveform Definitions
Figure 3. Deadtime Waveform Definitions
E
5
a)
g
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E
m
o
=
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z
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._
75C 725 C 25 ED 75 100 125
TemperatureC’C)
moo
Ma
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1..
E
: 600
E TYP
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C.’
E 200
._
o
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San
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> .
2 —.
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Em TY?
._
17
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VBIAS Supply Voltage (V)
Tum-On De1ay TlmE ms)
Turn-OW Delay Time (ms)
Turn-Off De1ay T1me (us
1400
1200
1000
800
600
400
200
ID 12 14 16 18 20
VBIAS Supp1y Vonage (V)
su
4M
an
Inc M
:u
725 i 25 su 75 IL“ 125
Temperature (‘01
1000
300
600
400
200
n 2 4 6 8 1o 12 14 1E 13 20
Inputvonage (V)
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9
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Figure 4A. Turn-On Time vs. Temperature
Figure 4B. Turn-On Time vs. Supply Voltage
Figure 4C. Turn-On Time vs. Input Voltage
Figure 5A. Turn-Off Time vs. Temperature
Figure 5B. Turn-Off Time vs. Supply Voltage
Figure 5C. Turn-Off Time vs. Input Voltage
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500
400
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400
200
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Temperature (”0)
Turn-On Rise Time (ns)
L0 12 14 16 18 20
VEIAS Suppry Voltage (V)
M3
Jun
50
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VBIAS Supply Vonage (V)
1400
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1000
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Deamrme (ns)
11 11 1 I 1 5 1 8 2C
VB‘AS Supply Voltage (V)
IR2103(S)PBF
10
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April 18, 2013
Figure 6A. Turn-On Rise Time vs. Temperature
Figure 6B. Turn-On Rise Time vs. Voltage
Figure 7A. Turn Off Fall Time vs. Temperature
Figure 7B. Turn Off Fall Time vs. Voltage
Figure 8A. Deadtime vs. Temperature
Figure 8B. Deadtime vs. Voltage
T 7
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m
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1 l
E I}
750 725 C 25 SD 75 10] 125 10 12 14 16 13 20
Temperature (°cl VB lAs Supply Voltage IV)
4 4
3 2 A 3.2
S a
m , w
E 1 a E 2.4
E E
> >
g. 1 E :i 16
5 Max 5 Max,
nae _____—_————— o_s_____—_—e———_——
C D
750 725 J 25 5] TS JED 125 10 12 1A 16 1E 20
Temperature co) Vcc Supply Voltage (V)
1 1
3 i
u 3.9 ma
3 E
= o
E a s g [1.6
55 §
8 :4 9 [1.4
— a:
n; >
S 3
g 3-2 may. I
a. ,7 ,i,,i,,i,i 9 ________
E I
I)
’50 ’2‘ 0 ZS 5n 7‘ 10( 125 10 12 14 16 18 20
Temperature (°cl Vc: Supply Voltage (V)
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11
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Figure 9A. Logic “1” ( HIN ¯¯¯) & Logic “0” ( LIN ¯¯¯) Input
Voltage vs. Temperature
Figure 9B. Logic “1” ( HIN ¯¯¯) & Logic “0” ( LIN ¯¯¯) Input
Voltage vs. Voltage
Figure 10A. Logic “0” ( HIN ¯¯¯)) & Logic “1” ( LIN ¯¯¯) Input
Voltage vs. Temperature
Figure 10B. Logic “0” (HIN) & Logic “1” (LIN) Input
Voltage vs. Voltage
Figure 11A. High Level Output vs. Temperature
Figure 11B. High Level Output vs. Voltage
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12
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Figure 12A. Low Level Output vs. Temperature
Figure 12B. Low Level Output vs. Voltage
Figure 13A. Offset Supply Current vs. Temperature
Figure 13B. Offset Supply Current vs. Voltage
Figure 14A. VBS Supply Current vs. Temperature
Figure 14B. VBS Supply Current vs. Voltage
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13
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Figure 15A. VCC Supply Current vs. Temperature
Figure 15B. VCC Supply Current vs. Voltage
Figure 16A. Logic “1” Input Current vs. Temperature
Figure 16B. Logic “1” Input Current vs. Voltage
Figure 17A. Logic “0” Input Current vs. Temperature
Figure 17B. Logic “0” Input Current vs. Voltage
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14
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Figure 18A. VCC Undervoltage Threshold (+) vs.
Temperature
Figure 18B. VCC Undervoltage Threshold (-) vs.
Temperature
Figure 19A. Output Source Current vs. Temperature
Figure 19B. Output Source Current vs. Voltage
Figure 20A. Output Sink Current vs. Temperature
Figure 20A. Output Sink Current vs. Voltage
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15
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April 18, 2013
Package Details: PDIP8, SO8N
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Tape and Reel Details: SO8N
CARRIER TAPE DIMENSION FOR 8SOICN
Code Min Max Min Max
A 7.90 8.10 0.311 0.318
B 3.90 4.10 0.153 0.161
C 11.70 12.30 0.46 0.484
D 5.45 5.55 0.214 0.218
E 6.30 6.50 0.248 0.255
F 5.10 5.30 0.200 0.208
G 1.50 n/a 0.059 n/a
H 1.50 1.60 0.059 0.062
REEL DIMENSIONS FOR 8SOICN
Code Min Max Min Max
A 329.60 330.25 12.976 13.001
B 20.95 21.45 0.824 0.844
C 12.80 13.20 0.503 0.519
D 1.95 2.45 0.767 0.096
E 98.00 102.00 3.858 4.015
F n/a 18.40 n/a 0.724
G 14.50 17.10 0.570 0.673
H 12.40 14.40 0.488 0.566
Metric
Imperial
Metric
Imperial
E
F
A
C
D
G
A
B
H
NOTE : CONTROLLING
DIMENSION IN MM
LOADED TAPE FEED DIRECTION
A
H
F
E
G
D
B
C
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Part Marking Information
IRxxxxx
IR logo
YWW ?
Part number
Date code
Pin 1
Identifier
Lot Code
(Prod mode –
4 digit SPN code)
Assembly site code
Per SCOP 200-002
? XXXX
MARKING CODE
Lead Free Released
Non-Lead Free Released
?
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Qualification Information†
Qualification Level
Industrial††
(per JEDEC JESD 47)
Comments: This family of ICs has passed JEDEC’s
Industrial qualification. IR’s Consumer qualification level is
granted by extension of the higher Industrial level.
Moisture Sensitivity Level
SOIC8N
MSL2†††
(per IPC/JEDEC J-STD 020)
PDIP8
Not applicable
(non-surface mount package style)
RoHS Compliant
Yes
†
Qualification standards can be found at International Rectifier’s web site http://www.irf.com/
††
Higher qualification ratings may be available should the user have such requirements. Please contact your
International Rectifier sales representative for further information.
†††
Higher MSL ratings may be available for the specific package types listed here. Please contact your
International Rectifier sales representative for further information.
The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no responsibility
for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of patents or of
other rights of third parties which may result from the use of this information. No license is granted by implication or otherwise under any
patent or patent rights of International Rectifier. The specifications mentioned in this document are subject to change without notice. This
document supersedes and replaces all information previously supplied.
For technical support, please contact IR’s Technical Assistance Center
http://www.irf.com/technical-info/
WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245
Tel: (310) 252-7105
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