March 2010 Doc ID 17326 Rev 1 1/56
56
L6717
High-efficiency hybrid AM2r2 controller
with I2C interface and embedded drivers
Features
■Hybrid controller for both PVI and SVI CPUs
■Dual controller with 2 embedded high current
drivers + 2 PWM for external driver for CPU
CORE and 1 embedded high current driver for
CPU NB
■Dynamic phase management (DPM)
■I2C interface to control offset, switching
frequency and power management options
■Dual-edge asynchronous architecture with LTB
technology®
■PSI management to increase efficiency in light-
load conditions
■Dual overcurrent protection: Total and per-
phase
■Accurate voltage positioning
■Dual remote sense
■Feedback disconnection protection
■Programmable OV protection
■Oscillator internally fixed at 200 kHz externally
adjustable
■LSLess startup to manage pre-biased output
■VFQFPN48 Package
Applications
■Hybrid high-current VRM / VRD for desktop /
Server / Workstation / IPC CPUs supporting
PVI and SVI interface
■High-density DC / DC converters
Description
L6717 is a hybrid CPU power supply controller
embedding 2 high-current drivers for the CORE
section and 1 driver for the NB section - requiring
up to 2 external drivers when the CORE section
works at 4 phase to optimize the application over-
all cost.
I2C interface allows to manage offset both CORE
and NB sections, switching frequency and
dynamic phase management saving in
component count, space and power consumption.
Dynamic phase management automatically
adjusts phase-count according to CPU load
optimizing the system efficiency under all load
conditions.
The dual-edge asynchronous architecture is
optimized by LTB technology® allowing fast load-
transient response minimizing the output
capacitor and reducing the total BOM cost.
Fast protection against load over current is
provided for both the sections. Feedback
disconnection protection prevents from damaging
the load in case of disconnections in the system
board.
L6717 is available in VFQFPN48 package.
VFQFPN48
VFQFPN48
Table 1. Device summary
Order codes Package Packing
L6717 VFQFPN48 Tray
L6717TR Tape and reel
www.st.com
Obsolete Product(s) - Obsolete Product(s)
Contents L6717
2/56 Doc ID 17326 Rev 1
Contents
1 Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 4
1.1 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4 Device description and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5 Hybrid CPU support and CPU_TYPE detection . . . . . . . . . . . . . . . . . . 19
5.1 PVI - parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2 PVI start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3 SVI - serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.4 SVI start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.4.1 Set VID command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.4.2 PWROK de-assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.4.3 PSI_L and efficiency optimization at light-load . . . . . . . . . . . . . . . . . . . 24
5.4.4 HiZ management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.4.5 Hardware jumper override - V_FIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6 Power manager I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1 Power manager commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1.1 Overspeeding command (OVRSPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1.2 Overvoltage threshold adjustment (OV_SET) . . . . . . . . . . . . . . . . . . . . 30
6.1.3 Switching frequency adjustment (FSW_ADJ) . . . . . . . . . . . . . . . . . . . . 30
6.1.4 Droop function adjustment (DRP_ADJ) . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.1.5 Power management flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.2 Dynamic phase management (DPM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Obsolete Product(s) - Obsolete Product(s)
L6717 Contents
Doc ID 17326 Rev 1 3/56
7 Output voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.1 CORE section - phase # programming . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.2 CORE section - current reading and current sharing loop . . . . . . . . . . . . 35
7.3 CORE section - defining load-line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.4 CORE section - analog offset (Optional - I2CDIS = 3.3 V) . . . . . . . . . . . . 37
7.5 NB section - current reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.6 NB section - defining load-line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.7 On-the-fly VID transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.8 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.8.1 LS-Less Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8 Output voltage monitoring and protections . . . . . . . . . . . . . . . . . . . . . 41
8.1 Programmable overvoltage (I2DIS = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . 41
8.2 Feedback disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.3 PWRGOOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.4 Overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.4.1 CORE section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.4.2 NB section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10 High current embedded drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.1 Boot capacitor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.2 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
11 System control loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
11.1 Compensation network guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
12 LTB Technology® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
13 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
13.1 Power components and connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
13.2 Small signal components and connections . . . . . . . . . . . . . . . . . . . . . . . 53
14 VFQFPN48 mechanical data and package dimensions . . . . . . . . . . . . 54
15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Obsolete Product(s) - Obsolete Product(s)
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Doc ID 17326 Flev 1
Typical application circuit and block diagram L6717
4/56 Doc ID 17326 Rev 1
1 Typical application circuit and block diagram
1.1 Application circuit
Figure 1. Typical 4+1 application circuit
HS1
LS1
L1
C
HF
C
BULK_IN
ST L6717 (4+1) Reference Schematic
HS2
LS2
L2
C
HF
C
OUT
PWM328
CS1P 15
CS1N 16
CS2P 17
CS3N20
CS3P19
C
MLCC
C
OUT_NB
C
MLCC_NB
PVI / SVID AM2 CPU
NB
CORE
L
IN
9
NB_FB
NB_COMP
10
FB
5
COMP
4
OSC / EN / FLT
14
VID1 / CORE_TYPE
33
VID3 / SVC
31 VID4 / I2C_DIS
30 VID5 / ADDRESS
29
PVI / SVID Bus
GND_PAD
VCC
2
VID2 / SVD
32
ST L6717
Hybrid PVID / SVID Controller
C
F
R
F
R
FB
C
F_NB
R
F_NB
R
FB_NB
R
OSC
R
G
R
G
R
C
R
C
R
C
BOOT
PWM
GND
LGATE
UGATE
VCC
L6743B
PHASE
34
1
35
VID0 / VFIX
PWROK
PWRGOOD
C
LTB
R
LTB
8 LTB
HS3
LS3
L3
R
C
VCC
BOOT
PWM
GND
LGATE
UGATE
L6743B
PHASE
HS4
LS4
L4
PWM4 27
CS4N 22
CS4P 21
R
G
R
G
18
C
HF
C
HF
HS_NB
LS_NB
L_NB
C
HF
23
R_NB
C_NB
R
G_NB
24
CS2N
NB_CSP
NB_CSN
UGATE1 47
PHASE1 46
LGATE1 45
UGATE2 40
PHASE2 41
LGATE2 44
NB_UGATE
37
NB_PHASE
38
NB_LGATE 43
6 VSEN
7 FBG
NB_VSEN
11
NB_FBG 12
VCCDRV
42
SDA / OVP
25
SCL / OS
26
NB_BOOT
36
BOOT1 48
BOOT2
39
49
SGND
3.3V
3.3V
3
SVI/PVI Interface
C
HF
Power Manager I2C
V
IN
C
HF
ILIM
R
ILIM
EN
EN
C
I
R
I
C
P
C
ILIM
5V SBY
Q_EN
EN 13
Obsolete Product(s) - Obsolete Product(s)
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5/56
Doc ID 17326 Flev 1
L6717 Typical application circuit and block diagram
Doc ID 17326 Rev 1 5/56
Figure 2. Typical 3+1 application circuit
HS1
LS1
L1
CHF
CBULK_IN
ST L6717 (3+1) Reference Schematic
HS2
LS2
L2
CHF
COUT
PWM328
CS1P 15
CS1N 16
CS2P 17
CS3N20
CS3P19
CMLCC
COUT_NB
CMLCC_NB
PVI / SVID AM2 CPU
NB
CORE
LIN
9
NB_FB
NB_COMP
10
FB
5
COMP
4
OSC / EN / FLT
14
VID1 / CORE_TYPE
33
VID3 / SVC
31 VID4 / I2C_DIS
30 VID5 / ADDRESS
29
PVI / SVID Bus
GND_PAD
VCC
2
VID2 / SVD
32
ST L6717
Hybrid PVID / SVID Controller
CF
RF
RFB
CF_NB RF_NB RFB_NB
RG
RG
R
C
R
C
R
C
BOOT
PWM
GND
LGATE
UGATE
VCC
L6743B
PHASE
34
1
35
VID0 / VFIX
PWROK
PWRGOOD
CLTB
RLTB
8 LTB
HS3
LS3
L3
PWM4 27
CS4N 22
CS4P 21
RG
RG
18
CHF
HS_NB
LS_NB
L_NB
CHF
23
R_NB
C_NB
RG_NB
24
CS2N
NB_CSP
NB_CSN
UGATE1 47
PHASE1 46
LGATE1 45
UGATE2 40
PHASE2 41
LGATE2 44
NB_UGATE
37
NB_PHASE
38
NB_LGATE 43
6 VSEN
7 FBG
NB_VSEN
11
NB_FBG 12
VCCDRV
42
SDA / OVP
25
SCL / OS
26
NB_BOOT
36
BOOT1 48
BOOT2
39
49
SGND
3.3V
3
SVI/PVI Interface
CHF
Power Manager I2C
CHF VIN
ILIM
EN
CI
RI
C
14
ROSC
RILIM
CILIM
5V SBY
Q_EN
EN 13
Obsolete Product(s) - Obsolete Product(s)
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Doc ID 17326 Flev 1
Typical application circuit and block diagram L6717
6/56 Doc ID 17326 Rev 1
Figure 3. Typical 2+1 application circuit
HS1
LS1
L1
CHF
CBULK_IN
ST L6717 (2+1) Re ference Schematic
HS2
LS2
L2
CHF
COUT
PWM328
CS1P 15
CS1N 16
CS2P 17
CS3N20
CS3P19
CMLCC
COUT_NB
CMLCC_NB
PVI / SVID AM2 CPU
NB
CORE
LIN
9
NB_FB
NB_COMP
10
FB
5
COMP
4
OSC / EN / FLT
14
VID1 / CORE_TYPE
33
VID3 / SVC
31 VID4 / I2C_DIS
30 VID5 / ADDRESS
29
PVI / SVID Bus
GND_PAD
VCC
2
VID2 / SVD
32
ST L6717
Hybrid PVID / SVID Controller
CF
RF
RFB
CF_NB RF_NB RFB_NB
RG
RG
R
C
R
C
34
1
35
VID0 / VFIX
PWROK
PWRGOOD
CLTB
RLTB
8 LTB
PWM4 27
CS4N 22
CS4P 21
RG
RG
18
HS_NB
LS_NB
L_NB
CHF
23
R_NB
C_NB
RG_NB
24
CS2N
NB_CSP
NB_CSN
UGATE1 47
PHASE1 46
LGATE1 45
UGATE2 40
PHASE2 41
LGATE2 44
NB_UGATE
37
NB_PHASE
38
NB_LGATE 43
6 VSEN
7 FBG
NB_VSEN
11
NB_FBG 12
VCCDRV
42
SDA / OVP
25
SCL / OS
26
NB_BOOT
36
BOOT1 48
BOOT2
39
49
SGND
3
SVI/PVI Interface
CHF
Power Manager I2C
CHF VIN
RG
ILIM
CI
RI
C
14
ROSC
RILIM
CILIM
5V SBY
Q_EN
EN 13
Obsolete Product(s) - Obsolete Product(s)
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Doc ID 17326 Rev 1 7/56
1.2 Block diagram
Figure 4. Block diagram
NB_CS+
DUAL CHANNEL
OSCILLATOR (4+1)
L6717
CONTROL LOGIC AND
I2C MANAGEMENT
CURRENT
BALANCE
AMD SVI / PVI FLEXIBLE
INTERFACE
CS2+
VID4 / I2CDIS
VID5 / ADDR
OSC / EN
PWROK
PWRGOOD
VCORE_REF
COMP
VSEN
FBG
ERROR
AMPLIFIER
FB
VCC
CS1-
SGND
CS1+
IDROOP
NB_PWM
64k
64k
64k
64kREMOTE
BUFFER
NB_REF
NB_COMP
NB_VSEN
NB_FBG
ERROR
AMPLIFIER
NB_FB
64k64k
64k
64k REMOTE
BUFFER
DIFFERENTIAL
CURRENT SENSE
OUTPUT VOLTAGE
MONITOR AND PROTECTION
MANAGEMENT
NB CURR
SENSE
PWM2
PWM1
Σ
Σ
Σ
Σ
CS2-
CS3+
CS3-
CS4+
CS4-
BOOT1
LGATE1
PWM3
PWM4
VCC
SGND
INB_DROOP
(from SVI/PVI decoding)
CORE_REF
& NB_REF
ILIM
CS1-
VID2 / SVD
VID3 / SVC
VID0 / V_FIX
VID1 / CORE_TYPE
ILIM
SDA / OVP
SCL / OS
BOOT1
UGATE1
PHASE1
LGATE1
BOOT2
UGATE2
PHASE2
LGATE2
UGATE1
PHASE1
BOOT2
UGATE2
PHASE2
LGATE2
EMBEDDED DRIVER
CORE PHASE #1
EMBEDDED DRIVER
CORE PHASE #2
LTB
LTB Technology
MODULATOR
NB_CS-
NB_BOOT
NB_UGATE
NB_PHASE
NB_LGATE
EMBEDDED DRIVER
CORE NB PHASE
NB_LGATE
NB_BOOT
NB_UGATE
NB_PHASE
VCCDR
GND_PAD
VCCDR
VCCDR
Obsolete Product(s) - Obsolete Product(s)
Pins description and connection diagrams L6717
8/56 Doc ID 17326 Rev 1
2 Pins description and connection diagrams
Figure 5. Pins connection (Top view)
2.1 Pin descriptions
48
47
46
45
44
43
42
41
40
39
38
37
13
14
15
16
17
18
19
20
21
22
23
24
36353433 323130292827 26 25
123456789 101112
CS1P
CS1N
CS2P
CS2N
CS3P
CS3N
CS4P
CS4N
ILIM
NB_CSP
NB_CSN
OSC / EN /FLT
BOOT1
UGATE1
PHASE1
LGATE1
LGATE2
NB_LGATE
VCCDRV
PHASE2
UGATE2
BOOT2
NB_PHASE
NB_UGATE
NB_BOOT
PWRGOOD
VID0 / V_FIX
VID1 / CORETYPE
VID2 / SVD
VID3 / SVC
VID4 / I2CDIS
VID5 / ADDR
PWM3
PWM4
SCL / OS
SDA / OVP
PWROK
SGND
VCC
COMP
FB
VSEN
FBG
LTB
NB_COMP
NB_FB
NB_VSEN
NB_FBG
L6717
PAD (GND)
Table 2. Pin description
Pin# Name Function
1PWROK
System-wide Power Good input (Ignored in PVI mode).
Internally pulled-low by 10μA. When low, the device will decode the two SVI bits SVC
and SVD to determine the Pre-PWROK Metal VID. When high, the device will actively
run the SVI protocol.
Pre-PWROK Metal VID are latched after EN is asserted and re-used in case of
PWROK de-assertion. Latch is reset by VCC or EN cycle.
2SGND
Device signal ground.
All the internal references are referred to this pin. Connect to the PCB signal ground.
3VCC
Device power supply.
Operative voltage is 12 ±15%. Filter with 1μF MLCC to SGND.
Do not connect VCC to any voltage greater than VCCDR.
4
CORE section
COMP
CORE error amplifier output.
Connect with an R
F
- C
F
to FB.
The CORE section and/or the device cannot be disabled by grounding this pin.
Obsolete Product(s) - Obsolete Product(s)
L6717 Pins description and connection diagrams
Doc ID 17326 Rev 1 9/56
5
CORE section
FB
CORE error amplifier inverting input.
Connect with a resistor R
FB
to VSEN and with an R
F
- C
F
to COMP. Droop current for
voltage positioning is sourced from this pin.
6VSEN
CORE output voltage monitor.
It manages OVP and UVP protections and PWRGOOD. Connect to the positive side
of the load for remote sensing. See Section 8 for details.
7FBG
CORE remote ground sense.
Connect to the negative side of the load for remote sensing. See Section 11 for proper
layout of this connection.
8LTB
LTB Technology® input pin.
Connect through an RLT B - CLT B network to the regulated voltage (CORE section) to
detect load transient. See Section 12 for details.
9
NB section
NB_COMP
NB error amplifier output.
Connect with an R
F_NB
- C
F_NB
to NB_FB.
The NB section and/or the device cannot be disabled by grounding this pin.
10 NB_FB
NB error amplifier inverting input.
Connect with a resistor R
FB_NB
to NB_VSEN and with an R
F_NB
- C
F_NB
to NB_COMP.
Droop current for voltage positioning is sourced from this pin.
11 NB_VSEN
NB output voltage monitor.
It manages OVP and UVP protections and PWRGOOD. Connect to the positive side
of the NB load to perform remote sensing. See Section 11 for proper layout of this
connection.
12 NB_FBG
NB remote ground sense.
Connect to the negative side of the load to perform remote sense. See Section 11 for
proper layout of this connection.
13
CORE section
ILIM
CORE over current pin.
A current ILIM=DCR/RG*IOUT proportional to the current delivered by the CORE
Section is sourced from this pin. The OC threshold is programmed by connecting a
resistor RILIM to SGND. When the generated voltage crosses the OC_TOT threshold
(VOC_TOT = 2.5V Typ) the device latches with all MOSFETs OFF (to recover, cycle
VCC or the EN pin).
This pin is monitored for dynamic phase management.
Filter with proper capacitor to provide OC masking time; do not exceed 30μsec. See
Section 8.4.1 for details.
14 OSC / EN /
FLT
OSC: It allows programming the switching frequency FSW of both sections. Switching
frequency can be increased according to the resistor ROSC connected to SGND with a
gain of 9.1kHz/µA (see Section 9 for details). If floating, the switching frequency is
200kHz per phase.
EN: Pull-low (tie to GND) to disable the device. When set free, the device immediately
checks for the VID1 status to determine the SVI / PVI protocol to be adopted and
configures itself accordingly.
FLT: The pin is internally forced high (3.3V) in case of an OV / UV fault. To recover
from this condition, cycle VCC or the EN pin.
To enable/disable the IC drive OSC/EN/FAUT pin by an open drain circuit.
Table 2. Pin description (continued)
Pin# Name Function
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15
CORE section
CS1P
Channel 1 current sense positive input.
Connect through an R-C filter to the phase-side of the channel 1 inductor. See
Section 11 for proper layout of this connection.
16 CS1N
Channel 1 current sense negative input.
Connect through a RG resistor to the output-side of the channel inductor. Filter the
Vout-side of RG resistor with 100nF to GND.
See Section 11 for proper layout of this connection.
17 CS2P
Channel 2 current sense positive input.
Connect through an R-C filter to the phase-side of the channel 2 inductor. See
Section 11 for proper layout of this connection.
18 CS2N
Channel 2 current sense negative input.
Connect through a RG resistor to the output-side of the channel inductor. Filter the
Vout-side of RG resistor with 100nF to GND.
See Section 11 for proper layout of this connection.
19 CS3P
Channel 3 current sense positive input.
Connect through an R-C filter to the phase-side of the channel 3 inductor. When
working at 2 phase, directly connect to Vout_CORE.
See Section 11 for proper layout of this connection.
20 CS3N
Channel 3 current sense negative input.
Connect through a RG resistor to the output-side of the channel inductor. When
working at 2 phase, connect through RG to CS3+. Filter the Vout-side of RG resistor
with 100nF to GND.
See Section 11 for proper layout of this connection.
21 CS4P
Channel 4 current sense positive input.
Connect through an R-C filter to the phase-side of the channel 4 inductor. When
working at 2 or 3 phase, directly connect to Vout_CORE.
See Section 11 for proper layout of this connection.
22 CS4N
Channel 4 current sense negative input.
Connect through a RG resistor to the output-side of the channel inductor. When
working at 2 or 3 phase, connect through RG to CS4+.Filter the Vout-side of RG
resistor with 100nF to GND.
See Section 11 for proper layout of this connection.
23
NB section
NB_CSP
NB channel current sense positive input.
Connect through an R-C filter to the phase-side of the NB channel inductor. See
Section 11 for proper layout of this connection.
24 NB_CSN
NB channel current sense negative input.
Connect through a RG resistor to the output-side of the channel inductor. Filter the
Vout-side of RG resistor with 100nF to GND.
See Section 11 for proper layout of this connection.
Table 2. Pin description (continued)
Pin# Name Function
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L6717 Pins description and connection diagrams
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25
Power manager I2C
SDA / OVP
SDA - power manager I2C data.
When power manager I2C is enabled, this is the data connection.
See Section 6 for details.
OVP - over voltage setting.
When power manager I2C is disabled (VID4 / I2CDIS to 3.3V) the pin is used to set
the OVP protection for CORE and NB sections. Define the OVP threshold by
connecting the pin to the center tap of a voltage divider from 3V3 to SGND.
See Section 8.1 for details.
26 SCL / OS
SCL - power manager I2C clock.
When power manager I2C is enabled, this is the clock connection.
See Section 6 for details.
OS - CORE section offset.
When power manager I2C is disabled (VID4 / I2CDIS to 3.3V) this pin is internally set
to 1.24V(2.0V): connecting a ROS resistor to GND (3.3V) allows setting a current that
is mirrored into FB pin in order to program a positive (negative) offset according to the
selected RFB. Short to GND to disable the function. See Section 7.4 for details.
27, 28 PWM4,
PWM3
PWM output for external drivers.
Connect to external drivers PWM inputs. The device is able to manage HiZ status by
setting the pins floating.
By shorting to GND PWM4 or PWM3 and PWM4, it is possible to program the CORE
section to work at 3 or 2 phase respectively.
See Section 5.4.4 for details about HiZ management.
29
SVI / PVI interface
VID5 /
ADDR
Voltage identification pin - I2C address pin.
Internally pulled-low by 10μA, it programs the output voltage in PVI mode. In SVI
mode, the pin is monitored on the EN pin rising-edge to modify the I2C address. See
Section 5 for details.
30 VID4 /
I2CDIS
Voltage identification pin - I2C disable pin.
Internally pulled-low by 10μA, it programs the output voltage in PVI mode. In SVI
mode, the pin is monitored on the EN pin rising-edge to enable/disable the I2C. See
Section 5 for details.
31 VID3 / SVC
Voltage IDentification Pin - SVI clock pin.
Internally pulled-low by 10μA, it programs the output voltage in both SVI and PVI
modes. In SVI mode, the 10μA pull down is disabled. See Section 5 for details.
32 VID2 / SVD
Voltage identification pins - SVI data pin.
Internally pulled-low by 10μA, it programs the output voltage in both SVI and PVI
modes. In SVI mode, the 10μA pull down is disabled. See Section 5 for details.
33
SVI / PVI interface
VID1 /
CORETYPE
Voltage identification pin.
Internally pulled-low by 10μA, it programs the output voltage in PVI mode. The pin is
monitored on the EN pin rising-edge to define the operative mode of the controller
(SVI or PVI). See Section 5 for details.
34 VID0 / VFIX
Voltage identification pin.
Internally pulled-low by 10μA, it programs the output voltage in PVI mode. If the pin is
pulled to 3.3V, the device enters V_FIX mode and SVI commands are ignored.
See Section 5 for details.
Table 2. Pin description (continued)
Pin# Name Function
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35 PWRGOOD
VCORE and NB Power Good.
It is an open-drain output set free after SS as long as both the voltage planes are
within specifications. Pull-up to 3.3V (typ) or lower, if not used it can be left floating.
When in PVI mode, it monitors the CORE section only.
36
Embedded drivers
NB_BOOT
NB section high-side driver supply.
This pin supplies the high-side floating driver. Connect through CBOOT capacitor to the
NB_PHASE pin.
See Section 10 for guidance in designing the capacitor value.
37 NB_UGATE
NB section high-side driver output.
Connect to NB section high-side MOSFET gate. A small series resistor may help in
reducing NB_PHASE pin negative spike as well as cooling the device.
38 NB_PHASE
NB section high-side driver return path.
Connect to the NB section high-side MOSFET source.
This pin is also monitored for the adaptive dead-time management.
39 BOOT2
CORE section, phase 2 high-side driver supply.
This pin supplies the High-Side floating driver. Connect through CBOOT capacitor to
the PHASE2 pin.
See Section 10 for guidance in designing the capacitor value.
40 UGATE2
High-side driver output.
Connect to Phase2 high-side MOSFET gate. A small series resistor may help in
reducing PHASE2 pin negative spike as well as cooling the device.
41 PHASE2
CORE section, phase 2 high-side driver return path. Connect to the Phase2 high-side
MOSFET source.
This pin is also monitored for the adaptive dead-time management.
42 VCCDRV
Supply voltage for low-side embedded drivers.
Operative voltage is flexible from 5V ±5% to 12 ±15%. Filter with 1μF MLCC to GND.
Do not connect VCC to any voltage greater than VCCDR.
43 to
45
Embedded drivers
NB_LGATE,
LGATE2,
LGATE1
Low-side driver output.
Connect directly to the low-side MOSFET gate of the related section. A small series
resistor can be useful to reduce dissipated power especially in high frequency
applications.
46 PHASE1
CORE section, phase 1 high-side driver return path. Connect to the phase1 high-side
MOSFET source.
This pin is also monitored for the adaptive dead-time management.
47 UGATE1
High-side driver output.
Connect to phase1 high-side MOSFET gate. A small series resistor may help in
reducing PHASE1 pin negative spike as well as cooling the device.
48 BOOT1
CORE section, phase 1 high-side driver supply.
This pin supplies the high-side floating driver. Connect through CBOOT capacitor to the
PHASE1 pin.
See Section 10 for guidance in designing the capacitor value.
Thermal
PA D GND All internal references, logic, and the Silicon substrate are referenced to this pin.
Connect to the PCB GND ground plane by multiple vias to improve heat dissipation.
Table 2. Pin description (continued)
Pin# Name Function
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2.2 Thermal data
Table 3. Thermal data
Symbol Parameter Value Unit
R
THJA
Thermal resistance junction to ambient
(Device soldered on 2s2p PC board) 40 °C/W
RTHJC Thermal resistance junction to case 1 °C/W
T
MAX
Maximum junction temperature 150 °C
T
STG
Storage temperature range -40 to 150 °C
T
J
Junction temperature range 0 to 125 °C
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3 Electrical specifications
3.1 Absolute maximum ratings
Table 4. Absolute maximum ratings
Symbol Parameter Value Unit
VCC,VCCDRV to GND -0.3 to 15 V
V
BOOTx
,
V
UGATEx
to GND
to PHASEx
41
15 V
V
PHASEx
to GND
to GND, t < 200nsec.
-8 to 26
30 V
V
LGATEx
to GND
to GND, t < 100nsec.
-0.3 to VCCDRV + 0.3
-3 V
All other pins to GND -0.3 to 3.6 V
Maximum withstanding voltage range test
condition: CDF-AEC-Q100-002- “human body
model” acceptance “normal performance”
±1750 V
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3.2 Electrical characteristics
V
CC
=12 V±15%, T
J
= 0 °C to 70 °C unless otherwise specified.
Table 5. Electrical characteristics
Symbol Parameter Test conditions Min. Typ. Max. Unit
Supply current and power-on
ICC VCC supply current
OSC = GND
15 mA
ICCDR VCCDR supply current 4 mA
IBOOTx BOOTx supply current 1.5 mA
UVLOVCC
VCC turn-ON VCC rising 4.5 V
VCC turn-OFF VCC falling 4 V
Oscillator
FSW
Main oscillator accuracy 180 200 220 kHz
Oscillator adjustability ROSC = 36kΩ425 500 575 kHz
ΔVOSC PWM ramp amplitude CORE and NB section 1.5 V
FAULT Voltage at pin OSC OVP, UVP latch active 3 3.6 V
EN Turn-OFF threshold OSC/EN falling 0.3 V
PVI / SVI interface
PWROK Input high 1.3 V
Input low 0.80 V
VID2,/SVD
VID3/SVC
Input high (SVI mode) 0.95 V
Input low (SVI mode) 0.65 V
SVD Voltage low (ACK) ISINK = -5mA 250 mV
VID0 to
VID5
Input high (PVI mode) 1.3 V
Input low (PVI mode) 0.80 V
V_FIX Entering V_FIX mode VID0/V_FIX rising 3 V
Power manager I2C
SDA, SCL Input high 1.3 V
Input low 0.8 V
SDA Voltage low (ACK) ISINK = -5mA 250 mV
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Voltage positioning (CORE and NB section)
CORE Output voltage accuracy VSEN to VCORE; FBG to GNDCORE -8 8 mV
NB NBVSEN to VNB; NBFBG to GNDFB -10 10 mV
OS
OFFSET bias voltage I2DIS=3.3V, IOS = 0 to 250μA 1.190 1.24 1.290 V
OFFSET current range I2DIS=3.3V 0 250 μA
OFFSET - IFB accuracy I2DIS=3.3V, IOS = 0μA -2.25 2.25 μA
I2DIS=3.3V, IOS = 250μA-9 9μA
DROOP DROOP accuracy IDROOP = 0 to 25μA, kDRP = 1/4 -3 3 μA
INB_DROOP = 0 to 6μA, kNBDRP = 1/4 -1 1 μA
A0EA DC gain 100 dB
SR Slew rate COMP, NB_COMP to SGND = 10pF 20 V/μs
PWM outputs (CORE only) and embedded drivers
PWM3,
PWM4
Output high I = 1mA 3 3.6 V
Output low I = -1mA 0.2 V
IPWMx Test current 10 μA
High current embedded drivers
RHIHS HS source resistance BOOT - PHASE = 12V; 100mA 2.3 2.8 Ω
IUGATE HS source current BOOT - PHASE = 12V; (1)
CUGATE to PHASE = 3.3nF 2A
RLOHS HS sink resistance BOOT - PHASE = 12V; 100mA 2 2.5 Ω
RHILS LS source resistance 100mA 1.3 1.8 Ω
ILGATE LS source current CLGATE to GND = 5.6nF, (1) 3A
RLOLS LS sink resistance 100mA 1 1.5 Ω
Protections
OVP Over voltage protection
I2C enabled, no commands issued,
wrt VID, CORE & NB section +200 +250 +300 mV
I2C disabled, V_FIX mode;
VSEN, NB_VSEN rising 1.800 V
SDA/OVP bias current I2CDIS = 3.3V 9 11 13 μA
UVP Under voltage protection VSEN, NB_VSEN falling; wrt Ref. -450 -400 -350 mV
PWRGOOD PGOOD threshold VSEN, NB_VSEN falling; wrt Ref -285 -250 -215 mV
Voltage low IPWRGOOD = -4mA 0.4 V
VFB-DISC FB disconnection VCSN rising, above VSEN
CORE and NB sections 600 mV
VFBG DISC FBG disconnection EA NI input wrt VID 500 mV
Table 5. Electrical characteristics (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
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VOC_TOT
CORE OC
2.425 2.500 2.575 V
kIILIM
ILIM = 0μA04μA
ILIM = 100μA100μA
1. Parameter(s) guaranteed by designed, not fully tested in production
Table 5. Electrical characteristics (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
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Device description and operation L6717
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4 Device description and operation
L6717 is a hybrid CPU power supply controller compatible with both parallel (PVI) and serial
(SVI) protocols for AMD Processors. The device provides complete control logic and
protections for a high-performance step-down DC-DC voltage regulator, optimized for
advanced microprocessor power supply supporting both PVI and SVI communication. It
embeds two independent controllers for CPU CORE and the integrated NB, each one with
its own set of protections. NB phase (when enabled) is automatically phase-shifted with
respect to the CORE phases in order to reduce the total input rms current amount.
The device features an additional power manager I2C interface to easy the system design
for enthusiastic application where the main parameters of the voltage regulator have to be
modified. L6717 is able to adjust the regulated voltage, the switching frequency and also the
OV protection threshold through the power manager I2C bus while the application is running
assuring fast and reliable transitions.
Dynamic phase management (DPM) allows the device to automatically adjust the phase
count according to the current delivered to the load. This feature allow the system to keep
alive only the phases really necessary to sustain the load saving in power dissipation so
optimizing the efficiency over the whole current range of the application. DPM can be
enabled through the power manager I2C bus.
L6717 is able to detect which kind of CPU is connected in order to configure itself to work as
a single-plane PVI controller or dual-plane SVI controller.
The controller performs a single-phase control for the NB section and a programmable 2-to-
4 phase control for the CORE section featuring dual-edge non-latched architecture: this
allows fast load-transient response optimizing the output filter consequently reducing the
total BOM cost. Further reduction in output filter can be achieved by enabling LTB
Technology®.
PSI_L flag is sent to the VR through the SVI bus. The controller monitors this flag and
selectively modifies the phase number in order to optimize the system efficiency when the
CPU enters low-power states. This causes the over-all efficiency to be maximized at light
loads so reducing losses and system power consumption.
Both sections feature programmable overvoltage protection and adjustable constant
overcurrent protection. Voltage positioning (LL) is possible thanks to an accurate fully-
differential current-sense across the main inductors for both sections.
L6717 features dual remote sensing for the regulated outputs (CORE and NB) in order to
recover from PCB voltage drops also protecting the load from possible feedback network
disconnections.
LSLess start-up function allows the controller to manage pre-biased start-up avoiding
dangerous current return through the main inductors as well as negative undershoot on the
output voltage if the output filter is still charged before start-up.
L6717 supports V_FIX mode for system debugging: in this particular configuration the SVI
bus is used as a static bus configuring 4 operative voltages for both the sections and
ignoring any serial-VID command.
When working in PVI mode, the device features on-the-fly VID management: VID code is
continuously sampled and the reference update according to the variation detected,
L6717 is available in VFQFPN48 package.
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5 Hybrid CPU support and CPU_TYPE detection
L6717 is able to detect the type of the CPU-core connected and to configure itself
accordingly. At system Start-up, on the rising-edge of the EN signal, the device monitors the
status of VID1 and configures the PVI mode (VID1 = 1) or SVI mode (VID1 = 0).
When in PVI mode, L6717 uses the information available on the VID[0: 5] bus to address the
CORE Section output voltage according to Table 6. NB Section is kept in HiZ mode, both
MOSFETs are kept OFF.
When in SVI mode, L6717 ignores the information available on VID0, VID4 and VID5 and
uses VID2 and VID3 as a SVI bus addressing the CORE and NB Sections according to the
SVI protocol.
Caution: To avoid any risk of errors in CPU type detection (i.e. detecting SVI CPU when PVI CPU is
installed on the socket and vice versa), it is recommended to carefully control the start-up
sequencing of the system hosting L6717 in order to ensure than on the EN rising-edge,
VID1 is in valid and correct state. Typical connections consider VID1 connected to CPU
CORE_TYPE through a resistor to correctly address the CPU detection.
5.1 PVI - parallel interface
PVI is a 6-bit-wide parallel interface used to address the CORE section reference. According
to the selected code, the device sets the CORE section reference and regulates its output
voltage as reported into Table 6.
NB section is always kept in HiZ; no activity is performed on this section and both the high-
side and low-side of this section are kept OFF. Furthermore, PWROK information is ignored
as well since the signal only applies to the SVI protocol.
5.2 PVI start-up
Once the PVI mode has been detected, the device uses the whole code available on the
VID[0:5] lines to define the reference for the CORE section. NB section is kept in HiZ. Soft-
start to the programmed reference is performed regardless of the state of PWROK.
See Section 7.8 for details about soft-start.
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Table 6. Voltage Identifications (VID) codes for PVI mode
VID5 VID4 VID3 VID2 VID1 VID0 Output
voltage VID5 VID4 VID3 VID2 VID1 VID0 Output
voltage
0000001.55001000000.7625
0000011.52501000010.7500
0000101.50001000100.7375
0000111.47501000110.7250
0001001.45001001000.7125
0001011.42501001010.7000
0001101.40001001100.6875
0001111.37501001110.6750
0010001.35001010000.6625
0010011.32501010010.6500
0010101.30001010100.6375
0010111.27501010110.6250
0011001.25001011000.6125
0011011.22501011010.6000
0011101.20001011100.5875
0011111.17501011110.5750
0100001.15001100000.5625
0100011.12501100010.5500
0100101.10001100100.5375
0100111.07501100110.5250
0101001.05001101000.5125
0101011.02501101010.5000
0101101.00001101100.4875
0101110.97501101110.4750
0110000.95001110000.4625
0110010.92501110010.4500
0110100.90001110100.4375
0110110.87501110110.4250
0111000.85001111000.4125
0111010.82501111010.4000
0111100.80001111100.3875
0111110.77501111110.3750
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5.3 SVI - serial interface
SVI is a two wire, clock and data, bus that connects a single master (CPU) to one slave
(L6717). The master initiates and terminates SVI transactions and drives the clock, SVC,
and the data, SVD, during a transaction. The slave receives the SVI transactions and acts
accordingly. SVI wire protocol is based on fast-mode I2C.
SVI interface also considers two additional signal needed to manage the system start-up.
These signals are EN and PWROK. The device return a PWRGOOD signal if the output
voltages are in regulation.
5.4 SVI start-up
Once the SVI mode has been detected on the EN rising-edge, L6717 checks for the status
of the two serial VID pins, SVC and SVD, and stores this value as the Pre-PWROK Metal
VID. The controller initiate a soft-start phase regulating both CORE and NB voltage planes
to the voltage level prescribed by the Pre-PWROK Metal VID. See Table 7 for details about
Pre-PWROK Metal VID codifications. The stored Pre-PWROK Metal VID value are re-used
in any case of PWROK de-assertion.
After bringing the output rails into regulation, the controller asserts the PWRGOOD signal
and waits for PWROK to be asserted. Until PWROK is asserted, the controller regulates to
the Pre-PWROK Metal VID ignoring any commands coming from the SVI interface.
After PWROK is asserted, the processor has initialized the serial VID interface and L6717
waits for commands from the CPU to move the voltage planes from the Pre-PWROK Metal
VID values to the operative VID values. As long as PWROK remains asserted, the controller
will react to any command issued through the SVI interface according to SVI protocol.
See Section 7.8 for details about Soft-Start.
Table 7. V_FIX mode and Pre-PWROK MetalVID
5.4.1 Set VID command
The set VID command is defined as the command sequence that the CPU issues on the SVI
bus to modify the voltage level of the CORE section and/or the NB section.
During a set VID command, the processor sends the start (START) sequence followed by
the address of the section which the set VID command applies. The processor then sends
the write (WRITE) bit. After the write bit, the voltage regulator (VR) sends the acknowledge
(ACK) bit. The processor then sends the VID bits code during the data phase. The VR
sends the acknowledge (ACK) bit after the data phase. Finally, the processor sends the stop
(STOP) sequence. After the VR has detected the stop, it performs an on-the-fly VID
SVC SVD
Output voltage [V]
Pre-PWROK metal VID V_FIX mode
0 0 1.1V 1.4V
0 1 1.0V 1.2V
1 0 0.9V 1.0V
1 1 0.8V 0.8V
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transition for the addressed section(s) or, more in general, react to the sent command
accordingly. Refer to Figure 6, Table 8 and Table 9 for details about the set VID Command.
L6717 is able to manage individual power OFF for both the sections. The CPU may issue a
serial VID command to power OFF or power ON one Section while the other one remains
powered. In this case, the PWRGOOD signal remains asserted.
Figure 6. SVI Communications - send byte
Table 8. SVI send byte - address and data phase description
bits Description
Address phase
6:4 Always 110b.
3 Not applicable, ignored.
2 Not applicable, ignored.
1CORE section(1).
If set then the following data byte contains the VID code for CORE section.
1. Assertion in both bit 1 and 0 will address the VID code to both CORE and NB simultaneously.
0NB section(1).
If set then the following data byte contains the VID code for NB section.
Data phase
7PSI_L flag (Active low).When asserted, the VR is allowed to enter power-saving
mode. See Section 5.4.3.
6:0 VID code. See Table 9.
SVC
SVD
START
110b
ACK ACK
Slave Addressing
(7 Clocks)
654 0
WRITE
(1Ck)
ACK
(1Ck)
7603
Data Phase
(8 Clocks)
ACK
(1Ck)
STOP
START SLAVE ADDRESSING + W ACK DATA PHASEACK STOP
BUS DRIVEN BY L6717 BUS DRIVEN BY MASTER (CPU)
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Table 9. Data phase - serial VID codes
SVI [6:0] Output
voltage SVI [6:0] Output
voltage SVI [6:0] Output
voltage SVI [6:0] Output
voltage
000_0000 1.5500 010_0000 1.1500 100_0000 0.7500 110_0000 0.3500
000_0001 1.5375 010_0001 1.1375 100_0001 0.7375 110_0001 0.3375
000_0010 1.5250 010_0010 1.1250 100_0010 0.7250 110_0010 0.3250
000_0011 1.5125 010_0011 1.1125 100_0011 0.7125 110_0011 0.3125
000_0100 1.5000 010_0100 1.1000 100_0100 0.7000 110_0100 0.3000
000_0101 1.4875 010_0101 1.0875 100_0101 0.6875 110_0101 0.2875
000_0110 1.4750 010_0110 1.0750 100_0110 0.6750 110_0110 0.2750
000_0111 1.4625 010_0111 1.0625 100_0111 0.6625 110_0111 0.2625
000_1000 1.4500 010_1000 1.0500 100_1000 0.6500 110_1000 0.2500
000_1001 1.4375 010_1001 1.0375 100_1001 0.6375 110_1001 0.2375
000_1010 1.4250 010_1010 1.0250 100_1010 0.6250 110_1010 0.2250
000_1011 1.4125 010_1011 1.0125 100_1011 0.6125 110_1011 0.2125
000_1100 1.4000 010_1100 1.0000 100_1100 0.6000 110_1100 0.2000
000_1101 1.3875 010_1101 0.9875 100_1101 0.5875 110_1101 0.1875
000_1110 1.3750 010_1110 0.9750 100_1110 0.5750 110_1110 0.1750
000_1111 1.3625 010_1111 0.9625 100_1111 0.5625 110_1111 0.1625
001_0000 1.3500 011_0000 0.9500 101_0000 0.5500 111_0000 0.1500
001_0001 1.3375 011_0001 0.9375 101_0001 0.5375 111_0001 0.1375
001_0010 1.3250 011_0010 0.9250 101_0010 0.5250 111_0010 0.1250
001_0011 1.3125 011_0011 0.9125 101_0011 0.5125 111_0011 0.1125
001_0100 1.3000 011_0100 0.9000 101_0100 0.5000 111_0100 0.1000
001_0101 1.2875 011_0101 0.8875 101_0101 0.4875 111_0101 0.0875
001_0110 1.2750 011_0110 0.8750 101_0110 0.4750 111_0110 0.0750
001_0111 1.2625 011_0111 0.8625 101_0111 0.4625 111_0111 0.0625
001_1000 1.2500 011_1000 0.8500 101_1000 0.4500 111_1000 0.0500
001_1001 1.2375 011_1001 0.8375 101_1001 0.4375 111_1001 0.0375
001_1010 1.2250 011_1010 0.8250 101_1010 0.4250 111_1010 0.0250
001_1011 1.2125 011_1011 0.8125 101_1011 0.4125 111_1011 0.0125
001_1100 1.2000 011_1100 0.8000 101_1100 0.4000 111_1100 OFF
001_1101 1.1875 011_1101 0.7875 101_1101 0.3875 111_1101 OFF
001_1110 1.1750 011_1110 0.7750 101_1110 0.3750 111_1110 OFF
001_1111 1.1625 011_1111 0.7625 101_1111 0.3625 111_1111 OFF
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5.4.2 PWROK de-assertion
Anytime PWROK de-asserts, while EN is asserted, the controller uses the previously stored
Pre-PWROK Metal VID and sets both CORE and NB planes voltage to the corresponding
level performing an on-the-fly VID transition.
Anytime the PWROK is de-asserted the PWRGOOD is tied low; after being pulled low the
PWRGOOD is treated appropriately and kept de-asserted until the output voltage of both
CORE and NB sections is within the PWRGOOD validity window referred to Pre-PWROK
Metal VID.
5.4.3 PSI_L and efficiency optimization at light-load
PSI_L is an active-low flag (i.e. low logic level when asserted) that can be set by the CPU to
allow the VR to enter power-saving mode to maximize the system efficiency when in light-
load conditions. The status of the flag is communicated to the controller through the SVI
bus.
When the PSI_L flag is asserted by the CPU through the SVI bus, the device adjusts the
phase number according to the programmed strategy. Default PSI_L strategy consists in
working in single phase. PSI_L strategy can be disabled as well as re-configured through
specific Power Manager I2C commands. See Section 6 for details.
When CPU issues PSI_L flag, L6717 adjusts phase number according to the selected
PSI_L strategy: the device sets HiZ on the related phases and re-configures internal phase-
shift to maintain the correct interleaving among active phases. Furthermore, the internal
current-sharing is adjusted considering the phase number reduction.
When PSI_L is de-asserted, the device will return to the original configuration.
Start-up is performed with all the configured phases enabled.
When PSI_L is active L6717 performs on-the-fly VID transitions with all the programmed
phases.
NB section is not impacted by PSI_L status change.
Figure 7 shows an example of the efficiency improvement that can be achieved by enabling
the PSI management.
Figure 7. System efficiency enhancement by PSI
1 PHASE 4 PHASE
1 PHASE 4 PHASE
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5.4.4 HiZ management
L6717 is able to manage HiZ both for internal driver and for external drivers through the
PWMx signals. When the controller needs to set HiZ state for a phase or section, it sets the
corresponding PWMx pin floating and, at the same time, turn OFF both HS and LS
MOSFETs by proper action of the corresponding embedded driver.
5.4.5 Hardware jumper override - V_FIX
VID0/V_FIX pin allows the device to operate in V_FIX mode.
Anytime L6717 is enabled it checks the pin VID0/V_FIX voltage level: pull up VID0/V_FIX to
3.3V to enter V_FIX mode.
When in V_FIX mode, both NB and CORE Section voltages are governed by the information
shown in Table 7.
Regardless of the state of VID1, the device will work in SVI mode and furthermore PWROK
logic level is ignored.
SVC and SVD are considered as static VID and the output voltage changes according to
their status. Dynamic SVC/SVD-change management is provided in this condition.
V_FIX mode is intended for system debug only.
Protection management differs in this case, see Section 8.1 for details.
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6 Power manager I2C
L6717 features a secondary power manager I2C bus to easy the implementation of power
management features as well as over-speeding for “enthusiastic” users. The power
manager I2C bus is operative after the PWRGOOD signal is driven high at the end of the
soft-start.
Power manager I2C is a two wire, SCL (Clock) and SDA (Data), bus connecting a single
master to one or more slaves (L6717) separately addressable. The master initiates and
terminates I2C transactions and drives both the clock, SCL, and the data, SDA, during a
transaction. The slave receives the I2C transactions and acts accordingly.
Power manager I2C wire protocol is based on fast-mode I2C.
Power manager I2C address configuration can be programmed through ADDR pin while
I2CDIS pin allows to disable the bus. See Table 10.
Power manager I2C and SVI bus are two independent buses working in parallel. In case two
commends are issued in the same time on the two buses, L6717 performs them in the same
time.
Table 10. Power manager I2C configuration
6.1 Power manager commands
Power manager I2C master issues different command sequences to modify several voltage
positioning parameters for CORE and/or NB Sections of L6717.
Moreover the power manager I2C commands allow to configure DPM and other power-
saving-related features.
During a power manager command:
– The bus master sends the start (START) sequence followed by the address of the
controller which the power manager command applies. The bus master then sends
the write (WRITE) bit. After the write bit, the voltage regulator (VR, L6717) sends the
acknowledge (ACK) bit.
– The bus master sends the command code during the command phase. The VR
(L6717) sends the acknowledge (ACK) bit after the command phase.
– The bus master sends the data stream related to the command phase previously
issued (if applicable). The VR (L6717) sends the acknowledge (ACK) bit after the data
stream. Finally, the bus master sends the stop (STOP) sequence.
– After the VR (L6717) has detected the STOP sequence, it performs operations
according to the command issued by the bus master.
I2CDIS ADDR Description
3.3V n/a
Power manager I2C disabled.
SDA/OVP now becomes OVP to program the OV threshold for
both CORE and NB sections.
SCL/OS now becomes OS to program Offset for the CORE
section.
OPEN 3.3V It sets I2C address to 1100111.
OPEN It sets I2C address to 1100110 (default).
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L6717 Power manager I2C
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Refer to Figure 8, Table 11 and Table 12 for details.
Figure 8. Power manager I2C communication format
Table 11. Power manager I2C - address and command phase description
bits Description
Address phase
1:6 Always 110011b.
7
Slave address.
According to ADDR connection, the device will act if addressed by 0b or 1b.
Default address bit is 0b.
8WRITE bit.
Command phase
1:3 Not applicable, ignored.
4:6 Command code
7, 8 Not applicable, ignored.
COMMAND
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Table 12. Power manager I2C command phase and data stream
Command
code [4:6]
Data stream
[1:8] Description
1CN
[1:2] xx
[3] SIGN
[4:8] OVRSPD
OVERSPEEDING: Adds a positive/negative offset to the regulation
according to the SIGN bit with 50mV LSB and 5bit resolution.
[3] SIGN: 1b for positive offset, 0b for negative offset.
Negative offset is applicable only to CORE section (NB does not react
to negative OS command)
[4:8] OVRSPD: 5bit code (4:MSB to 8:LSB), defines the offset to add
to the programmed reference (VID).
Maximum CORE output voltage reachable is limited to 2.8V.
Maximum NB output voltage reachable is limited by the Maximum NB
Offset: +600mV (over VID)
“CN” bits in command code address CORE section (“C” bit) or NB
section (“N” bit) if set to 1b. Asserting both C and N bits will apply the
command to both CORE and NB section.
See Table 13 for details about OVRSPD codification.
000
[1:4] xxxx
[5:6] OV_NB
[7:8] OV_CORE
OV_SET: Overvoltage threshold setup for CORE and/or NB sections.
Sets the OV threshold above the programmed VID (including
OVRSPD) in with three 200mV steps from + 250mV up to +850mV
(up to 650mV for NB).
[1:4]: ignored
[5:6] OV_NB: NorthBridge OVP. 2bit code, defines the OV threshold
for the NB section above the programmed reference (VID).
[7:8] OV_CORE: Core OVP. 2bit code, defines the OV threshold for
the CORE section above the programmed reference (VID).
Default OV threshold is +250mV above reference for both sections.
See Table 14 for details about OV_SET codification.
001 [1:5] xxxxx
[6:8] FSW
FSW_ADJ: Switching frequency adjustment. Modifies the switching
frequency programmed through OSC pin according to FSW code by
+/- 10% or +/-20%.
[1:5]: ignored
[6:8]: FSW: Switching frequency adjustment. 3 bits code to adjust the
switching frequency with respect programmed voltage.
See Table 15 for details about FSW_ADJ codification.
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6.1.1 Overspeeding command (OVRSPD)
This command allows to add a variable positive/negative offset to the CORE and/or NB
reference programmed by the SVI bus in order to overspeed the CPU. L6717 allows adding
up to 1.550 V in 50 mV steps to the reference.
The maximum possible output voltage for CORE section is internally limited to 2.8 V. In case
the SVI programmed reference plus the offset set through the OVRSPD command exceed
this value, the reference for the regulation is clamped to 2.8 V.
The maximum possible output voltage for NB section is internally limited by the maximum
offset achievable for NB section that is +600 mV over the SVI programmed reference.
Once the controller acknowledges the command and recognizes the OVRSPD command,
the reference will step up or down until reaching the target offset performing a on-the-fly VID
transition. In case a new overspeed command is issued while the output voltage is not yet
stabilized (i.e. the reference is still stepping to the target), the target is updated according to
the new offset defined.
The command addresses both sections through two separate bits in the command code
(“CN” bits - See Table 12). By asserting the corresponding bit, the subsequent data stream
will apply to the identified section. Asserting both bits (“CN” = 11b) will address both
sections. CN = 00b will be ignored regardless of the data Stream provided. “CN” = 10b and
“CN” = 01b allow to address only CORE or only NB section respectively.
010
[1:4] xxxx
[5:6] kDRPNB
[7:8] kDRP
DRP_ADJ: Droop function adjustment. Modifies the slope of the
output voltage implemented through the droop function.
[1:4]: ignored
[5:6]: kDRPNB. Defines the kDRP factor for NB section.
[7:8]: kDRP
. Defines the kDRPNB factor for CORE section.
Default value is kDRPx = 1/4 for both sections.
See Table 16 for details about DRP_ADJ codification and Section 7.3
and Section 7.6 for LoadLine definition.
011
[1:3] xxx
[4:5] DPMTH
[6] PSI_A
[7] PSI_EN
[8] DPM_ON
Power management flags: Set of three flags to define power
management actions of the controller.
[1:3]: ignored
[4:5]: DPM thresholds. Default is 00b.
[6] PSI_A: PSI action. It defines the action to take when PSI_L flag is
asserted by SVI bus. The same action is considered by DPM. Send
0b to work in single phase (default) or 1b to work at two phases.
[7] PSI_EN: PSI enable. It enables or disables the PSI management.
Set to 1b (default) to manage PSI_L according to PSI_A or set to 0b
to ignore PSI_L flag sent through SVI bus.
[8] DPM_ON: Dynamic phase management. It enables or disables
the DPM mode. Set to 1b to enable DPM or set to 0b (default) to
disable it.
When enabled DPM acts automatically cutting phases according to
PSI action flag at light load.
See Section 6.2 for details about DPM.
Table 12. Power manager I2C command phase and data stream
Command
code [4:6]
Data stream
[1:8] Description
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See Table 12 and Table 13 for details about the codification of the command and the data
stream.
6.1.2 Overvoltage threshold adjustment (OV_SET)
This command allows to adjust the overvoltage threshold independently for CORE and NB
Sections. The default OVP threshold value of +250 mV over the reference is adjustable, in
200 mV steps up to +850 mV above the reference for CORE and +650 mV above the
reference for NB.
See Table 12 and Table 14 for details about the codification of the command and the data
stream.
Table 14. OVP_SET command - threshold codification
6.1.3 Switching frequency adjustment (FSW_ADJ)
This command allows to adjust the switching frequency for the system in +/-10% steps
across the main level defined by the OSC pin. Switching frequency margining may benefit
the system from the thermal and performance point of view.
See Table 12 and Table 15 for details about the codification of the command and the data
stream.
Table 13. OVRSPD command - offset codification (1) (2)
1. Offset is added with an OTF VID transition above the programmed VID.
2. Maximum regulated output voltage is internally limited to 2.8V maximum: regardless the offset over VID
reference the IC does not allow to reach an higher voltage.
Data
stream
[4:8]
Offset to
reference
[V]
Data
stream
[4:8]
Offset to
reference
[V]
Data
stream
[4:8]
Offset to
reference
[V]
Data
stream
[4:8]
Offset to
reference
[V]
00000 0.00 01000 0.40 10000 0.80 11000 1.20
00001 0.05 01001 0.45 10001 0.85 11001 1.25
00010 0.10 01010 0.50 10010 0.90 11010 1.30
00011 0.15 01011 0.55 10011 0.95 11011 1.35
00100 0.20 01100 0.60 10100 1.00 11100 1.40
00101 0.25 01101 0.65 10101 1.05 11101 1.45
00110 0.30 01110 0.70 10110 1.10 11110 1.50
00111 0.35 01111 0.75 10111 1.15 11111 1.55
Data stream [5:6] and [7:8] OVP threshold [V]
00 +250mV (Default)
01 +450mV
10 +650mV
11 +850mV CORE / +650mV for NB
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6.1.4 Droop function adjustment (DRP_ADJ)
This command allows to adjust the slope for the output voltage load line once the external
components are defined by modifying the kDRP and kDRPNB parameters defined in
Section 7.3 and Section 7.6.
See Table 12 and Table 16 for details about the codification of the command and the data
stream.
6.1.5 Power management flags
This command allows to set several flags to configure L6717 power management.
The flags allows to define:
– PSI_A. This flag defines phase shedding strategy adopted when CPU asserts PSI_L
by SVI bus. Set PSI_A = 0b (default) to program the device to work in single phase or
set PSI_A = 1b to program two phase mode.
The selected strategy applies also to DPM mode.
See Section 5.4.3 for details about PSI management and light-load efficiency
optimizations. See Section 6.2 for details about DPM.
– PSI_EN. This flag defines whether to enable or not the PSI_L management. Default is
to manage PSI_L flag assertion through SVI bus (PSI_EN = 1b).
– DPM_ON. This flag defines whether to enable or not the DPM mode. The strategy
adopted by DPM is defined through the PSI_A flag. See Section 6.2 for details about
DPM. DPM is disabled by default (DPM_ON = 0h).
– DPMTH. Allow to program up to 4 different strategies for DPM mode by properly
adjusting the VDPM threshold. See Section 6.2 for details about DPM.
See Table 12 and Table 17 for details about the codification of the command and the data
stream.
Table 15. FSW_ADJ command - switching frequency adjustment codification
Data stream
[6:8] Fsw adjustment Data stream
[6:8] Fsw adjustment
000 Reset to frequency
programmed by OSC 100 Reset to frequency
programmed by OSC
001 -10% 101 +10%
010 -20% 110 +20%
011 Ignored 111 Ignored
Table 16. DRP_ADJ command - droop function adjustment codification
Data stream [5:6] and [7:8] DRP adjustment kDRPNB[5:6] and kDRP[7:8]
00 1/4
01 1/2
10 Ignored
11 Droop disabled
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6.2 Dynamic phase management (DPM)
Dynamic phase management allows to adjust the number of working phases according to
the delivered current still maintaining the benefits of the multiphase regulation.
Phase number is reduced by monitoring the voltage level across ILIM pin: L6717 reduces
the number of working phase according to the strategy defined by the PSI_A flag when the
voltage across ILIM pin is lower than VDPM. When the load current increases the phase
number is restored to the original value as soon as the voltage across ILIM pin exceeds
VDPM.
VDPM is selected through the DPMTH command. See Section 6.1.
The current at which the transition happens (IDPM) can be estimated as:
VDPM thresholds are defined as a percentage of the voltage on ILIM pin corresponding to
the Thermal Design Current of the application.
1.8V on ILIM pin corresponds to 100% of the load and DPM threshold are defined as a
percentage of 1.8V (see Table 18 for details).
An hysteresis is provided for each threshold in order to avoid multiple DPM actions
triggering in steady load conditions.
DPM is disabled by default: Soft-start is performed with all the available phases.
Table 17. Power management flags
Data stream bit Flag Description
[1:3] n/a Ignored.
[4:5] DPMTH DPM threshold. Allow to define 4 different values for VDPM.
See Section 6.2 for code/thresholds correspondence.
[6] PSI_A 0b (default): IC working in single phase when PSI_L asserted.
1b:IC working in two phase when PSI_L asserted.
[7] PSI_EN
0b: PSI_L flag in SVI ignored.
1b (default): PSI_L flag in SVI monitored and phase dropping
enabled according to PSI_A.
[8] DPM_ON 0b (default): DPM disabled.
1b: DPM enabled.
Table 18. VDPM thresholds
CODE VDPM (ILIM rising) VDPM (ILIM falling)
00 (default) 20% 15%
01 25% 20%
10 30% 25%
11 35% 30%
IDPM
VDPM
RILIM
---------------
RG
DCR
-------------
⋅=
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When the soft start is over and once PWRGOOD rise to Logic “1”, L6717 can receive
commands on power manager I2C bus to enable DPM.
Once DPM is enabled, L6717 starts monitoring the ILIM voltage: the voltage is compared
with the internal VDPM threshold defining the current level to trigger the number modification.
DPM is reset in particular conditions:
– during OTF VID transition issued by the CPU;
– when LTB Technology® detects a load transient.
After being reset, DPM is re-enabled with a proper delay: the phase number is again defined
according to the ILIM pin voltage with respect VDPM.
Delay in the intervention of DPM can be adjusted by properly sizing the filer across ILIM pin.
Increasing the capacitance results in increased delay in the DPM intervention.
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7 Output voltage positioning
Output voltage positioning is performed by selecting the controller operative-mode (SVI, PVI
and V_FIX) and by programming the droop function and offset to the reference of both the
sections (See Figure 9). The controller reads the current delivered by each section by
monitoring the voltage drop across the DCR Inductors. The current (IDROOP / IDROOP_NB)
sourced from the FB / NB_FB pin, directly proportional to the read current, causes the
related section output voltage to vary according to the external RFB / RFB_NB resistor so
implementing the desired load-line effect.
L6717 embeds a dual remote-sense buffer to sense remotely the regulated voltage of each
Section without any additional external components. In this way, the output voltage
programmed is regulated compensating for board and socket losses. Keeping the sense
traces parallel and guarded by a power plane results in common mode coupling for any
picked-up noise.
Figure 9. Voltage positioning
1.2V
R
OS
SCL/OS
CORE_REFERENCE
FB COMP VSEN FBG
R
F
C
F
R
FB
To VDD_CORE
(Remote Sense)
k
DRP
I
DROOP
-I
OS
I
OS
CORE Protection
Monitor
from SVI DAC...
NB_REFERENCE
NB_FB NB_COMP
NB_VSEN NB_FBG
R
F_NB
C
F_NB
R
FB_NB
To VDD_NB
(Remote Sense)
k
DRPNB
I
DROOP_NB
NB Protection
Monitor
from DAC...
CORE SECTION
VOLTAGE POSITIONING
NB SECTION
VOLTAGE POSITIONING
Operative only when Power Manager I2C disabled
Offset from Power Manager I2C
(Active when enabled)
Clamp to 2.8V
max
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7.1 CORE section - phase # programming
CORE section implements a flexible 2 to 4 interleaved-phase converter. To program the
desired number of phase, simply short to GND the PWMx signal that is not required to be
used according to Table 19. For three phase operation, short PWM4 to GND while for two
phase operation, short PWM3 and PWM4 to GND.
Caution: For the disabled phase(s), the current reading pins need to be properly connected to avoid
errors in current-sharing and voltage-positioning: CSxP needs to be connected to the
regulated output voltage while CSxN needs to be connected to CSxP through the same RG
resistor used for the active phases. See Figure 2 and Figure 3 for details in 3-phase and 2-
phase connections.
Table 19. CORE section - phase number programming
7.2 CORE section - current reading and current sharing loop
L6717 embeds a flexible, fully-differential current sense circuitry for the CORE Section that
is able to read across inductor parasitic resistance or across a sense resistor placed in
series to the inductor element. The fully-differential current reading rejects noise and allows
placing sensing element in different locations without affecting the measurement's accuracy.
The trans-conductance ratio is issued by the external resistor RG placed outside the chip
between CSxN pin toward the reading points. The current sense circuit always tracks the
current information, the pin CSxP is used as a reference keeping the CSxN pin to this volt-
age. To correctly reproduce the inductor current an R-C filtering network must be introduced
in parallel to the sensing element. The current that flows from the CSxN pin is then given by
the following equation (See Figure 10):
Considering now to match the time constant between the inductor and the R-C filter applied
(Time constant mismatches cause the introduction of poles into the current reading network
causing instability. In addition, it is also important for the load transient response and to let
the system show resistive equivalent output impedance) it results:
RG resistor is typically designed in order to have an information current IINFOx in the range of
about 35μA (IOCTH) at the OC Threshold.
Phase number PWM3 PWM4
2GND GND
3 To driver GND
4 To driver To driver
ICSxN
DCR
RG
------------- 1 s L DCR⁄⋅+
1sRC⋅⋅+
--------------------------------------I⋅PHASEx
⋅=
L
DCR
------------- RC I
CSxN
RL
RG
--------IPHASEx
⋅=⇒⋅ IINFOx
==
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Figure 10. Current reading
The current read through the CSxP / CSxN pairs is converted into a current IINFOx propor-
tional to the current delivered by each phase and the information about the average current
IAVG = ΣIINFOx / N is internally built into the device (N is the number of working phases). The
error between the read current IINFOx and the reference IAVG is then converted into a voltage
that with a proper gain is used to adjust the duty cycle whose dominant value is set by the
voltage error amplifier in order to equalize the current carried by each phase.
7.3 CORE section - defining load-line
L6717 introduces a dependence of the output voltage on the load current recovering part of
the drop due to the output capacitor ESR in the load transient. Introducing a dependence of
the output voltage on the load current, a static error, proportional to the output current,
causes the output voltage to vary according to the sensed current.
Figure 10 shows the current sense circuit used to implement the load-line. The current flow-
ing across the inductor(s) is read through the R - C filter across CSxP and CSxN pins. RG
programs a trans-conductance gain and generates a current ICSx proportional to the current
of the phase. The sum of the ICSx current, with proper gain defined by the DRP_ADJ com-
mand (kDRP), is then sourced by the FB pin (kDRPIDROOP). RFB gives the final gain to pro-
gram the desired load-line slope (Figure 9).
Time constant matching between the inductor (L / DCR) and the current reading filter (RC)
is required to implement a real equivalent output impedance of the system so avoiding over
and/or under shoot of the output voltage as a consequence of a load transient. See
Section 7.2. The output characteristic vs. load current is then given by:
Where RLL is the resulting load-line resistance implemented by the CORE Section. kDRP
value is determined by the Power Manager I2C and its default value is 1/4.
RFB resistor can be then designed according to the RLL specifications and DRP_ADJ setting
as follow:
See Section 6.2 for details about DRP_ADJ command.
Lx
CSxP
CSxN
DCRx
R
C
RG
IPHASEx
Inductor DCR Current Sense
ICSxN=IINFOx
VOUT
VCORE VID RFB kDRP IDROOP
⋅⋅–VID kDRP RFB
DCR
RG
------------- IOUT
⋅⋅ ⋅–VID RLL IOUT
⋅–== =
RFB
RLL
kDRP
-------------
RG
DCR
-------------
⋅=
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L6717 Output voltage positioning
Doc ID 17326 Rev 1 37/56
7.4 CORE section - analog offset (Optional - I2CDIS = 3.3 V)
When power manager I2C is disabled (I2CDIS = 3.3 V), L6717 still provide the way to add
positive/negative offset to the CORE section. In this particular conditions, the pin SCL/OS
becomes a virtual ground and allows programming a positive/negative offset (V
OS
) for the
CORE section output voltage by connecting a resistor R
OS
to SGND/VCC. The pin is inter-
nally fixed at 1.240 V (2.0 V in case of negative offset, ROS tied to VCC) so a current is pro-
grammed by connecting the resistor R
OS
between the pin and SGND/VCC: this current is
mirrored and then properly sunk/sourced from the FB pin as shown in Figure 9. Output volt-
age is then programmed as follow:
Offset resistor can be designed by considering the following relationship (R
FB
is be fixed by
the droop effect):
(positive offset)
(negative offset)
Caution: Offset implementation is optional, in case it is not desired, simply short the pin to GND.
Note: In the above formulas, RFB has to be considered being the total resistance connected
between FB pin and the regulated voltage. kDRP has to be considered having its default
value since power manager I2C is disabled.
7.5 NB section - current reading
NB section performs the same differential current reading across DCR as the CORE Sec-
tion. According to Section 7.2, the current that flows from the NB_CSN pin is then given by
the following equation (See Figure 10):
RG_NB resistor is typically designed according to the OC threshold. See Section 8.4 for
details.
7.6 NB section - defining load-line
This method introduces a dependence of the output voltage on the load current recovering
part of the drop due to the output capacitor ESR in the load transient. Introducing a depen-
dence of the output voltage on the load current, a static error, proportional to the output cur-
rent, causes the output voltage to vary according to the sensed current.
Figure 10 shows the current sense circuit used to implement the load-line. The current flow-
ing across the inductor DCR is read through RG_NB. RG_NB programs a trans-conductance
gain and generates a current IDROOP_NB proportional to the current delivered by the NB
Section that is then sourced from the NB_FB pin with proper gain defined by the DRP_ADJ
VCORE VID RFB kDRP IDROOP
⋅IOS
–()⋅–=
ROS
1.240V
VOS
-------------------RFB
⋅=
ROS
VCC 2.0V–
VOS
--------------------------------RFB
⋅=
INB_CSN
DCR(NB)
RG_NB
-------------------------INB
⋅IDROOP_NB
==
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Output voltage positioning L6717
38/56 Doc ID 17326 Rev 1
command (kDRPNB). RFB_NB gives the final gain to program the desired load-line slope
(Figure 9).
The output characteristic vs. load current is then given by:
Where RLL_NB is the resulting Load-Line resistance implemented by the NB Section.
kDRPNB value is determined by the Power Manager I2C and its default value is 1/4.
RFB_NB resistor can be then designed according to the RLL_NB specifications and DRP_ADJ
setting as follow:
7.7 On-the-fly VID transitions
L6717 manages on-the-fly VID Transitions that allow the output voltage of both sections to
modify during normal device operation for CPU power management purposes. OV, UV and
PWRGOOD signals are masked during every OTF-VID Transition and they are re-activated
with a 16 clock cycle delay to prevent from false triggering.
When changing dynamically the regulated voltage (OTF-VID), the system needs to charge
or discharge the output capacitor accordingly. This means that an extra-current I
OTF-VID
needs to be delivered (especially when increasing the output regulated voltage) and it must
be considered when setting the over current threshold of both the sections. This current
results:
where dV
OUT
/ dT
VID
depends on the operative mode (3mV/μsec. in SVI or externally driven
in PVI).
Overcoming the OC threshold during the dynamic VID causes the device latch and disable.
Dynamic VID transition is managed in different ways according to the device operative
mode:
●PVI mode.
L6717 checks for VID code modifications (See Figure 11) on the rising-edge of an
internal additional OTFVID-clock and waits for a confirmation on the following falling
edge. Once the new code is stable, on the next rising edge, the reference starts
stepping up or down in LSB increments every two OTFVID-clock cycle until the new
VID code is reached. During the transition, VID code changes are ignored; the device
re-starts monitoring VID after the transition has finished on the next rising-edge
available. OTFVID-clock frequency (FOTFVID) is 500 kHz.
If the new VID code is more than 1 LSB different from the previous, the device will
execute the transition stepping the reference with the OTFVID-clock frequency FOTFVID
VOUT_NB=VID R
FB_NB kDRPNB IDROOP_NB
⋅⋅–
VID RFB_NB kDRPNB
DCR NB()
RG_NB
--------------------------- IOUT
⋅⋅ ⋅–VID RLL_NB IOUT_NB
⋅–=
RFB_NB
RLL_NB
kDRPNB
---------------------
RG_NB
DCR NB()
---------------------------
⋅=
IOTF-VID COUT
dVOUT
dTVID
------------------
⋅=
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H"HYHYYHYYHYYHYHY"HY
L6717 Output voltage positioning
Doc ID 17326 Rev 1 39/56
until the new code has reached. The output voltage rate of change will be of 12.5 mV /
4 μsec. = 3.125 mV/μsec.
Figure 11. PVI mode - on-the-fly VID transitions
●SVI mode.
As soon as the controller receives a new valid command to set the VID level for one (or
both) of the two sections, the reference of the involved section steps up or down
according to the target-VID with a 3 mV/μsec. slope (Typ). until the new VID code is
reached.
If a new valid command is issued during the transition, the device updates the target-
VID level and performs the on-the-fly transition up to the new code.
Pre-PWROK Metal-VID OTF-VID are not managed in this case because the Pre-
PWROK Metal VID are stored after EN is asserted.
●V_FIX mode.
L6717 checks for SVC/SVD modifications and, once the new code is stable, it steps the
reference of both sections up or down according to the target-VID with a 3 mV/μsec.
slope (Typ). until the new VID code is reached.
OV, UV and PWRGOOD are masked during the transition and re-activated with a 16 clock
cycle delay after the end of the transition to prevent from false triggering.
T
OTFVID
x 4 Step VID Transition
t
t
t
VID Sampled
VID Sampled
VID Sampled
Ref Moved (1)
Ref Moved (2)
Ref Moved (3)
Ref Moved (4)
VID Stable
VID [0:5]
Int. Reference
Vout
Tsw
VID Sampled
VID Sampled
Ref Moved (1)
Ref Moved (1)
Ref Moved (1)
VID Sampled
VID Sampled
4 x 1 Step VID Transition
T
VID
VID Sampled
VID Sampled
VID Sampled
VID Sampled
VID Sampled
VID Stable
VID Stable
VID Stable
Ref Moved (1)
VID Sampled
VID Sampled
VID Stable
VID Sampled
VID Sampled
VID Sampled
t
OTFVID Clock
Vout Slope Controlled by internal
OTFVID-Clock Oscillator
Vout Slope Controlled by external
driving circuit (T
VID
)
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Output voltage positioning L6717
40/56 Doc ID 17326 Rev 1
7.8 Soft-start
L6717 implements a soft-start to smoothly charge the output filter avoiding high in-rush cur-
rents to be required to the input power supply. In SVI mode, soft-start time is intended as the
time required by the device to set the output voltages to the Pre-PWROK Metal VID. During
this phase, the device increases the reference of the enabled section(s) from zero up to the
programmed reference in closed loop regulation. Soft-start is implemented only when VCC
is above UVLO threshold and the EN pin is set free. See Section 5 for details about the SVI
interface and how SVC/SVD are interpreted in this phase.
At the end of the digital soft-start, PWRGOOD signal is set free.
Protections are active during this phase as follow:
– Undervoltage is enabled when the reference voltage reaches 0.5 V.
– Overvoltage is always enabled according to the programmed threshold (by ROVP).
– FB disconnection is enabled.
Reference is increased with fixed dV/dt; Soft-start time depends on the programmed voltage
as follow:
Figure 12. System start-up: SVI (left) and PVI (right)
7.8.1 LS-Less Start-up
In order to avoid any kind of negative undershoot on the load side during start-up, L6717
performs a special sequence in enabling the drivers for both sections: during the soft-start
phase, the LS MOSFET is kept OFF (PWMx set to HiZ and ENDRV = 0) until the first PWM
pulse. After the first PWM pulse, the PWMx outputs switches between logic “0” and logic “1”
and ENDRV are set to logic “1”.
This particular sequence avoids the dangerous negative spike on the output voltage that
can happen if starting over a pre-biased output especially when exiting from a CORE-OFF
state.
Low-side MOSFET turn-on is masked only from the control loop point of view: protections
are still allowed to turn-ON the low-side MOSFET in case of over voltage if needed.
TSS ms[]Target_VID 2.56⋅=
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L6717 Output voltage monitoring and protections
Doc ID 17326 Rev 1 41/56
8 Output voltage monitoring and protections
L6717 monitors the regulated voltage of both sections through pin VSEN and NB_VSEN in
order to manage OV, UV and PWRGOOD. The device shows different thresholds when in
different operative conditions but the behavior in response to a protection event is still the
same as described below.
Protections are active also during soft-start (See Section 7.8) while they are masked during
OTF-VID transitions with an additional delay to avoid false triggering.
Table 20. L6717 protection at a glance
8.1 Programmable overvoltage (I2DIS = 3.3 V)
When power manager I2C is disabled, L6717 provides the possibility to adjust OV threshold
(common for both sections) through the SDA/OVP pin. Connecting the pin to the center tap
of a voltage divider from 3.3 V to SGND, the OVP threshold becomes the voltage present at
the pin.
The OVP threshold results:
L6717
Section
CORE North bridge
Overvoltage
(OV)
SVI / PVI: +250mV above reference, programmable by power manager I2C bus.
I2CDIS = 3.3V: Programmable through SDA/OVP pin.
V_FIX: Fixed to 1.8V.
Action: IC Latch; LS=ON & PWMx = 0 (if applicable);
Other section (SVI only): HiZ; FLT driven high.
Undervoltage
(UV)
VSEN, NB_VSEN = VID -400mV. Active after Ref > 500mV
Action: IC latch; both sections HiZ; FLT driven high.
PWRGOOD
PWRGOOD is the logic AND between internal CORE and NB PGOOD in SVI
mode while is the CORE section PGOOD in PVI mode.
Each PGOOD is set to zero when the related voltage falls below the
programmed reference -250mV.
Action: Section(s) continue switching, PWRGOOD driven low.
VSEN, NB_VSEN
disconnection
Set when VSEN > CS1N +600mV.
Action: UV-Like
Set when VSEN > NB_CSN +600mV.
Action: UV-Like (SVI only)
FBG, NB_FBG
disconnection
Internal comparator across the opamp to recover from GND losses.
Action: UV-Like
Over Current
(OC)
Current monitor across inductor DCR.
Dual protection, per-phase and
average.
Action: UV-Like
Current monitor across inductor DCR.
Constant current.
Action: UV-Like
On-the-fly VID Protections masked with the exception of OC with additional 16 clock delay to
prevent from false triggering (both SVI and PVI).
OVPTH 3.3 ROVPL
ROVPH R+OVPL
-------------------------------------------
⋅=
Obsolete Product(s) - Obsolete Product(s)
8.2
42/56
Analog OVP Sening
When 1he vollage sensed by VSEN and/or NB_VSEN overc
froller:
7 Permanemly sels 1he PWM of me involved secfion
seclion high in order lo keep all me low7side MOS
1he secfion in OV condifion.
7 Permanemly sefs fhe PWM of me non7involved se
ENDFlV of me non7involved secfion low in order fo
non7involved secfion.
7 Drives me 080/ FLT pin high.
7 Power supply or EN pin cycling is required lo resfa
Filler OVP pin Wlm 1nF(1yp)1o SGND.
Feed back disconnection
L6717 prowdes pofh CORE and NB secfions wi1h FB discon
ac1s in order 1o slop 1he device lrom regulaling dangerous v
sense connec1ions are lelf floaling. The prolecfion is availab
operafes lor bofh fhe posmve and negalive sense.
According 1o Figure 14, me prolecfion works as lollow:
0 CORE secfion:
Posilive sense is performed moniloring 1he CORE oufp
and CS1 N. As soon as CSlN is more man 600 mV hig
lalches in HiZ. FLT pin is driven high. A 30 “A pull7dow
fhe dewce lo delecf fhis faul1 condifion.
Nega1ive sense is performed moniloring 1he infernal 0
losses by comparing ifs ou1puf and me infernal referen
soon as me dilference between me oufpuf and fhe inpu
500 mV, fhe device lafches in HiZ. FLT pin is driven hig
0 NB seclion (SVI only)
Posifive sense is performed moniforing 1he NB ou1puf v
and NB_CSN. As soon as NB_CSN is more fhan 600 m
device lafches in HiZ. FLT pin is driven high. A 30 WA p
NB_VSEN forces fhe device fo delecf 1his faul1 condi1io
Nega1ive sense is performed moniloring 1he infernal 0
losses by comparing ifs ou1puf and me infernal referen
Doc ID 17326 Rev 1 £7]
Output voltage monitoring and protections L6717
42/56 Doc ID 17326 Rev 1
Figure 13. Analog OVP threshold
When the voltage sensed by VSEN and/or NB_VSEN overcomes the OV threshold, the con-
troller:
– Permanently sets the PWM of the involved section to zero keeping ENDRV of that
section high in order to keep all the low-side MOSFETs on to protect the load of
the section in OV condition.
– Permanently sets the PWM of the non-involved section to HiZ while keeping
ENDRV of the non-involved section low in order to realize an HiZ condition of the
non-involved section.
– Drives the OSC/ FLT pin high.
– Power supply or EN pin cycling is required to restart operations.
Filter OVP pin with 1nF(typ) to SGND.
8.2 Feedback disconnection
L6717 provides both CORE and NB sections with FB disconnection protection. This feature
acts in order to stop the device from regulating dangerous voltages in case the remote
sense connections are left floating. The protection is available for both the sections and
operates for both the positive and negative sense.
According to Figure 14, the protection works as follow:
●CORE section:
Positive sense is performed monitoring the CORE output voltage through both VSEN
and CS1N. As soon as CS1N is more than 600 mV higher than VSEN, the device
latches in HiZ. FLT pin is driven high. A 30 μA pull-down current on the VSEN forces
the device to detect this fault condition.
Negative sense is performed monitoring the internal OpAmp used to recover the GND
losses by comparing its output and the internal reference generated by the DAC. As
soon as the difference between the output and the input of this OpAmp is higher than
500 mV, the device latches in HiZ. FLT pin is driven high.
●NB section (SVI only)
Positive sense is performed monitoring the NB output voltage through both NB_VSEN
and NB_CSN. As soon as NB_CSN is more than 600 mV higher than NB_VSEN, the
device latches in HiZ. FLT pin is driven high. A 30 μA pull-down current on the
NB_VSEN forces the device to detect this fault condition.
Negative sense is performed monitoring the internal OpAmp used to recover the GND
losses by comparing its output and the internal reference generated by the DAC. As
SDA/OVP
R
OVPH
Analog OVP Setting (I2C Disabled)
3V3
R
OVPL
C
OVP
Obsolete Product(s) - Obsolete Product(s)
8.3
8.4
8.4.1
m o
cons “a NE 5mm VVSEN AND Far; DiscoNNEcrl
PWRGOOD
I1 is an openrdrain signal se1 free after lhe softrslarl se
AND belween 1he imernal CORE and NB PGOOD (orju
I1 is pulled low when 1he oulpul vollage o1 one of me tw
programmed vollage. ll is masked during onrlherfly VID
CORE sec1ion is se110 OFF (from SVI bus) while 1he N
Overcurrent
The overcurrem lhreshold has 10 be programmed lo a
each seclion doesn'1 emer 00 during normal opera1ion
imo consideralion also lhe exlra currem needed during
lhe process spread and lemperalure varialions of lhe 5
Moreover, since also 1he in1ernal1hreshold spreads, lh
mum/maximum values of lhe 1hreshold. Considering 1h
Will show differem behawors in OC.
CORE section
L6717 performs 1wo diflerem OC proleclions for me 00
currem and lhe periphase currem and allows lo se1 an
7 Periphase 00.
Maximum inlorma1ion currem periphase (IINF
endrolrscale currem ('00 TH) is compared wi
lor each phase (I‘NFOX). lflhe currenl informa
endrolrscale currem (i.e. if IINFOX > '00 TH),1
MOSFET unlil lhe 1hreshold is rercrosseu (i.e
7 Tolal currem OC.
ILIM pin allows 10 define a maximum lolal ou
IUM currem is sourced lrom lhe ILIM pin (nor
connecling a resislor RIUM lo SGND, a load i
Doc ID 17326 Flev 1
L6717 Output voltage monitoring and protections
Doc ID 17326 Rev 1 43/56
soon as the difference between the output and the input of this OpAmp is higher than
500mV, the device latches in HiZ. FLT pin is driven high.
To recover from a latch condition, cycle VCC or EN.
Figure 14. FB disconnection protection
8.3 PWRGOOD
It is an open-drain signal set free after the soft-start sequence has finished; it is the logic
AND between the internal CORE and NB PGOOD (or just the CORE PGOOD in PVI mode).
It is pulled low when the output voltage of one of the two sections drops 250 mV below the
programmed voltage. It is masked during on-the-fly VID transitions as well as when the
CORE section is set to OFF (from SVI bus) while the NB section is still operative.
8.4 Overcurrent
The overcurrent threshold has to be programmed to a safe value, in order to be sure that
each section doesn't enter OC during normal operation of the device. This value must take
into consideration also the extra current needed during the OTF-VID transition (IOTF-VID) and
the process spread and temperature variations of the sensing elements (Inductor DCR).
Moreover, since also the internal threshold spreads, the design has to consider the mini-
mum/maximum values of the threshold. Considering the reading method, the two sections
will show different behaviors in OC.
8.4.1 CORE section
L6717 performs two different OC protections for the CORE section: it monitors both the total
current and the per-phase current and allows to set an OC threshold for both.
– Per-phase OC.
Maximum information current per-phase (IINFOx) is internally limited to 35 μA. This
end-of-scale current (IOC_TH) is compared with the information current generated
for each phase (IINFOx). If the current information for the single phase exceed the
end-of-scale current (i.e. if IINFOx > IOC_TH), the device will turn-on the LS
MOSFET until the threshold is re-crossed (i.e. until IINFOx < IOC_TH).
– Total current OC.
ILIM pin allows to define a maximum total output current for the system (IOC_TOT).
ILIM current is sourced from the ILIM pin (not altered by DRP_ADJ command). By
connecting a resistor RILIM to SGND, a load indicator with 2.5 V (VOC_TOT) end-of-
CORE_REFERENCE
FB COMP VSEN FBG
R
F
C
F
R
FB
To VDD_CORE
(Remote Sense)
from DAC...
CORE and NB SECTION - VSEN AND FBG DISCONNECTION
500mV
FBG DISCONNECTED
CS1-
30μA
600mV
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Output voltage monitoring and protections L6717
44/56 Doc ID 17326 Rev 1
scale can be implemented. When the voltage present at the ILIM pin crosses
VOC_TOT
, the device detects an OC and immediately latches with all the MOSFETs
of all the sections OFF (HiZ).
Typical design considers the intervention of the total current OC before the per-phase OC,
leaving this last one as an extreme-protection in case of hardware failures in the external
components. Typical design flow is the following:
– Define the maximum total output current (IOC_TOT) according to system
requirements
– Design per-phase OC and RG resistor in order to have IINFOx = IOC_TH (35 μA)
when IOUT is about 10% higher than the IOC_TOT current. It results:
where N is the number of phases and DCR the DC resistance of the inductors. RG
should be designed in worst-case conditions.
– Design the total current OC and RILIM in order to have the ILIM pin voltage to
VOC_TOT at the desired maximum current IOC_TOT
. It results:
where VOC_TOT is typically 2.5V and IOC_TOT is the total current OC threshold
desired.
– Adjust the defined values according to bench-test of the application.
– An additional capacitor in parallel to RILIM can be considered to add a delay in the
protection intervention.
Note: What previously listed is the typical design flow. Custom design and specifications may
require different settings and ratios between the per-phase OC threshold and the Total
Current OC threshold. Applications with huge ripple across inductors may be required to set
per-phase OC to values different than 110%: design flow should be modified accordingly.
Note: DRP_ADJ command from power manager I2C does not alter the current information used
for per-phase OC and total current OC.
RG
1.1 IOC_TOT
⋅()DCR⋅
NI⋅OCTH
--------------------------------------------------------=
RILIM
VOC_TOT RG
⋅
IOC_TOT DCR⋅
---------------------------------------= ILIM
DCR
RG
------------- IOUT
⋅=
⎝⎠
⎛⎞
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DCF
IOCJJEmax ‘
L6717 Output voltage monitoring and protections
Doc ID 17326 Rev 1 45/56
8.4.2 NB section
NB section performs per-phase over current: its maximum information current (IINFO_NB) is
internally limited to IOCTH_NB (35 μA typ). If the current information for the NB phase
exceeds the end-of-scale current (i.e. if IINFO_NB > IOCTH_NB), the device will turn-on the
low-side MOSFET, also skipping clock cycles, until the threshold is re-crossed (i.e. until
IINFO_NB < IOCTH_NB).
After exiting the OC condition, the low-side MOSFET is turned off and the high-side is
turned on with a duty cycle driven by the PWM comparator.
Design RG_NB resistor in order to have IDROOP_NB = IOCTH_NB (35μA) at the IOC_NBmax
current.
It results:
Note: DRP_ADJ command from power manager I2C does not alter the current information used
for per-phase OC.
RGNB
IOC_NBmax DC
R
⋅
IOCTH_NB
------------------------------------------
-
=
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Hose
Main oscillator L6717
46/56 Doc ID 17326 Rev 1
9 Main oscillator
The controller embeds a dual-oscillator: one section is used for the CORE and it is a multi-
phase programmable oscillator managing equal phase-shift among all phases and the other
section is used for the NB section. Phase-shift between the CORE and NB ramps is
automatically adjusted according to the CORE phase # programmed.
The internal oscillator generates the triangular waveform for the PWM charging and
discharging with a constant current an internal capacitor. The switching frequency for each
channel, F
SW
, is internally fixed at 200 kHz: the resulting switching frequency for the CORE
section at the load side results in being multiplied by N (number of configured phases).
The current delivered to the oscillator is typically 20 μA (corresponding to the free running
frequency F
SW
=200 kHz) and it may be varied using an external resistor (R
OSC
) typically
connected between the OSC pin and SGND. Since the OSC pin is fixed at 1.240 V, the
frequency is varied proportionally to the current sunk from the pin considering the internal
gain of 9.1 kHz/μA (See Figure 15).
Connecting R
OSC
to SGND the frequency is increased (current is sunk by the pin),
according to the following relationships:
Connecting R
OSC
to a positive voltage (recommended 3.3 V rail) the frequency is reduced
(current is injected into the pin), according to the following relationships:
where +V is the positive voltage which the ROSC resistor is connected.
Figure 15. R
OSC
vs. switching frequency
FSW 200kHz 1.240V
ROSC
-------------------9.1kHz
μA
-----------
⋅+=
FSW 200kHz +V 1.240–
ROSC
---------------------------- 9.1kHz
μA
-----------
⋅–=
FSW vs. Rosc
75
125
175
225
275
325
375
425
0 50 100 150 200 250 300 350 400 450
Rosc [kOhm]
Fsw [kHz]
Rosc+ (to SGND)
Rosc- (to 3V3)
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L6717 High current embedded drivers
Doc ID 17326 Rev 1 47/56
10 High current embedded drivers
L6717 provides high-current driving control for CORE and NB sections. The driver for the
high-side MOSFET use BOOTx pin for supply and PHASEx pin for return. The driver for the
low-side MOSFET use the VCCDR pin for supply and GND pin for return.
The embedded driver embodies an anti-shoot-through and adaptive dead-time control to
minimize low-side body diode conduction time maintaining good efficiency saving the use of
Schottky diodes: when the high-side MOSFET turns off, the voltage on its source begins to
fall; when the voltage reaches about 2 V, the low-side MOSFET gate drive voltage is
suddenly applied. When the low-side MOSFET turns off, the voltage at LGATE pin is
sensed. When it drops below about 1 V, the high-side MOSFET gate drive voltage is
suddenly applied. If the current flowing in the inductor is negative, the source of high-side
MOSFET will never drop. To allow the low-side MOSFET to turn-on even in this case, a
watchdog controller is enabled: if the source of the High-Side MOSFET doesn't drop, the
low-side MOSFET is switched on so allowing the negative current of the inductor to
recirculate. This mechanism allows the system to regulate even if the current is negative.
10.1 Boot capacitor design
Bootstrap capacitor needs to be designed in order to show a negligible discharge due to the
high-side MOSFET turn-on. In fact it must give a stable voltage supply to the high-side driver
during the MOSFET turn-on also minimizing the power dissipated by the embedded boot
diode. Figure 16 gives some guidelines on how to select the capacitance value for the
bootstrap according to the desired discharge and depending on the selected MOSFET.
To prevent bootstrap capacitor to extra-charge as a consequence of large negative spikes,
an external series resistance RBOOT (in the range of few ohms) may be required in series to
BOOT pin.
Figure 16. Bootstrap capacitor design
0.0
0.5
1.0
1.5
2.0
2.5
0 102030405060708090100
High-Side MOSFET Gate Charge [nC]
BOOT Cap discharge [V]
Cboot = 47nF
Cboot = 100nF
Cboot = 220nF
Cboot = 330nF
Cboot = 470nF
0
500
1000
1500
2000
2500
0.0 0.2 0.4 0.6 0.8 1.0
Boot Cap Delta Voltage [V]
Bootstrap Cap [uF]
Qg = 10nC
Qg = 25nC
Qg = 50nC
Qg = 100nC
Obsolete Product(s) - Obsolete Product(s)
High current embedded drivers L6717
48/56 Doc ID 17326 Rev 1
10.2 Power dissipation
It is important to consider the power that the device is going to dissipate in driving the exter-
nal MOSFETs in order to avoid overcoming the maximum junction operative temperature.
Two main terms contribute in the device power dissipation: bias power and drivers' power.
●Device power (PDC) depends on the static consumption of the device through the
supply pins and it is simply quantifiable as follow:
●Drivers' power is the power needed by the driver to continuously switch ON and OFF
the external MOSFETs; it is a function of the switching frequency and total gate charge
of the selected MOSFETs. It can be quantified considering that the total power PSW
dissipated to switch the MOSFETs dissipated by three main factors: external gate
resistance (when present), intrinsic MOSFET resistance and intrinsic driver resistance.
This last term is the important one to be determined to calculate the device power
dissipation.
The total power dissipated to switch the MOSFETs for each phase featuring embedded
driver results:
Where QGHSx is the total gate charge of the HS MOSFETs and QGLSx is the total gate
charge of the LS MOSFETs for both CORE and NB sections (only Phase1 and Phase2
for CORE section); VBOOTx is the driving voltage for the HSx MOSFETs.
PDC VCC ICC VVCCDR IVCCDR
⋅+⋅=
PSWx FSW QGLSx VCCDR⋅QGHSx VBOOTx⋅+()⋅=
Obsolete Product(s) - Obsolete Product(s)
This means 1ha1 lhe same analysis can be used for bolh lhe seclions wi1h ihe only exceplion
of me differem equivalem induclor value (L=LNB for NB seclion and L=LcoRE/N for me
CORE seclion) and lhe currem reading gain (DCR/RG NB for NB Seclion and DCFl/FlG for
ihe COFlE seclion). 7
The comrol loop gain resulls (oblained opening 1he loop allerlhe COMP pm):
Where:
0 RLL is me equivalem ouipul resislance delermined by lhe droop funclion;
o Zp(s) is ihe impedance resulling by ihe parallel ol 1he ouipm capacilor (and ils ESFl)
and me applied load Flo;
Z;(s) is me compensalion network impedance;
ZL(s) is me equivalem induclor impedance;
A(s) is ihe error amplifier gain;
is me PWM lransler funclion.
The con1rol loop gain lor each seclion is designed in order lo obiain a high DC gain lo
minimize slaiic error and 10 cross lhe OdB axes wi1h a conslanl 720 dB/Dec. slope wi1h lhe
desired crossover lrequency ruT. Neglecling 1he ef‘lecl o1 ZF(s), ihe 1ransferfunc1ion has one
zero and lwo poles; bolh ihe poles are fixed once 1he oulpm filler is designed (LC liller
resonance mm) and me zero (ruESR) is fixed by ESFl and me droop resislance.
Doc ID 17326 Flev 1 49/56
L6717 System control loop compensation
Doc ID 17326 Rev 1 49/56
11 System control loop compensation
The device embeds two separate and independent control loops for CORE and NB section.
The control loop for NB section is a simple voltage-mode control loop with (optional) voltage
positioning featured when DROOP pin is shorted with FB. The control loop for the CORE
section also features a current-sharing loop to equalize the current carried by each of the
configured phases.
The CORE control system can be modeled with an equivalent single-phase converter
whose only difference is the equivalent inductor L/N (where each phase has an L inductor
and N is the number of the configured phases). See Figure 17.
Figure 17. Equivalent control loop for NB and CORE sections
This means that the same analysis can be used for both the sections with the only exception
of the different equivalent inductor value (L=LNB for NB section and L=LCORE/N for the
CORE section) and the current reading gain (DCR/RG_NB for NB Section and DCR/RG for
the CORE section).
The control loop gain results (obtained opening the loop after the COMP pin):
Where:
●R
LL
is the equivalent output resistance determined by the droop function;
●Z
P
(s) is the impedance resulting by the parallel of the output capacitor (and its ESR)
and the applied load R
O
;
●Z
F
(s) is the compensation network impedance;
●Z
L
(s) is the equivalent inductor impedance;
●A(s) is the error amplifier gain;
● is the PWM transfer function.
The control loop gain for each section is designed in order to obtain a high DC gain to
minimize static error and to cross the 0dB axes with a constant -20 dB/Dec. slope with the
desired crossover frequency ω
T
. Neglecting the effect of Z
F
(s), the transfer function has one
zero and two poles; both the poles are fixed once the output filter is designed (LC filter
resonance ω
LC
) and the zero (ω
ESR
) is fixed by ESR and the droop resistance.
Ref
NB_COMP
NB_VSEN
NB_FBG
R
F_NB
C
F_NB
R
FB_NB
PWM
L
NB
ESR_NB
C
O_NB
R
O_NB
d V
NB_COMP
V
OUT_NB
Z
F
(s)
Z
FB
(s)
k
DRPNB
I
DROOP_NB
VID_NB
V
NB_COMP
Ref
COMP
VSEN
FBG
R
F
C
F
R
FB
PWM
L
CORE
/N
ESR
C
O
R
O
d V
COMP
V
OUT
Z
F
(s)
Z
FB
(s)
k
DRP
I
DROOP
VID_CORE
V
COMP
FB NB_FB
GLOOP s() PWM ZFs() RLL ZPs()+()⋅⋅
ZPs() ZLs()+[]
ZFs()
As()
-------------- 11
As()
------------+
⎝⎠
⎛⎞
RFB
⋅+⋅
-------------------------------------------------------------------------------------------------------------------–=
PWM 3
5
---
VIN
ΔVOSC
-------------------
⋅=
Obsolete Product(s) - Obsolete Product(s)
System control loop compensation L6717
50/56 Doc ID 17326 Rev 1
Figure 18. Control loop bode diagram and fine tuning (not in scale)
To obtain the desired shape an R
F
-C
F
series network is considered for the Z
F
(s)
implementation. A zero at ω
F
=1/R
F
C
F
is then introduced together with an integrator. This
integrator minimizes the static error while placing the zero ω
F
in correspondence with the L-
C resonance assures a simple -20 dB/Dec. shape of the gain.
In fact, considering the usual value for the output filter, the LC resonance results to be at
frequency lower than the above reported zero.
Compensation network can be simply designed placing ω
F
=ω
LC
and imposing the cross-
over frequency ω
T
as desired obtaining (always considering that ω
T
might be not higher than
1/10th of the switching frequency F
SW
):
11.1 Compensation network guidelines
The compensation network design assures to having system response according to the
cross-over frequency selected and to the output filter considered: it is anyway possible to
further fine-tune the compensation network modifying the bandwidth in order to get the best
response of the system as follow (See Figure 18):
– Increase R
F
to increase the system bandwidth accordingly;
– Decrease R
F
to decrease the system bandwidth accordingly;
– Increase C
F
to move ω
F
to low frequencies increasing as a consequence the
system phase margin.
Having the fastest compensation network gives not the confidence to satisfy the
requirements of the load: the inductor still limits the maximum dI/dt that the system can
afford. In fact, when a load transient is applied, the best that the controller can do is to
“saturate” the duty cycle to its maximum (d
MAX
) or minimum (0) value. The output voltage
dV/dt is then limited by the inductor charge / discharge time and by the output capacitance.
In particular, the most limiting transition corresponds to the load removal since the inductor
results being discharged only by V
OUT
(while it is charged by d
MAX
V
IN
-V
OUT
during a load
appliance).
dB
ω
Z
F
(s)
G
LOOP
(s)
K
ω
LC =
ω
F
ω
ESR
ω
T
R
F
[dB]
dB
ω
Z
F
(s)
G
LOOP
(s)
K
ω
LC =
ω
F
ω
ESR
ω
T
R
F
[dB]
R
F
C
F
RF
RFB ΔVOSC
⋅
VIN
----------------------------------3
5
---ωT
L
NR
LL ESR+()⋅
-------------------------------------------
⋅⋅ ⋅=
CF
COL⋅
RF
--------------------=
Obsolete Product(s) - Obsolete Product(s)
The LTB deleclor is able lo delecl ou1pu1 load lransiems by coupling lhe pulp
lhrough an FlLTB . CLTB ne1work.Allerdelec1ing a load 1ransien1, 1he LTB Flam
lhen compared wi1h lhe COMP pin level. The resulling dulyrcycle programme
ed wi1h lhe PWMx signal of each phase byrpassing 1he main comrol loop. All
lhen be 1urnedron logelher and me EA lalenCies resulls bypassed as well.
Sensilivity of lhe load 1ransien1 deleclor can be programmed in orderlo conlr
bolh 1he undershool and me ringrback.
RLTB . CUB is designed according lo 1he oulpul vollage devialion dVoUT which
comroller lo be sensilive as lollow:
LTB Technology/E design tips.
7 Decrease FlLTB lo increase lhe syslem sensmvily making me syslem
smaller dVouT-
7 Increase CUB lo increase 1he syslem sensilivily making lhe syslem
higher dV/dl.
Doc ID 17326 Flev 1
L6717 LTB Technology®
Doc ID 17326 Rev 1 51/56
12 LTB Technology®
LTB Te ch n ol o gy® further enhances the performances of dual-edge asynchronous systems
by reducing the system latencies and immediately turning ON all the phases to provide the
correct amount of energy to the load. By properly designing the LTB network as well as the
LTB gain, the undershoot and the ring-back can be minimized also optimizing the output
capacitors count. LTB Technology® applies only to the CORE section.
LTB Te ch n ol o gy® monitors the output voltage through a dedicated pin detecting Load-
Transients with selected dV/dt, it cancels the interleaved phase-shift, turning-on
simultaneously all phases. it then implements a parallel, independent loop that reacts to
load-transients bypassing E/A latencies.
LTB Te ch n ol o gy® control loop is reported in Figure 19.
Figure 19. LTB Technology® control loop (CORE section)
The LTB detector is able to detect output load transients by coupling the output voltage
through an RLT B - CLTB network. After detecting a load transient, the LTB Ramp is reset and
then compared with the COMP pin level. The resulting duty-cycle programmed is then OR-
ed with the PWMx signal of each phase by-passing the main control loop. All the phases will
then be turned-on together and the EA latencies results bypassed as well.
Sensitivity of the load transient detector can be programmed in order to control precisely
both the undershoot and the ring-back.
RLTB - CLTB is designed according to the output voltage deviation dVOUT which is desired the
controller to be sensitive as follow:
LTB Te ch n ol o gy® design tips.
– Decrease RLT B to increase the system sensitivity making the system sensitive to
smaller dVOUT
.
– Increase CLTB to increase the system sensitivity making the system sensitive to
higher dV/dt.
Ref
FBCOMP VSEN
FBG
R
F
C
F
R
FB
PWM
L/N
ESR
C
O
R
O
d V
COMP
V
OUT
Z
F
(s) Z
FB
(s)
VID
V
COMP
C
H
C
FB
LTB
Monitor
R
LTB
C
LTB
PWM_BOOST
LTB Ramp
LTB LT Detect
LT Detect
RLTB
dVOUT
25μA
------------------=CLTB
1
2πNR
LTB FSW
⋅⋅ ⋅
--------------------------------------------------=
Obsolete Product(s) - Obsolete Product(s)
eNmPAm FHASEX
LSX DRWER HSX DR‘VER
52/56 Doc ID 17326 Rev 1 £7]
Layout guidelines L6717
52/56 Doc ID 17326 Rev 1
13 Layout guidelines
Layout is one of the most important things to consider when designing high current
applications. A good layout solution can generate a benefit in lowering power dissipation on
the power paths, reducing radiation and a proper connection between signal and power
ground can optimize the performance of the control loops.
Two kind of critical components and connections have to be considered when laying-out a
VRM based on L6717: power components and connections and small signal components
connections.
13.1 Power components and connections
These are the components and connections where switching and high continuous current
flows from the input to the load. The first priority when placing components has to be
reserved to this power section, minimizing the length of each connection and loop as much
as possible. To minimize noise and voltage spikes (EMI and losses) these interconnections
must be a part of a power plane and anyway realized by wide and thick copper traces: loop
must be anyway minimized. The critical components, i.e. the power transistors, must be
close one to the other. The use of multi-layer printed circuit board is recommended.
Traces between the driver section and the MOSFETs should be wide to minimize the
inductance of the trace so minimizing ringing in the driving signals. Moreover, VIAs count
needs to be minimized to reduce the related parasitic effect.
Locate the bypass capacitor (VCC, VCCDR and BOOT capacitors) close to the device with
the shortest possible loop and use wide copper traces to minimize parasitic inductance.
Systems that do not use Schottky diodes in parallel to the low-side MOSFET might show big
negative spikes on the phase pin. This spike can be limited as well as the positive spike but
it causes the bootstrap capacitor to be over-charged. This extra-charge can cause, in the
worst case condition of maximum input voltage and during particular transients, that boot-to-
phase voltage overcomes the abs.max.ratings also causing device failures. It is then
suggested in this cases to limit this extra-charge by adding a small resistor RBOOT in series
to the boot capacitor or the boot diode. The use of RBOOT also contributes in the limitation of
the spike present on the BOOT pin.
Figure 20. Driver turn-on and turn-off paths
R
GATE
R
INT
C
GD
C
GS
C
DS
VCCDR
LSx DRIVER LS MOSFET
GND (PAD)
LGATEx
R
GATE
R
INT
C
GD
C
GS
C
DS
BOOTx
HSx DRIVER HS MOSFET
PHASEx
HGATEx
R
BOOT
Obsolete Product(s) - Obsolete Product(s)
L6717 Layout guidelines
Doc ID 17326 Rev 1 53/56
For heat dissipation, place copper area under the IC. This copper area must be connected
with internal copper layers through several VIAs to improve the thermal conductivity. The
combination of copper pad, copper plane and VIAs under the controller allows the device to
reach its best thermal performances.
13.2 Small signal components and connections
These are small signal components and connections to critical nodes of the application as
well as bypass capacitors for the device supply. Locate the bypass capacitor close to the
device and refer sensible components such as frequency set-up resistor R
OSC
, offset
resistor and OVP resistor R
OVP
to SGND (when applicable). Star grounding is suggested:
use the device exposed PAD as a connection point.
VSEN pin filtered vs. SGND helps in reducing noise injection into device and EN pin filtered
vs. SGND helps in reducing false trip due to coupled noise: take care in routing driving net
for this pin in order to minimize coupled noise.
Remote buffer connection must be routed as parallel nets from the FBG/FBR pins to the
load in order to avoid the pick-up of any common mode noise. Connecting these pins in
points far from the load will cause a non-optimum load regulation, increasing output
tolerance.
Locate current reading components close to the device. The PCB traces connecting the
reading point must use dedicated nets, routed as parallel traces in order to avoid the pick-up
of any common mode noise. It's also important to avoid any offset in the measurement and,
to get a better precision, to connect the traces as close as possible to the sensing elements.
Symmetrical layout is also suggested. Small filtering capacitor can be added, near the
controller, between V
OUT
and SGND, on the CSxN line when reading across inductor to
allow higher layout flexibility.
Obsolete Product(s) - Obsolete Product(s)
u 2
”2 EXPOSED FAD \ :32?
Q - wwwiwwww
» 33 w "
g 3 I E N
l g \ g E
a \ E
3 ‘ E
’5 ””” \ ”””” E ' “
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3 ‘ E
3 E
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JEL b A
BOTTOM V‘EW S‘DE V‘EW
54/56 Doc ID 17326 Flev
VFQFPN48 mechanical data and package dimensions L6717
54/56 Doc ID 17326 Rev 1
14 VFQFPN48 mechanical data and package dimensions
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Figure 21. VFQFPN48 mechanical data and package dimensions
OUTLINE AND
MECHANICAL DATA
DIM.
mm
MIN. TYP. MAX. MIN. TYP. MAX.
A 0.800 0.900 1.000 31.50 39.37
A3 0.200 7.874
b 0.180 0.250 0.300 7.087 9.843 11.81
D 6.900 7.000 7.100 271.6 275.6 279.5
D2 5.050 5.150 5.250 198.8 .202.7 206.7
E 6.900 7.000 7.100
E2 5.050 5.150 5.250
e 0.500 19.68
L 0.300 0.400 0.500 11.81 15.75
ddd 0.080 3.150
VFQFPN-48 (7x7x1.0mm)
Very Fine Quad Flat Package No lead
ddd
mils
35.43
271.6 275.6 279.5
198.8 202.7 206.7
19.68
Obsolete Product(s) - Obsolete Product(s)
L6717 Revision history
Doc ID 17326 Rev 1 55/56
15 Revision history
Table 21. Document revision history
Date Revision Changes
29-Mar-2010 1Initial release.
Obsolete Product(s) - Obsolete Product(s)
L6717
56/56 Doc ID 17326 Rev 1
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