MC33290 Datasheet by NXP USA Inc.

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0" :o" freescale'“ semtcanducmr
Document Number: MC33290
Rev 8.0, 8/2008
Freescale Semiconductor
Technical Data
Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as
may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2006-2008. All rights reserved.
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ISO K Line Serial Link Interface
The 33290 is a serial link bus interface device designed to provide
bi-directional half-duplex communication interfacing in automotive
diagnostic applications. It is designed to interface between the
vehicle’s on-board microcontroller and systems off-board the vehicle
via the special ISO K line. The 33290 is designed to meet the
Diagnostic Systems ISO9141 specification. The device’s K line bus
driver’s output is fully protected against bus shorts and
overtemperature conditions.
The 33290 derives its robustness to temperature and voltage
extremes by being built on a SMARTMOS process, incorporating
CMOS logic, bipolar/MOS analog circuitry, and DMOS power FETs.
Although the 33290 was principally designed for automotive
applications, it is suited for other serial communication applications.
It is parametrically specified over an ambient temperature range of
-40ºC TA 125ºC and 8.0 V VBB 18 V supply. The economical
SO-8 surface-mount plastic package makes the 33290 very cost
effective.
Features
Operates Over Wide Supply Voltage of 8.0 to 18V
Operating Temperature of -40 to 125°C
Interfaces Directly to Standard CMOS Microprocessors
ISO K Line Pin Protected Against Shorts to Ground
Thermal Shutdown with Hysteresis
ISO K Line Pin Capable of High Currents
ISO K Line Can Be Driven with up to 10 nF of Parasitic
Capacitance
8.0 kV ESD Protection Attainable with Few Additional Components
Standby Mode: No VBat Current Drain with VDD at 5.0 V
Low Current Drain During Operation with VDD at 5.0 V
Pb-Free Packaging Designated by Suffix Code EF
Figure 1. 33290 Simplified Application Diagram
ISO9141 PHYSICAL INTERFACE
D SUFFIX
EF SUFFIX (PB-FREE)
98ASB42564B
8-PIN SOICN
33290
ORDERING INFORMATION
Device Temperature
Range (TA)Package
MC33290D/R2 -40 to 125°C 8-SOICN
MCZ33290EF/R2
VDD
Dx
SCIR
xD
SCIT
xD
VDD
33290
+VBAT
ISO K-Line
RxD
TxD
MCU
RX
TX
CEN
VDD
VBB
GND
ISO
Analog Integrated Circuit Device Data
2Freescale Semiconductor
33290
INTERNAL BLOCK DIAGRAM
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INTERNAL BLOCK DIAGRAM
Figure 2. 33290 Simplified Block Diagram
VBB
CEN
VDD
TX
RX
ISO
40 V
Thermal
Shutdown
RHys
Master
Bias
6
4
3
1
8
7
5
3.0 kΩ
20 V50 V
10 V 10 V
10 V 10 V
2.0 kΩ
200 Ω
GND
125 kΩ
125 kΩ
III: IIII
Analog Integrated Circuit Device Data
Freescale Semiconductor 3
33290
PIN CONNECTIONS
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PIN CONNECTIONS
Figure 3. 33290 Pin Connections
Table 1. 33290 Pin Definitions
Pin Number Pin Name Definition
1VBB Battery power through external resistor and diode.
2NC Not to be connected. (1)
3GND Common signal and power return.
4ISO Bus connection.
5TX Logic level input for data to be transmitted on the bus.
6RX Logic output of data received on the bus.
7VDD Logic power source input.
8CEN Chip enable. Logic “1” for active state. Logic “0” for sleep state.
Notes
1. NC pins should not have any connections made to them. NC pins are not guaranteed to be open circuits.
2
3
4
8
7
6
5
1
1
2
4
3
8
7
5
6
CEN
VDD
TX
VBB
NC
GND
ISO
RX
IVIAA/
Analog Integrated Circuit Device Data
4Freescale Semiconductor
33290
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
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ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Rating Symbol Value Unit
VDD DC Supply Voltage VDD -0.3 to 7.0 V
VBB Load Dump Peak Voltage VBB(LD) 45 V
ISO Pin Load Dump Peak Voltage (2) VISO 40 V
ISO Short Circuit Current Limit IISO(LIM) 1.0 A
ESD Voltage (3)
Human Body Model (4)
Machine Model (4)
VESD1
VESD2
±2000
±200
V
ISO Clamp Energy (5) Eclamp 10 mJ
Storage Temperature Tstg -55 to +150 °C
Operating Case Temperature TC-40 to +125 °C
Operating Junction Temperature TJ-40 to +150 °C
Power Dissipation
TA = 25°C
PD
0.8
W
Peak Package Reflow Temperature During Reflow (6), (7) TPPRT Note 7. °C
Thermal Resistance
Junction-to-Ambient
RθJA
150
°C/W
Notes
2. Device will survive double battery jump start conditions in typical applications for 10 minutes duration, but is not guaranteed to remain
within specified parametric limits during this duration.
3. ESD data available upon request.
4. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in
accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
5. Nonrepetitive clamping capability at 25°C.
6. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
7. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL),
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.
MC33xxxD enter 33xxx), and review parametrics.
Analog Integrated Circuit Device Data
Freescale Semiconductor 5
33290
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
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STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions of 4.75 V VDD 5.25 V, 8.0 V VBB 18 V, -40°C TC 125°C, unless otherwise
noted.
Characteristic Symbol Min Typ Max Unit
POWER AND CONTROL
VDD Sleep State Current
Tx = 0.8 VDD, CEN = 0.3 VDD
IDD(SS)
0.1
mA
VDD Quiescent Operating Current
Tx = 0.2 VDD, CEN = 0.7 VDD
IDD(Q)
1.0
mA
VBB Sleep State Current
VBB = 16 V, Tx = 0.8 VDD, CEN = 0.3 VDD
IBB(SS)
50
µA
VBB Quiescent Operating Current
TX = 0.2 VDD, CEN = 0.7 VDD
IBB(Q)
1.0
mA
Chip Enable
Input High-Voltage Threshold (8)
Input Low-Voltage Threshold (9)
VIH(CEN)
VIL(CEN)
0.7 VDD
0.3 VDD
V
Chip Enable Pull-Down Current (10) IPD(CEN) 2.0 40 µA
TX Input Low-Voltage Threshold
RISO = 510 Ω (11)
VIL(Tx)
0.3 x VDD
V
TX Input High-Voltage Threshold
RISO = 510 Ω (12)
VIH(Tx)
0.7 x VDD – –
V
TX Pull-Up Current (13) IPU(Tx) -40 -2.0 µA
RX Output Low-Voltage Threshold
RISO = 510 Ω, TX = 0.2 VDD, Rx Sinking 1.0 mA
VOL(Rx)
0.2 VDD
V
RX Output High-Voltage Threshold
RISO = 510 Ω, TX = 0.8 VDD, RX Sourcing 250 µA
VOH(Rx) 0.8 VDD – –
V
Thermal Shutdown (14) TLIM 150 170 °C
Notes
8. When IBB transitions to >100 µA.
9. When IBB transitions to <100 µA.
10. Enable pin has an internal current pull-down. Pull-down current is measured with CEN pin at 0.3 VDD.
11. Measured by ramping TX down from 0.7 VDD and noting TX value at which ISO falls below 0.2 VBB.
12. Measured by ramping TX up from 0.3 VDD and noting the value at which ISO rises above 0.9 VBB.
13. Tx pin has internal current pull-up. Pull-up current is measured with TX pin at 0.7 VDD.
14. Thermal Shutdown performance (TLIM) is guaranteed by design but not production tested.
oml'
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6Freescale Semiconductor
33290
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
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Table 3. Static Electrical Characteristics (Continued)
Characteristics noted under conditions of 4.75 V VDD 5.25 V, 8.0 V VBB 18 V, -40°C TC 125°C, unless otherwise
noted.
Characteristic Symbol Min Typ Max Unit
ISO I/O
Input Low Voltage Threshold
RISO = 0 Ω, TX = 0.8 VDD (15)
VIL(ISO)
0.4 x VBB
V
Input High Voltage Threshold
RISO = 0 Ω, TX = 0.8 VDD (16)
VIH(ISO)
0.7 x VBB – –
V
Input Hysteresis (17) VHys(ISO) 0.05 x VBB 0.1 x VBB V
Internal Pull-Up Current
RISO = Ω, TX = 0.8 VDD, VISO = 9.0 V, VBB = 18 V
IPU(ISO)
-5.0 -140
µA
Short Circuit Current Limit (18)
RISO = 0 Ω, TX = 0.4 VDD, VISO = VBB
ISC(ISO)
50 1000
mA
Output Low Voltage
RISO = 510 Ω, TX = 0.2 VDD
VOL(ISO)
0.1 x VBB
V
Output High Voltage
RISO = Ω, TX = 0.8 VDD
VOH(ISO)
0.95 x VBB – –
V
Notes
15. ISO ramped from 0.8 VBB to 0.4 VBB, Monitor RX, Value of ISO voltage at which RX transitions to 0.3 VDD.
16. ISO ramped from 0.4 VBB to 0.8 VBB, Monitor RX, Value of ISO voltage at which RX transitions to 0.7 VDD.
17. Input Hysteresis, VHys(ISO) = VIH(ISO) - VIL(ISO).
18. ISO has internal current limiting.
Analog Integrated Circuit Device Data
Freescale Semiconductor 7
33290
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
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DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions of 4.75 V VDD 5.25 V, 8.0 V VBB 18 V, -40°C TC 125°C, unless otherwise
noted.
Characteristic Symbol Min Typ Max Unit
Fall Time (19)
RISO = 510 Ω to VBB, CISO = 10 nF to Ground
tfall(ISO)
2.0
µs
ISO Propagation Delay (20)
High to Low: RISO = 510 Ω, CISO = 500 pF (21)
Low to High: RISO = 510 Ω, CISO = 500 pF (22)
tPD(ISO)
2.0
2.0
µs
Notes
19. Time required ISO voltage to transition from 0.8 VBB to 0.2 VBB.
20. Changes in the value of CISO affect the rise and fall time but have minimal effect on Propagation Delay.
21. Step TX voltage from 0.2 VDD to 0.8 VDD. Time measured from VIH(ISO) until VISO reaches 0.3 VBB.
22. Step TX voltage from 0.8 VDD to 0.2 VDD. Time measured from VIL(ISO) until VISO reaches 0.7 VBB.
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33290
ELECTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES
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ELECTRICAL PERFORMANCE CURVES
Figure 4. ISO Input Threshold/VBB vs. Temperature
Figure 5. ISO Output/VBB vs. Temperature
Figure 6. ISO Fall Time vs. Temperature
Figure 7. ISO Propagation Delay vs. Temperature
-50 0 50 100 150
0.475
0.5
0.525
0.55
0.575
0.6
TA, AMBIENT TEMPERATURE (°C)
VIH; VDD = 5.25 V, VBB =
18 V
VIH; VDD = 4.75 V, VBB =
8.0 V
VIL; VDD = 5.25 V, VBB =
18 V
VIL; VDD = 4.75 V, VBB =
8.0 V
VIL and VIH, INPUT THRESHOLD (RA-
-50 0 50 100 150
TA, AMBIENT TEMPERATURE (°C)
0.65
0.7
0.75
0.8
0.85
0.9
0.95
VDD = 5.25 V, VBB = 18 V
VDD = 4.75 V, VBB = 8.0 V
tfall(ISO), ISO FALL TIME (µs)
VOH
VOL
TA, AMBIENT TEMPERATURE (°C)
-50 0 50 100 150
0
0.2
0.4
0.6
0.8
1.0
1.2
VDD = 4.75 V, VBB = 8.0 V
and
VDD = 5.25 V, VBB = 18 V
VOL and VOH, ISO OUTPUT (RATIO)
-50 0 50 100 150
TA, AMBIENT TEMPERATURE (°C)
0.2
0.3
0.4
0.5
0.6
0.7
PdH-L
PdL-H
VDD = 5.25 V, VBB = 18 V
VDD = 4.75 V, VBB = 8.0 V
VDD = 4.75 V, VBB = 8.0 V
VDD = 5.25 V, VBB = 18 V
tPD(ISO), PROPAGATION DELAY (µs)
onm
Analog Integrated Circuit Device Data
Freescale Semiconductor 9
33290
TYPICAL APPLICATIONS
INTRODUCTION
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TYPICAL APPLICATIONS
INTRODUCTION
The 33290 is a serial link bus interface device conforming
to the ISO 9141 physical bus specification. The device was
designed for automotive environment usage compliant with
On-Board Diagnostic (OBD) requirements set forth by the
California Air Resources Board (CARB) using the ISO K line.
The device does not incorporate an ISO L line. It provides bi-
directional half-duplex communications interfacing from a
microcontroller to the communication bus. The 33290
incorporates circuitry to interface the digital translations from
5.0 V microcontroller logic levels to battery level logic and
from battery level logic to 5.0 V logic levels. The 33290 is built
using Freescale Semiconductor’s SMARTMOS process and
is packaged in an 8-pin plastic SOIC.
FUNCTIONAL DESCRIPTION
The 33290 transforms 5.0 V microcontroller logic signals
to battery level logic signals and visa versa. The maximum
data rate is set by the fall time and the rise time. The fall time
is set by the output driver. The rise time is set by the bus
capacitance and the pull-up resistors on the bus. The fall time
of the 33290 allows data rates up to 150 kbps using a 30
percent maximum bit time transition value. The serial link
interface will remain fully functional over a battery voltage
range of 6.0 to 18 V. The device is parametrically specified
over a dynamic VBB voltage range of 8.0 to 18 V.
Required input levels from the microcontroller are ratio-
metric with the VDD voltage normally used to power the
microcontroller. This enhances the 33290’s ability to remain
in harmony with the RX and TX control input signals of the
microcontroller. The RX and TX control inputs are compatible
with standard 5.0 V CMOS circuitry. For fault-tolerant
purposes the TX input from the microcontroller has an internal
passive pull-up to VDD, while the CEN input has an internal
passive pull-down to ground.
A pull-up to battery is internally provided as well as an
active data pull-down. The internal active pull-down is
current-limit-protected against shorts to battery and further
protected by thermal shutdown. Typical applications have
reverse battery protection by the incorporation of an external
510 Ω pull-up resistor and diode to battery.
Reverse battery protection of the device is provided by
using a reverse battery blocking diode (“D” in the Simplified
Application Diagram on page 1). Battery line transient
protection of the device is provided for by using a 45 V zener
and a 500 Ω resistor connected to the VBB source as shown
in the same diagram. Device ESD protection from the
communication lines exiting the module is through the use of
the capacitor connected to the VBB device pin and the
capacitor used in conjunction with the 27 V zener connected
to the ISO pin.
rmuK www.freescale.com RA a" ‘H‘Sfé SEATING PLANE ‘ MECHANXCAL OUTLINE PRINT VERSION NOT To SCALE TITLE‘ DOCUMENT NO: 98ASE42564B REV: u 8LD SOIC NARROW BODY CASE NUMBER: 751707 07 APR 2005 STANDARD JEDEC MSrDlZAA
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33290
PACKAGING
PACKAGE DIMENSIONS
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PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below.
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Freescale Semiconductor 11
33290
REVISION HISTORY
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REVISION HISTORY
REVISION DATE DESCRIPTION OF CHANGES
6.0 7/2006 Implemented Revision History page
Converted to Freescale format and updated to the prevailing for and style
Added Pb-free suffix EF
Removed MC33290EG/R2 and replaced with MCZ33290EG/R2 in the Ordering
Information block
7.0 10/2006 Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter
from Maximum Ratings on page 4. Added note with instructions to obtain this information
from www.freescale.com.
8.0 8/2008 Corrected the Document header information.
Updated to the current Freescale form and style.
0" :o" freescale” semrcnnducmr
MC33290
Rev 8.0
8/2008
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