TDA9950 Datasheet by NXP USA Inc.

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1. General description
The TDA9950 is a single-chip CEC/I2C-bus translator with a processor, dedicated to the
control and interfacing of the Consumer Electronics Control (CEC), a feature of the
High-Definition Multimedia Interface (HDMI).
The TDA9950 is an interface between the CEC protocol and timings and the standard
I2C-bus. A message received on the I2C-bus interface is written in a buffer and sent on the
CEC line. A message received from the CEC line is stored in a buffer, and an interrupt is
generated indicating that a message can be read via the I2C-bus. To reduce its power
consumption the TDA9950 sets itself to Idle mode when there is no message on the CEC
line nor on the I2C-bus.
2. Features
2.1 Principal features
nReceive and transmit CEC messages with compliant Signal Free Time handling
nI2C-bus interface to host supporting 100 kbit/s and 400 kbit/s communication
nSupports multiple CEC logical addresses
nSupports CEC messages up to 16 bytes in length
nProgrammable retry count
nComprehensive arbitration and collision handling
n3.0 V to 3.6 V VDD operating range
nAutomatic Idle mode to reduce power consumption when there is no message on CEC
line and I2C-bus
nI/O pins are 5 V tolerant
2.2 Additional features
nProcessor with embedded software to control the interface between CEC line and
I2C-bus
nActive-LOW reset input and on-chip power-on reset allows operation without external
reset components. A reset counter and reset glitch suppression circuitry prevent
spurious and incomplete resets.
nOn-chip oscillator for 12 MHz crystal
nSchmitt trigger port inputs
TDA9950
CEC/I2C-bus translator
Rev. 02 — 22 October 2009 Product data sheet
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Product data sheet Rev. 02 — 22 October 2009 2 of 22
NXP Semiconductors TDA9950
CEC/I2C-bus translator
3. Applications
nAll devices using an HDMI connector
nYCBCR or RGB high-speed video digitizer
nProjector, plasma and LCD TV
nRear-projection TV
nHigh-end TV
nHome-theater amplifier
nDVD recorder
4. Quick reference data
5. Ordering information
Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
VDD supply voltage 3.0 3.3 3.6 V
Tamb ambient temperature 0 - 70 °C
Ptot total power dissipation Operating mode - 33 46.8 mW
Idle mode - 16 25.2 mW
I2C-bus: (5 V tolerant) pins SDA and SCL
fclk clock frequency Standard mode - - 100 kHz
Fast mode - - 400 kHz
Table 2. Ordering information
Type number Package
Name Description Version
TDA9950TT TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm SOT360-1
jjjjjjjjjj O EEEEEEEEEE , pe,
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Product data sheet Rev. 02 — 22 October 2009 3 of 22
NXP Semiconductors TDA9950
CEC/I2C-bus translator
6. Block diagram
7. Pinning information
7.1 Pinning
7.2 Pin description
Fig 1. Block diagram
001aag922
TDA9950 CPU
DATA RAM
internal
bus
CEC-BUS
CEC_IN
CEC_OUT
XTAL1
XTAL2
A0
A1
SCL
SDA
INT
INT_POL
RST
CONFIGURABLE
OSCILLATOR
CRYSTAL POWER-ON RESET
INTERRUPT
I2C-BUS
Fig 2. Pin configuration
TDA9950
RSVD1 A0
INT A1
CEC_OUT INT_POL
RST RSVD7
VSS RSVD6
XTAL1 VDD
XTAL2 RSVD5
CEC_IN RSVD4
SDA RSVD3
SCL RSVD2
001aag923
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
Table 3. Pin description
Symbol Pin Type[1] Description
RSVD1 1 I RSVD1 — Reserved pin; shall be connected to ground
INT 2 O INT — Interrupt line to the host processor to indicate data is
available for reading. The polarity of this signal depends on the
state of pin INT_POL.
CEC_OUT 3 O CEC_OUT — Output for CEC line (open-drain).
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NXP Semiconductors TDA9950
CEC/I2C-bus translator
[1] I = input, O = output, P = power supply.
8. Functional description
The TDA9950 uses an internal processor with embedded software to control the interface
between the CEC line and the I2C-bus.
8.1 Device addressing
The TDA9950 is a slave I2C-bus device and the SCL pin is an input pin only. The timing
and protocol for the I2C-bus are standard.
[1] The Most Significant Bit (MSB), b7, is sent first.
A1 and A0 are hardware-selectable pins.
RST 4 I RST — External reset input. A LOW state on this pin resets the
translator.
VSS 5P Ground: 0 V reference (GND).
XTAL1 6 I XTAL1 — Input to the oscillator circuit and internal clock
generator circuits (12 MHz crystal).
XTAL2 7 O XTAL2 — Output from the oscillator amplifier.
CEC_IN 8 I CEC_IN — Input for CEC line.
SDA 9 I/O SDA — I2C-bus serial data input/output (open-drain).
SCL 10 I SCL — I2C-bus serial clock input.
RSVD2 11 I RSVD2 — Reserved pin (should be connected to ground).
RSVD3 12 O RSVD3 — Reserved pin.
RSVD4 13 O RSVD4 — Reserved pin.
RSVD5 14 I RSVD5 — Reserved pin (should be connected to ground).
VDD 15 P Power supply — This is the (core digital 3.3 V) power supply
voltage for normal operation as well as Idle and Power-down
modes.
RSVD6 16 I RSVD6 — Reserved pin (should be connected to ground).
RSVD7 17 I RSVD7 — Reserved pin (should be connected to ground).
INT_POL 18 I INT_POL — Sets the polarity of the active output required on
the INT signal (pin 2). Leave floating or pull-up to VDD for a
HIGH output when active (rising edge), connect to VSS for a
LOW output when active (falling edge). This input is latched at
reset.
A1 19 I A1 — I2C-bus slave address bit 2.
A0 20 I A0 — I2C-bus slave address bit 1.
Table 3. Pin description
…continued
Symbol Pin Type[1] Description
Table 4. Device address code
Address code Device code Chip enable R/W
Bit b7[1] b6 b5 b4 b3 b2 b1 b0
Value 01101A1A0R/
W
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NXP Semiconductors TDA9950
CEC/I2C-bus translator
In case of independent CEC, a system could have up to four TDA9950 devices on the
same I2C-bus.
The four addresses are defined by the state of the inputs A0 and A1 (logic 1 when
connected to VDD, logic 0 when connected to GND).
8.2 Configuring the TDA9950
The TDA9950 is controlled via a series of registers.
The first byte of any I2C-bus write frame configures the address pointer register APR,
which determines the first TDA9950 register that will be read or written in the remainder of
the I2C-bus transfer. If a read is carried out without a prior write to the address pointer
register, the register returned will be that to which the address pointer register was last
set.
The address pointer auto-increments after a successful read or write for all address
pointer values other than 00h. Auto-incremented addresses above 19h are invalid and
ignored.
Registers 01h to 06h are used for configuration of the TDA9950, whilst repeated
auto-incremented reads starting at register 07h are used to transfer CEC data. Setting the
address pointer register higher than 07h is treated as setting it to 07h, as all message
data transfers must start from register 07h and continue by auto-incrementing in one
contiguous transfer. Transfers via the data registers are formatted using the data register
protocol described in Section 8.5.
8.3 Use of the INT line
As the TDA9950 is an I2C-bus slave device, it provides an additional I/O line to signal to
the host that data is available for reading. This is the INT output line, which should be
monitored by the host. An additional TDA9950 input, on pin INT_POL, allows
configuration of the polarity of operation of the INT line. When the INT line is active, it will
match the state of the input on pin INT_POL.
The state of the INT line is always reflected in the TDA9950 Status Register, so it is
possible to regularly poll this register instead of monitoring the INT line. However, this
method is less efficient and not recommended. The INT indication in the TDA9950 Status
Register is not affected by the setting of the INT polarity input on pin INT_POL.
Table 5. I2C-bus register configuration
Register Description Address Read/Write
APR Address Pointer Register 00h W
CSR TDA9950 Status Register 00h R
CER TDA9950 Error Register 01h R
CVR TDA9950 Version Register 02h R
CCR TDA9950 Control Register 03h R/W
ACKH CEC Address ACK High register 04h R/W
ACKL CEC Address ACK Low register 05h R/W
CCONR CEC Configuration Register 06h R/W
CDR CEC Data Registers 07h - 19h R/W
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NXP Semiconductors TDA9950
CEC/I2C-bus translator
8.4 Register descriptions
Table 6. APR - Address Pointer Register (address 00h) bit description (Write mode)
Bit Symbol Description
7 to 5 reserved reserved (must be set to 000)
4 to 0 REG_PTR[4:0] Address Pointer: Address of the register that will be
read/written during further I2C-bus communication.
Table 7. CSR - TDA9950 Status Register (address 00h) bit description (Read mode)
Bit Symbol Description
7 BUSY BUSY:
0 = the TDA9950 is able to handle requests.
1 = the TDA9950 is busy and cannot accept any further
request.
6 INT INT:
0 = the INT interrupt output is inactive.
1 = the INT interrupt output is active.
5 ERR ERR:
0 = no error.
1 = an error occurred (specified in the TDA9950 Error
Register). Cleared by a read of the TDA9950 Error Register.
4 to 0 - not used
Table 8. CER - TDA9950 Error Register (address 01h) bit description (Read only)
Bit Symbol Description
7 to 0 CER[7:0] TDA9950 Error Register: This register provides details of the
last error that occurred. Reading this register resets the ERR
bit in the TDA9950 Status Register.
00h = no error has occurred since reset.
01h = watchdog reset has occurred.
02h = long CEC message with no End Of Message (EOM)
detected.
03h = CEC overrun - no buffer available to receive.
Table 9. CVR - TDA9950 Version Register (address 02h) bit description (Read only)
Bit Symbol Description
7 to 4 CVR_MAJ[3:0] TDA9950 major version register: Major version
3 to 0 CVR_MIN[3:0] TDA9950 minor version register: Minor version
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NXP Semiconductors TDA9950
CEC/I2C-bus translator
Table 10. CCR - TDA9950 Control Register (address 03h) bit description (Read/Write)
Bit Symbol Description
7 RESET RESET: Resets the TDA9950. Any transmission in progress
will be completed first - the reset occurs once the TDA9950
returns to the idle state. All default values will be restored.
0 = no specific action.
1 = resets the TDA9950.
6 ON_OFF ON_OFF:
0 = the TDA9950 is disabled (after completion of any pending
CEC transmission or reception) and will no longer
acknowledge any message on the CEC line or accept any
message for transmission.
1 = the TDA9950 is enabled and will acknowledge messages
according to the logical address bits in the CEC Address ACK
High and CEC Address ACK Low registers.
5 to 0 - not used
Table 11. ACKH - CEC Address ACK High register (address 04h) bit description
(Read/Write)
Bit Symbol Description
7 reserved reserved (must be set to 0)
6 to 0 ACKH[6:0] CEC Address ACK High register
For each bit:
0 = messages to the corresponding logical address will not be
acknowledged.
1 = messages to the corresponding logical address are
acknowledged and forwarded to the host.
Table 12. ACKL - CEC Address ACK Low register (address 05h) bit description
(Read/Write)
Bit Symbol Description
7 to 0 ACKL[7:0] CEC Address ACK Low register
For each bit:
0 = messages to the corresponding logical address will not be
acknowledged.
1 = messages to the corresponding logical address are
acknowledged and forwarded to the host.
Table 13. CCONR - CEC Configuration Register (address 06h) bit description (Read/Write)
Bit Symbol Description
7 to 5 - not used
Tb Tb Tb
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NXP Semiconductors TDA9950
CEC/I2C-bus translator
8.5 Data register protocol
Communication between the TDA9950 and the host using the CEC Data Registers is
carried out using frames of information. The host is the master of all data transfers; the
TDA9950 uses the INT line to inform the host that it has data available.
Before a frame is read or written, the host must set the REG_PTR field in the Address
Pointer Register to the base CEC Data Register address. Successive reads or writes
automatically increment the REG_PTR as the frame is transferred. Message transfers can
only start from the first CEC Data Register at address 07h and not from higher addresses,
as messages must be transferred complete and not in fragments.
Each frame consists of a byte count, a service selector and then zero or more (up to 17)
parameters as shown in Figure 3.
The FrameByteCount indicates the number of bytes in the frame (including the
FrameByteCount itself). The service is specified by the ServiceSelector (see Table 15).
The remaining bytes of the frame, if any, contain the parameters associated with a
particular service. The maximum length of a frame is 19 bytes. The TDA9950 will only
accept a single outstanding request. Reading message bytes beyond FrameByteCount
will return FFh.
Table 15 shows the organization of the ServiceSelector values. If an unused
ServiceSelector is sent to the TDA9950 it will respond with the confirmation Bad .req
service (see Table 17). For every service, the parameters that are defined in the following
sections are mandatory. No service contains optional parameters.
4 ENABLE_ERROR ENABLE_ERROR:
0 = no specific action.
1 = notify the host of all errors via the TDA9950 Error Register
and via the CECData.err service (see Section 8.5.4).
3 - not used
2 to 0 RETRY[2:0] RETRY[2:0]: retry count to be used by the TDA9950. The
maximum value is 5; values greater than 5 will still give 5
retries.
Table 14. CDR[0:18] - CEC Data Registers (addresses 07h to 19h) bit description
(Read/Write)
Bit Symbol Description
7 to 0 FrameByteCount/
ServiceSelector/
Parameters[7:0]
FrameByteCount/ServiceSelector/Parameters:
Length of message in B, Type of message, 17 B for message
content; see Section 8.5 “Data register protocol”.
Table 13. CCONR - CEC Configuration Register (address 06h) bit description (Read/Write)
Bit Symbol Description
Fig 3. Frame format for the data register protocol
001aag924
FrameByteCount ServiceSelector [Parameters]
Register CDR0 Register CDR1 Register CDR2 [...] [...]
Tb Tb Tb
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NXP Semiconductors TDA9950
CEC/I2C-bus translator
8.5.1 CECData.req service
This service is used to transfer CEC message data. The parameters for the service are
shown in Table 16. Transmission of the CEC message commences as soon as the
complete message has been received by the TDA9950 (subject to the appropriate Signal
Free Time rules being satisfied).
8.5.2 CECData.cnf service
This service is used by the TDA9950 to inform the host of the success or other result of a
CECData.req service. The parameters are shown in Table 17.
8.5.3 CECData.ind service
This service is used to transfer a CEC message, received from a remote device, to the
host. The parameters are listed in Table 18.
Table 15. CEC Data services
ServiceSelector From host to TDA9950 From TDA9950 to host Section
00h CECData.req 8.5.1
01h CECData.cnf 8.5.2
81h CECData.ind
(indication, no TDA9950 error) 8.5.3
82h CECData.err
(no indication, TDA9950 error) 8.5.4
83h CECData.ier
(indication, TDA9950 error) 8.5.5
Table 16. Parameters for CECData.req service
Parameter Comments
AddressByte Source and destination logical addresses in the form SSSS DDDD
DataBytes Bytes of message data up to the data length indicated by FrameByteCount
Table 17. Parameters for CECData.cnf service
Parameter Comments Value Meaning
ResultCode A value indicating the result
of the transmission 00h Success
80h TDA9950 in off state
81h Bad .req service
82h Failed, unable to access CEC line
83h Failed, arbitration error
84h Failed, bit timing error
85h Failed, destination address not
acknowledged
86h Failed, data byte not acknowledged
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NXP Semiconductors TDA9950
CEC/I2C-bus translator
8.5.4 CECData.err service
This service is used to alert the host to an error condition. There are no parameters. The
host should read the TDA9950 Error Register CER for details of the error. This indication
will only occur when bit ENABLE_ERROR of the CEC Configuration Register CCONR is
set to enable error indications.
8.5.5 CECData.ier service
This service is used to transfer a CEC message, received from a remote device, to the
host. In addition, it also alerts the host to an error condition. The parameters are listed in
Table 19. The host should read the TDA9950 Error Register CER for details of the error.
This indication will only occur when bit ENABLE_ERROR of the CEC Configuration
Register CCONR is set to enable error indications.
This service will not be used if no such errors are implemented.
Table 18. Parameters for CECData.ind service
Parameter Comments
AddressByte Source and destination logical addresses in the form SSSS DDDD
DataBytes Bytes of message data up to the data length indicated by FrameByteCount
Table 19. Parameters for CECData.ier service
Parameter Comments
AddressByte Source and destination logical addresses in the form SSSS DDDD
DataBytes Bytes of message data up to the data length indicated by FrameByteCount
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NXP Semiconductors TDA9950
CEC/I2C-bus translator
8.6 Example communication sequences
When writing, the first byte after the slave address will contain the Address Pointer
Register value. Subsequent bytes are written to the register addressed by the Address
Pointer Register.
If the host wishes to write to two or more discontiguous registers, two separate write
sequences must be used with a STOP/START or repeated START condition between
them. Contiguous ranges of registers can be written in one communication sequence
between a START and STOP condition. Messages in the CEC Data Registers must be
written and read as contiguous ranges of registers.
When reading, values are read starting at the register currently addressed by the Address
Pointer Register. The pointer auto-increments after each read. If the host should read past
register 19h, or read more bytes than indicated by the FrameByteCount in register CDR[0]
(address 07h), the value FFh will be returned.
When the address pointer is 00h, it does not auto-increment. This allows repetitive polling
of the TDA9950 Status Register without the need to reset the Address Pointer Register.
If the address pointer needs to be set before a read takes place, the host must first write to
the Address Pointer Register and then, after a repeated start condition (or a STOP/START
sequence), commence reading as many data bytes as it requires.
A = acknowledge (SDA = LOW)
S = START condition
P = STOP condition
Fig 4. Host reads TDA9950 Status Register - after setting address pointer
A = acknowledge (SDA = LOW)
S = START condition
P = STOP condition
Fig 5. Host reads TDA9950 Status Register - without setting address pointer (was at 0)
001aag925
SLAVE ADDRESS
from master to slave
SWAA0000 0000
'0' (write)
SLAVE ADDRESS R A PASr <CSR>
Sr = repeated START condition
write address pointer '1' (read) read status
from slave to master
001aag926
SLAVE ADDRESSSRAPA<CSR>
'1' (read) read status
from master to slave from slave to master
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Product data sheet Rev. 02 — 22 October 2009 12 of 22
NXP Semiconductors TDA9950
CEC/I2C-bus translator
8.6.1 Notes on writing the CEC Data Registers
The CEC Data Registers should be written starting from the first CEC Data Register,
for the number of registers indicated by the contents of that first CEC Data Register, in
one contiguous operation.
A = acknowledge (SDA = LOW)
S = START condition
P = STOP condition
R = read
W = write
Fig 6. Host reads CEC Address ACK registers - after setting address pointer
001aag927
SLAVE ADDRESSSWAA0000 0100
'0' (write)
SLAVE ADDRESS R A A PA....Sr <ACKL><ACKH>
Sr = repeated START condition read address H
write address pointer '1' (read) read address L
from master to slave from slave to master
A = acknowledge (SDA = LOW)
S = START condition
P = STOP condition
W = write
Fig 7. Host writes CEC Configuration Register - after setting address pointer
A = acknowledge (SDA = LOW)
A = not acknowledge (SDA = HIGH)
P = STOP condition
Fig 8. Host writes last three CEC Data Registers
001aag928
SLAVE ADDRESSS W A 0000 0110
'0' (write)
PA<CCONR>A
write address pointer
write config
from master to slave from slave to master
001aag929
<DATA 17h> <DATA 18h> <DATA 19h>..... A A
write data 17h
PA
write data 18h
write data 19h
from master to slave from slave to master
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NXP Semiconductors TDA9950
CEC/I2C-bus translator
The length of the message is given by the byte in the first CEC Data Register. This will
be at least 3 for the shortest message. A value less than 3 indicates an invalid
message.
If fewer CEC Data Registers are written than the number indicated by the first CEC
Data Register, the partial message will be ignored and no confirmation will be
returned.
If more CEC Data Registers are written than the number indicated by the first CEC
Data Register, the message will be processed as soon as the message's last CEC
Data Register is written, and the extra bytes written will be ignored.
If the highest CEC Data Register is written and more message bytes are indicated by
the first CEC Data Register, the message will be processed as soon as the highest
CEC Data Register is written, and the extra bytes written will be ignored.
8.6.2 Notes on reading the CEC Data Registers
The CEC Data Registers only contain a valid message when the INT line is set and
the INT bit in the TDA9950 Status Register is set.
If CEC Data Registers are read when the INT line is not set, the first CEC Data
Register will contain 0, indicating that there are no bytes to read. Any further reads
before a STOP condition will return the value FFh.
The CEC Data Registers should be read starting from the first CEC Data Register, for
the number of registers indicated by that first CEC Data Register, in one contiguous
operation.
If the host writes CEC Data Registers and then begins reading without first resetting
the Address Pointer Register, reading will automatically commence from the first CEC
Data Register.
If reading stops before all indicated CEC Data Registers are read, the TDA9950 will
reset the INT line and the message is discarded by the TDA9950 and will not be
available for reading again.
If reading continues for more CEC Data Registers than are indicated by the first CEC
Data Register, the value FFh will be read. The INT line is reset when the last valid
CEC Data Register for the current message is read.
8.7 Using the TDA9950
8.7.1 Initialization
After a reset, first configure the TDA9950 with its logical address or addresses (as
required):
I2C_WRITE: 04h, 00h, 08h
Set Address Pointer to 04h (ACKH), set ACKH to 00h, and set ACKL to 08h.
The TDA9950 is now configured to acknowledge messages to the logical address 3
(Tuner 1 (see HDMI1.3a specification) or STB1 (see HDMI1.2a specification)).
Then set the TDA9950 to the ON state (mandatory):
I2C_WRITE: 03h, 40h
Set Address Pointer to 03h (CCR), set CCR to 40h.
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NXP Semiconductors TDA9950
CEC/I2C-bus translator
The TDA9950 is now enabled. Messages addressed to logical address Tuner 1 (see
HDMI1.3a specification) or STB1 (see HDMI1.2a specification) will be acknowledged
and forwarded to the host processor.
8.7.2 Sending a CEC message
Example: the host processor of Playback Device 1 (see HDMI1.3a specification) or DVD1
(see HDMI1.2a specification) wishes to send the message <TextView On> to TV:
I2C_WRITE: 00h; I2C_READ, I2C_READ, ....
Set Address Pointer to 00h (CSR), read TDA9950 Status Register - repeat read until
TDA9950 is no longer busy (bit CSR[7] = 0).
I2C_WRITE: 07h, 04h, 00h, 40h, 0Dh
Set Address Pointer to 07h (CEC Data Register 1), write CEC Data Registers.
FrameByteCount = 4, ServiceSelector = CECData.req, AddressByte = DVD/TV,
DataByte = <TextView On>.
Wait for INT line to be asserted
When TDA9950 has a response, it will assert the INT line (the host could also poll bit
CSR[6]).
I2C_WRITE: 07h; I2C_READ: 03h, 01h, 00h
Set Address Pointer to 07h (Data Register 1), read CEC Data Registers.
FrameByteCount = 3, ServiceSelector = CECData.cnf, ResultCode = Success.
8.7.3 Receiving a CEC message
Example: TV sends the message <Give Physical Address> to Playback Device 1 (see
HDMI1.3a specification) or DVD1 (see HDMI1.2a specification):
INT line is asserted
The TDA9950 at Playback Device 1 (see HDMI1.3a specification) or DVD1 (see
HDMI1.2a specification) has acknowledged the message from TV and it is now
available for reading by the Playback Device 1 (see HDMI1.3a specification) or DVD1
(see HDMI1.2a specification) host processor.
I2C_WRITE: 07h; I2C_READ: 04h, 81h, 04h, 83h
Set Address Pointer to 07h (Data Register 1), read CEC Data Registers.
FrameByteCount = 4, ServiceSelector = CECData.ind, AddressByte = TV/DVD,
DataByte = <Give Physical Address>.
In accordance with the Absolute Maximum Rating System (IEC 60134;,
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Product data sheet Rev. 02 — 22 October 2009 15 of 22
NXP Semiconductors TDA9950
CEC/I2C-bus translator
9. Limiting values
[1] Parameters are valid over ambient temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise
noted.
Table 20. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
[1]
Symbol Parameter Conditions Min Max Unit
Tamb ambient temperature 0 70 °C
Tstg storage temperature 65 +150 °C
IOH(I/O) HIGH-level output current
per input/output pin all I/O and output pins - 8 mA
IOL(I/O) LOW-level output current
per input/output pin -20mA
II/O(tot)(max) maximum total I/O current - 80 mA
Vxtal crystal voltage on pins XTAL1, XTAL2 - VDD + 0.5 V
Vnvoltage on any other pin except pins XTAL1, XTAL2, VDD 0.5 +5.5 V
TDA9950_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 22 October 2009 16 of 22
NXP Semiconductors TDA9950
CEC/I2C-bus translator
10. Static characteristics
[1] Typical ratings are not guaranteed. The values listed are at room temperature and VDD = 3.3 V.
[2] See Section 9 “Limiting values” for steady state (non-transient) limits on IOL or IOH.IfI
OL /I
OH exceeds the test condition, VOL /V
OH may
exceed the related specification.
[3] Pin capacitance is characterized but not tested.
Table 21. Static characteristics
V
DD
= 3.0 V to 3.6 V; T
amb
=0
°
Cto+70
°
C for industrial application; unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max Unit
VDD supply voltage 3.0 3.3 3.6 V
IDD supply current VDD = 3.6 V; fosc =12MHz
Operating mode - 10 13 mA
Idle mode - 5 7 mA
dV/dt rate of change of voltage rise rate of VDD - - 2 mV/µs
fall rate of VDD - - 50 mV/µs
VPOR power-on reset voltage - - 0.2 V
Vth(HL) negative-going threshold
voltage except pins SCL, SDA 0.22VDD 0.4VDD -V
Vth(LH) positive-going threshold
voltage except pins SCL, SDA - 0.6VDD 0.7VDD V
Vhys hysteresis voltage pins RST, CEC_IN, SDA,
SCL, RSVD2 - 0.2VDD -V
VIL LOW-level input voltage pins SCL, SDA only 0.5 - 0.3VDD V
VIH HIGH-level input voltage pins SCL, SDA only 0.7VDD - 5.5 V
VOL LOW-level output voltage VDD = 2.4 V to 3.6 V;
pin CEC_OUT
IOL =20mA [2] - 0.6 1.0 V
IOL = 3.2 mA [2] - 0.2 0.3 V
VOH HIGH-level output voltage VDD = 2.4 V to 3.6 V;
pin CEC_OUT
IOH =3.2 mA VDD 0.7 VDD 0.4 - V
IOH =20 µAV
DD 0.3 VDD 0.2 - V
Vxtal crystal voltage on pins XTAL1, XTAL2;
with respect to VSS
0.5 - +4.0 V
Vnvoltage on any other pin except pins XTAL1, XTAL2,
VDD; with respect to VSS
0.5 - +5.5 V
Vtrip(bo) brownout trip voltage 2.4 V < VDD < 3.6 V 2.40 - 2.70 V
Ptot total power dissipation Operating mode - 33 46.8 mW
Idle mode - 16 25.2 mW
Rpu(int)(RST_N) internal pull-up resistance on
pin RST 10 - 30 k
I2C-bus: (5 V tolerant) pins SDA and SCL
Cin input capacitance [3] - - 10 pF
TDA9950_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 22 October 2009 17 of 22
NXP Semiconductors TDA9950
CEC/I2C-bus translator
11. Dynamic characteristics
12. Application information
Table 22. Dynamic characteristics (12 MHz)
V
DD
= 3.0 V to 3.6 V; T
amb
=0
°
Cto+70
°
C for industrial applications; f
osc
= 12 MHz (crystal); unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Glitch filter
tgr glitch rejection time pin RST - - 50 ns
any pin except RST - - 15 ns
tsa signal acceptance time pin RST 125 - - ns
any pin except RST 50 - - ns
I2C-bus: (5 V tolerant) pins SDA and SCL
fclk clock frequency Standard mode - - 100 kHz
Fast mode - - 400 kHz
Fig 9. Application diagram
001aag930
18 k
47 k
100 k
27 k
220
220 pF 220 pF PMLL4148
BC817
VDD
CEC line
TDA9950
8
3
2
9I
2C-bus
configuration
10
18
19
1
20
CEC_IN
CEC_OUT
INT
SDA
SCL
(polarity) INT_POL
(I2C address) A1
RSVD1
(I2C address) A0
d ‘ 7* t , H H H HHDHLH H HHL_ Ea
TDA9950_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 22 October 2009 18 of 22
NXP Semiconductors TDA9950
CEC/I2C-bus translator
13. Package outline
Fig 10. Package outline SOT360-1 (TSSOP20)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 6.6
6.4 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.5
0.2 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT360-1 MO-153 99-12-27
03-02-19
wM
bp
D
Z
e
0.25
110
20 11
pin 1 index
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
A
max.
1.1
TDA9950_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 22 October 2009 19 of 22
NXP Semiconductors TDA9950
CEC/I2C-bus translator
14. Revision history
Table 23. Revision history
Document ID Release date Data sheet status Change notice Supersedes
TDA9950_2 20091022 Product data sheet - TDA9950_1
Modifications: Figure 1 “Block diagram”: removed pin name CEC_POL
Figure 2 “Pin configuration”: changed pin name CEC_POL by RSVD1
Table 3 “Pin description”: changed pin name CEC_POL by RSVD1
Table 3 “Pin description”: updated description pin CEC_OUT
Figure 9 “Application diagram”: changed pin name CEC_POL by RSVD1
TDA9950_1 20071116 Product data sheet - -
TDA9950_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 22 October 2009 20 of 22
NXP Semiconductors TDA9950
CEC/I2C-bus translator
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
TDA9950_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 22 October 2009 21 of 22
NXP Semiconductors TDA9950
CEC/I2C-bus translator
17. Tables
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.1 Principal features . . . . . . . . . . . . . . . . . . . . . . . 1
2.2 Additional features . . . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
5 Ordering information . . . . . . . . . . . . . . . . . . . . . 2
6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
8 Functional description . . . . . . . . . . . . . . . . . . . 4
8.1 Device addressing . . . . . . . . . . . . . . . . . . . . . . 4
8.2 Configuring the TDA9950 . . . . . . . . . . . . . . . . . 5
8.3 Use of the INT line . . . . . . . . . . . . . . . . . . . . . . 5
8.4 Register descriptions . . . . . . . . . . . . . . . . . . . . 6
8.5 Data register protocol . . . . . . . . . . . . . . . . . . . . 8
8.5.1 CECData.req service . . . . . . . . . . . . . . . . . . . . 9
8.5.2 CECData.cnf service . . . . . . . . . . . . . . . . . . . . 9
8.5.3 CECData.ind service . . . . . . . . . . . . . . . . . . . . 9
8.5.4 CECData.err service. . . . . . . . . . . . . . . . . . . . 10
8.5.5 CECData.ier service. . . . . . . . . . . . . . . . . . . . 10
8.6 Example communication sequences . . . . . . . 11
8.6.1 Notes on writing the CEC Data Registers . . . 12
8.6.2 Notes on reading the CEC Data Registers . . 13
8.7 Using the TDA9950 . . . . . . . . . . . . . . . . . . . . 13
8.7.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8.7.2 Sending a CEC message. . . . . . . . . . . . . . . . 14
8.7.3 Receiving a CEC message . . . . . . . . . . . . . . 14
9 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 15
10 Static characteristics . . . . . . . . . . . . . . . . . . . 16
11 Dynamic characteristics. . . . . . . . . . . . . . . . . 17
12 Application information . . . . . . . . . . . . . . . . . 17
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18
14 Revision history . . . . . . . . . . . . . . . . . . . . . . . 19
15 Legal information . . . . . . . . . . . . . . . . . . . . . . 20
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20
15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
15.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 20
16 Contact information . . . . . . . . . . . . . . . . . . . . 20
17 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
18 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
19 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
18. Figures
Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Fig 2. Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . .3
Fig 3. Frame format for the data register protocol . . . . . .8
Fig 4. Host reads TDA9950 Status Register - after
setting address pointer. . . . . . . . . . . . . . . . . . . . .11
Fig 5. Host reads TDA9950 Status Register -
without setting address pointer (was at 0) . . . . . .11
Fig 6. Host reads CEC Address ACK registers -
after setting address pointer . . . . . . . . . . . . . . . .12
Fig 7. Host writes CEC Configuration Register -
after setting address pointer . . . . . . . . . . . . . . . .12
Fig 8. Host writes last three CEC Data Registers . . . . .12
Fig 9. Application diagram . . . . . . . . . . . . . . . . . . . . . . .17
Fig 10. Package outline SOT360-1 (TSSOP20). . . . . . . .18
founded by PHILIPS
NXP Semiconductors TDA9950
CEC/I2C-bus translator
© NXP B.V. 2009. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 22 October 2009
Document identifier: TDA9950_2
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
19. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.1 Principal features . . . . . . . . . . . . . . . . . . . . . . . 1
2.2 Additional features . . . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
5 Ordering information . . . . . . . . . . . . . . . . . . . . . 2
6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
8 Functional description . . . . . . . . . . . . . . . . . . . 4
8.1 Device addressing . . . . . . . . . . . . . . . . . . . . . . 4
8.2 Configuring the TDA9950 . . . . . . . . . . . . . . . . . 5
8.3 Use of the INT line . . . . . . . . . . . . . . . . . . . . . . 5
8.4 Register descriptions . . . . . . . . . . . . . . . . . . . . 6
8.5 Data register protocol . . . . . . . . . . . . . . . . . . . . 8
8.5.1 CECData.req service . . . . . . . . . . . . . . . . . . . . 9
8.5.2 CECData.cnf service . . . . . . . . . . . . . . . . . . . . 9
8.5.3 CECData.ind service . . . . . . . . . . . . . . . . . . . . 9
8.5.4 CECData.err service. . . . . . . . . . . . . . . . . . . . 10
8.5.5 CECData.ier service. . . . . . . . . . . . . . . . . . . . 10
8.6 Example communication sequences . . . . . . . 11
8.6.1 Notes on writing the CEC Data Registers. . . . 12
8.6.2 Notes on reading the CEC Data Registers. . . 13
8.7 Using the TDA9950 . . . . . . . . . . . . . . . . . . . . 13
8.7.1 Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8.7.2 Sending a CEC message . . . . . . . . . . . . . . . . 14
8.7.3 Receiving a CEC message. . . . . . . . . . . . . . . 14
9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 15
10 Static characteristics. . . . . . . . . . . . . . . . . . . . 16
11 Dynamic characteristics . . . . . . . . . . . . . . . . . 17
12 Application information. . . . . . . . . . . . . . . . . . 17
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 19
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 20
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
16 Contact information. . . . . . . . . . . . . . . . . . . . . 20
17 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
18 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

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