0N Semiconductorg
r0 Semxconducl
October. 20
© Semiconductor Components Industries, LLC, 2009
October, 2009 − Rev. 1
1Publication Order Number:
NBXSPA008/D
NBXSPA008
2.5 V / 3.3 V, 161.1328MHz
LVDS Clock Oscillator
The NBXSPA008 single frequency crystal oscillator (XO) is
designed to meet today’s requirements for 2.5 V and 3.3 V LVDS
clock generation applications. The device uses a high Q fundamental
crystal and Phase Lock Loop (PLL) multiplier to provide
161.1328 MHz, ultra low jitter and phase noise LVDS differential
output.
This device is a member of ON Semiconductor’s PureEdget clock
family that provides accurate and precision clock solutions.
Available in 5 mm x 7 mm SMD (CLCC) package on 16 mm tape
and reel in quantities of 1000.
Features
•LVDS Differential Output
•Uses High Q Fundamental Mode Crystal and PLL Multiplier
•Ultra Low Jitter and Phase Noise − 0.5 ps (12 kHz − 20 MHz)
•Output Frequency − 161.1328 MHz
•Hermetically Sealed Ceramic SMD Package
•RoHS Compliant
•Operating Range: 2.5 V ±5%
Operating Range: 3.3 V ±10%
•Total Frequency Stability − $50 ppm
•This is a Pb−Free Device
Applications
•Ethernet, Gigabit Ethernet
•WAN
•Networking
Figure 1. Simplified Logic Diagram
PLL
Clock
Multiplier
Crystal
GNDNCOE
CLK CLKVDD
654
123
http://onsemi.com
Device Package Shipping†
ORDERING INFORMATION
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
NBXSPA008LN1TAG CLCC−6
(Pb−Free)
1000/
Tape & Reel
MARKING DIAGRAM
NBXSPA008 = NBXSPA008 (±50 PPM)
161.1328 = Output Frequency (MHz)
AA = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G or G= Pb−Free Package
6 PIN CLCC
LN SUFFIX
CASE 848AB
NBXSPA008
161.1328
AAWLYYWWG
NBXSPA008LNHTAG CLCC−6
(Pb−Free)
100/
Tape & Reel
NBXSPA008
http://onsemi.com
2
NC
OE
GND
CLK
VDD
CLK
1
2
3
6
5
4
Figure 2. Pin Connections (Top View)
Table 1. PIN DESCRIPTION
Pin No. Symbol I/O Description
1 OE LVTTL/LVCMOS
Control Input
Output Enable Pin. When left floating pin defaults to logic HIGH and output is active.
See OE pin description Table 2.
2 NC N/A No Connect
3 GND Power Supply Ground 0 V
4 CLK LVDS Output Non−Inverted Clock Output. Typically loaded with 100 W receiver termination resistor
across differential pair.
5 CLK LVDS Output Inverted Clock Output. Typically loaded with 100 W receiver termination resistor across
differential pair.
6 VDD Power Supply Positive power supply voltage. Voltage should not exceed 2.5 V ±5% or 3.3 V ±10%.
Table 2. OUTPUT ENABLE TRI−STATE FUNCTION
OE Pin Output Pins
Open Active
HIGH Level Active
LOW Level High Z
Table 3. ATTRIBUTES
Characteristic Value
Input Default State Resistor 170 kW
ESD Protection Human Body Model
Machine Model
2 kV
200 V
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Units
VDD Positive Power Supply GND = 0 V 4.6 V
Iout LVDS Output Current Continuous
Surge
25
50
mA
TAOperating Temperature Range −40 to +85 °C
Tstg Storage Temperature Range −55 to +120 °C
Tsol Wave Solder See Figure 5 260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
NBXSPA008
http://onsemi.com
3
Table 5. DC CHARACTERISTICS (VDD = 2.5 V ± 5% or VDD = 3.3 V ± 10%, GND = 0 V, TA = −40°C to +85°C) (Note 2)
Symbol Characteristic Conditions Min. Typ. Max. Units
IDD Power Supply Current 85 105 mA
VIH OE Input HIGH Voltage 2000 VDD mV
VIL OE Input LOW Voltage GND − 300 800 mV
IIH Input HIGH Current −100 +100 mA
IIL Input LOW Current −100 +100 mA
DVOD Change in Magnitude of VOD for
Complementary Output States
(Note 3)
0 1 25 mV
VOS Offset Voltage 1125 1375 mV
DVOS Change in Magnitude of VOS for
Complementary Output States
(Note 3)
0 1 25 mV
VOH Output HIGH Voltage VDD = 2.5 V
VDD = 3.3 V
1425 1600 mV
VOL Output LOW Voltage VDD = 2.5 V
VDD = 3.3 V
900 1075 mV
VOD Differential Output Voltage 250 450 mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Measurement taken with outputs terminated with 100 ohm across differential pair. See Figure 4.
3. Parameter guaranteed by design verification not tested in production.
Whase Nowse W UUdBl Re? In UUdB‘IHé [Smo]
mm p
Cimav mmm MHz .s‘mwa
a: mu N1 SEC/Hz
Zr 1 kHz SEC/Hz
3: m m dEC/Nz
4. mu m flit/HZ
s: 1 m: dfizmz
a: m m GECNZ
)7: 20 m '153.5363 GBCNZ
XI 5m: 12 m
Sxau m mm
mm moms m:
Mflysws kings x- 3m Mirker
Ma‘ysws mg: v am Mirkir
1an N01: - 7655095 aux / 2939 um
ms Nmse: Szmsss wad
30,0721 mam
ms mm: SIBAIB BK
mm“! m: amaze Hz
NBXSPA008
http://onsemi.com
4
Table 6. AC CHARACTERISTICS (VDD = 2.5 V ± 5% or VDD = 3.3 V ± 10%, GND = 0 V, TA = −40°C to +85°C) (Note 4)
Symbol Characteristic Conditions Min. Typ. Max. Units
fCLKOUT Output Clock Frequency 161.1328 MHz
DfFrequency Stability − NBXSPA008 (Note 5) ±50 ppm
FNOISE Phase−Noise Performance 100 Hz of Carrier −101 dBc/Hz
fCLKout = 161.1328 MHz
(See Figures 3 and NO TAG)
1 kHz of Carrier −119 dBc/Hz
10 kHz of Carrier −126 dBc/Hz
100 kHz of Carrier −127 dBc/Hz
1 MHz of Carrier −135 dBc/Hz
10 MHz of Carrier −159 dBc/Hz
tjit(F)RMS Phase Jitter 12 kHz to 20 MHz 0.5 0.75 ps
tjitter Cycle to Cycle, RMS 1000 Cycles 1 8 ps
Cycle to Cycle, Peak−to−Peak 1000 Cycles 7 35 ps
Period, RMS 10,000 Cycles 0.6 4 ps
Period, Peak−to−Peak 10,000 Cycles 5 20 ps
tOE/OD Output Enable/Disable Time 200 ns
tDUTY_CYCLE Output Clock Duty Cycle
(Measured at Cross Point)
48 50 52 %
tROutput Rise Time (20% and 80%) 115 400 ps
tFOutput Fall Time (80% and 20%) 115 400 ps
tstart Start−up Time 1 5 ms
Aging 1st Year 3 ppm
Every Year After 1st 1 ppm
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Measurement taken with outputs terminated with 100 ohm across differential pair. See Figure 4.
5. Parameter guarantees 10 years of aging. Includes initial stability at 25°C, shock, vibration and first year aging.
Figure 3. Typical Phase Noise Plot at 161.1328 MHz
20 - 40 sec, ma
hemp 260’
NBXSPA008
http://onsemi.com
5
Table 7. RELIABILITY COMPLIANCE
Parameter Standard Method
Shock Mechanical MIL−STD−833, Method 2002, Condition B
Solderability Mechanical MIL−STD−833, Method 2003
Vibration Mechanical MIL−STD−833, Method 2007, Condition A
Solvent Resistance Mechanical MIL−STD−202, Method 215
Resistance to Soldering Heat Mechanical MIL−STD−203, Method 210, Condition I or J
Thermal Shock Environment MIL−STD−833, Method 1001, Condition A
Moisture Resistance Environment MIL−STD−833, Method 1004
Figure 4. Typical Termination for Output Driver and Device Evaluation
Driver
Device
Receiver
Device
CLK D
CLK D
Zo = 50 W
Zo = 50 W
100 W
NBXSPA008
260
217
175
150
Temperature (°C)
temp. 260°C
20 − 40 sec. max.
Time
60180 sec.
3°C/sec. max.
cooling
6°C/sec. max.
60150 sec.
reflow
peak
pre−heat
ramp−up
Figure 5. Recommended Reflow Soldering Profile
PACKA
6 PIN C
CA
um
33‘ ans
BOTTOM VIEW
0N Semxcanduclnvand J5
manymumm scum:
NBXSPA008
http://onsemi.com
6
PACKAGE DIMENSIONS
6 PIN CLCC, 7x5, 2.54P
CASE 848AB−01
ISSUE C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
A
B
E
D
BOTTOM VIEW
b
e
6X
0.10 B
0.05
AC
C
0.15 C
TERMINAL 1
INDICATOR
TOP VIEW
A
A1
A3
0.10 C
CSEATING
PLANE
SIDE VIEW
L
6X
12
56
D3
DIM
A
MIN NOM MAX
MILLIMETERS
1.70 1.80 1.90
A1 0.70 REF
b1.30 1.40 1.50
D1 6.17 6.20 6.23
D2 6.66 6.81 6.96
E1 4.37 4.40 4.43
R0.70 REF
L1.17 1.27 1.37
A2 0.36 REF
A3 0.08 0.10 0.12
D7.00 BSC
D3 5.08 BSC
E5.00 BSC
E2 4.65 4.80 4.95
E3 3.49 BSC
e2.54 BSC
D1
E1
D2
E2
A2
3
4
E3
R
4X
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
PITCH
2.54
1.50
6X
5.06
1.50
6X
DIMENSION: MILLIMETERS
H
H1.80 REF
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
NBXSPA008/D
PureEdge is a trademark of Semiconductor Components Industries, LLC (SCILLC).
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
Products related to this Datasheet
IC OSC XTAL 161.1328MHZ 6-CLCC
IC OSC XTAL 161.1328MHZ 6-CLCC
IC OSC XTAL 161.1328MHZ 6CLCC
IC OSC XTAL 161.1328MHZ 6CLCC