74OL6000/01/10/11 Datasheet by ON Semiconductor

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PACKAGE SYMBOL
10/1/03
Page 1 of 15
© 2003 Fairchild Semiconductor Corporation
TTL BUFFER 74OL6000
TTL INVERTER 74OL6001
CMOS BUFFER 74OL6010
CMOS INVERTER 74OL6011
LSTTL TO
OPTOPLANAR
®
HIGH-SPEED
LOGIC-TO-LOGIC OPTOCOUPLERS
DESCRIPTION
OPTOLOGIC™ is the first family of truly logic compatible optically coupled logic interface gates.
The family consists of four device types offering LSTTL to TTL and LSTTL to CMOS interfacing. Each of these interfacing functions
is available as a buffer (A=B), or as an inverter (A=B).
The LSTTL input compatibility is provided by an input integrated circuit, with industry standard logic levels. This input amplifier IC
switches a temperature compensated current source driving a high speed 850 nm AlGaAs LED emitter. This novel integration
scheme eliminates CTR degradation over time and temperature.
The emitter is optically coupled to an integrated photodetector/high-gain, high-speed output amplifier IC. The superior 15kV/µS
common-mode noise rejection is ensured through the use of an optically transparent noise shield.
The TTL compatible output has a totem-pole with a fan-out of 10. The CMOS compatible output has an open collector Schottky-
clamped transistor that interfaces to any CMOS logic between 4.5 and 15 volts. The 74OL6010/11 may also by used to drive power
MOSFETS or transistors up to 15 volts.
The Optologic coupler family typically offers propagation of delays of 60 ns and can support 15 MBaud data communication.
The two input chips and the output chip are assembled in a 6-pin DIP high insulation voltage plastic package. Fairchild’s proprietary
OPTOPLANAR
®
construction provides a withstand test voltage of 5300 VRMS (1 minute).
6
1
6
1
6
1
BUFFER
INVERTER
FEATURES
Industry first LSTTL to TTL and LSTTL to CMOS complete
logic-to-logic optocoupler
Incorporates LED drive circuitry use as logic gate
Very high speed
Choice of buffer or inverter
Choice of TTL or CMOS compatible output up to 15 volts
Fan-out of 10 TTL loads, fan-in 1 LSTTL load
Internal noise shield very high CMR of ±15 kV/µS
UL recognized (File #E90700)
Same noise immunity as LSTTL/TTL.
APPLICATIONS
Transmission line interface receiver and driver
Excellent as bridged receiver in fast LAN highways
Bus interface
Logic family interface with ground loop noise elimination
High speed AC/DC voltage sensing
Driver for power semiconductor devices
Level shifting
Replaces fast pulse transformers
— FAIRCHILD ESEl\/||(:CJNDLJ(3TCJR‘1D gmm Emu; I / o " \ W \_,_G W _\ if chD
10/1/03
Page 2 of 15
© 2003 Fairchild Semiconductor Corporation
TTL BUFFER 74OL6000
TTL INVERTER 74OL6001
CMOS BUFFER 74OL6010
CMOS INVERTER 74OL6011
LSTTL TO
OPTOPLANAR
®
HIGH-SPEED
LOGIC-TO-LOGIC OPTOCOUPLERS
PIN CONFIGURATION
1-V
CCI
(Input V
CC
) 6-V
CCO
(Output V
CC
)
2-V
IN
(Data In) 5-V
O
(Data Out)
3-GND, (Input GND) 4-GND
O
(Output GND)
DEVICE CONFIGURATION
Part Number
Logic Compatibility
Logic Function Output Configuration
Input Output
74OL 6000 LSTTL TTL BUFFER TOTEM POLE
74OL 6001 LSTTL TTL INVERTER TOTEM POLE
74OL 6010 LSTTL CMOS BUFFER OPEN COLLECTOR
74OL 6011 LSTTL CMOS INVERTER OPEN COLLECTOR
22 k TYP.
INPUT
Vcc
GND
LSTTL INPUT CIRCUIT
Vcc
150 TYP.
TTL OUTPUT CIRCUIT
GND
OUTPUT
Vcc
R
GND
CMOS OUTPUT CIRCUIT
OUTPUT
L
All Inputs
74OL6000/01 Output 74OL6010/11 Output
FAIRCHILD ESEl\/||(:CJNDLJ(3TCJR‘1D
10/1/03
Page 3 of 15
© 2003 Fairchild Semiconductor Corporation
TTL BUFFER 74OL6000
TTL INVERTER 74OL6001
CMOS BUFFER 74OL6010
CMOS INVERTER 74OL6011
LSTTL TO
OPTOPLANAR
®
HIGH-SPEED
LOGIC-TO-LOGIC OPTOCOUPLERS
SCHEMATIC
LSTLL to TTL Buffer
NOISE
SHIELD
1
2
3
74OL
OL
6000
6
5
4
LSTLL to TTL Inverter
NOISE
SHIELD
1
2
3
74OL
OL
6001
6
5
4
LSTLL to CMOS Buffer
NOISE
SHIELD
1
2
3
74OL
OL
6010
6
5
4
LSTLL to CMOS Inverter
NOISE
SHIELD
1
2
3
74OL
OL
6011
6
5
4
— FAIRCHILD SEMICONDUCTOR“ Vcco
10/1/03
Page 4 of 15
© 2003 Fairchild Semiconductor Corporation
TTL BUFFER 74OL6000
TTL INVERTER 74OL6001
CMOS BUFFER 74OL6010
CMOS INVERTER 74OL6011
LSTTL TO
OPTOPLANAR
®
HIGH-SPEED
LOGIC-TO-LOGIC OPTOCOUPLERS
*All typical values are at T
A
=25°C
ELECTRICAL CHARACTERISTICS
(T
A
= 0°C to 70°C Unless otherwise specified)
Parameter Symbol Min Typ* Max Units Test Conditions Notes
74OL6000 74OL6001 74OL6000/01
TTL OUTPUT 74OL6000/01
Input Supply Voltage V
CCI
4.5 5.0 5.5 V 1
Output Supply Voltage V
CCO
4.5 5.0 5.5 V 1
High-Level Input Voltage V
IH
2.0 V 1
Low-Level Input Voltage V
IL
0.8 V 1
Input Clamp Voltage V
IK
-1.2 V V
CCI
= 4.5 V, I
I
= -18 mA 1
High-Level Input Current I
IH
1.0 40.0 µA V
CCI
= 5.5 V, V
IH
= 4.5 V 1
Low-Level Input Current I
IL
-200.0 -400.0 µA V
CCI
= 5.5 V, V
IL
= 0.4 V 1
Input Supply Current (high) I
CCIH
10.0 14.0 mA V
CCI
= 5.5 V, V
IN
= V
IH
1
Input Supply Current (low) I
CCIL
10.0 14.0 mA V
CCI
= 5.5 V, V
IN
= V
IL
1
High-Level Output Voltage V
OH
2.4 3.0 V V
IN
= 2.0 V V
IN
= 0.8 V V
CCI
= 4.5 V, V
CCO
= 4.5 V,
I
OH
= -400 mA 1
Low-Level Output Voltage V
OL
0.3
0.6
VV
IN
= 0.8V V
IN
= 2.0V
V
CCI
= 4.5 V, V
CCO
= 4.5 V,
I
OL
= 16 mA 1
0.5 V
CCI
= 4.5 V, V
CCO
= 4.5 V,
I
OL
= 4 mA
High-Level Output Current I
OH
-8.0 -10.0 mA V
IN
= V
IH
V
IN
= V
IL
V
CCI
= 4.5 V, V
CCO
= 4.5 V,
V
OH
= 2.4 V 1
Low-Level Output Current I
OL
16.0 mA V
IN
= 0.8 V V
IN
= 2.0V V
CCI
= 4.5 V, V
CCO
= 4.5 V,
V
OL
= 0.6 V 1
Short-Circuit Output Current I
OS
-5.0 -25.0 -40.0 mA V
IN
= V
IH
V
IN
= V
IL
V
CCI
= 5.5 V, V
CCO
= 5.5 V, 1
Output Supply Current (high) I
CCOH
9.0 15.0 mA V
IN
= V
IH
V
IN
= V
IL
V
CCI
= 5.5 V, V
O
= V
OH
,
V
CCO
= 5.5 V 1
Output Supply Current (low) I
CCOL
8.0 12.0 mA V
IN
= V
IL
V
IN
= V
IH
V
CCI
= 5.5 V, V
O
= V
OL
,
V
CCO
= 5.5 V 1
SWITCHING CHARACTERISTCS
(T
A
= 25°C Unless otherwise specified)
Parameter Symbol Min Typ Max Units Test Conditions Fig. Notes
TTL OUTPUT 74OL6000/01
V
CCI
= 5 V, V
CCO
= 5 V
Propagation Delay Time For Output Low Level t
PHL
60 100 ns 15, 17 1
Propagation Delay Time For Output High Level t
PLH
70 100 ns 15, 17 1
Output Rise Time For Output High Level t
r45 n 15, 17 1
Output Fall Time For Output Low Level tf5 ns 15, 17 1
— FAIRCHILD SEMICONDUCTOR“ Vcco
10/1/03
Page 5 of 15
© 2003 Fairchild Semiconductor Corporation
TTL BUFFER 74OL6000
TTL INVERTER 74OL6001
CMOS BUFFER 74OL6010
CMOS INVERTER 74OL6011
LSTTL TO
OPTOPLANAR® HIGH-SPEED
LOGIC-TO-LOGIC OPTOCOUPLERS
*All typical values are at TA=25°C
ELECTRICAL CHARACTERISTICS (TA = 0°C to 70°C Unless otherwise specified)
Parameter Symbol Min Typ* Max Units Test Conditions Notes
74OL6010 74OL6011 74OL6010/11
CMOS OUTPUT 74OL6010/11
Input Supply Voltage VCCI 4.5 5.0 5.5 V 1
Output Supply Voltage VCCO 4.5 15.0 V 1,3
High-Level Input Voltage VIH 2.0 V 1
Low-Level Input Voltage VIL 0.8 V 1
Input Clamp Voltage VIK -1.2 V VCCI = 4.5 V, II = -18 mA 1
High-Level Input Current IIH 1.0 40.0 µA VCCI = 5.5 V, VIH = 4.5 V 1
Low-Level Input Current IIL -200.0 -400.0 µA VCCI = 5.5 V, VIL = -0.4 V 1
Input Supply Current (high) ICCIH 10.0 14.0 mA VCCI = 5.5 V, VIN = VIH 1
Input Supply Current (low) ICCIL 10.0 14.0 mA VCCI = 5.5 V, VIN = VIL 1
Low-Level Output Voltage VOL 0.4
0.6
VV
IN = 0.8V VIN = 2.0V
VCCI = 4.5 V, VCCO = 4.5 V,
IOL = 16 mA 1
0.5 VCCI = 4.5 V, VCCO = 4.5 V,
IOL = 4 mA
High-Level Output Current IOH 1.0 100.0 µA VIN = VIH VIN = VIL
VCCI = 4.5 V, VOH = 15 V,
VCCO = 4.5 - 15 V 1
Low-Level Output Current IOL 16.0 mA VIN = 0.8 V VIN = 2.0V VCCI = 4.5 V, VOL = 0.6V,
VCCO = 4.5 - 15 V 1
Output Supply Current (high) ICCOH
9.0 12.0
mA VIN = VIH VIN = VIL
VCCI = 5.5 V, VO = VOH,
VCCO = 4.5 V 1
11.0 18.0 VCCI = 5.5 V, VO = VOL,
VCCO = 15 V
Output Supply Current (low) ICCOL
8.0 12.0
mA VIN = VIL VIN = VIH
VCCI = 5.5 V, VO = VOL,
VCCO = 4.5 V 1
11.0 18.0 VCCI = 5.5 V, VO = VOL,
VCCO = 15 V
SWITCHING CHARACTERISTCS (TA = 25°C Unless otherwise specified)
Parameter Symbol Min Typ Max Units Test Conditions Fig. Notes
TTL OUTPUT 74OL6010/11
VCCI = 5 V,
VCCO = 5 V, RL = 470
Propagation Delay Time For Output Low Level tPHL 60 120 ns 15, 18 1
Propagation Delay Time For Output High Level tPLH 100 180 ns 15, 18 1
Output Rise Time For Output High Level tr50 ns 15, 18 1
Output Fail Time For Output Low Level tf5 ns 15, 18 1
— FAIRCHILD SEMICONDUCTOR“
10/1/03
Page 6 of 15
© 2003 Fairchild Semiconductor Corporation
TTL BUFFER 74OL6000
TTL INVERTER 74OL6001
CMOS BUFFER 74OL6010
CMOS INVERTER 74OL6011
LSTTL TO
OPTOPLANAR® HIGH-SPEED
LOGIC-TO-LOGIC OPTOCOUPLERS
ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise specified)
Parameter Symbol Device Value Units
TOTAL DEVICE
Storage Temperature TSTG All -55 to +125 °C
Operating Temperature TOPR All 0 to +70 °C
Lead Solder Temperature TSOL All 260 for 10 sec °C
Power Dissipation PDAll 350 mW
EMITTER
Input Supply Voltage VCCI All 7 V
Input Voltage VIN All 7 V
DETECTOR
Average Output Current IO (avg) All 40 mA
Output Supply Voltage VCCO
74OL6000/01 7 V
74OL6010/11 18
Output Voltage VO
74OL6000/01 7 V
74OL6010/11 18
ELECTRICAL CHARACERISTICS (TA = 0°C to 70°C Unless otherwise specified)
Parameter Symbol Min Typ Max Units Test Conditions Fig. Notes
74OL6000/01/10/11
Common Mode Transient Immunity at
Logic High Level Output CMH5000 15000 V/µS VCCI = 5 V, VCCO = 5 V,
VCM = 50 Vp-p
16, 19
Common Mode Transient Immunity at
Logic Low Level Output CML-5000 -15000 V/µS 16, 19
Common Mode Coupling Capacitance CCM 0.005 pF
Capacitance (input-output) CI-O 0.7 pF VI-O = 0, f = 1 MHz 2
Withstand Insulation Test Voltage VISO 5300 VRMS TA = 25°C,
t = 1 min, II-O 1mA 2
Insulation Resistance RISO 10 VI-O = 500 VDC 2
— FAIRCHILD ESEl\/||(:CJNDLJ(3TCJR‘1D
10/1/03
Page 7 of 15
© 2003 Fairchild Semiconductor Corporation
TTL BUFFER 74OL6000
TTL INVERTER 74OL6001
CMOS BUFFER 74OL6010
CMOS INVERTER 74OL6011
LSTTL TO
OPTOPLANAR® HIGH-SPEED
LOGIC-TO-LOGIC OPTOCOUPLERS
-200
-300
0
100
-100
-40 -20 0 20 40 60 80 100
TA - AMBIENT TEMPERATURE (˚C)
Figure 1. Input Current vs. Ambient Temperature
II - INPUT CURRENT (µA)
VCCI = 5.5V
VIH = 4.5V
VIL = 0.4V
15
14
13
12
11
10
9
8
7
6
5
-40 -20 0 20 40 60 80 100
TA - AMBIENT TEMPERATURE (˚C)
Figure 2. Input Supply Current vs. Ambient Temperature
ICCI - INPUT SUPPLY CURRENT (mA)
ICCIH - 74OL6000-6010
ICCIL - 74OL6001-6011
ICCIH - 74OL6001-6011
ICCIL - 74OL6000-6010
VCCI = 5.5V
3
0
9
12
15
6
-40 -20 0 20 40 60 80 100
TA - AMBIENT TEMPERATURE (˚C)
Figure 3. Output Supply Current vs. Ambient Temperature Figure 4. Output Current vs. Ambient Temperature
ICCO - OUTPUT SUPPLY CURRENT (mA)
-20
-30
-10
20
10
30
50
40
60
0
-40 -20 0 20 40 60 80 100
TA - AMBIENT TEMPERATURE (˚C)
IO - OUTPUT SUPPLY CURRENT (mA)
IIH
IIL
VCCI = 5.5V
VCCO = 15V
VCCI = 5.5V
VCCO = 5.5V
74OL6010/6011
VCCI = 5.5V
VCCO = 5.5V
74OL6000/6001
74OL6010/6011
ICCOH
ICCOL
ICCOH
ICCOL
ICCOH
ICCOL
(74OL6000/6001)
IOH
IOL
VCCI = 4.5V
VCCO = 4.5V
VOL = 0.6V
VOH = 2.4V
1
0
3
4
5
2
-40 -20 0 20 40 60 80 100
TA - AMBIENT TEMPERATURE (˚C)
Figure 5. High-Level Output Voltage vs. Ambient Temperature Figure 6. Low-Level Output Voltage vs. Ambient Temperature
VOH - HIGH-LEVEL OUTPUT VOLTAGE (V)
0.1
0.2
0.3
0.4
0.5
-40 -20 0 20 40 60 80 100
TA - AMBIENT TEMPERATURE (˚C)
VOL - LOW-LEVEL OUTPUT VOLTAGE (V)
VCCI = 4.5V
VCCO = 4.5V
IOH = -400µA
@ IOL = 16mA
@ IOL = 4mA
VCCI = 4.5V
VCCO = 4.5V
— FAIRCHILD ESEl\/||(:CJNDLJ(3TCJR‘1D
10/1/03
Page 8 of 15
© 2003 Fairchild Semiconductor Corporation
TTL BUFFER 74OL6000
TTL INVERTER 74OL6001
CMOS BUFFER 74OL6010
CMOS INVERTER 74OL6011
LSTTL TO
OPTOPLANAR® HIGH-SPEED
LOGIC-TO-LOGIC OPTOCOUPLERS
1
0
3
4
5
2
-40 -20 0 20 40 60 80 100
TA - AMBIENT TEMPERATURE (˚C)
Figure 7. 74OL6010/11 Leakage Current vs. Ambient Temperature
IOH - LEAKAGE CURRENT (µA)
VCCIN = 4.5V
VCCO = 15V
VOUT = 15V 200
100
50
10
5
1
-40 -20 0 20 40 60 80 100
TA - AMBIENT TEMPERATURE (˚C)
Figure 8. 74OL6000/01 Switching Times vs. Ambient Temperature
SWITCHING TIME (ns)
tf
tf
5
1
50
100
200
10
-40 -20 0 20 40 60 80 100
TA - AMBIENT TEMPERATURE (˚C)
Figure 9. 74OL6010/11 Switching Times vs. Ambient Temperature Figure 10. Common Mode Rejection vs. Common Mode Voltage
SWITCHING TIME (ns)
1
2
5
4
6
8
7
9
10
11
3
0 500 1000 15000 2000 2500
VCM - COMMON MODE TRANSIENT
CM - COMMON MODE TRANSIENT IMMUNITY (KV/µS)
2
0
6
8
10
12
4
4 5 6 7 8 9 10 11 12 13 14 15
VCC - SUPPLY VOLTAGE (V)
Figure 11. Supply Current vs. Supply Voltage Figure 12. Power Dissipation vs. Ambient Temperature
ICC - SUPPLY CURRENT (mA)
0
100
200
300
4 5 6 7 8 9 10 11 12 13 14 15
VCCO - OUTPUT SUPPLY VOLTAGE (V)
PT - TOTAL PACKAGE POWER DISSIPATION (mW)
VCCO = 5V
VCCO = 15V
VCCI = 5V
RL = 470
P.W = 200ns
PERIOD = 1µS
MAXIMUM ALLOWABLE POWER
DISSIPATION @ TA = 25˚C
tPLH
tPHL
tr
VCCI = 5.0V
VCCO = 5.0V
P.W = 200ns
PERIOD = 1µS
tPLH
tPLH
tr
tr
tf
tf
tPHL
VCCO = 5V
VCCO = 5V
VOH = 2V
VOL = 0.8V
RL = 470 (74OL6010/6011)
ICC
VCCO
RANGE FOR 74OL6000/6001
ICCO
@TA = 55˚C
@TA = 70˚C
@TA = 85˚C
VCCI = 5.5V
VCCI = 4.5V
— FAIRCHILD SEMICONDUCTDRGD TM 7E??? FE? r1? T 1:45 /’_\
10/1/03
Page 9 of 15
© 2003 Fairchild Semiconductor Corporation
TTL BUFFER 74OL6000
TTL INVERTER 74OL6001
CMOS BUFFER 74OL6010
CMOS INVERTER 74OL6011
LSTTL TO
OPTOPLANAR® HIGH-SPEED
LOGIC-TO-LOGIC OPTOCOUPLERS
1.0
0.0
1.3
1.4
1.5
1.6
1.2
1.1
-40 -20 0 20 40 60 80 100
TA - AMBIENT TEMPERATURE (°C)
Figure 13. Input Threshold Voltage vs. Ambient Temperature
Figure 15. Switching Time Test Circuit
VINTH - INPUT THRESHOLD VOLTAGE (V)
VCCI = 5.0V
VCCO = 5.0V
0
100
-100
-200
-300
0123456
VIN - INPUT VOLTAGE (V)
Figure 14. Input Current vs. Input Voltage
IIN - INPUT CURRENT (µA)
VCCI = 4.5V
1
2
3
6
5
4
.1µF
VCCI
+5 V
PULSE
GEN
PW =200ns
PERIOD = 1µS
tr = 5ns
Zo = 50
.1µF
CL*
VCCO
+5 V
VO
470 (74OL6010/11)
*CL = 15pF STRAY CAPACITANCE
INCLUDING PROBE
Figure 16. Common Mode Rejection Test Circuit
1
2
3
+
VCM
-
6
5
6
.1µF
H/L
L/H
1k
.1µF
VCCO
+5 V
470 (74OL6010/11)
FAIRCHILD CCCCCCCCCCCCCC
10/1/03
Page 10 of 15
© 2003 Fairchild Semiconductor Corporation
TTL BUFFER 74OL6000
TTL INVERTER 74OL6001
CMOS BUFFER 74OL6010
CMOS INVERTER 74OL6011
LSTTL TO
OPTOPLANAR® HIGH-SPEED
LOGIC-TO-LOGIC OPTOCOUPLERS
NOTE
1. The VCCO and VCCI supply voltages to the device must each be bypassed by a 0.1µF capacitor or larger. This can be either a
ceramic or solid tantalum capacitor with good high frequency characteristics. Its purpose is to stabilize the operation of the high-
gain amplifiers. Failure to provide the bypass will impair the DC and switching properties. The total lead length between capaci-
tor and optocoupler should not exceed 1.5mm. See Fig. 20.
2. Device considered a two-terminal device. Pins 1, 2 and 3 shorted together, and Pins 4, 5 and 6 shorted together.
3. For example, assuming a VCCI of 5.0V, and an ambient temperature of 70°C, the maximum allowable VCCO is 12.1V.
3.2V
1.3V
90%
90%
10%
INPUT, VI
tPLH
tPHL
tr
tf
tf
tr
tPHL
1.3V
10%
1.3V
OUTPUT, VO
(74OL6000)
OUTPUT, VO
(74OL6001)
tPLH
Figure 17. 74OL6000/01 Switching Times vs. Ambient Temperature
Figure 19. Common Mode Rejection Waveforms Figure 20. Suggested PCB Lay-Out
3.2V
1.3V
90%
50%
90%
50%
10%
INPUT, VI
tPLH
tPHL
tr
tf
tf
tr
tPHL
10%
OUTPUT, VO
(74OL6010)
OUTPUT, VO
(74OL6011)
tPLH
Figure 18. Switching Parameters 74OL6010/11
VCM
VOH
VOL
0V
50V
dVCM
dt
VCM
CMH
CML
VO = 2.0V (MIN.)
VO = 0.8V (MAX.)
tr
=
INPUT
VCC
BUS
DATA
IN
INPUT
GND
BUS
OUTPUT
GND
BUS
OUTPUT
VCC
BUS
.1µF
1
2
3
.1µF
6
5
4
DATA
OUT
— FAIRCHILD — SEMICCJNDLJCTCJR“D
10/1/03
Page 11 of 15
© 2003 Fairchild Semiconductor Corporation
TTL BUFFER 74OL6000
TTL INVERTER 74OL6001
CMOS BUFFER 74OL6010
CMOS INVERTER 74OL6011
LSTTL TO
OPTOPLANAR® HIGH-SPEED
LOGIC-TO-LOGIC OPTOCOUPLERS
NOTE
All dimensions are in inches (millimeters)
Package Dimensions (Through Hole) Package Dimensions (Surface Mount)
Package Dimensions (0.4 Lead Spacing) Recommended Pad Layout for
Surface Mount Leadform
0.100 (2.54)
TYP
0.020 (0.51)
MIN
0.350 (8.89)
0.330 (8.38)
0.270 (6.86)
0.240 (6.10)
PIN 1
ID.
0.022 (0.56)
0.016 (0.41)
0.070 (1.78)
0.045 (1.14)
0.200 (5.08)
0.115 (2.92)
0.300 (7.62)
TYP
0° to 15°
0.154 (3.90)
0.100 (2.54)
SEATING PLANE
0.016 (0.40)
0.008 (0.20)
Lead Coplanarity : 0.004 (0.10) MAX
0.270 (6.86)
0.240 (6.10)
0.350 (8.89)
0.330 (8.38)
0.300 (7.62)
TYP
0.405 (10.30)
MAX
0.315 (8.00)
MIN
0.016 (0.40) MIN
2
5
PIN 1
ID.
0.016 (0.41)
0.008 (0.20)
0.100 (2.54)
TYP
0.022 (0.56)
0.016 (0.41)
0.070 (1.78)
0.045 (1.14)
0.200 (5.08)
SEATING PLANE
0.165 (4.18)
4
3
0.020 (0.51)
MIN
1
6
SEATING PLANE
0.016 (0.40)
0.008 (0.20)
0.070 (1.78)
0.045 (1.14)
0.350 (8.89)
0.330 (8.38)
0.154 (3.90)
0.100 (2.54)
0.200 (5.08)
0.135 (3.43)
0.004 (0.10)
MIN
0.270 (6.86)
0.240 (6.10)
0.400 (10.16)
TYP
0° to 15°
0.022 (0.56)
0.016 (0.41)
0.100 (2.54) TYP
PIN 1
ID.
0.070
(
1.78
)
0.060
(
1.52
)
0.030
(
0.76
)
0.100
(
2.54
)
0.295
(
7.49
)
0.415
(
10.54
)
— FAIRCHILD SEMICONDUCTOR“ xi;
10/1/03
Page 12 of 15
© 2003 Fairchild Semiconductor Corporation
TTL BUFFER 74OL6000
TTL INVERTER 74OL6001
CMOS BUFFER 74OL6010
CMOS INVERTER 74OL6011
LSTTL TO
OPTOPLANAR® HIGH-SPEED
LOGIC-TO-LOGIC OPTOCOUPLERS
ORDERING INFORMATION
MARKING INFORMATION
Option Order Entry Identifier Description
S .S Surface Mount Lead Bend
SD .SD Surface Mount; Tape and Reel
W .W 0.4" Lead Spacing
300 .300 VDE 0884
300W .300W VDE 0884, 0.4" Lead Spacing
3S .3S VDE 0884, Surface Mount
3SD .3SD VDE 0884, Surface Mount, Tape and Reel
74OL6000
V XX YY K
1
2
6
43 5
Definitions
1 Fairchild logo
2 Device number
3VDE mark (Note: Only appears on parts ordered with VDE
option See order entry table)
4 Two digit year code, e.g., 03
5 Two digit work week ranging from 01 to 53
6 Assembly package code
FAIRCHILD SEMICONDUCTOR“ P‘ L—4
10/1/03
Page 13 of 15
© 2003 Fairchild Semiconductor Corporation
TTL BUFFER 74OL6000
TTL INVERTER 74OL6001
CMOS BUFFER 74OL6010
CMOS INVERTER 74OL6011
LSTTL TO
OPTOPLANAR® HIGH-SPEED
LOGIC-TO-LOGIC OPTOCOUPLERS
Reflow Profile (Black Package, No Suffix)
Peak reflow temperature: 225° C (package surface temperature)
Time of temperature higher than 183° C for 60150 seconds
One time soldering reflow is recommended
215°C, 1030 s
225 C peak
Time (Minute)
0
300
250
200
150
100
50
0
0.5 1 1.5 2 2.5 3 3.5 4 4.5
Temperature (°C)
Time above 183° C, 60150 sec
Ramp up = 3 C/sec
— FAIRCHILD — SEMICONDUCTDRG mu n5 aw \NTERVAL Lm -Hsm -vw -Hgm - mm 4. page ‘ 740Lsnoo swan 740 L30
10/1/03
Page 14 of 15
© 2003 Fairchild Semiconductor Corporation
TTL BUFFER 74OL6000
TTL INVERTER 74OL6001
CMOS BUFFER 74OL6010
CMOS INVERTER 74OL6011
LSTTL TO
OPTOPLANAR® HIGH-SPEED
LOGIC-TO-LOGIC OPTOCOUPLERS
0.1 µ
F
10
1.1 K
100 µ
F
1 K
1.1 K
1N6263
ALL DIODES
2N4252
2N4252
2N2222
PRSG
100 ns BIT
INTERVAL
12
250 FT.
4
8
74OL6000
LS04 9
5
LS04
250 FT.
1110
250 FT.250 FT.
6
LS04
7
LS04
BUFFER
600174OL 6001
OL
74 6001
OL
74 600174OL
1000 FT.
75
TERMINAION
3
APPLICATION
Local area data communication systems can greately improve their noise immunity by including OPOTOLOGIC gates in the
design.
The Optologic input amplifier offers the feature of very high input impedance that permits their use as bridged line receivers. The
system show above illustrates an optically isolated transmitter and multidrop receiver system. The network uses a 74OL6000 and
buffer (Figure D) to isolate the transmitter and drive the 75 coax cable. This application uses a 1000 ft. aerial suspension 75
CATV coax cable with data taps at 250 ft. intervals. The 74OL6001s function as bridged receivers, and as many as 30 receivers
could be placed along the line with minimal signal degradation. The communication cable is terminated with a single 75 load at
the far end of the line.
Signal quality "Eye Pattern" is shown in Figures A, B and C with a 10MBaud NRZ Psuedo-Random Sequence (PRS). Traces 1-3 in
Figure A describes the transmitter section. Traces 4-7 in Figure B show the output of the four Optologic bridged terminations.
Traces 8-11 in Figure C illustrate "Eye Pattern" as seen at the output of a 74LS04 logic gate. The data quality is well preserved in
that only a 30% Eye closure is seen at the receiver located 1000 ft. from the transmitter.
The data communication system is completely optically isolated from all of the terminal equipments. Power for the transmitter
(VCCO) and receiver (VCCI) is taken from an isolated power supply and distributed through a drain or messenger wire.
Figure A Figure B Figure C
HORIZONTAL = 20 ns/DIV 42-11 HORIZONTAL = 20 ns/DIV 42-12, 02 HORIZONTAL = 20 ns/DIV 42-13/03
VERTICAL = 2 V/DIV VERTICAL = 2 V/DIV VERTICAL = 2 V/DIV
Figure D Buffer
— FAIRCHILD SEMICONDUCTOR“
LIFE SUPPORT POLICY
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
10/1/03
Page 15 of 15
© 2003 Fairchild Semiconductor Corporation
TTL BUFFER 74OL6000
TTL INVERTER 74OL6001
CMOS BUFFER 74OL6010
CMOS INVERTER 74OL6011
LSTTL TO
OPTOPLANAR® HIGH-SPEED
LOGIC-TO-LOGIC OPTOCOUPLERS

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