AT88SC1616C Summary Datasheet by Microchip Technology

Atmet This is a summary document.

AT88SC1616C

Atmel CryptoMemory, 16-Kbit

SUMMARY DATASHEET

Features

• One of a family of nine devices with user memories from 1-Kbit to 256-Kbit

• 16-Kbit (2-Kbyte) EEPROM user memory

• Sixteen 128-byte (1-Kbit) zones

• Self-timed write cycle

• Single byte or 16-byte page write mode

• Programmable access rights for each zone

• 2-Kbit configuration zone

• 37-byte OTP area for user-defined codes

• 160-byte area for user-defined keys and passwords

• High security features

• 64-bit mutual authentication protocol (under license of ELVA)

• Encrypted checksum

• Stream encryption

• Four key sets for authentication and encryption

• Eight sets of two 24-bit passwords

• Anti-tearing function

• Voltage and frequency monitor

• Smart card features

• ISO 7816 Class A (5V) or Class B (3V) operation

• ISO 7816-3 asynchronous T = 0 protocol (Gemplus® patent) *

• Multiple zones, key sets and passwords for multi-application use

• Synchronous 2-wire serial interface for faster device initialization *

• Programmable 8-byte answer-to-reset register

• ISO 7816-2 compliant modules

• Embedded application features

• Low voltage operation: 2.7V to 5.5V

• Secure nonvolatile storage for sensitive system or user information

• 2-wire serial interface

• 1.0MHz compatibility for fast operation

• Standard 8-lead plastic packages, green compliant (exceeds RoHS)

• Same pinout as 2-wire Serial EEPROMs

• High Reliability

• Endurance: 100,000 cycles

• Data retention: 10 years

• ESD protection: 4,000V min

* Note: Modules available with either T=0 / 2-wire modes or 2-wire mode only

This is a summary document.

The complete document is

available on the Atmel website

at www.atmel.com.

Atmel-2030MS-CryptoMem-AT88SC1616C-Datasheet-Summary_122013

Pad on ISO Module TWI Module Standard Package Iso Smart Card Module S—lead SOIC. PDIP I: I: I: I: |:| |:| |:| |:| Atmel

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Table 1. Pin Assignment

Pad Description ISO Module TWI Module Standard Package Pin

VCC Supply Voltage C1 C1 8

GND Ground C5 C5 4

SCL/CLK Serial Clock Input C3 C3 6

SDA/IO Serial Data Input/Output C7 C7 5

RST Reset Input C2 NC NC

Figure 1. Pin Configuration

1. Description

The Atmel® AT88SC1616C member of the Atmel CryptoMemory® family is a high-performance secure memory providing

16-Kbits of user memory with advanced security and cryptographic features built in. The user memory is divided into 16 128-

byte zones, each of which may be individually set with different security access rights or effectively combined together to

provide space for 1 to 16 data files.

1.1 Smart Card Applications

The AT88SC1616C provides high security, low cost, and ease of implementation without the need for a microprocessor

operating system. The embedded cryptographic engine provides for dynamic and symmetric mutual authentication between

the device and host, as well as performing stream encryption for all data and passwords exchanged between the device and

host. Up to four unique key sets may be used for these operations. The AT88SC1616C offers the ability to communicate with

virtually any smart card reader using the asynchronous T = 0 protocol (Gemplus patent) defined in ISO 7816-3.

1.2 Embedded Applications

Through dynamic and symmetric mutual authentication, data encryption, and the use of encrypted checksums, the

AT88SC1616C provides a secure place for storage of sensitive information within a system. With its tamper detection circuits,

this information remains safe even under attack. A 2-wire serial interface running at 1.0MHz is used for fast and efficient

communications with up to 15 devices that may be individually addressed. The AT88SC1616C is available in industry standard

8-lead packages with the same familiar pinout as 2-wire serial EEPROMs.

=C1

RST=C2

SCL/CLK=C3

NC=C4

ISO Smart Card Module

C5=GND

C6=NC

C7=SDA/IO

C8=NC

GND

8-lead SOIC, PDIP

SCL

SDA

=C1

NC=C2

SCL/CLK=C3

NC=C4

TWI Smart Card Module

C5=GND

C6=NC

C7=SDA/IO

C8=NC

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Figure 1-1. Block Diagram

2. Pin Descriptions

2.1 Supply Voltage (VCC)

The VCC input is a 2.7V to 5.5V positive voltage supplied by the host.

2.2 Clock (SCL/CLK)

In the asynchronous T = 0 protocol, the SCL/CLK input is used to provide the device with a carrier frequency f. The nominal

length of one bit emitted on I/O is defined as an “elementary time unit” (ETU) and is equal to 372/f. When the synchronous

protocol is used, the SCL/CLK input is used to positive edge clock data into the device and negative edge clock data out of the

device.

2.3 Reset (RST)

The AT88SC1616C provides an ISO 7816-3 compliant asynchronous answer to reset sequence. When the reset sequence is

activated, the device will output the data programmed into the 64-bit answer-to-reset register. An internal pull-up on the RST

input pad allows the device to be used in synchronous mode without bonding RST. The AT88SC1616C does not support the

synchronous answer-to-reset sequence.

2.4 Serial Data (SDA/IO)

The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wired with any number of other

open drain or open collector devices. An external pull-up resistor should be connected between SDA and VCC. The value of

this resistor and the system capacitance loading the SDA bus will determine the rise time of SDA. This rise time will determine

the maximum frequency during read operations. Low value pull-up resistors will allow higher frequency operations while

drawing higher average power. SDA/IO information applies to both asynchronous and synchronous protocols.

When the synchronous protocol is used, the SCL/CLK input is used to positive edge clock data into the device and negative

edge clock data out of the device.

Random

Generator

Authentication,

Encryption and

Certification Unit

EEPROM

Answer to Reset

Data Transfer

Password

Verification

Reset Block

Asynchronous

ISO Interface

Synchronous

Interface

Power

Management

GND

SCL/CLK

SDA/IO

RST

*Nolice: Skresses beyond those listed under “Absolute Symbol Parameter ‘TestCondition \ Min \ Typ Max Units Vccm (U (1) (U H(1K2) H(1K2) \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ Hr! “27 ‘ ‘ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ 4 Atmel

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3. Absolute Maximum Ratings*

Operating temperature .................... −40°C to +85°C

Storage temperature ................... −65°C to + 150°C

Voltage on any pin

with respect to ground ............... − 0.7 to VCC +0.7V

Maximum operating voltage ............................. 6.0V

DC output current ......................................... 5.0mA

*Notice: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional

operation of the device at these or any other condition

beyond those indicated in the operational sections of

this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods of

time may affect device reliability.

Table 3-1. DC Characteristics

Applicable over recommended operating range from VCC = +2.7 to 5.5V, TAC = -40°C to +85°C (unless otherwise noted)

Symbol Parameter Test Condition Min Typ Max Units

VCC

(2)

Supply Voltage

2.7

5.5 V

ICC Supply Current (VCC = 5.5V) Async Read at 3.57MHz

5 mA

ICC Supply Current (VCC = 5.5V) Async Write at 3.57MHz

5 mA

ICC Supply Current (VCC = 5.5V) Synch Read at 1MHz

5 mA

ICC Supply Current (VCC = 5.5V) Synch Write at 1MHz

5 mA

ISB Standby Current (VCC = 5.5V) VIN = VCC or GND

100 µA

VIL

(1)

SDA/IO Input Low Threshold

VCC x 0.2 V

VIL(1) SCL/CLK Input Low Threshold

VCC x 0.2 V

VIL(1) RST Input Low Threshold

VCC x 0.2 V

VIH

(1)(2)

SDA/IO Input High Threshold

VCC x 0.7

VCC V

VIH(1)(2) SCL/CLK Input High Threshold

VCC x 0.7

VCC V

VIH(1)(2) RST Input High Threshold

VCC x 0.7

VCC V

IIL SDA/IO Input Low Current 0 < VIL < VCC x 0.15

15 µA

IIL SCL/CLK Input Low Current 0 < VIL < VCC x 0.15

15 µA

IIL RST Input Low Current 0 < VIL < VCC x 0.15

50 µA

IIH SDA/IO Input High Current VCC x 0.7 < VIH < VCC

20 µA

IIH SCL/CLK Input High Current VCC x 0.7 < VIH < VCC

100 µA

IIH RST Input High Current VCC x 0.7 < VIH < VCC

150 µA

VOH SDA/IO Output High Voltage 20K ohm external pull-up VCC x 0.7

VCC V

VOL SDA/IO Output Low Voltage IOL = 1mA 0

VCC x 0.15 V

IOH SDA/IO Output High Current VOH

20 µA

Notes: 1. VIL min and VIH max are reference only and are not tested

2. To prevent latch up conditions from occurring during power up of the AT88SCxxxxC, VCC must be turned on

before applying VIH. For powering down, VIH must be removed before turning VCC off

Symbol Palameler Atmel 5

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Table 3-2. AC Characteristics

Applicable over recommended operating range from VCC = +2.7 to 5.5V, TAC = -40°C to +85°C, CL = 30pF

(unless otherwise noted)

Symbol Parameter Min Max Units

fCLK Async Clock Frequency (VCC Range: +4.5 - 5.5V) 1 5 MHZ

fCLK Async Clock Frequency (VCC Range: +2.7 - 3.3V) 1 4 MHZ

fCLK Synch Clock Frequency 0 1 MHZ

Clock Duty cycle 40 60 %

tR Rise Time - I/O, RST

1 µS

tF Fall Time - I/O, RST

1 µS

tR Rise Time - CLK

9% x period µS

tF Fall Time - CLK

9% x period µS

tAA Clock Low to Data Out Valid

35 nS

tHD.STA Start Hold Time 200

tSU.STA Start Set-up Time 200

tHD.DAT Data In Hold Time 10

tSU.DAT Data In Set-up Time 100

tSU.STO Stop Set-up Time 200

tDH Data Out Hold Time 20

tWR Write Cycle Time (at 25

5 mS

tWR Write Cycle Time (-40° to +85°C)

7 mS

4. Device Operation for Synchronous Protocols

Clock and Data Transitions:

The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time

periods (see Figure 4-3 on page 7). Data changes during SCL high periods will indicate a start or stop condition as defined

below.

Start Condition:

A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 4-4 on

page 7).

Stop Condition:

A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the

EEPROM in a standby power mode (see Figure 4-4 on page 7).

Acknowledge:

All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to

acknowledge that it has received each word. This happens during the ninth clock cycle (see Figure 4-5 on page 7).

Memory Reset:

After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by following these steps:

1. Clock up to nine cycles

2. Look for SDA high in each cycle while SCL is high

3. Create a start condition

”T” 7 ”E s ’//////////M __ﬂ H H W H H S:X\ﬂ Atmel

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Figure 4-1. Bus Timing for 2-wire Communications

SCL: Serial Clock, SDA – Serial Data I/O

Figure 4-2. Write Cycle Timing: SCL

Serial Clock, SDA – Serial Data I/O

Note: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal

clear/write cycle

SCL

SDA IN

SDA OUT

HIGH

LOW

BUF

SU.STO

SU.DAT

HD.DAT

HD.STA

SU.STA

(1)

STOP

CONDITION

START

CONDITION

WORDn

ACK

8th BIT

SCL

SDA

DATA CHANGE ALLOWED // l/ ﬂﬁ START STOP Atmel

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Figure 4-3. Data Validity

Figure 4-4. Start and Stop Definitions

Figure 4-5. Output Acknowledge

DATA

CHANGE

ALLOWED

DATA STABLEDATA STABLE

SDA

SCL

SDA

SCL

START STOP

SCL

DATA IN

DATA OUT

EGDELWONK

CATRATS

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5. Device Architecture

5.1 User Zones

The EEPROM user memory is divided into 16 zones of 1024 bits each. Multiple zones allow for different types of data or files

to be stored in different zones. Access to the user zones is allowed only after security requirements have been met. These

security requirements are defined by the user during the personalization of the device in the configuration memory. If the same

security requirements are selected for multiple zones, then these zones may effectively be accessed as one larger zone.

Figure 5-1. User Zones

Zone

User 0 $00

─

128 bytes

─

$78

User 1

─

User 14

$00

─

$78

User 15 $00

─

128 bytes

─

$78

6. Control Logic

Access to the user zones occurs only through the control logic built into the device. This logic is configurable through access

registers, key registers and keys programmed into the configuration memory during device personalization. Also implemented

in the control logic is a cryptographic engine for performing the various higher-level security functions of the device.

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7. Configuration Memory

The configuration memory consists of 2048 bits of EEPROM memory used for storing passwords, keys and codes and for

defining security levels to be used for each user zone. Access rights to the configuration memory are defined in the control

logic and may not be altered by the user.

Figure 7-1. Configuration Memory

$0 $1 $2 $3 $4 $5 $6 $7

$00 Answer to Reset Identification

$08 Fab Code MTZ Card Manufacturer Code

$10 Lot History Code Read Only

$18 DCR Identification Number Nc

Access Control

$20 AR0 PR0 AR1 PR1 AR2 PR2 AR3 PR3

$28 AR4 PR4 AR5 PR5 AR6 PR6 AR7 PR7

$30 AR8 PR8 AR9 PR9 AR10 PR10 AR11 PR11

$38 AR12 PR12 AR13 PR13 AR14 PR14 AR15 PR15

$40 Issuer Code

$48

$50

For Authentication and Encryption Use Cryptography

$58

$60

$68

$70

$78

$80

$88

$90

For Authentication and Encryption Use Secret

$98

$A0

$A8

$B0 PAC Write 0 PAC Read 0

Password

$B8 PAC Write 1 PAC Read 1

$C0 PAC Write 2 PAC Read 2

$C8 PAC Write 3 PAC Read 3

$D0 PAC Write 4 PAC Read 4

$D8 PAC Write 5 PAC Read 5

$E0 PAC Write 6 PAC Read 6

$E8 PAC Write 7 PAC Read 7

$F0 Reserved Forbidden

$F8

10 [ CLK»scL W Atmel

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8. Security Fuses

There are three fuses on the device that must be blown during the device personalization process. Each fuse locks certain

portions of the configuration memory as OTP memory. Fuses are designed for the module manufacturer, card manufacturer

and card issuer and should be blown in sequence, although all programming of the device and blowing of the fuses may be

performed at one final step.

9. Protocol Selection

The AT88SC1616C supports two different communication protocols.

• Smart Card Applications:

The asynchronous T = 0 protocol defined by ISO 7816-3 is used for compatibility with the industry’s standard smart

card readers

• Embedded Applications:

A 2-wire serial interface is used for fast and efficient communication with logic or controllers

The power-up sequence determines which of the two communication protocols will be used.

9.1 Asynchronous T = 0 Protocol

This power-up sequence complies with ISO 7816-3 for a cold reset in smart card applications.

• VCC goes high; RST, I/O-SDA and CLK-SCL are low

• Set I/O-SDA in receive mode

• Provide a clock signal to CLK-SCL

• RST goes high after 400 clock cycles

The device will respond with a 64-bit ATR code, including historical bytes to indicate the memory density within the

CryptoMemory family. Once the asynchronous mode has been selected, it is not possible to switch to the synchronous mode

without powering off the device.

Figure 9-1. Asynchronous T = 0 Protocol (Gemplus Patent)

Vcc

I/O-SDA

RST

CLK-SCL

ATR

Mode Configuration Data User Data Passwords Data Integrity Check Atmel ‘1

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9.2 Synchronous 2-wire Serial Interface

The synchronous mode is the default after powering up VCC due to an internal pull-up on RST. For embedded applications

using CryptoMemory in standard plastic packages, this is the only communication protocol.

• Power-up VCC, RST goes high also

• After stable VCC, CLK-SCL and I/O-SDA may be driven

Figure 9-2. Synchronous 2-wire Protocol

Note: Five clock pulses must be sent before the first command is issued

10. Communication Security Modes

Communications between the device and host operate in three basic modes. Standard mode is the default mode for the

device after power-up. Authentication mode is activated by a successful authentication sequence. Encryption mode is

activated by a successful encryption activation following a successful authentication.

Table 10-1. Communication Security Modes(1)

Mode Configuration Data User Data Passwords Data Integrity Check

Standard Clear Clear Clear MDC

Authentication Clear Clear Encrypted MAC

Encryption Clear Encrypted Encrypted MAC

Notes: 1. Configuration data include viewable areas of the configuration zone except the passwords:

 MDC: Modification Detection Code

 MAC: Message Authentication Code

Vcc

I/O-SDA

RST

CLK-SCL 12345

12 Address $0 $1 $2 $3 $4 $5 $6 $7 Atmel

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11. Security Options

11.1 Anti-tearing

In the event of a power loss during a write cycle, the integrity of the device’s stored data may be recovered. This function is

optional – the host may choose to activate the anti-tearing function, depending on application requirements. When anti-tearing

is active, write commands take longer to execute, since more write cycles are required to complete them, and data are limited

to eight bytes.

Data are written first to a buffer zone in EEPROM instead of the intended destination address, but with the same access

conditions. The data are then written in the required location. If this second write cycle is interrupted due to a power loss, the

device will automatically recover the data from the system buffer zone at the next power-up.

In 2-wire mode, the host is required to perform ACK polling for up to 8mS after write commands when anti-tearing is active. At

power-up, the host is required to perform ACK polling, in some cases for up to 2mS, in the event that the device needs to carry

out the data recovery process.

11.2 Write Lock

If a user zone is configured in the write lock mode, the lowest address byte of an 8-byte page constitutes a write access byte

for the bytes of that page.

Example: The write lock byte at $080 controls the bytes from $080 to $087

Table 11-1. Write Lock Example

Address $0 $1 $2 $3 $4 $5 $6 $7

$080 11011001 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx

locked locked

locked

The write lock byte may also be locked by writing its least significant (rightmost) bit to “0”. Moreover, when write lock mode is

activated, the write lock byte can only be programmed – that is, bits written to “0” cannot return to “1”. In the write lock

configuration, only one byte can be written at a time. Even if several bytes are received, only the first byte will be taken into

account by the device.

‘7:- Atmel *0 13

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12. Password Verification

Passwords may be used to protect read and/or write access of any user zone. When a valid password is presented, it is

memorized and active until power is turned off, unless a new password is presented or RST becomes active. There are eight

password sets that may be used to protect any user zone. Only one password is active at a time, but write passwords give

read access also.

12.1 Authentication Protocol

The access to a user zone may be protected by an authentication protocol. Any one of four keys may be selected to use with a

user zone.

The authentication success is memorized and active as long as the chip is powered, unless a new authentication is initialized

or RST becomes active. If the new authentication request is not validated, the card loses its previous authentication and it

should be presented again. Only the last request is memorized.

Note: Password and authentication may be presented at any time and in any order. If the trials limit has been reached

(after four consecutive incorrect attempts), the password verification or authentication process will not be taken

into account

Figure 12-1. Password and Authentication Operations

Device (Card)

Card Number

VERIFY A

COMPUTE Challenge B

Challenge B

VERIFY RPW

DATA

Checksum (CS)

VERIFY WPW

VERIFY CS

Write DATA

Host (Reader)

COMPUTE Challenge A

Challenge A

VERIFY B

Read Password (RPW)

VERIFY CS

Write Password (WPW)

DATA

AUTHENTICATION

READ ACCESS

WRITE ACCESS

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12.2 Checksum

The AT88SC1616C implements a data validity check function in the form of a checksum, which may function in standard,

authentication or encryption modes.

In the standard mode, the checksum is implemented as a Modification Detection Code (MDC), in which the host may read an

MDC from the device in order to verify that the data sent was received correctly.

In the authentication and encryption modes, the checksum becomes more powerful since it provides a bidirectional data

integrity check and data origin authentication capability in the form of a Message Authentication Code (MAC). Only the

host/device that carried out a valid authentication is capable of computing a valid MAC. While operating in the authentication

or encryption modes, the use of a MAC is required. For an ingoing command, if the device calculates a MAC different from the

MAC transmitted by the host, not only is the command abandoned but the mode is also reset. A new authentication and/or

encryption activation will be required to reactivate the MAC.

12.3 Encryption

The data exchanged between the device and the host during read, write and verify password commands may be encrypted to

ensure data confidentiality.

The issuer may choose to require encryption for a user zone by settings made in the configuration memory. Any one of four

keys may be selected for use with a user zone. In this case, activation of the encryption mode is required in order to read/write

data in the zone and only encrypted data will be transmitted. Even if not required, the host may elect to activate encryption

provided the proper keys are known.

12.4 Supervisor Mode

Enabling this feature allows the holder of one specific password to gain full access to all eight password sets, including the

ability to change passwords.

12.5 Modify Forbidden

No write access is allowed in a user zone protected with this feature at any time. The user zone must be written during device

personalization prior to blowing the security fuses.

12.6 Program Only

For a user zone protected by this feature, data within the zone may be changed from a “1” to a “0”, but never from a “0” to a

“1”.

13. Initial Device Programming

To enable the security features of CryptoMemory, the device must first be personalized to set up several registers and load in

the appropriate passwords and keys. This is accomplished through programming the configuration memory of CryptoMemory

using simple write and read commands. To gain access to the configuration memory, the secure code must first be

successfully presented. For the AT88SC1616C device, the secure code is $20 0C E0. After writing and verifying data in the

configuration memory, the security fuses must be blown to lock this information in the device. For additional information on

personalizing CryptoMemory, please see the application notes Programming CryptoMemory for Embedded Applications and

Initializing CryptoMemory for Smart Card Applications (at www.Atmel.com).

Almel Order 9 Code Package \ Voltage Range Temperature Range Package Type“) ‘21 Atmel 15

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14. Ordering Information

Atmel Ordering Code Package Voltage Range Temperature Range

AT88SC1616C-MJ

AT88SC1616C-MP

AT88SC1616C-MJTG

AT88SC1616C-MPTG

M2 – J Module – ISO

M2 – P Module - ISO

M2 – J Module – TWI

M2 – P Module - TWI

2.7V–5.5V Commercial (0°C–70°C)

AT88SC1616C-PU

AT88SC1616C-SH

8P3

8S1

2.7V–5.5V Green compliant (exceeds RoHS)

Industrial (−40°C–85°C)

AT88SC1616C-WI 7 mil wafer 2.7V–5.5V Industrial (−40°C–85°C)

Package Type

(1) (2)

Description

M2 – J Module : ISO or TWI M2 ISO 7816 smart card module

M2 – P Module : ISO or TWI M2 ISO 7816 smart card module with Atmel® logo

8P3 8-lead, 0.300” wide, Plastic Dual Inline (PDIP)

8S1 8-lead, 0.150” wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

Notes: 1. Formal drawings may be obtained from an Atmel sales office

2. Both the J and P module packages are used for either ISO (T=0 / 2-wire mode) or TWI (2-wire mode only)

16 Atmel

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15. Packaging Information

Ordering Code: MJ or MJTG Ordering Code: MP or MPTG

Module Size: M2

Dimension*: 12.6 x 11.4 [mm]

Glob Top: Round - ∅ 8.5 [mm]

Thickness: 0.58 [mm]

Pitch: 14.25mm

Module Size: M2

Dimension*: 12.6 x 11.4 [mm]

Glob Top: Square - 8.8 x 8.8 [mm]

Thickness: 0.58 [mm]

Pitch: 14.25mm

Note: *The module dimensions listed refer to the dimensions of the exposed metal contact area. The actual dimensions

of the module after excise or punching from the carrier tape are generally 0.4mm greater in both directions

(i.e., a punched M2 module will yield 13.0 x 11.8mm)

8»lead SOIC 8»lead PDIP w : Vear ww : Work Week o1 Assembly v: Year M : Momh 12 2012 02.Week 2 2 2012 A: January AtmeL Atmel 17

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15.1 Atmel AT88SC1616C Package Marking Information

DRAWING NO. REV.

TITLE

U YYWW

1616C

AT88SC

8-lead PDIP

H YMXX @

1616C

AT88SC

8-lead SOIC

Note 2: Package drawings are not to scale

Note 1: designates pin 1

No Bottom side mark (this package)

88SC1616CSM A

3/5/12

88SC1616CSM, AT88SC1616C Package Marking Information

Date Codes Grade/Lead Finish Material

YY = Year WW = Work Week of Assembly Y = Year M = Month U: Industrial/Matte Tin

12: 2012 02:Week 2 2: 2012 A = January H: Industrial/NiPdAu

13: 2013 04:Week 4 3: 2013 B = February

14: 2014 ... 4: 2014 ...

15: 2015 52:Week 52 5: 2015 L = December

Country of Assembly Lot Number Atmel Truncation

@ = Country of Assembly Marked on Bottom side for the PDI P only! AT: Atmel

Marked on Bottom side unless in

Injector Mold for PDI P only!

Trace Code

XX = Trace Code (Atmel Lot Numbers to Correspond to Code)

Example: AA, AB.... YZ, ZZ

AT88SC1616C: Package Marking Information

Package Mark Contact:

DL-CSO-Assy_eng@atmel.com

AtmeL ‘8 Atmel

AT88SC1616C [SUMMARY DATASHEET]

Atmel-2030MS-CryptoMem-AT88SC1616C-Datasheet-Summary_122013

15.2 Ordering Code: SH

8S1 – 8-lead JEDEC SOIC

DRAWING NO. REV.TITLE GPC

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A1 0.10 –0.25

A1.35 –1.75

b0.31 –0.51

C0.17 –0.25

D4.80 –5.05

E1 3.81 –3.99

E5.79 –6.20

e1.27 BSC

L0.40 –1.27

0° –8°

TOP VIEW

END VIEW

SIDE VIEW

Package Drawing Contact:

packagedrawings@atmel.com

8S1 G

6/22/11

Notes: This drawing is for general information only.

Refer to JEDEC Drawing MS-012, Variation AA

for proper dimensions, tolerances, datums, etc.

8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing

Small Outline (JEDEC SOIC) SWB

AT88SC1616C [SUMMARY DATASHEET]

Atmel-2030MS-CryptoMem-AT88SC1616C-Datasheet-Summary_122013

15.3 Ordering Code: PU

8P3 – 8-lead PDIP

DRAWING NO. REV.TITLE GPC

Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.

2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.

3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.

4. E and eA measured with the leads constrained to be perpendicular to datum.

5. Pointed or rounded lead tips are preferred to ease insertion.

6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).

COMMON DIMENSIONS

(Unit of Measure = inches)

SYMBOL MIN NOM MAX NOTE

A2 A

4 PLCS

A0.210 2

A2 0.115 0.130 0.195

b0.014 0.018 0.022 5

b2 0.045 0.060 0.070 6

b3 0.030 0.039 0.045 6

c0.008 0.010 0.014

D0.355 0.365 0.400 3

D1 0.005 3

E0.300 0.310 0.325 4

E1 0.240 0.250 0.280 3

e0.100 BSC

eA 0.300 BSC 4

L 0.115 0.130 0.150 2

Top View

Side View

End View

Package Drawing Contact:

packagedrawings@atmel.com

8P3 D

06/21/11

8P3, 8-lead, 0.300” Wide Body, Plastic Dual

In-line Package (PDIP) PTC

Comments 2° Atmel

AT88SC1616C [SUMMARY DATASHEET]

Atmel-2030MS-CryptoMem-AT88SC1616C-Datasheet-Summary_122013

16. Revision History

Doc. Rev. Date Comments

2030MS 12/2013 Add package marking information.

Update Atmel logos and disclaimer page.

2030LS 12/2011 Update template.

Update package drawings.

Change AT88SC1616C-SU to AT88SC1616C-SH.

2030KS 10/2009 Features Section – add ‘Green compliant (exceeds RoHS) to end of ‘Standard

8-lead Plastic Packages’ bullet added Note to DC Characteristics table and

applied to VCC and all 3 instances of Vih symbols in table.

Ordering Information page: Add ‘Green compliant (exceeds RoHS) to middle

row of Temperature Range Replace ‘Lead-free/Halogen-free. Keep industrial.

SB - TWI Package update.

2030JS 11/2008 Removed P module offering.

2030IS 04/2007 Updated timing diagrams.

2030IS 01/2007 Final release version.

2030IS 01/2007 Replaced User Zone, Configuration Memory, and Write Lock.

Example tables with new information.

Atmet ‘ Enabling UnHmiKed Posswbilities‘ “an. i ‘W

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