dsPIC33FJ(32,64,128)MC(x02,x04) Errata & Datasheet Clarification by Microchip Technology

6‘ MICROCHIP Conﬂgure>Select Del/Ice (DebuggebSe/ect T00! (DebuggebConnect

 2009-2015 Microchip Technology Inc. DS80000442K-page 1

dsPIC33FJ32MC302/304,

dsPIC33FJ64MCX02/X04 and

dsPIC33FJ128MCX02/X04

The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/

X04 and dsPIC33FJ128MCX02/X04 family devices that

you have received conform functionally to the current

Device Data Sheet (DS70291G), except for the

anomalies described in this document.

The silicon issues discussed in the following pages are

for silicon revisions with the Device and Revision IDs

listed in Table 1. The silicon issues are summarized in

Table 2.

The errata described in this document will be addressed

in future revisions of the dsPIC33FJ32MC302/304,

dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/

X04 silicon.

Data Sheet clarifications and corrections start on

Page 13, following the discussion of silicon issues.

The silicon revision level can be identified using the

current version of MPLAB

IDE and Microchip’s

programmers, debuggers and emulation tools, which

are available at the Microchip corporate web site

(www.microchip.com).

For example, to identify the silicon revision level using

MPLAB IDE in conjunction with MPLAB ICD 3 or

PICkit™ 3:

1. Using the appropriate interface, connect the device

to the MPLAB ICD 3 programmer/debugger or

PICkit 3.

2. From the main menu in MPLAB IDE, select

Configure>Select Device, and then select the

target part number in the dialog box.

3. Select the MPLAB hardware tool

(Debugger>Select Tool).

4. Perform a “Connect” operation to the device

(Debugger>Connect). Depending on the devel-

opment tool used, the part number and Device

Revision ID value appear in the Output window.

The Device and Revision ID values for the various

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04

and dsPIC33FJ128MCX02/X04 silicon revisions are

shown in Table 1.

Note: This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the

issues indicated in the last column of

Table 2 apply to the current silicon

revision (A5).

Note: If you are unable to extract the silicon

revision level, please contact your local

Microchip sales office for assistance.

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and

dsPIC33FJ128MCX02/X04 Family

Silicon Errata and Data Sheet Clarification

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/X04

DS80000442K-page 2  2009-2015 Microchip Technology Inc.

TABLE 1: SILICON DEVREV VALUES

Part Number Device ID

(1)

Revision ID for Silicon Revision

(2)

A1 A2 A3 A4 A5

dsPIC33FJ32MC302 0x0601

0x3001 0x3002 0x3002 0x3003 0x3004

dsPIC33FJ32MC304 0x0603

dsPIC33FJ64MC202 0x0611

dsPIC33FJ64MC204 0x0613

dsPIC33FJ64MC802 0x0619

dsPIC33FJ64MC804 0x061B

dsPIC33FJ128MC202 0x0621

0x3001 0x3002 0x3002 0x3003 0x3004

dsPIC33FJ128MC204 0x0623

dsPIC33FJ128MC802 0x0629

dsPIC33FJ128MC804 0x062B

Note 1: The Device and Revision IDs (DEVID and DEVREV) are located at the last two implemented addresses in

program memory.

2: Refer to the “dsPIC33F/PIC24H Flash Programming Specification” (DS70152) for detailed information on

Device and Revision IDs for your specific device.

 2009-2015 Microchip Technology Inc. DS80000442K-page 3

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/X04

TABLE 2: SILICON ISSUE SUMMARY

Module Feature Item

Number Issue Summary

Affected

Revisions

(1)

A1 A2 A3 A4 A5

UART IR Mode 1. The 16x baud clock signal on the BCLK pin is present

only when the module is transmitting. XXXXX

UART High-Speed

Mode 2. When the UART is in 4x mode (BRGH = 1) and using

two Stop bits (STSEL = 1), it may sample the first Stop

bit instead of the second one.

XXXXX

SPI Transmit

Operation 3. The SPIx Transmit Buffer Full (SPITBF) flag does not

get set immediately after writing to the buffer. XXXXX

SPI Frame Mode 4. The SPIx module will generate incorrect frame

synchronization pulses in Frame Master mode if

FRMDLY = 1.

XXXXX

CSFR Writes 5. The BCL bit in I2CxSTAT can only be cleared with word

instructions, and can be corrupted with byte instructions

and bit operations.

XXXXX

C10-Bit

Addressing 6. When the I

C module is configured for 10-Bit

Addressing, using the same Address bits (A10 and A9)

as other I

C devices, A10 and A9 bits may not work as

expected.

XXXXX

C10-Bit

Addressing 7. When the I

C module is configured as a 10-bit slave

with an address of 0x02, the I2CxRCV register content

for the lower address byte is 0x01 rather than 0x02.

XXXXX

C—8. With the I

C module enabled, the PORT bits and

external interrupt input functions (if any) associated with

the SCLx and SDAx pins will not reflect the actual digital

logic levels on the pins.

XXXXX

C10-Bit

Addressing 9. The 10-bit slave does not set the RBF flag or load the

I2CxRCV register on address match if the Least

Significant bits (LSbs) of the address are the same as

the 7-bit reserved addresses.

XXXXX

C—10. After the ACKSTAT bit is set when receiving a NACK, it

may be cleared by the reception of a Start or Stop bit. XXXXX

UART Interrupts 11. The UART error interrupt may not occur, or may occur

at an incorrect time, if multiple errors occur during a

short period of time.

XXXXX

UART IR Mode 12. When the UART module is operating in 8-bit mode

(PDSEL<1:0> = 0x) and using the IrDA

encoder/

decoder (IREN = 1), the module incorrectly transmits a

data payload of 80h as 00h.

XXXXX

Comparator Output Pin 13. When the CxOUTEN (CMCON) bit is set, the

comparator output pin cannot be used as a general

purpose I/O pin, even if the comparator is disabled.

XXXXX

Internal

Voltage

Regulator

Sleep Mode 14. When the VREGS bit (RCON<8>) is set to a logic ‘0’, the

device may reset and higher Sleep current may be

observed.

XXXXX

PSV

Operations —15. An address error trap occurs in certain addressing modes

when accessing the first four bytes of any PSV page. XXXXX

ECAN™ Sleep Mode 16. The WAKIF bit in the CiINTF register cannot be cleared

by software instruction after the device is interrupted

from Sleep due to activity on the CAN bus.

XXXXX

Note 1: Only those issues indicated in the last column apply to the current silicon revision.

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/X04

DS80000442K-page 4  2009-2015 Microchip Technology Inc.

ECAN™ Receive

Operation 17. The ECAN™ module may not store the received data in

the correct location. XXX

CPU EXCH

Instruction 18. The EXCH instruction does not execute correctly. X X X X X

PWM Debug Mode 19. PTMR does not keep counting down after halting code

execution in Debug mode. XXXXX

PWM Doze Mode 20. The Motor Control PWM module generates more

interrupts than expected when Doze mode is used and

the output postscaler value is different than 1:1.

XXXXX

SPI Transmit

Operation 21. Writing to the SPIxBUF register as soon as the TBF bit is

cleared will cause the SPIx module to ignore written data. XXXXX

UART Break

Character

Generation

22. The UARTx module will not generate back-to-back

Break characters. XXXXX

QEI Timer Gated

Accumulation

Mode

23. When Timer Gated Accumulation mode is enabled, the

QEI does not generate an interrupt on every falling

edge.

XXXXX

QEI Timer Gated

Accumulation

Mode

24. When Timer Gated Accumulation mode is enabled, and

an external signal is applied, the POSxCNT increments

and generates an interrupt after a match with MAXxCNT.

XXXXX

Audio DAC Voltage

Specifications 25. The audio DAC positive and negative output differential

voltages may not meet the specifications listed in the

data sheet.

XXX

ADC Current

Consumption

in Sleep Mode

26. If the ADC module is in an enabled state when the device

enters Sleep mode, the Power-Down (I

) current of the

device may exceed the device data sheet specifications.

XXXXX

JTAG Boundary

Scan 27. On 28-pin devices, boundary scan does not function

correctly for Pin 7. XXXXX

RTCC Operation

During Reset 28. The RTCC module gets reset on any device Reset,

instead of getting reset only on a POR or BOR. XXXXX

All +150°C

Operation 29. These revisions of silicon only support +140°C

operation instead of +150°C for high-temperature

operating temperature.

XXX

I/O Port Data Direction

Setting 30. When the RB8 pin is in open-drain configuration, the

data direction depends upon the TRISB9 bit instead of

the TRISB8 bit.

XXXXX

CPU Interrupt

Disable 31. When a previous DISI instruction is active (i.e., the

DISICNT register is non-zero), and the value of the

DISICNT register is updated manually, the DISICNT

XXXXX

CPU div.sd 32. When using the div.sd instruction, the Overflow bit is

not getting set when an overflow occurs. XXXXX

UART TX Interrupt 33. A Transmit (TX) interrupt may occur before the data

transmission is complete. XXXXX

JTAG Flash

Programming 34. JTAG Flash programming is not supported. X X X X X

CSlave mode 35. Clock stretching may not occur when enabled. X X X X X

TABLE 2: SILICON ISSUE SUMMARY (CONTINUED)

Module Feature Item

Number Issue Summary

Affected

Revisions

(1)

A1 A2 A3 A4 A5

Note 1: Only those issues indicated in the last column apply to the current silicon revision.

Work around Work around Allecled Silicon Revisions Allecled Silicon Revisions Work around Alleoled w can Revisions Allecled Silicon Revisions Work around Allecled Silicon Revisions

 2009-2015 Microchip Technology Inc. DS80000442K-page 5

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/X04

Silicon Errata Issues

1. Module: UART

When the UARTx is configured for IR interface

operations (UxMODE<9:8> = 11), the 16x baud

clock signal on the BCLK pin is present only when

the module is transmitting. The pin is Idle at all

other times.

Work around

Configure one of the output compare modules to

generate the required baud clock signal when the

UARTx is receiving data or in an Idle state.

Affected Silicon Revisions

2. Module: UART

When the UARTx is in 4x mode (BRGH = 1) and

using two Stop bits (STSEL = 1), it may sample the

first Stop bit instead of the second one.

This issue does not affect the other UARTx

configurations.

Work around

Use the 16x baud rate option (BRGH = 0) and

adjust the baud rate accordingly.

Affected Silicon Revisions

3. Module: SPI

The SPIx Transmit Buffer Full (SPITBF) flag does

not get set immediately after writing to the buffer.

Work around

After a write to the SPIx buffer, poll the SPITBF flag

until the flag gets set, indicating that the transmit

buffer is not full. Afterwards, poll the SPITBF flag

again until the flag gets cleared, indicating that the

transmit has started and that the transmit buffer is

empty, and another write can occur.

Affected Silicon Revisions

4. Module: SPI

The SPIx module will generate incorrect frame

synchronization pulses when configured in Frame

Master mode if the start of data is selected to

coincide with the start of the frame synchronization

pulse (FRMEN = 1, SPIFSD = 0, FRMDLY = 1).

However, the module functions correctly in Frame

Slave mode and also in Frame Master mode if

FRMDLY = 0.

Work around

If DMA is not being used, manually drive the SSx

pin (x = 1 or 2) high, using the associated PORT

1 bit time pulse width. This operation needs to be

performed when the transmit buffer is written.

If DMA is being used, and if no other peripheral

modules are using DMA transfers, use a timer

interrupt to periodically generate the frame

synchronization pulse (using the method

described above) after every 8 or 16-bit period

(depending on the data word size configured using

the MODE16 bit).

If FRMDLY = 0, no work around is needed.

Affected Silicon Revisions

5. Module: I

The BCL bit in I2CxSTAT can only be cleared with

word instructions, and can be corrupted with byte

instructions and bit operations.

Work around

Use word instructions to clear the BCL bit.

Affected Silicon Revisions

Note: This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the

issues indicated by the shaded column in

the following tables apply to the current

silicon revision (A5).

A1 A2 A3 A4 A5

XXXXX

A1 A2 A3 A4 A5

XXXXX

A1 A2 A3 A4 A5

XXXXX

A1 A2 A3 A4 A5

XXXXX

A1 A2 A3 A4 A5

XXXXX

Work around Allecled Silicon Revisions Work around Allecled Silicon Revisions Work around Allecled Silicon Revisions Work around Allecled Silicon Revisions Work around Allecled Silicon Revisions Work around Allecled Silicon Revisions

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/X04

DS80000442K-page 6  2009-2015 Microchip Technology Inc.

6. Module: I

If there are two I

C devices on the bus, one of

them is acting as the master receiver and the other

as the slave transmitter. If both devices are

configured for 10-Bit Addressing mode, and have

the same value in the A10 and A9 bits of their

addresses, then when the slave select address is

sent from the master, both the master and slave

Acknowledge it. When the master sends out the

read operation, both the master and the slave

enter into Read mode and both of them transmit

the data. The resultant data will be the ANDing of

the two transmissions.

Work around

In all I

C devices, the addresses, as well as bits,

A10 and A9, should be different.

Affected Silicon Revisions

7. Module: I

When the I

C module is configured as a 10-bit slave

with an address of 0x02, the I2CxRCV register

content for the lower address byte is 0x01, rather

than 0x02; however, the module Acknowledges

both address bytes.

Work around

None.

Affected Silicon Revisions

8. Module: I

With the I

C module enabled, the PORT bits and

external interrupt input functions (if any), associ-

ated with the SCLx and SDAx pins, do not reflect

the actual digital logic levels on the pins.

Work around

If the SDAx and/or SCLx pins need to be polled,

these pins should be connected to other port pins

in order to be read correctly. This issue does not

affect the operation of the I

C module.

Affected Silicon Revisions

9. Module: I

In 10-Bit Addressing mode, some address matches

do not set the RBF flag or load the I2Cx Receive

matches the reserved addresses. In particular,

these include all addresses with the form,

‘xx0000xxxx’ and ‘xx1111xxxx’, with the

following exceptions:

•‘001111000x’

•‘011111001x’

•‘101111010x’

•‘111111011x’

Work around

Ensure that the lower address byte in 10-Bit

Addressing mode does not match any 7-bit

reserved addresses.

Affected Silicon Revisions

10. Module: I

When the I

C module is operating in either Master

or Slave mode, after the ACKSTAT bit is set when

receiving a NACK, it may be cleared by the

reception of a Start or Stop bit.

Work around

Store the value of the ACKSTAT bit immediately

after receiving a NACK from the master.

Affected Silicon Revisions

11. Module: UART

The UARTx error interrupt may not occur, or may

occur at an incorrect time, if multiple errors occur

during a short period of time.

Work around

Read the error flags in the UxSTA register

whenever a byte is received to verify the error

status. In most cases, these bits will be correct,

even if the UARTx error interrupt fails to occur.

Affected Silicon Revisions

A1 A2 A3 A4 A5

XXXXX

A1 A2 A3 A4 A5

XXXXX

A1 A2 A3 A4 A5

XXXXX

A1 A2 A3 A4 A5

XXXXX

A1 A2 A3 A4 A5

XXXXX

A1 A2 A3 A4 A5

XXXXX

Work around Allecled can Rev Work around Work around Allecled Silicon Revisions Work around Allecled ' can Revisions Allecled Silicon Revisions Work around Allecled Silicon Revisions

 2009-2015 Microchip Technology Inc. DS80000442K-page 7

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/X04

12. Module: UART

When the UARTx is operating in 8-bit mode

(PDSEL<1:0> = 0x) and using the IrDA encoder/

decoder (IREN = 1), the module incorrectly

transmits a data payload of 80h as 00h.

Work around

None.

Affected Silicon Revisions

13. Module: Comparator

If the CxOUTEN (CMCON) bit is set and the

Comparator x Enable bit, CxEN (CMCON), is

disabled, the remappable Comparator Output

pins, C1OUT and C2OUT, cannot be used as

general purpose I/O pins.

Work around

When the comparator module is disabled, the

CxOUTEN bit should be reset so that the

remappable Comparator Output pins, C1OUT and

C2OUT, are not driven onto the output pad.

Affected Silicon Revisions

14. Module: Internal Voltage Regulator

When the VREGS bit (RCON<8>) is set to a logic

‘0’, the device may reset and a higher Sleep

current may be observed.

Work around

Ensure that the VREGS bit (RCON<8>) is set to a

logic ‘1’ for device Sleep mode operation.

Affected Silicon Revisions

15. Module: PSV Operations

An address error trap occurs in certain addressing

modes when accessing the first four bytes of a

PSV page. This only occurs when using the

following addressing modes:

• MOV.D

• Register Indirect Addressing (Word or Byte

mode) with Pre/Post-Decrement

Work around

Do not perform PSV accesses to any of the first

four bytes using the above addressing modes. For

applications using the C language, MPLAB

C30

Version 3.11 or higher provides the following

command-line switch that implements a work

around for the erratum.

-merrata=psv_trap

Refer to the readme.txt file in the MPLAB C30

v3.11 toolsuite for further details.

Affected Silicon Revisions

16. Module: ECAN™

The WAKIF bit in the CiINTF register cannot be

cleared by software instructions after the device is

interrupted from Sleep due to activity on the CAN

bus.

When the device wakes up from Sleep due to CAN

bus activity, the ECAN module is placed in

Operational mode. The ECAN event interrupt

occurs due to the WAKIF flag. Trying to clear the

flag in the Interrupt Service Routine (ISR) may not

clear the flag. The WAKIF bit being set will not

cause repetitive Interrupt Service Routine

execution.

Work around

Although the WAKIF bit does not clear, the device

Sleep and ECAN wake function continue to work

as expected. If the ECAN event is enabled, the

CPU will enter the Interrupt Service Routine due to

the WAKIF flag getting set. The application can

maintain a secondary flag, which tracks the device

Sleep and wake events.

Affected Silicon Revisions

A1 A2 A3 A4 A5

XXXXX

A1 A2 A3 A4 A5

XXXXX

A1 A2 A3 A4 A5

XXXXX

A1 A2 A3 A4 A5

XXXXX

A1 A2 A3 A4 A5

XXXXX

Work around Allecled Silicon Revisions Work around (Pm am > Build Ognons > Pm'ects > MPLAB 030 > Use Alternate Settings Allecled can Revisions Work around Allecled S ons Work around Allecled Silicon Revisions Work around Allecled Silicon Revisions

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/X04

DS80000442K-page 8  2009-2015 Microchip Technology Inc.

17. Module: ECAN

The ECAN module may not store received data in

the correct location. When this occurs, the receive

buffers will become corrupted. In addition, it is also

possible for the transmit buffers to become

corrupted. This issue is more likely to occur as the

CAN bus speed approaches 1 Mbps.

Work around

Do not use the DMA with ECAN in Peripheral

Indirect mode. Use the DMA in Register Indirect

mode, Continuous mode enabled and Ping-Pong

mode disabled. The receive DMA channel count

should be set to 8 words. The transmit DMA

channel count should be set for the actual

message size (maximum of 7 words for Extended

CAN messages and 6 words for Standard CAN

messages). To simplify application error handling

while using this mode, only one TX buffer should

be used. While message filtering is not affected,

messages will not be stored at distinct RX buffers.

Instead, all messages are stored contiguously in

memory. The start of this memory is pointed to by

the receive DMA channel. The application must

still clear the RXFULx flags and other interrupt

flags. The application must also manage the RX

buffer memory.

Affected Silicon Revisions

18. Module: CPU

The EXCH instruction does not execute correctly.

Work around

If writing source code in assembly, the

recommended work around is to replace:

EXCH Wsource, Wdestination

with:

PUSH Wdestination

MOV Wsource, Wdestination

POP Wsource

If using the MPLAB C30 C compiler, specify the

compiler option: -merrata=exch (Project > Build

Options > Projects > MPLAB C30 > Use Alternate

Settings).

Affected Silicon Revisions

19. Module: PWM

If the PTDIR bit is set (when PTMR is counting

down), and the CPU execution is halted (after a

breakpoint is reached), PxTMR will start counting

up as if PTDIR was zero.

Work around

None.

Affected Silicon Revisions

20. Module: PWM

When the device is operated in Doze mode and the

Motor Control PWM module has a postscaler set to

any value different than 1:1 (PTOPS<3:0> > 0 in the

PxTCON register), the Motor Control PWM module

generates more interrupts than expected.

Work around

Do not use Doze mode with the Motor Control PWM

if the time base output postscaler is different than

1:1 (PTOPS<3:0> > 0 in the PxTCON register).

Affected Silicon Revisions

21. Module: SPI

Writing to the SPIxBUF register as soon as the

TBF bit is cleared will cause the SPIx module to

ignore the written data. Applications which use

SPIx with DMA will not be affected by this erratum.

Work around

After the TBF bit is cleared, wait for a minimum

duration of one SPI clock before writing to the

SPIxBUF register.

Alternatively, do one of the following:

• Poll the RBF bit and wait for it to get set before

writing to the SPIxBUF register

• Poll the SPIx interrupt flag and wait for it to get

set before writing to the SPIxBUF register

• Use an SPI Interrupt Service Routine

•Use DMA

Affected Silicon Revisions

A1 A2 A3 A4 A5

XXX

A1 A2 A3 A4 A5

XXXXX

A1 A2 A3 A4 A5

XXXXX

A1 A2 A3 A4 A5

XXXXX

A1 A2 A3 A4 A5

XXXXX

Work around Allecled Silicon Revisions Work around Allecled Silicon Revisions Work around Allecled Silicon Revisions Work around Allecled Silicon Revisions

 2009-2015 Microchip Technology Inc. DS80000442K-page 9

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/X04

22. Module: UART

The UARTx module will not generate consecutive

Break characters. Trying to perform a back-to-

back Break character transmission will cause the

UARTx module to transmit the dummy character,

used to generate the first Break character, instead

of transmitting the second Break character. Break

characters are generated correctly if they are

followed by a non-Break character transmission.

Work around

None.

Affected Silicon Revisions

23. Module: QEI

When the TQCS and TQGATE bits in the

QEIxCON register are set, a QEI interrupt should

be generated after an input pulse on the QEA

input. This interrupt is not generated in the affected

silicon.

Work around

None.

Affected Silicon Revisions

24. Module: QEI

When the TQCS and TQGATE bits in the

QEIxCON register are set, the POSxCNT counter

should not increment, but erroneously does, and if

allowed to increment to match MAXxCNT, a QEI

interrupt will be generated.

Work around

To prevent the erroneous increment of POSxCNT

while running the QEI in Timer Gated Accumulation

mode, initialize MAXxCNT = 0.

Affected Silicon Revisions

25. Module: Audio DAC

The audio DAC positive differential output

voltage and negative differential output voltage

(Parameters DA01 and DA02, respectively) may

not meet the specifications listed in the data sheet.

Work around

None.

Affected Silicon Revisions

A1 A2 A3 A4 A5

XXXXX

A1 A2 A3 A4 A5

XXXXX

A1 A2 A3 A4 A5

XXXXX

A1 A2 A3 A4 A5

XXX

Work around 2: Work around 1: Allecled can Revisions

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/X04

DS80000442K-page 10  2009-2015 Microchip Technology Inc.

26. Module: ADC

If the ADC module is in an enabled state when the

device enters Sleep mode, as a result of executing

a PWRSAV #0 instruction, the device Power-Down

) current may exceed the specifications listed

in the device data sheet. This may happen even if

the ADC module is disabled by clearing the ADON

bit prior to entering Sleep mode.

Work around 1:

In order to remain within the I

specifications listed

in the device data sheet, the user software must

completely disable the ADC module by setting the

ADC module disable bit in the corresponding

Peripheral Module Disable x register (PMDx), prior

to executing a PWRSAV #0 instruction.

Work around 2:

If the ADC module was previously initialized and

enabled before entering Sleep, execute the lines

of code provided in Example 1.

EXAMPLE 1:

Affected Silicon Revisions

Note: The ADC module must be reinitialized by

the user application before resuming ADC

operation.

Note: Unlike Work around 1, the user

application does not need to reinitialize

the ADC module; however, it is necessary

to re-enable the ADC module by setting

the ADON bit after waking from Sleep.

AD1CON1bits.ADON = 0; //Disable the ADC module

__asm__ volatile ("REPEAT #50"); //Wait 50 Tcy

__asm__ volatile ("NOP"); //Repeat NOP 51 times

Sleep(); // Execute PWRSAV #0 and go to Sleep

A1 A2 A3 A4 A5

XXXXX

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dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/X04

27. Module: JTAG

On 28-pin devices, JTAG boundary scan does not

function correctly for Pin 7. Both Pins 6 and 7

respond to stimulus applied to Pin 7.

Work around

Do not include Pin 7 in the JTAG boundary scan

chain for 28-pin devices.

Affected Silicon Revisions

28. Module: RTCC

The RTCC module gets reset on any device

Reset, instead of getting reset only on a POR or

BOR.

Work around

None.

Affected Silicon Revisions

29. Module: All

The affected silicon revisions listed below are not

warranted for operation at +150°C.

Work around

Only use the affected revisions of silicon for the

high-temperature operating range from -40°C to

+140°C.

Affected Silicon Revisions

30. Module: I/O Port

When the ODCB8 bit (Open-Drain Configuration)

is set to ‘1’, the data direction on the RB8 pin is

controlled by the TRISB9 bit instead of the TRISB8

bit.

Work around

Do not use the RB8 pin in open-drain configuration

while simultaneously using the RB9 pin.

Affected Silicon Revisions

31. Module: CPU

When a previous DISI instruction is active (i.e., the

DISICNT register is non-zero), and the value of the

DISICNT register is updated manually, the DISICNT

Work around

Avoid updating the DISICNT register manually.

Instead, use the DISI #n instruction with the

required value for ‘n’.

Affected Silicon Revisions

32. Module: CPU

When using the Signed 32-Bit by 16-Bit Division

instruction, div.sd, the Overflow bit does not

always get set when an overflow occurs.

Work around

Test for and handle overflow conditions outside of

the div.sd instruction.

Affected Silicon Revisions

A1 A2 A3 A4 A5

XXXXX

A1 A2 A3 A4 A5

XXXXX

A1 A2 A3 A4 A5

XXX

A1 A2 A3 A4 A5

XXXXX

A1 A2 A3 A4 A5

XXXXX

A1 A2 A3 A4 A5

XXXXX

Work around Allecled Silicon Revisions Work around Allecled Silicon Revisions Work around Allecled Silicon Revisions

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/X04

DS80000442K-page 12  2009-2015 Microchip Technology Inc.

33. Module: UART

When using UTXISEL<1:0> = 01 (interrupt when last

character is shifted out of the Transmit Shift Register)

and the final character is being shifted out through

the Transmit Shift Register, the Transmit (TX)

interrupt may occur before the final bit is shifted out.

Work around

If it is critical that the interrupt processing occur

only when all transmit operations are complete,

hold off the interrupt routine processing by adding

a loop at the beginning of the routine that polls the

Transmit Shift Register Empty bit (TRMT) before

processing the rest of the interrupt.

Affected Silicon Revisions

34. Module: JTAG

JTAG Flash programming is not supported.

Work around

None.

Affected Silicon Revisions

35. Module: I

In Slave mode, clock stretching may not occur

during address detect, even when it has been

enabled (STREN = 1). As a result, the SCLREL bit

may not be cleared upon address reception when

the R/W bit is ‘0’. This is seen in both 7-Bit and

10-Bit Addressing modes.

Work around

User software should read the Acknowledged

address from the receive buffer before the data

byte is received. User software also needs to

configure the slave interrupt priority, such that, the

interrupt latency time should be less (before the

reception of the data byte).

Affected Silicon Revisions

A1 A2 A3 A4 A5

XXXXX

A1 A2 A3 A4 A5

XXXXX

A1 A2 A3 A4 A5

XXXXX

 2009-2015 Microchip Technology Inc. DS80000442K-page 13

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/X04

Data Sheet Clarifications

The following typographic corrections and clarifications

are to be noted for the latest version of the device data

sheet (DS70291G):

1. Module: Electrical Characteristics

For Parameter DC60d (Base I

) in Table 31-7, the

maximum value is corrected to read as 85 A.

2. Module: Electrical Characteristics

For Parameter DI51d (Input Leakage Current) in

Table 31-9, the maximum value is corrected to

read as ±12 µA.

3. Module: Electrical Characteristics

For Parameter F21 (Internal RC Accuracy) in

Table 31-19, the minimum and maximum values for

the temperature range of -40°C to +85°C are

corrected to read as -30% for minimum and +30%

for maximum.

4. Module: Electrical Characteristics

For Parameter DA01 (Positive Output Differential

Voltage) in Table 31-48, the minimum value is

corrected to read as 0.8V.

5. Module: Electrical Characteristics

Table 31-18: AC Characteristics: Internal RC

Accuracy should be replaced with the following

table.

Note: Corrections are shown in bold. Where

possible, the original bold text formatting

has been removed for clarity.

TABLE 31-18: AC CHARACTERISTICS: INTERNAL RC ACCURACY

AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C T

+85°C for Industrial

-40°C T

+125°C for Extended

Param

No. Characteristic Min Typ Max Units Conditions

Internal FRC Accuracy @ 7.3728 MHz

(1,2)

F20 FRC -3 — 3 % -40°C  T

 -10°C V

= 3.0-3.6V

FRC -2 — 2 % -10°C  T

 +85°C V

= 3.0-3.6V

FRC -5 — 5 % +85°C  T

 +125°C V

= 3.0-3.6V

Note 1: Frequency calibrated at +25°C and 3.3V. TUNx bits can be used to compensate for temperature drift.

2: Negative current is defined as current sourced by the pin.

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/X04

DS80000442K-page 14  2009-2015 Microchip Technology Inc.

6. Module: High-Temperature Electrical

Characteristics

A new table, Table 32-8: DC Characteristics: I/O

Pin Input Specifications and Parameter HDI51f

(Input Leakage Current, RB9-RB12), are added to

this chapter under DC Characteristics. They are

shown in Table 32-8 below. The following tables in

this chapter will be renumbered sequentially.

7. Module: High-Temperature Electrical

Characteristics

A new table, Table 32-19: AC Characteristics:

Internal FRC Accuracy, is added to this chapter

under AC Characteristics. Table 32-19 summarizes

the internal oscillator tolerance over the entire

temperature range.

TABLE 32-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS

DC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C T

+150°C for Extended Temperature

Param

No. Symbol Characteristic Min Typ

(1)

Max Units Conditions

HDI51f I

Input Leakage Current,

RB9 through RB12 ——±15µAV

 V

pin at high-impedance,

-40°C  T

 +150°C

Note 1:

Negative current is defined as current sourced by the pin.

TABLE 32-19: AC CHARACTERISTICS: INTERNAL FRC ACCURACY

AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C T

+150°C for High Temperature

Param

No. Characteristic Min Typ Max Units Conditions

HF20 FRC

(1,2)

-5 — 5 % -40°C  T

 +150°C V

= 3.0-3.6V

Note 1:

Negative current is defined as current sourced by the pin.

Frequency is calibrated at +25°C and 3.3V. The TUNx bits can be used to compensate for temperature drift.

Rev A Documenl 3/2009 Rev B Documenl 4/2009 Rev C Documenl 8/2009 Rev D Documenl 1/2010 Rev E Documenl 6/2010 Rev F Documenl (10/2010 Rev G Documenl 3/2011 Rev H Documenl 11/2011 Rev J Documenl (11/2013) Rev K Documenl (11/2015)

 2009-2015 Microchip Technology Inc. DS80000442K-page 15

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/X04

APPENDIX A: REVISION HISTORY

Rev A Document (3/2009)

Initial release of this document; issued for revision A1,

A2 and A3 silicon.

Includes silicon issues 1-2 (UART), 3-4 (SPI), 5-10 (I

C),

11-12 (UART), 13 (Comparator), 14 (Internal Voltage

Regulator), 15 (PSV Operations), 16-17 (ECAN™), 18

(CPU), 19-20 (PWM) and 21 (SPI).

This document replaces the following errata document:

“dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04

and dsPIC33FJ128MCX02/X04 Rev. A1/A2/A3 Silicon

Errata” (DS80372)

Rev B Document (4/2009)

Corrected part numbers.

Rev C Document (8/2009)

Added silicon issues 22 (UART) and 23-24 (QEI).

Rev D Document (1/2010)

Added Rev. A4 silicon information.

Added silicon issue 25 (Audio DAC).

Rev E Document (6/2010)

Updated silicon issue 18 (CPU).

Added silicon issues 26 (ADC), 27 (JTAG) and 28 (RTCC),

and data sheet clarification 1 (DC Characteristics: I/O Pin

Input Specifications).

Rev F Document (10/2010)

Updated the work around in silicon issue 26 (ADC).

Added silicon issue 29 (All).

Rev G Document (3/2011)

Removed data sheet clarification 1.

Updated the Affected Silicon Revisions for item 29 in

Table 2 and in silicon issue 29 (All).

Added silicon issue 30 (I/O Port).

Rev H Document (11/2011)

Updated the current Device Data Sheet revision to “F”.

Added Rev. A5 silicon information.

Added silicon issues 31 (CPU), 32 (CPU), 33 (UART),

and 34 (JTAG).

Rev J Document (11/2013)

Updated the current Device Data Sheet revision to “G”.

Added data sheet clarifications 1 through 5 (Electrical

Characteristics) and 6 through 7 (High-Temperature

Electrical Characteristics).

Other minor typographic changes to improve table

readability.

Rev K Document (11/2015)

Added silicon issue 35 (I

C).

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/X04

DS80000442K-page 16  2009-2015 Microchip Technology Inc.

NOTES:

YSTEM

 2009-2015 Microchip Technology Inc. DS80000442K-page 17

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

FlashFlex, flexPWR, JukeBlox, K

, K

logo, Kleer,

LANCheck, MediaLB, MOST, MOST logo, MPLAB,

OptoLyzer, PIC, PICSTART, PIC

logo, RightTouch, SpyNIC,

SST, SST Logo, SuperFlash and UNI/O are registered

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

The Embedded Control Solutions Company and mTouch are

registered trademarks of Microchip Technology Incorporated

in the U.S.A.

Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,

CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit

Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,

KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB

Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,

Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,

PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O,

Total Endurance, TSHARC, USBCheck, VariSense,

ViewSpan, WiperLock, Wireless DNA, and ZENA are

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

Silicon Storage Technology is a registered trademark of

Microchip Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology

Germany II GmbH & Co. KG, a subsidiary of Microchip

Technology Inc., in other countries.

All other trademarks mentioned herein are property of their

respective companies.

ISBN: 978-1-5224-0056-1

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC

MCUs and dsPIC

DSCs, KEELOQ

code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

QUALITY MANAGEMENT S

YSTEM

CERTIFIED BY DNV

== ISO/TS 16949 ==

6‘ ‘MICRDCHIP

DS80000442K-page 18  2009-2015 Microchip Technology Inc.

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