TC1270A/70AN/71A Datasheet by Microchip Technology

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2007-2011 Microchip Technology Inc. DS22035D-page 1
TC1270A/70AN/71A
Features:
Precision Voltage Monitor
- 2.63V, 2.93V, 3.08V, 4.38V and 4.63V Trip
Points (Typical)
Manual Reset Input
Reset Time-Out Delay:
- Standard: 280 ms (Typical)
- Optional: 2.19 ms, and 35 ms (Typical)
Power Consumption 15 µA max
No glitches on outputs during power-up
Active Low Output Options:
- Push-Pull Output and Open-Drain Output
Active High Output Option:
- Push-Pull Output
Replacement for (Specification compatible with):
- TC1270, TC1271
- TCM811, TCM812
Fully Static Design
Low-Voltage Operation (1.0V)
ESD Protection:
- 4 kV Human Body Model (HBM)
- 400V Machine Model (MM)
Extended (E) Temperature Range:
-40°C to +125°C
Package Options:
- 4-Lead SOT-143
- 5-Lead SOT-23
- Pb-free Device
Package Types
Functional Block Diagram
Device Features
1
2
4
3
TC1271A
SOT-143
VSS VDD
RST MR
1
2
4
3
TC1270A
TC1270AN
SOT-143
VSS VDD
RST MR
1
2
3
5
4
TC1271A
SOT-23-5
1
2
3
5
4
SOT-23-5
NC NC
VDD
MR RST
VSS VSS
VDD
MR RST
TC1270A
TC1270AN
18.5 k
VDD
MR
RST
RST
Glitch Filter
Voltage
Detector
PP
PP
Output
Driver
Circuitry (TC1271A)
(TC1270A)
Reset
Generator
and Delay
Timer
(2.19 ms,
35 ms,
280 ms) OD RST
(TC1270AN)
Device
Output
Reset Delay
(ms) (Typ)(3)
Reset Trip
Point (V)(3)
Voltage
Range (V)
Temperature
Range
Packages Comment
Type Active
Level
TC1270A Push-Pull Low
2.19, 35,
280(1)
4.63, 4.38,
3.08, 2.93,
2.63(4)
1.0V to
5.5V -40°C to
+125°C
SOT-143(2),
SOT-23-5 Replaces TC1270 and
TCM811
TC1270AN Open-Drain Low SOT-143(2),
SOT-23-5
New Option
TC1271A Push-Pull High SOT-143(2),
SOT-23-5 Replaces TC1271 and
TCM812
Note 1: The 280 ms Reset delay time-out is compatible with the TC1270, TC1271, TCM811 and TCM812 devices.
2: The SOT-143 package is compatible with the TC1270, TC1271, TCM811 and TCM812 devices.
3: Custom Reset trip points and Reset delays available, contact your local Microchip sales office.
4: The TC1270/1 and TCM811/12 1.75V trip point option is not supported.
Voltage Supervisor with Manual Reset Input
TC1270A/70AN/71A
DS22035D-page 2 2007-2011 Microchip Technology Inc.
NOTES:
2007-2011 Microchip Technology Inc. DS22035D-page 3
TC1270A/70AN/71A
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
Supply Voltage (VDD to VSS)...............................+7.0V
Input Current, VDD..............................................10 mA
Output Current, RESET, Reset ..........................10 mA
Voltage on all inputs and outputs
w.r.t. VSS ............................ -0.6V to (VDD + 1.0V)
Storage Temperature Range..............-65°C to +150°C
Operating Temperature Range ..........-40°C to +125°C
Maximum Junction Temperature, TS.................. 150°C
ESD protection on all pins
Human Body Model   4kV
Machine Model   400V
† Notice: Stresses above those listed under Absolute
Maximum Ratings” may cause permanent damage to a
device. The absolute maximum values are merely
stress ratings – functional operation of a device at
those, or any other conditions above those indicated in
the operational listing of these specifications, is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
ELECTRICAL CHARACTERISTICS
Electrical Characteristics: Unless otherwise noted, VDD = 5V for L/M versions, VDD = 3.3V for T/S versions,
VDD = 3V for R version, TA = -40°C to +125°C. Typical values are at TA = +25°C.
Parameter Sym Min Typ(1)Max Units Test Conditions
Operating Voltage Range VDD 1.0 5.5 V
Supply Current IDD —715µAV
DD > VTRIP
, for L/M/R/S/T,
VDD = 5.5V
—4.7510 µAV
DD > VTRIP
, for R/S/T, VDD = 3.6V
—1015µAV
DD < VTRIP
, for L/M/R/S/T
Reset Trip Point
Threshold (3) VTRIP 4.54 4.63 4.72 V TC127xAL: TA = +25°C
4.50 — 4.75 V TA = –40°C to +125°C
4.30 4.38 4.46 V TC127xAM: TA = +25°C
4.25 — 4.50 V TA = –40°C to +125°C
3.03 3.08 3.14 V TC127xAT: TA = +25°C
3.00 — 3.15 V TA = –40°C to +125°C
2.88 2.93 2.98 V TC127xAS: TA = +25°C
2.85 — 3.00 V TA = –40°C to +125°C
2.72 2.77 2.82 VTC127xA:(5)TA = +25°C
2.70 2.85 V TA = –40°C to +125°C
2.58 2.63 2.68 V TC127xAR: TA = +25°C
2.55 — 2.70 V TA = –40°C to +125°C
Note 1: Data in the Typical (“Typ”) column is at 5V, +25C, unless otherwise stated.
2: RST output for TC1270A and TC1270AN, RST output for TC1271A.
3: TC127XA refers to the TC1270A, TC1270AN or TC1271A device.
4: Hysteresis is within the VTRIP(MIN) to VTRIP(MAX) window.
5: Custom-ordered voltage trip point. Minimum order volume requirement.
6: This specification allows this device to be used in PIC® microcontroller applications that require the
In-Circuit Serial Programming™ (ICSP™) feature (see device-specific programming specifications for
voltage requirements). The total time that the RST pin can be above the maximum device operational
voltage (5.5V) is 100s. Current into the RST pin should be limited to 2 mA. It is recommended that the
device operational temperature be maintained between 0°C to +70°C (+25°C preferred). For additional
information, refer to Figure 2-41.
VDD VTRIHMAX) SINK VDD V‘rmmmm) SINK VDD VTRImMAx) SOURCE VDD VTFUPLMAX]
TC1270A/70AN/71A
DS22035D-page 4 2007-2011 Microchip Technology Inc.
Reset Threshold Tempco ±30 ppm/°C
Reset Trip Point
Hysteresis (1)VHYS 0.3 % Percentage of VTRIP Voltage
MR Input High Threshold VIH 2.3 V VDD > VTRIP(MAX), L/M only
0.7 VDD —— VV
DD > VTRIP(MAX), R/S/T only
MR Input Low Threshold VIL ——0.8 VV
DD > VTRIP(MAX), L/M only
—— 0.25 V
DD VV
DD > VTRIP(MAX), R/S/T only
MR Pull-up Resistance 10 18.5 40 k
Open-Drain High Voltage
on Output VODH 13.5 V Open-Drain Output pin only.
VDD = 3.0V, Time voltage > 5.5
applied 100s. Current into pin
limited to 2 mA +25°C operation
recommended (6)
Reset
Output
Voltage
Low (2)
TC1270A/
TC1270AN VOL 0.3 V R/S/T only,
ISINK = 1.2 mA, VDD = VTRIP(MIN)
TC1271A 0.3 V R/S/T only,
ISINK = 1.2 mA, VDD = VTRIP(MAX)
TC1270A/
TC1270AN 0.4 V L/M only,
ISINK = 3.2 mA, VDD = VTRIP(MIN)
TC1271A 0.3 V L/M only,
ISINK = 3.2 mA, VDD = VTRIP(MAX)
TC1270A/
TC1270AN 0.3 V L/M only,
ISINK = 50 µA, VDD > 1.0V
Reset
Output
Voltage
High (2)
TC1270A VOH 0.8 VDD V R/S/T only,
ISOURCE = 500 µA, VDD = VTRIP(MAX)
TC1270A VDD - 1.5 V L/M only,
ISOURCE = 800 µA, VDD = VTRIP(MAX)
TC1271A 0.8 VDD —— VI
SOURCE = 500 µA, VDD VTRIP(MIN)
Input Leakage Current IIL ——±1µAV
PIN = VDD
Open-Drain RST Output
Leakage IOLOD 1 µA Open-Drain configuration only.
Capacitive Loading
Specification on Output
Pins
CIO 50 pF
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Characteristics: Unless otherwise noted, VDD = 5V for L/M versions, VDD = 3.3V for T/S versions,
VDD = 3V for R version, TA = -40°C to +125°C. Typical values are at TA = +25°C.
Parameter Sym Min Typ(1)Max Units Test Conditions
Note 1: Data in the Typical (“Typ”) column is at 5V, +25C, unless otherwise stated.
2: RST output for TC1270A and TC1270AN, RST output for TC1271A.
3: TC127XA refers to the TC1270A, TC1270AN or TC1271A device.
4: Hysteresis is within the VTRIP(MIN) to VTRIP(MAX) window.
5: Custom-ordered voltage trip point. Minimum order volume requirement.
6: This specification allows this device to be used in PIC® microcontroller applications that require the
In-Circuit Serial Programming™ (ICSP™) feature (see device-specific programming specifications for
voltage requirements). The total time that the RST pin can be above the maximum device operational
voltage (5.5V) is 100s. Current into the RST pin should be limited to 2 mA. It is recommended that the
device operational temperature be maintained between 0°C to +70°C (+25°C preferred). For additional
information, refer to Figure 2-41.
2007-2011 Microchip Technology Inc. DS22035D-page 5
TC1270A/70AN/71A
1.1 AC CHARACTERISTICS
1.1.1 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created
following one of the following formats:
FIGURE 1-1: Test Load Conditions.
1. TppS2ppS 2. TppS
T
F Frequency T Time
E Error
Lowercase letters (pp) and their meanings:
pp
io Input or Output pin osc Oscillator
rx Receive tx Transmit
bitclk RX/TX BITCLK RST Reset
drt Device Reset Timer
Uppercase letters and their meanings:
S
FFall PPeriod
HHigh RRise
I Invalid (High-impedance) V Valid
L Low Z High-impedance
Pin
VSS
CL = 50 pF
VTRIP x VTRWMIN)
TC1270A/70AN/71A
DS22035D-page 6 2007-2011 Microchip Technology Inc.
TIMING DIAGRAMS AND SPECIFICATIONS
MR Pin and Reset Pin Waveform
Device Voltage and Reset Pin (Active Low) Waveform
Reset and Device Reset Timer Requirements
Electrical Characteristics: Unless otherwise noted, VDD = 5V for L/M versions, VDD = 3.3V for T/S versions,
VDD = 3V for R version, TA = -40°C to +125°C. Typical values are at TA = +25°C.
Parameter Sym Min Typ(1)Max Units Test Conditions
VDD to Reset Delay tRD —50µsV
DD = VTRIP(MAX) to
VTRIP(MIN) –125 mV
Reset Active
Time Out
Period
TC127XAxBVyy(3) t
RST 1.09 2.19 4.38 ms VDD = VTRIP(MAX)
TC127XAxAVyy(3) 17.5 35 70 ms VDD = VTRIP(MAX)
TC127XAxVyy(3)140 280 560 ms VDD = VTRIP(MAX)
MR Minimum Pulse Width tMR 10 — — µs
MR Noise Immunity tMRNI —0.1— µs
MR to Reset Propagation Delay tMD —0.2— µs
Note 1: Unless otherwise stated, data in the Typical (“Typ”) column is at 5V, +25C.
2: RST output for TC1270A, RST output for TC1271A.
3: TC127XA refers to the TC1270A, TC1270AN or TC1271A device.
“x” indicates the selected voltage trip point, while “yy” indicates the package code.
MR
RST
tRST
tMR
RST
tMD
tMRNI
VTRIP(MAX)
VTRIP(MIN)
1V
VDD
VTRIP
tRST
RST(1)
RST
tRST
tRD
VDD < 1V is outside the device operating specification. The RST (or RST) output state is unknown while VDD < 1V.
Note 1: The TC1270AN requires an external pull-up resistor.
2007-2011 Microchip Technology Inc. DS22035D-page 7
TC1270A/70AN/71A
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +1.0V to +5.5V, VSS = GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Specified Temperature Range TA-40 +125 °C
Operating Temperature Range TA-40 +125 °C
Storage Temperature Range TA-65 +150 °C
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23 JA —256°C/W
Thermal Resistance, 4L-SOT-143 JA —426°C/W
TC1270A/70AN/71A
DS22035D-page 8 2007-2011 Microchip Technology Inc.
NOTES:
2007-2011 Microchip Technology Inc. DS22035D-page 9
TC1270A/70AN/71A
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, all limits are specified for VDD = 1V to 5.5V, TA = –40°C to +125°C.
FIGURE 2-1: IDD vs. Temperature (Reset
Power-up Timer Inactive)
(TC1270AL, TC1270ANL, TC1271AL
- 4.50V min./4.63V typ./4.75V max.).
FIGURE 2-2:
I
DD
vs. Temperature (Reset
Power-up Timer Inactive)
(TC1270AT,
TC1270ANT,
TC1271AT
- 3.00V min./3.08V typ./3.15V max.).
FIGURE 2-3: IDD vs. Temperature (Reset
Power-up Timer Inactive)
(TC1270AR,
TC1270ANR,
TC1271AR
- 2.55V min./2.63V typ./2.70V max.).
FIGURE 2-4: IDD vs. Temperature (Reset
Power-up Timer Active)
(TC1270AL,
TC1270ANL,
TC1271AL
- 4.50V min./4.63V typ./4.75V max.).
FIGURE 2-5: IDD vs. Temperature (Reset
Power-up Timer Active)
(TC1270AT, TC1270ANT, TC1271AT
- 3.00V min./3.08V typ./3.15V max.).
FIGURE 2-6: IDD vs. Temperature (Reset
Power-up Timer Active)
(TC1270AR,
TC1270ANR,
TC1271AR
- 2.55V min./2.63V typ./2.70V max.).
Note: The graphs and tables that follow this note are the result of a statistical summary based on a limited number
of samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0
0.5
1
1.5
2
2.5
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
IDD (µA)
1.0V
2.0V
3.0V
4.0V
5.0V
0
0.5
1
1.5
2
2.5
3
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
IDD (µA)
1.0V
2.0V
3.0V
4.0V
5.0V
0
0.5
1
1.5
2
2.5
3
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
IDDA)
1.0V
2.0V
3.0V
4.0V
5.0V
4.5
5
5.5
6
6.5
7
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
IDD (µA)
4.8V
5.5V
3
3.5
4
4.5
5
5.5
6
6.5
7
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
IDD (µA)
4.5V
5.5V
3.5V
2.5
3
3.5
4
4.5
5
5.5
6
6.5
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
IDD (µA)
4.0V
5.0V
3.0V
m K
TC1270A/70AN/71A
DS22035D-page 10 2007-2011 Microchip Technology Inc.
Note: Unless otherwise indicated, all limits are specified for VDD = 1V to 5.5V, TA = –40°C to +125°C.
FIGURE 2-7: IDD vs. VDD (Reset
Power-up Timer Inactive)
(TC1270AL, TC1270ANL, TC1271AL
- 4.50V min./4.63V typ./4.75V max.).
FIGURE 2-8: IDD vs. VDD (Reset
Power-up Timer Inactive)
(TC1270AT,
TC1270ANT,
TC1271AT
- 3.00V min./3.08V typ./3.15V max.).
FIGURE 2-9: IDD vs. VDD (Reset
Power-up Timer Inactive)
(TC1270AR,
TC1270ANR,
TC1271AR
- 2.55V min./2.63V typ./2.70V max.).
FIGURE 2-10: IDD vs. VDD (Reset
Power-up Timer Active)
(TC1270AL,
TC1270ANL,
TC1271AL
- 4.50V min./4.63V typ./4.75V max.).
FIGURE 2-11: IDD vs. VDD (Reset
Power-up Timer Active)
(TC1270AT,
TC1270AN
T, TC1271AT
- 3.00V min./3.08V typ./3.15V max.).
FIGURE 2-12: IDD vs. VDD (Reset
Power-up Timer Active)
(TC1270AR,
TC1270ANR,
TC1271AR
- 2.55V min./2.63V typ./2.70V max.).
0
0.5
1
1.5
2
2.5
3
12345
VDD (V)
IDD (µA)
-40°C
+125°C
+25°C
0
0.5
1
1.5
2
2.5
3
12345
VDD (V)
IDD (µA)
-40°C
+125°C
+25°C
0
0.5
1
1.5
2
2.5
3
3.5
12345
VDD (V)
IDD (µA)
-40°C
+125°C
+25°C
4.5
5
5.5
6
6.5
7
4.54.74.95.15.35.5
VDD (V)
IDD (µA)
-40°C
+125°C
+25°C
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
3 3.5 4 4.5 5 5.5
VDD (V)
IDD (µA)
-40°C
+125°C
+25°C
2
3
4
5
6
7
2.533.544.555.5
VDD (V)
IDD (µA)
-40°C
+125°C
+25°C
2007-2011 Microchip Technology Inc. DS22035D-page 11
TC1270A/70AN/71A
Note: Unless otherwise indicated, all limits are specified for VDD = 1V to 5.5V, TA = –40°C to +125°C.
FIGURE 2-13: VTRIP and VHYS vs.
Temperature
(TC1270AL,
TC1270ANL,
TC1271AL
- 4.50V min./4.63V typ./4.75V max.).
FIGURE 2-14: VTRIP and VHYS vs.
Temperature
(TC1270AT,
TC1270ANT,
TC1271AT
- 3.00V min./3.08V typ./3.15V max.).
FIGURE 2-15: VTRIP and VHYST vs.
Temperature
(TC1270AR,
TC1270ANR,
TC1271AR
- 2.55V min./2.63V typ./2.70V max.).
FIGURE 2-16: VOL vs. IOL
(TC1270AL,
TC1270AN
L, TC1271AL
- 4.50V min./4.63V typ./4.75V max.).
FIGURE 2-17: VOL vs. IOL
(TC1270AT,
TC1270ANT,
TC1271AT
- 3.00V min./3.08V typ./3.15V max.).
FIGURE 2-18: VOL vs. IOL
(TC1270AR,
TC1270ANR,
TC1271AR
- 2.55V min./2.63V typ./2.70V max.).
4.605
4.61
4.615
4.62
4.625
4.63
4.635
4.64
4.645
4.65
-40 25 125
Temperature (°C)
VTRIP (V)
0.2
0.22
0.24
0.26
0.28
0.3
0.32
0.34
0.36
0.38
0.4
VHYS (%)
VTRIP (with VDD
Falling)
VHYS
VTRIP (with VDD
Rising)
3.066
3.068
3.07
3.072
3.074
3.076
3.078
3.08
3.082
3.084
3.086
-40 25 125
Temperature (°C)
VTRIP (V)
0.2
0.22
0.24
0.26
0.28
0.3
0.32
0.34
0.36
0.38
0.4
VHYS (%)
V
HYS
VTRIP (with VDD
Falling)
VTRIP (with VDD
Rising)
2.61
2.615
2.62
2.625
2.63
2.635
2.64
-40 25 125
Temperature (°C)
VTRIP (V)
0.2
0.22
0.24
0.26
0.28
0.3
0.32
0.34
0.36
0.38
0.4
VHYS (%)
VHYS
VTRIP (with VDD
Falling)
VTRIP (with VDD
Rising)
0
0.02
0.04
0.06
0.08
0.1
0.12
0.00 1.00 2.00 3.00 4.00
IOL (mA)
VOL (V)
2.0V
3.0V
4.3V
4.4V
4.5V
0
0.05
0.1
0.15
0.2
0.25
02468
IOL (mA)
VOL (V)
3.2V
4.0V
4.5V
5.0V
5.5V
3.15
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
0.18
0.2
01234
IOL (mA)
VOL (V)
2.0V 2.45V
2.5V
TC1270A/70AN/71A
DS22035D-page 12 2007-2011 Microchip Technology Inc.
Note: Unless otherwise indicated, all limits are specified for VDD = 1V to 5.5V, TA = –40°C to +125°C.
FIGURE 2-19: VOL vs. Temperature
(TC1270AL,
TC1270ANL,
TC1271AL
- 4.50V min./4.63V typ./4.75V max.).
@ VDD = 4.5V).
FIGURE 2-20: VOL vs. Temperature
(TC1270AT,
TC1270ANT,
TC1271AT
- 3.00V min./3.08V typ./3.15V max.).
@ VDD = 2.7V).
FIGURE 2-21: VOL vs. Temperature
(TC1270AR,
TC1270ANR,
TC1271AR
- 2.55V min./2.63V typ./2.70V max.).
@ VDD = 1.8V).
FIGURE 2-22: VOH vs. IOL
(TC1270AL,
TC1270ANL,
TC1271AL
- 4.50V min./4.63V typ./4.75V max.)
@ +25°C).
FIGURE 2-23: VOH vs. IOH
(TC1270AT,
TC1270ANT,
TC1271AT
- 3.00V min./3.08V typ./3.15V max.)
@ +25°C).
FIGURE 2-24: VOH vs. IOH
(TC1270AR,
TC1270ANR,
TC1271AR
- 2.55V min./2.63V typ./2.70V max.)
@ +25°C).
0
0.02
0.04
0.06
0.08
0.1
0.12
-40 10 60 110
Temperature (°C)
VOL (V)
4 mA
2 mA
1 mA 0.5 0.35 mA
0.2
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
-40 10 60 110
Temperature (°C)
VOL (V)
8 mA
6 mA
4 mA
2 mA 1 mA 0.5
0
0.05
0.1
0.15
0.2
-40 10 60 110
Temperature (°C)
VOL (V)
4 mA
2 mA
1 mA 0.5 0.35 mA
0.2
4.2
4.4
4.6
4.8
5
5.2
5.4
5.6
0.00 1.00 2.00 3.00 4.00 5.00
IOH (mA)
VOH (V)
5.5V
5.0V
4.8V
4.75V
1.7
1.9
2.1
2.3
2.5
2.7
2.9
012345
IOH (mA)
VOH (V)
2.9V
2.7V
2.5V
2
2.5
3
3.5
4
4.5
5
5.5
6
012345
IOH (mA)
VOH (V)
5.5V
5.0V
4.5V
4.0V
3.0V
2.8V
2007-2011 Microchip Technology Inc. DS22035D-page 13
TC1270A/70AN/71A
Note: Unless otherwise indicated, all limits are specified for VDD = 1V to 5.5V, TA = –40°C to +125°C.
FIGURE 2-25: VDD Falling to Reset
Propagation Delay (tRPD) vs. Temperature
(TC1270AL,
TC1270ANL,
TC1271AL
- 4.50V min./4.63V typ./4.75V max.).
FIGURE 2-26: VDD Falling to Reset
Propagation Delay (tRPD) vs. Temperature
(TC1270AT,
TC1270AN
T, TC1271AT
- 3.00V min./3.08V typ./3.15V max.).
FIGURE 2-27: VDD Falling to Reset
Propagation Delay (tRPD) vs. Temperature
(TC1270AR,
TC1270ANR,
TC1271AR
- 2.55V min./2.63V typ./2.70V max.).
FIGURE 2-28: Reset Time-Out Period (tRST)
vs. Temperature
(TC1270AL,
TC1270ANL,
TC1271AL
- 4.50V min./4.63V typ./4.75V max.).
FIGURE 2-29: Reset Time-Out Period (tRST)
vs. Temperature
(TC1270AT,
TC1270ANT,
TC1271AT
- 3.00V min./3.08V typ./3.15V max.).
FIGURE 2-30: Reset Time-Out Period (tRST)
vs. Temperature
(TC1270AR,
TC1270ANR,
TC1271AR
- 2.55V min./2.63V typ./2.70V max.).
48
49
50
51
52
53
54
55
-40 10 60 110
Temperature (°C)
tRPD (µs)
48
49
50
51
52
53
54
55
-40 10 60 110
Temperature (°C)
tRPD (µs)
48
49
50
51
52
53
54
55
-40 10 60 110
Temperature (°C)
tRPD (µs)
275
280
285
290
295
300
305
310
315
320
-40 10 60 110
Temperature (°C)
tRST (ms)
5.5V
5.0V
4.75V
275
280
285
290
295
300
305
310
315
320
325
-40 10 60 110
Temperature (°C)
tRST (ms)
5.5V
5.0V
4.5V
4.0V
3.2V
3.15
275
280
285
290
295
300
305
310
315
320
-40 10 60 110
Temperature (°C)
tRST (ms)
5.5V
5.0V
4.5V
4.0V
3.0V
2.8V
TC1270A/70AN/71A
DS22035D-page 14 2007-2011 Microchip Technology Inc.
Note: Unless otherwise indicated, all limits are specified for VDD = 1V to 5.5V, TA = –40°C to +125°C.
FIGURE 2-31: Reset Time-Out Period (tRST)
(C time out option) vs. Temperature
(TC1270AL,
TC1270ANL,
TC1271AL
- 4.50V min./4.63V typ./4.75V max.).
FIGURE 2-32: Reset Time-Out Period (tRST)
(C time out option) vs. Temperature
(TC1270AT,
TC1270ANT,
TC1271AT
- 3.00V min./3.08V typ./3.15V max.).
FIGURE 2-33: Reset Time-Out Period (tRST)
(C time out option) vs. Temperature
(TC1270AR,
TC1270ANR,
TC1271AR
- 2.55V min./2.63V typ./2.70V max.).
FIGURE 2-34: Reset Time-Out Period (tRST)
(B time out option) vs. Temperature
(TC1270AL,
TC1270ANL,
TC1271AL
- 4.50V min./4.63V typ./4.75V max.).
FIGURE 2-35: Reset Time-Out Period (tRST)
(B time out option) vs. Temperature
(TC1270AT,
TC1270ANT,
TC1271AT
- 3.00V min./3.08V typ./3.15V max.).
FIGURE 2-36: Reset Time-Out Period (tRST)
(B time out option) vs. Temperature
(TC1270AR,
TC1270ANR,
TC1271AR
- 2.55V min./2.63V typ./2.70V max.).
34
35
36
37
38
39
40
-40 10 60 110
Temperature (°C)
tRST (ms)
5.5V
5.0V
4.75V
34
35
36
37
38
39
40
-40 10 60 110
Temperature (°C)
tRST (ms)
5.5V
5.0V
4.5V
4.0V
3.2V
3.15V
34
35
36
37
38
39
40
-40 10 60 110
Temperature (°C)
tRST (ms)
5.5V
5.0V
4.5V
4.0V
3.0V
2.8V
2.1
2.15
2.2
2.25
2.3
2.35
2.4
2.45
2.5
-40 10 60 110
Temperature (°C)
tRST (ms)
5.5V
5.0V
4.75V
2.1
2.15
2.2
2.25
2.3
2.35
2.4
2.45
2.5
-40 10 60 110
Temperature (°C)
tRST (ms)
5.5V
5.0V
4.5V 4.0V
3.2V
3.15V
2.1
2.15
2.2
2.25
2.3
2.35
2.4
2.45
2.5
-40 10 60 110
Temperature (°C)
tRST (ms)
5.5V
5.0V
4.5V
4.0V
3.0V
2.8V
1L
2007-2011 Microchip Technology Inc. DS22035D-page 15
TC1270A/70AN/71A
Note: Unless otherwise indicated, all limits are specified for VDD = 1V to 5.5V, TA = –40°C to +125°C.
FIGURE 2-37: MR Low to Reset
Propagation Delay (tMD) vs. Temperature
(TC1270AL,
TC1270ANL,
TC1271AL
- 4.50V min./4.63V typ./4.75V max.).
FIGURE 2-38: MR Low to Reset
Propagation Delay (tMD) vs. Temperature
(TC1270AT,
TC1270ANT,
TC1271AT
- 3.00V min./3.08V typ./3.15V max.).
FIGURE 2-39: MR Low to Reset
Propagation Delay (tMD) vs. Temperature
(TC1270AR,
TC1270ANR,
TC1271AR
- 2.55V min./2.63V typ./2.70V max.).
FIGURE 2-40: VDD Transient Duration vs.
Reset Threshold Overdrive
(VTRIP (minimum) - VDD).
FIGURE 2-41: Open-Drain Leakage
Current vs. Voltage Applied to RST Pin
(TC1270AR, TC1270ANR, TC1271AR
- 2.55V minimum).
0.17
0.18
0.19
0.2
0.21
0.22
-40 10 60 110
Temperature (°C)
tMD (µs)
5.5V
5.0V
4.8V
4.75V
0.17
0.18
0.19
0.2
0.21
0.22
-40 10 60 110
Temperature (°C)
tMD (µs)
5.5V
5.0V
4.5V
4.0V
0.17
0.18
0.19
0.2
0.21
0.22
-40 10 60 110
Temperature (°C)
tMD (µs)
5.5V
5.0V 4.5V
4.0V
0
10
20
30
40
50
60
0.001 0.01 0.1 1 10
VTRIPMIN - VDD (V)
Transient Duration (µs)
4.63V
3.08V
2.63VAbove Line, Reset Occurs
Below Line, No Reset Occurs
1.E-14
1.E-12
1.E-10
1.E-08
1.E-06
1.E-04
1.E-02
01234567891011121314
Output Voltage (V)
Leakage Current (A)
-40°C
+25°C
+125°C
13.5V
TC1270A/70AN/71A
DS22035D-page 16 2007-2011 Microchip Technology Inc.
NOTES:
2007-2011 Microchip Technology Inc. DS22035D-page 17
TC1270A/70AN/71A
3.0 PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PINOUT DESCRIPTION
Pin Number
Sym
Pin
Standard Function
TC1270A
(Push-Pull,
active-low)
TC1270AN
(Open-Drain,
active-low)
TC1271A
(Push-Pull,
active-high)
SOT-23-5
SOT-143-4
SOT-23-5
SOT-143-4
SOT-23-5
SOT-143-4
Type Buffer /
Driver
51 15 1V
SS Power Ground
42 — — —RSTO Push-
Pull Reset output (Push-Pull), active-low
H = VDD > VTRIP
, Reset pin is inactive
(after Reset Delay Timer completes)
L = VDD < VTRIP
, Reset pin is active
Goes active (Low) if one of these conditions
occurs:
1. If VDD falls below the selected Reset
voltage threshold.
2. If the MR pin is forced low.
3. During power-up.
—4 2—RSTO Open-
Drain Reset output (Open-Drain), active-low
Float = VDD > VTRIP
, Reset pin is inactive
(after Reset Delay Timer completes)
L = VDD < VTRIP
, Reset pin is active
Goes active (Low) if one of these conditions
occurs:
1. If VDD falls below the selected Reset
voltage threshold.
2. If the MR pin is forced low.
3. During power-up.
— — 4 2 RST O Push-
Pull Reset output (Push-Pull), active-high
H = VDD < VTRIP
, Reset pin is active
L = VDD > VTRIP
, Reset pin is inactive
(after Reset Delay Timer completes)
Goes active (High) if one of these conditions
occurs:
1. If VDD falls below the selected Reset
voltage threshold.
2. If the MR pin is forced low.
3. During power-up.
Note 1: The MR pin has an internal weak pull-up (18.5 k typical).
TC1270A/70AN/71A
DS22035D-page 18 2007-2011 Microchip Technology Inc.
3.1 Ground Terminal (VSS)
VSS provides the negative reference for the analog
input voltage. Typically, the circuit ground is used.
3.2 Supply Voltage (VDD)
VDD can be used for power supply monitoring or a
voltage level that requires monitoring.
3.3 Reset Output (RST and RST)
There are three types of Reset output pins. These are:
1. Push-Pull active-low Reset
2. Push-Pull active-high Reset
3. Open-Drain active-low Reset, external pull-up
resistor required.
3.3.1 ACTIVE-LOW (RST) – PUSH-PULL
The RST push-pull output remains low while VDD is
below the Reset voltage threshold (VTRIP). The time
that the RST pin is held low after the device voltage
(VDD) returns to a high level (> VTRIP) is typically
280 ms. After the Reset Delay Timer expires, the RST
pin will be driven to the high state.
3.3.2 ACTIVE-HIGH (RST) – PUSH-PULL
The RST push-pull output remains high while VDD is
below the Reset voltage threshold (VTRIP). The time
that the RST pin is held high after the device voltage
(VDD) returns to a high level (> VTRIP) is typically
280 ms. After the Reset Delay Timer expires, the RST
pin will be driven to the low state.
3.3.3 ACTIVE-LOW (RST) – OPEN-DRAIN
The RST open-drain output remains low while VDD is
below the Reset voltage threshold (VTRIP). The time
that the RST pin is held low after the device voltage
(VDD) returns to a high level (> VTRIP) depends on the
Reset time-out selected. After the Reset Delay Timer
expires, the RST pin will float.
3.4 Manual Reset Input (MR)
The Manual Reset (MR) input pin allows a push button
switch to easily be connected to the system. When the
push button is depressed, it forces a system Reset.
This pin has circuitry that filters noise that may be
present on the MR signal.
The MR pin is active-low and has an internal pull-up
resistor.
33 3 33 3MR
IST
(1) Manual Reset Input Pin
This input allows a push button switch to be
directly connected to a TC1270A/70AN/71A
device’s MR pin, which can be used to force a
system Reset. The input filter ignores noise
pulses that occur on the MR pin.
H = Switch is open (internal pull-up resistor
pulls signal high). State of the RST/RST
pin is determined by other system condi-
tions.
L = Switch is depressed (shorted to ground).
This forces the RST/RST pin Active.
24 2 42 4V
DD Power Supply Voltage
1—1—1 NC No Connection
TABLE 3-1: PINOUT DESCRIPTION (CONTINUED)
Pin Number
Sym
Pin
Standard Function
TC1270A
(Push-Pull,
active-low)
TC1270AN
(Open-Drain,
active-low)
TC1271A
(Push-Pull,
active-high)
SOT-23-5
SOT-143-4
SOT-23-5
SOT-143-4
SOT-23-5
SOT-143-4
Type Buffer /
Driver
Note 1: The MR pin has an internal weak pull-up (18.5 k typical).
2007-2011 Microchip Technology Inc. DS22035D-page 19
TC1270A/70AN/71A
4.0 DEVICE OPERATION
4.1 General Description
For many of today’s microcontroller applications, care
must be taken to prevent low-power conditions that can
cause many different system problems. The most
common causes are brown-out conditions, where the
system supply drops below the operating level
momentarily. The second most common cause is when
a slowly decaying power supply causes the
microcontroller to begin executing instructions without
sufficient voltage to sustain volatile memory (RAM),
thus producing indeterminate results.
The TC127XA family (TC1270A, TC1270AN and
TC1271A) are cost-effective voltage supervisor
devices designed to keep a microcontroller in Reset
until the system voltage has reached and stabilized at
the proper level for reliable system operation. These
devices also operate as protection from brown-out
conditions when the system supply voltage drops
below a safe operating level.
A Manual Reset input (MR pin) is provided. This allows
a push button switch to be directly connected to the
TC127XA device, and is suitable for use as a push
button Reset. This allows the system to easily be reset
from the external control of the push button switch. No
external components are required.
The Reset pin (RST or RST) will be forced active, if any
of the following occur:
During device power-up
•V
DD goes below the device threshold voltage
The Manual Reset input (MR) goes low
Figure 4-1 shows a high level block diagram of the
devices. The device can be described with three
functional blocks. These are:
Voltage detect circuit
Manual Reset with glitch filter circuit
Reset generator circuit
The Reset generator circuit controls the Reset delay
time of the Reset output signal.
There are three Reset Delay Timer options. Depending
on the option, the Reset signal (RST/RST pin) will be
held active for a minimum of 1.09 ms, 17.5 ms, or
140 ms.
The TC1271A has an active-high RST output while the
TC1270A and TC1270AN have an active-low RST
output.
The TC1270A and TC1271A have a push-pull output
driver, while the TC1270AN has an open-drain output.
Figure 4-2 shows a typical circuit for a push-pull device
and Figure 4-3 shows a typical circuit for an open-drain
device.
FIGURE 4-1: TC127XA High Level Block
Diagram.
FIGURE 4-2: Typical Push-Pull
Application Circuit.
FIGURE 4-3: Typical Open-Drain
Application Circuit.
The TC1270A and TC1271A devices are available in a
4-Pin SOT-143 package (to maintain footprint
compatibility with the TC1270, TC1271, TCM811 and
TCM812 devices) and a SOT-23-5 package. The
TC1270AN is only available in the SOT-23-5 package.
Low supply current makes these devices suitable for
battery-powered applications.
Device specific block diagrams are presented in
Figure 4-4 through Figure 4-6.
VDD
MR
RST
RST
Voltage
Detect
Reset
Circuit
Manual Reset
with Glitch
Filter Circuit
Generator
Circuit or
VRST
MRRST
Push
Button
MR
VSS VSS
VDD
VDD
Reset Input
TC1270A/1A
VDD
0.1 µF
RST
or
RST
Push
Button
MR
VSS VSS
VDD
VDD
RST Reset Input
TC1270AN
VDD
0.1 µF
TC1270A/70AN/71A
DS22035D-page 20 2007-2011 Microchip Technology Inc.
FIGURE 4-4: TC1270A Block Diagram.
FIGURE 4-5: TC1270AN Block Diagram.
FIGURE 4-6: TC1271A Block Diagram.
4.2 Voltage Detect Circuit
The voltage detect circuit monitors VDD. The device’s
Reset voltage trip point (VTRIP) is selected when the
device is ordered. The voltage on the device’s VDD pin
determines the output state of the RST/RST pin.
VDD voltages above the VTRIP(MAX) force the RST/RST
pin inactive. VDD voltages below the VTRIP(MIN) force
the RST/RST pin active. The state of the RST/RST pin
is unknown for VDD voltages between VTRIP(MAX) and
VTRIP(MIN). This is shown in Table 4-1
TABLE 4-1: VDD LEVELS TO RST/RST
OUTPUT STATES
The term VTRIP will be used as the general term for the
trip point voltage where the device actually trips.
In the case where VDD is falling (for voltages starting
above VTRIP(MAX)):
Voltages above VTRIP(MAX) will never cause the
RST/RST output pin to be driven active.
Voltages below VTRIP(MIN) will always cause the
RST/RST output pin to be driven active.
In the case where VDD is rising (for voltages starting
below VTRIP(MIN)):
Voltages above VTRIP(MAX) will always cause the
RST/RST output pin to be driven inactive, (or
floated, in the TC1270AN) after the Reset Delay
Timer (tRST), times out.
VDD
Comparator
+
Output
Driver RST
Reference
Noise Filter
MR
Voltage Delay
(Push-
Pull)
VDD
Comparator
+
RST
Reference
VSS
Noise Filter
MR
Voltage Delay
Output
Driver
(Open-
Drain)
VDD
Comparator
+
RST
Reference
Noise Filter
MR
Voltage Delay
Output
Driver
(Push-
Pull)
VDD Voltage Level Output State
RST RST
VDD VTRIP(MAX) H
(1, 2)L(1)
VTRIP(MIN) < VDD < VTRIP(MAX) UU
VDD VTRIP(MIN) LH
Legend: H = Driven High L = Driven Low
U = Unknown, driven either High or Low
Note 1: The RST/RST pin will be driven inactive
after the Reset Delay Timer (tRST) times
out.
2: The TC1270AN RST pin will be floated
after the Reset Delay Timer (tRST) times
out.
2007-2011 Microchip Technology Inc. DS22035D-page 21
TC1270A/70AN/71A
Table 4-2 shows the various device trip point options
and their VTRIP(MAX) and VTRIP(MIN) voltages. The neg-
ative percentage change from common regulated
voltages is also shown.
If the VDD is falling from the regulated voltage as it
crosses the VTRIP voltage, the RST/RST pin is driven
active. Then, the desired circuitry is forced into Reset,
or the circuitry has the indication that the VDD is below
the selected VTRIP
.
If the VDD is rising as it crosses the VTRIP voltage, the
RST/RST pin is driven inactive after the Reset Delay
Timer elapses. Then, the desired circuitry is released
from Reset and will start to operate in its Normal mode,
or the circuitry has the indication that the VDD is above
the selected VTRIP
.
TABLE 4-2: SELECTING THE TRIP POINT
The TC1270A/TC1270AN/TC1271A devices are
optimized to reject fast transient glitches on the VDD
line. If the low input signal (which is below VTRIP) is not
rejected, the Reset output is driven active within 50 µs
of VDD falling through the Reset voltage threshold.
After the device exits the Reset condition, the delay
circuitry will hold the RST/RST pin active until the
appropriate Reset delay time (tRST) has elapsed.
During device power-up, the input voltage is below the
trip point voltage. The device must enter the valid oper-
ating range for the device to start operation.
4.2.1 HYSTERESIS
There is also a minimal hysteresis (VHYS) on the trip
point. This is so that small noise signals on the device
voltage (VDD) do not cause the Reset pin (RST/RST) to
“jitter” (oscillate between active and inactive levels).
The characterization graphs shown in Figures 2-13
through 2-15 show the device hysteresis as a
percentage of the voltage trip point (VTRIP).
The Reset Delay Timer (tRST) gives a time-based
hysteresis for the system.
4.2.2 POWER-UP/RISING VDD
As the device VDD rises, the device’s Reset circuit will
remain active until the voltage rises above the “actual”
trip point (VTRIP).
Figure 4-7 shows a power-up sequence and the
waveform of the RST and RST pins. As the device
powers up, the voltage will start below the valid
operating voltage of the device. At this voltage, the
RST/RST output is not valid. Once the voltage is above
the minimum operating voltage (1V) and below the
selected VTRIP
, the Reset output will be active.
Once the device voltage rises above the VTRIP voltage,
the Reset Delay Timer (tRST) starts. When the Reset
Delay Timer times out, the Reset output (RST/RST) is
driven inactive.
FIGURE 4-7: RST/RST Pin Operation
Power-up.
Trip
Voltage
Selection
VTRIP(MAX)(1)/
VTRIP(MIN)(2)
- % From
Regulated Voltage
5.0V 3.3V 3.0V
L 4.75V 5.0% —
4.50V 10.0% —
M 4.50V 10.0% —
4.25V 15.0% —
T 3.15V — 4.5% —
3.00V — 9.2% —
S 3.00V — 9.2% —
2.85V 13.7% —
R 2.70V — 10.0%
2.55V — 15.0%
Note 1: Voltage regulator circuit must have tighter
tolerance (%) than VTRIP(MAX)% from
regulated voltage.
2: Circuitry being reset must have a wider
tolerance (%) than VTRIP(MIN)% from
regulated voltage.
VTRIP
1V
VDD tRST(1)
RST(2)
RST
Note 1: Additional system current is consumed
during the tRST time.
2: The TC1270AN requires an external
pull-up resistor.
TC1270A/70AN/71A
DS22035D-page 22 2007-2011 Microchip Technology Inc.
4.2.3 POWER-DOWN/BROWN-OUT
As the device powers-down/browns-out, the VDD falls
from a voltage above the devices trip point (VTRIP). The
device will trip at a voltage between the maximum trip
point (VTRIP(MAX)) and the minimum trip point
(VTRIP(MIN)). Once the device voltage (VDD) goes
below this voltage, the RST/RST pin will be forced to
the active state. Table 4-3 shows the state of the RST
or RST pins.
Figure 4-8 shows the waveform of the RST pin as
determined by the VDD voltage. As the VDD voltage falls
from the normal operating point, the device “enters”
Reset by crossing the VTRIP voltage (between
VTRIP(MAX) and VTRIP(MIN)). Then, when VDD voltage
rises, the device “exits” Reset by crossing the VTRIP
voltage (below, or at, VTRIP(MAX)). After the “exit” state
has been detected, the Reset Delay Timer (tRST) starts.
When the tRST time completes, the Reset pin is driven
inactive.
TABLE 4-3: RESET PIN STATES
FIGURE 4-8: RST Operation as determined by the VTRIP
.
Device State of RST Pin when: State of RST Pin when: Output Driver
VDD < VTRIP VDD > VTRIP(1)VDD < VTRIP VDD > VTRIP(1)
TC1270A LHPush-Pull
TC1271A ——H LPush-Pull
Note 1: The RST/RST pin will be driven inactive after the Reset Delay Timer (tRST) times out.
VDD VTRIP
RST(1)
1V
< 1V is outside the
device specifications
tRD
tRST
tRD
tRST
VTRIP
(with VDD Falling)
(with VDD Rising)
Note 1: The TC1270AN requires an external pull-up resistor.
2007-2011 Microchip Technology Inc. DS22035D-page 23
TC1270A/70AN/71A
4.3 Negative-Going VDD Transients
The minimum pulse width (time) required to cause a
Reset may be an important criteria in the
implementation of a Power-on Reset (POR) circuit.
This time is referred to as transient duration. The
TC127XA devices are designed to reject a level of
negative-going transients (glitches) on the power
supply line.
Transient duration is the amount of time needed for
these supervisory devices to respond to a drop in VDD.
The transient duration time (tTRAN) is dependent on the
magnitude of VTRIP – VDD (overdrive). Any combination
of duration and overdrive that lies under the duration/
overdrive curve will not generate a Reset signal.
Generally speaking, the transient duration time
decreases with an increase in the VTRIP – VDD voltage.
Figure 4-9 shows an example transient duration vs.
Reset comparator overdrive. It shows that the farther
below the trip point the transient pulse goes, the shorter
the duration of the pulse required to cause a Reset
gets. So, any combination of duration and overdrive
that lays under the curve will not generate a Reset
signal. Combinations above the curve are detected as
a brown-out or power-down.
Transient immunity can be improved by adding a
bypass capacitor (typically 0.1 µF) as close as possible
to the VDD pin of the TC127XA device.
FIGURE 4-9: Example of Typical
Transient Duration Waveform.
4.4 Manual Reset with Glitch Filter
Circuit
The Manual Reset input pin (MR) allows the Reset pins
(RST/RST) to be manually forced to their active states.
The MR pin has circuitry to filter noise pulses that may
be present on the pin. Figure 4-10 shows a block
diagram for using the TC127XA with a push button
switch. To minimize the required external components,
the MR input has an internal pull-up resistor.
A mechanical push button or active logic signal can
drive the MR input.
Once MR has been low for a time, tMD (the manual
Reset delay time), the Reset output pins are forced
active. The Reset output pins will remain in their active
states for the Reset Delay Timer time-out period (tRST).
Figure 4-11 shows a waveform for the manual Reset
switch input and the Reset pins output.
FIGURE 4-10: Push Button Reset.
FIGURE 4-11: MR Input – Push Button.
4.4.1 NOISE FILTER
The noise filter filters out noise spikes (glitches) on the
Manual Reset pin (MR). Noise spikes less than 100 ns
(typical) are filtered.
Time (µs)
0V
Supply Voltage
5V
VTRIP(MIN) - VDD
tTRAN (Duration)
VTRIP(MAX)
VTRIP(MIN)
(Overdrive)
Transient Overdrive Voltage (mV)
Transient Duration (ms)
Area below curve will
not generate a Reset signal
Area above curve will
generate a Reset signal
VDD
MR
VSS
RST MCLR
+5V
TC127XA PIC® MCU
RST
VIL
tMR
RST
tMD
VIH
tRST
MR
The MR input typically ignores input pulses
of 100 ns.
TC1270A/70AN/71A
DS22035D-page 24 2007-2011 Microchip Technology Inc.
4.5 Reset Generator Circuit
The output signals from the voltage detect circuit and
the manual Reset with glitch filter circuit are OR’d
together and used to activate the Reset generator
module.
After the Reset conditions have been removed (the MR
pin is no longer forced low and the input voltage is
greater than the trip point voltage), the Reset generator
circuit determines the Reset delay time-out required.
There are three options for the delay circuit. These are:
2.19 ms (typical) delay
35 ms (typical) delay
280 ms (typical) delay
4.5.1 RESET DELAY TIMER
The Reset Delay Timer ensures that the TC127XA
device will “hold” the embedded system in Reset until
the system voltage has stabilized. The Reset Delay
Timer time-out is shown in Table 4-4.
The Reset Delay Timer starts when the voltage detect
circuit output AND the manual Reset with glitch filter
circuit output become inactive. While the Reset Delay
Timer is active, the RST or RST pin is driven to the
active state. When the Reset Delay Timer times out,
the RST or RST pin is driven inactive.
The Reset Delay Timer (tRST) starts after the device
voltage rises above the “actual” trip point (VTRIP).
When the Reset Delay Timer times out, the Reset out-
put pin (RST/RST) is driven inactive.
The Reset Delay Timer is cleared if either, or both, the
voltage detector circuit output and the manual Reset
with glitch filter circuit output become active. The RST
or RST pin continues to be driven to the active state.
Figure 4-12 illustrates when the Reset Delay Timer
(tRST) is active or inactive.
4.5.2 EFFECT OF TEMPERATURE ON
RESET POWER-UP TIMER (tRPU)
The Reset Delay Timer time-out period (tRST)
determines how long the device remains in the Reset
condition. This time out is affected by the device VDD
and the temperature. Typical responses for varying
VDD values and temperatures are presented in
Figures 2-28, 2-29 and 2-30.
TABLE 4-4: RESET DELAY TIMER
TIME OUTS
FIGURE 4-12: Reset Power-up Timer
Waveform.
tRST Units
Min Typ Max
1.09 2.19 4.38 ms
17.5 35 70 ms
140 280 560 ms

This is the
minimum time that
the Reset Delay
Timer will “hold”
the Reset pin
active after VDD
rises above VTRIP
This is the
maximum time that
the Reset Delay
Timer will “hold”
the Reset pin
active after VDD
rises above VTRIP
Note 1: Shaded rows are custom-ordered time
outs.
VTRIP
VDD
RST tRST
Reset Delay
Timer Inactive
Reset
Delay
Timer
Inactive
Reset Delay
Timer Active
See Figures 2-9,
2-7 and 2-8
See Figures 2-12, 2-11 and 2-10
See Figures 2-9,
2-7 and 2-8
2007-2011 Microchip Technology Inc. DS22035D-page 25
TC1270A/70AN/71A
5.0 APPLICATION INFORMATION
This section presents application-related information
that may be useful for your particular design require-
ments.
5.1 Supply Monitor Noise Sensitivity
The TC127XA devices are optimized for fast responses
to negative-going changes in VDD. A system with an
inordinate amount of electrical noise on VDD (such as a
system using relays) may require a 0.01 µF or 0.1 µF
bypass capacitor to reduce detection sensitivity. This
capacitor should be installed as close to the TC127XA
as possible to keep the capacitor lead length short.
FIGURE 5-1: Typical Application Circuit
with Bypass Capacitor.
5.2 Conventional Voltage Monitoring
Figure 5-2 and Figure 5-3 show the TC127XA in
conventional voltage monitoring applications.
FIGURE 5-2: Battery Voltage Monitor.
FIGURE 5-3: Power Good Monitor.
5.3 Using in PIC® Microcontroller,
ICSP™ Applications
Figure 5-4 shows the typical application circuit for using
the TC1270AN for voltage supervisory function when
the PIC microcontroller will be programmed via the
In-Circuit Serial Programming™ (ICSP™) feature.
Additional information is available in the Microchip
Technical Brief TB087, “Using Voltage Supervisors with
PICmicro® Microcontroller Systems which Implement
In-Circuit Serial Programming™” (DS91087).
FIGURE 5-4: Typical Application Circuit
for PIC Microcontroller with the ICSP Feature.
TC127XA
VDD
RST
VSS
0.1 µF
RST
MR
VDD
RST
VSS
BATLOW
TC127XA
+
VDD
RST
VSS
Power Good
TC127XA
+
Pwr
Sply
Note: This operation can only be done using the
device that has an Open-Drain RST pin
(TC1270AN).
Note: It is recommended that the current into the
RST pin is current that is limited by a 1 k
resistor.
TC1270AN
VDD
VDD/VPP
VDD
RST MCLR
Reset input)
(Active-Low)
VSS VSS
PIC®
Microcontroller
RPU
0.1 µF
1k
TC1270A/70AN/71A
DS22035D-page 26 2007-2011 Microchip Technology Inc.
5.4 Modifying The Trip Point, VTRIP
Although the TC127XA device has a fixed voltage trip
point (VTRIP), it can be necessary to make custom
adjustments. This is accomplished by connecting an
external resistor divider to the TC127XA VDD pin. This
causes the VSOURCE voltage to be higher than it is
when the TC127XA input equals its VTRIP voltage
(Figure 5-5).
To maintain detector accuracy, the bleeder current
through the divider should be significantly higher than
the 15 µA maximum operating current required by the
TC127XA. A reasonable value for this bleeder current
is 1 mA (67 times the 10 µA required by the TC127XA).
For example, if VTRIP = 2V and the desired trip point is
2.5V, the value of R1 + R2 is 2.5 k (2.5V/1 mA). The
value of R1 + R2 can be rounded to the nearest
standard value and plugged into the equation shown in
Figure 5-5 to calculate values for R1 and R2.
1% tolerance resistors are recommended.
FIGURE 5-5: Modifying Trip-Point using
External Resistor Divider.
5.5 MOSFET Low-Drive Protection
Low operating power and small physical size make the
TC1270AN series ideal for many voltage detector
applications. Figure 5-6 shows a low-voltage gate drive
protection circuit that prevents the logic-level MOSFET
from overheating due to insufficient gate voltage. When
the input signal is below the threshold of the
TC1270AN, its output grounds the gate of the
MOSFET.
FIGURE 5-6: MOSFET Low-Drive
Protection.
TC127XA
VDD RST
VSS
R1
VSOURCE
R2
or RST
VSOURCE
R1
R1R2
+
--------------------
VTRIP
Where:
Note: In this example, VSOURCE must be greater
than VTRIP.
VSOURCE = Voltage to be monitored
VTRIP = Threshold Voltage setting
VDD
RST
VSS
TC1270AN
270(1)
MTP3055EL
VDD
RL
VTRIP
Note 1: This resistance should be sized appro-
priately for the selected trip point volt-
age related to the VOL operation.
2007-2011 Microchip Technology Inc. DS22035D-page 27
TC1270A/70AN/71A
5.6 Controllers and Processors With
Bidirectional I/O Pins
Some microcontrollers have bidirectional Reset pins.
Depending on the current drive capability of the
controller pin, an indeterminate logic level may result if
there is a logic conflict. This can be avoided by adding
a 4.7 k resistor in series with the output of the
TC127XA (Figure 5-7). If there are other components
in the system that require a Reset signal, they should
be buffered so as not to load the Reset line. If the other
components are required to follow the Reset I/O of the
microcontroller, the buffer should be connected as
shown with the solid line.
FIGURE 5-7: Interfacing the TC1270A or
TC1271A Push-Pull Output to a Bidirectional
Reset I/O pin.
5.7 Migration Paths
Figure 5-8 shows the 5-pin SOT-23 footprint of the
TC1270A, TC1270AN and TC1271A devices. Devices
that are in the 3-pin SOT-23 package could be used in
that circuit with the loss of manual Reset functionality.
Examples of compatible footprint devices in the SOT-
23-3 package are the MCP111, MCP112, TC54 and
TC51 devices. This allows the system to be designed
to offer a “base” functionality and a higher end system
with the “enhanced” functionality, which includes a
manual Reset.
FIGURE 5-8: SOT-23 5-pin to 3-pin
Comparison.
5.8 Reset Signal Integrity During
Power-Down
The TC1270A and TC1271A Reset output is valid
down to VDD = 1.0V. Below this voltage the output
becomes an “open circuit” and does not sink current.
This means CMOS logic inputs to the microcontroller
will be floating at an undetermined voltage. Most digital
systems are completely shut down well above this volt-
age. However, in situations where the Reset signal
must be maintained valid to VDD = 0V, external circuitry
is required.
For devices where the Reset signal is active-low, a
pull-down resistor must be connected from the
TC1270A RST pin to ground to discharge stray
capacitances and hold the output low (Figure 5-9).
Similarly for devices where the Reset signal is
active-high, a pull-up resistor to VDD is required to
ensure a valid high RST signal for VDD below 1.0V
(Figure 5-10).
This resistor value, though not critical, should be
chosen such that it does not appreciably load the Reset
pin under normal operation (100 k should be suitable
for most applications).
FIGURE 5-9: Ensuring a valid active-low
Reset pin output state as VDD approaches 0V.
FIGURE 5-10: Ensuring a valid active-high
Reset pin output state as VDD approaches 0V.
MR
VSS VSS
VDD
VDD
RST Reset I/O
TC1270A/71A
VDD
or
RST
Buffered
Reset to
system
4.7 k
3
2
1
SOT-23-3
1
2
3
5
4
SOT-23-5
NC
VDD
MR RST
VSS VSS
VDD
or
RST
RST
or
RST
MR
VSS
VDD
RST
TC1270A
VDD
R1
100 k
MR
VSS
VDD
RST
TC1271A
VDD
R1
100 k
TC1270A/70AN/71A
DS22035D-page 28 2007-2011 Microchip Technology Inc.
NOTES:
2007-2011 Microchip Technology Inc. DS22035D-page 29
TC1270A/70AN/71A
6.0 STANDARD DEVICES
Table 6-1 shows the standard devices, with order
numbers, as well as the corresponding configurations.
Configurations can include the following options:
Voltage Trip Point (VTRIP)
Reset Time Out (tRST)
TABLE 6-1: STANDARD VERSIONS
Device
Reset Threshold (V) Reset Time Out (ms)
Package
Order Number Replaces
Minimum
Typical
Maximum
Code
Minimum
Typical
Maximum
Code(1)
TC1270A 4.50 4.63 4.75 L 140 280 560 “blank
SOT-23-5 TC1270ALVCTTR
SOT-143 TC1270ALVRCTR TC1270LERC/
TCM811LERC
TC1270A 4.25 4.38 4.50 M 140 280 560 “blank”
SOT-23-5 TC1270AMVCTTR
SOT-143 TC1270AMVRCTR TC1270MERC/
TCM811MERC
TC1270A 3.00 3.08 3.15 T 140 280 560 “blank”
SOT-23-5 TC1270ATVCTTR
SOT-143 TC1270ATVRCTR TC1270TERC/
TCM811TERC
TC1270A 2.85 2.93 3.00 S 140 280 560 “blank”
SOT-23-5 TC1270ASVCTTR
SOT-143 TC1270ASVRCTR TC1270SERC/
TCM811SERC
TC1270A 2.55 2.63 2.70 R 140 280 560 “blank”
SOT-23-5 TC1270ARVCTTR
SOT-143 TC1270ARVRCTR TC1270RERC/
TCM811RERC
TC1270AN 4.50 4.63 4.75 L 140 280 560 “blank” SOT-23-5 TC1270ANLVCTTR
SOT-143 TC1270ANLVRCTR —
TC1270AN 4.25 4.38 4.50 M 140 280 560 “blank” SOT-23-5 TC1270ANMVCTTR —
SOT-143 TC1270ANMVRCTR —
TC1270AN 3.00 3.08 3.15 T 140 280 560 “blank” SOT-23-5 TC1270ANTVCTTR
SOT-143 TC1270ANTVRCTR —
TC1270AN 2.85 2.93 3.00 S 140 280 560 “blank” SOT-23-5 TC1270ANSVCTTR
SOT-143 TC1270ANSVRCTR —
TC1270AN 2.55 2.63 2.70 R 140 280 560 “blank” SOT-23-5 TC1270ANRVCTTR
SOT-143 TC1270ANRVRCTR —
TC1271A 4.50 4.63 4.75 L 140 280 560 “blank
SOT-23-5 TC1271ALVCTTR
SOT-143 TC1271ALVRCTR TC1271LERC/
TCM812LERC
TC1271A 4.25 4.38 4.50 M 140 280 560 “blank”
SOT-23-5 TC1271AMVCTTR
SOT-143 TC1271AMVRCTR TC1271MERC/
TCM812MERC
TC1271A 3.00 3.08 3.15 T 140 280 560 “blank”
SOT-23-5 TC1271ATVCTTR
SOT-143 TC1271ATVRCTR TC1271TERC/
TCM812TERC
TC1271A 2.85 2.93 3.00 S 140 280 560 “blank”
SOT-23-5 TC1271ASVCTTR
SOT-143 TC1271ASVRCTR TC1271SERC/
TCM812SERC
TC1271A 2.55 2.63 2.70 R 140 280 560 “blank
SOT-23-5 TC1271ARVCTTR
SOT-143 TC1271ARVRCTR TC1271RERC/
TCM812RERC
Note 1: “A” time-out delay options are only standard in the SOT-23-5 package. SOT-143 package is a custom request.
TC1270A/70AN/71A
DS22035D-page 30 2007-2011 Microchip Technology Inc.
NOTES:
2007-2011 Microchip Technology Inc. DS22035D-page 31
TC1270A/70AN/71A
7.0 CUSTOM CONFIGURATIONS
The following Custom Reset Trip Point is available (see
Table 7-1).
TABLE 7-1: CUSTOM TRIP POINT
Table 7-2 shows the codes that specify the desired
Reset time out (tRST) for custom devices.
TABLE 7-2: DELAY TIME OUT ORDERING CODES
Trip
Voltage
Selection
VTRIP(MAX)/
VTRIP(MIN)
- % From
Regulated Voltage
3.0V
(1)2.85V 5.0%
2.70V 10.0%
Note 1: Contact your local Microchip sales office
for additional information.
Code Reset Delay
Time (Typ) (ms) Comment
A35 Note 1
B2.19 Note 1
“blank” 280 Delay timings for standard device offerings
Note 1: This delay timing option is not the standard offering. For information on ordering devices with these delay
times, contact your local Microchip sales office. Minimum purchase volumes are required.
TC1270A/70AN/71A
DS22035D-page 32 2007-2011 Microchip Technology Inc.
NOTES:
www.microchig.com
2007-2011 Microchip Technology Inc. DS22035D-page 33
TC1270A/70AN/71A
8.0 DEVELOPMENT TOOLS
8.1 Evaluation/Demonstration Boards
The SOT-23-5/6 Evaluation Board (VSUPEV2) can be
used to evaluate the characteristics of the TC127XA
devices.
This blank PCB has footprints for:
Pull-up Resistor
Pull-down Resistor
Loading Capacitor
In-line Resistor
There is also a power supply filtering capacitor.
For evaluating the TC127XA devices, the selected
device should be installed into the Option A footprint.
FIGURE 8-1: SOT-23-5/6 Voltage
Supervisor Evaluation Board (VSUPEV2).
The SOIC-14 Evaluation Board (SOIC14EV) has a
SOT-23-6 footprint that can be jumpered into any por-
tion of the circuit. This will allow any footprint that the
TC1270A requires in the SOT-23-5 package.
FIGURE 8-2: SOIC-14 Evaluation Board
(Microchip Part Number SOIC14EV).
The PCB number, 102-00094, appears on the lower left
side of the board. These evaluation boards can be pur-
chased directly from the Microchip web site at
www.microchip.com.
TC1270A/70AN/71A
DS22035D-page 34 2007-2011 Microchip Technology Inc.
NOTES:
NN
2007-2011 Microchip Technology Inc. DS22035D-page 35
TC1270A/70AN/71A
9.0 PACKAGING INFORMATION
9.1 Package Marking Information
5-Pin SOT-23
Part Number Code Part Number Code
TC1270ALVCTTR F1NN TC1271ALVCTTR J1NN
TC1270AMVCTTR F2NN TC1271AMVCTTR J2NN
TC1270ATVCTTR F3NN TC1271ATVCTTR J3NN
TC1270ASVCTTR F4NN TC1271ASVCTTR J4NN
TC1270ARVCTTR F5NN TC1271ARVCTTR J5NN
TC1270ANLVCTTR FSNN
TC1270ANMVCTTR FTNN
TC1270ANTVCTTR FUNN
TC1270ANSVCTTR FVNN
TC1270ANRVCTTR FWNN
Example:
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
XXNN F125
4-Lead SOT-143
XXNN
Example:
C125
Part Number Code Part Number Code
TC1270ALVRCTR D1NN TC1271ALVRCTR C1NN
TC1270AMVRCTR D2NN TC1271AMVRCTR C2NN
TC1270ATVRCTR D3NN TC1271ATVRCTR C3NN
TC1270ASVRCTR D4NN TC1271ASVRCTR C4NN
TC1270ARVRCTR D5NN TC1271ARVRCTR C5NN
TC1270ANLVRCTR E1NN
TC1270ANMVRCTR E2NN
TC1270ANTVRCTR E3NN
TC1270ANSVRCTR E4NN
TC1270ANRVRCTR E5NN
TC1270A/70AN/71A
DS22035D-page 36 2007-2011 Microchip Technology Inc.
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2007-2011 Microchip Technology Inc. DS22035D-page 37
TC1270A/70AN/71A
5-Lead Plastic Small Outline Transistor (CT) [SOT-23]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
TC1270A/70AN/71A
DS22035D-page 38 2007-2011 Microchip Technology Inc.
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4-Lead Plastic Small Outline Transistor (RC) [SOT-143] 1' S1LK SCREEN \ ‘ —| 1 1 +0 -1 +x2+ RECOMMENDED LAND PATTERN 52—» Umts MILUMETERS D1mension mes MIN 1 NOM 1 MAX Contact Pitch E1 1.90 850 Contact Pitch E2 1.60 BSC Contact W1dlh ><1 0.60="" contact="" w1dlh=""><2 1.00="" contact="" length="" y="" 1.30="" contact="" pad="" spacmg="" c="" 2.10="" nales'="" 1="" dimenswnlng="" and="" to1erancmg="" per="" asme="" v14="" 5m="" esc="" easlc="" dtmensmn="" theorencauy="" exact="" value="" shown="" w1thout="" to1erances="" microcmp="" technolmgy="" drawmg="" no.="" goa—2031a="">
2007-2011 Microchip Technology Inc. DS22035D-page 39
TC1270A/70AN/71A
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TC1270A/70AN/71A
DS22035D-page 40 2007-2011 Microchip Technology Inc.
9.2 Product Tape and Reel Specifications
FIGURE 9-1: EMBOSSED CARRIER DIMENSIONS (8 MM TAPE ONLY)
FIGURE 9-2: 5-LEAD SOT-23 DEVICE TAPE AND REEL SPECIFICATIONS
TABLE 1: CARRIER TAPE/CAVITY DIMENSIONS
Case
Outline Package
Type
Carrier
Dimensions Cavity
Dimensions Output
Quantity
Units
Reel
Diameter in
mm
W
mm P
mm A0
mm B0
mm K0
mm
CT SOT-23 5L 8 4 3.23 3.17 1.37 3000 180
RC SOT-143 4L 8 4 3.1 2.69 1.3 3000 330
Hl'l I‘ll—I DEWCE SNIXHVW MARK‘NG EDI/GIG |_| Ll IJ Ll DIRECTION OF FEED PIN 1 |—— P ——’ STANDARD REEL REVERSE REEL
2007-2011 Microchip Technology Inc. DS22035D-page 41
TC1270A/70AN/71A
FIGURE 9-3: 4-LEAD SOT-143 DEVICE TAPE AND REEL SPECIFICATIONS
Component Taping Orientation for 4-Pin SOT-143 Devices
Carrier Tape, Number of Components Per Reel and Reel Size:
Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size
4-Pin SOT-143 8 mm 4 mm 3000 7 in.
TC1270A/70AN/71A
DS22035D-page 42 2007-2011 Microchip Technology Inc.
NOTES:
2007-2011 Microchip Technology Inc. DS22035D-page 43
TC1270A/70AN/71A
APPENDIX A: REVISION HISTORY
Revision D (August 2011)
The following is the list of modifications:
1. Added the SOT-143 package to the TC1270AN
device and related information throughout the
document.
Revision C (October 2010)
The following is the list of modifications:
1. Modified the Product Identification System
section to reflect the custom manufacturing
code used for devices with a Reset Delay time
out of 35 ms (was a “C”, now is an “A”).
2. Clarified information presented in Section 4.2
“Voltage Detect Circuit” (page 21).
Revision B (June 2007)
The following is the list of modifications:
1. Added new options:
- Open-Drain output
- New Reset Delay time outs.
2. Updated Package Outline Drawings
3. Updated Revision History
4. Added new options to Product Identification
System
Revision A (March 2007)
Original Release of this Document.
TC1270A/70AN/71A
DS22035D-page 44 2007-2011 Microchip Technology Inc.
NOTES:
PART NO. XX T 44x 41x 41x
2007-2011 Microchip Technology Inc. DS22035D-page 45
TC1270A/70AN/71A
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: TC1270A: Voltage Supervisor with Manual Reset
TC1270AN: Voltage Supervisor with Manual Reset
TC1271A: Voltage Supervisor with Manual Reset
VTRIP Options: R = 2.55V (min.) / 2.63V (typ.) / 2.70V (max.)
S = 2.85V (min.) / 2.93V (typ.) / 3.00V (max.)
T = 3.00V (min.) / 3.08V (typ.) / 3.15V (max.)
M = 4.25V (min.) / 4.38V (typ.) / 4.50V (max.)
L = 4.50V (min.) / 4.63V (typ.) / 4.75V (max.)
Time-Out Options: “blank” = tRST = 280 ms (typ)
A=t
RST = 35 ms (typ)
B=t
RST = 2.19 ms (typ)
Temperature Range: V = -40°C to +125°C
Package: CT = Plastic Small Outline Transistor, SOT-23, 5-lead
RC = Plastic Small Outline Transistor, SOT-143,
4-lead
Tape/Reel Option: TR = Tape and Reel
Examples:
a) TC1270ASVCTTR:
2.85V min./2.93V typ./3.00V max.
voltage trip point,
Push-pull active-low Reset,
Reset Delay Timer = 280 ms,
5-LD SOT-23, Tape and Reel,
-40°C to +125°C
b) TC1270ALVRCTR:
4.50V min./4.63V typ./4.75V max.
voltage trip point,
Push-pull active-low Reset,
Reset Delay Timer = 280 ms,
4-LD SOT-143, Tape and Reel,
-40°C to +125°C
c) TC1270ANMBVCTTR:
4.25V min./4.38V typ./4.50V max.
Open-drain active-low Reset,
Reset Delay Timer = 2.19 ms,
5-Lead SOT-23, Tape and Reel,
-40°C to +125°C
d) TC1270ANLAVCT:
4.50V min./4.63V typ./4.75V max.
Open-drain active-low Reset,
Reset Delay Timer = 35 ms,
5-Lead SOT-23,
-40°C to +125°C
e) TC1271ARVCTTR:
2.55V min./2.63V typ./2.70V max.
voltage trip point,
Push-pull active-high Reset,
Reset Delay Timer = 280 ms,
5-LD SOT-23, Tape and Reel,
-40°C to +125°C
f) TC1271ATVRCTR:
3.00V min./3.08V typ./3.15V max.
voltage trip point,
Push-pull active-high Reset,
Reset Delay Timer = 280 ms,
4-LD SOT-143, Tape and Reel,
-40°C to +125°C
PART NO. XX X
Temperature
VTRIP
Options
Device Range
XX
Package
X
Tape/Reel
Option
X
Reset Delay
Options
TC1270A/70AN/71A
DS22035D-page 46 2007-2011 Microchip Technology Inc.
NOTES:
QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV = ISO/TS 169492009:
2007-2011 Microchip Technology Inc. DS22035D-page 47
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007-2011, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-466-8
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
6‘ ‘MICRDCHIP
DS22035D-page 48 2007-2011 Microchip Technology Inc.
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