MCP3905A,05L,06A Datasheet by Microchip Technology

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MCP3905A/05L/06A

Features

• Supplies active (real) power measurement for

single-phase, residential energy metering

• Supports IEC 62053 International Energy

Metering Specification and legacy IEC

1036/61036/687 Specifications

• Two multi-bit, DAC, second-order, 16-bit, Delta-

Sigma Analog-to-Digital Converters (ADCs)

• Reduced pulse-width of calibration output

frequency and mechanical counter drive for low

power meter designs (MCP3905L)

• Increased output frequency constant options for

meter design (MCP3905L)

• 0.1% typical measurement error over 500:1

dynamic range (MCP3905A / MCP3905L)

• 0.1% typical measurement error over 1000:1

dynamic range (MCP3906A)

• Programmable Gain Amplifier (PGA) for small

signal inputs supports low value shunt current

sensor:

-16:1 PGA - MCP3905A / MCP3905L

-32:1 PGA - MCP3906A

• Ultra-low drift on-chip reference:

15 ppm/°C (typical)

• Direct drive for electromagnetic mechanical

counter and two-phase stepper motors

•Low I

DD of 4 mA (typical)

• Tamper output pin for negative power indication

• Industrial Temperature Range: -40°C to +85°C

• Extended Temperature Range: -40°C to +125°C

• Supplies instantaneous real power on HFOUT for

meter calibration

Description

The MCP3905A/05L/06A devices are energy-metering

ICs designed to support the IEC 62053 international

metering standard specification. They supply a

frequency output proportional to the average active real

power, as well as a higher-frequency output

proportional to the instantaneous power for meter

calibration. The MCP3905L offers reduced pulse width

of calibration output frequency and mechanical counter

drive for lower power meter designs. They include two

16-bit, Delta-Sigma ADCs for a wide range of IB and

IMAX currents and/or small shunt (<200 µOhms) meter

designs. It includes an ultra-low drift voltage reference

with < 15 ppm/°C through a specially designed band

gap temperature curve for the minimum gradient

across the industrial temperature range. A fixed-

function DSP block is on-chip for active real-power

calculation. A no-load threshold block prevents any

current creep measurements. A Power-On Reset

(POR) block restricts meter performance during low-

voltage situations. These accurate energy metering ICs

with high field reliability are available in the industry

standard pinout.

Package Type

Functional Block Diagram

FOUT0

DGND

NEG

FOUT1

OSC2

OSC1

DVDD

HPF

AVDD

CH0+

CH0-

CH1-

CH1+

HFOUT

169G0

MCLR

11 G1

REFIN/OUT

AGND

12 F1

24-Pin SSOP

16-bit

ΔΣ ADC

MCLR

–

CH0+

CH0-

Reference

2.4V

–

CH1+

CH1-

HPF1

LPF1 E-to-F

conversion

REFIN/

FOUT1

HFOUT

G0 G1

F2 F1

FOUT0

OSC1 OSC2

OUT

NEG

HPF

Multi-level

16-bit

ΔΣ ADC

Multi-level

HPF1

PGA

POR

Energy Metering ICs with Active Real Power Pulse Output

MCP3905A/05L/06A

NOTES:

REF AGND Demo

MCP3905A/05L/06A

1.0 ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings †

VDD...................................................................................7.0V

Digital inputs and outputs w.r.t. AGND........ -0.6V to VDD +0.6V

Analog input w.r.t. AGND .........................................-6V to +6V

VREF input w.r.t. AGND............................... -0.6V to VDD +0.6V

Storage temperature .....................................-65°C to +150°C

Ambient temp. with power applied................-65°C to +125°C

Soldering temperature of leads (10 seconds) .............+300°C

ESD on the analog inputs (HBM,MM).................5.0 kV, 500V

ESD on all other pins (HBM,MM)........................5.0 kV, 500V

† Notice: Stresses above those listed under “Maximum

Ratings” may cause permanent damage to the device.

This is a stress rating only and functional operation of

the device at those or any other conditions above those

indicated in the operation listings of this specification is

not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 4.5V – 5.5V,

Internal VREF

, HPF turned on (AC mode), AGND, DGND = 0V, MCLK = 3.58 MHz; TA = -40°C to +85°C.

Parameter Sym Min Typ Max Units Comment

Overall Measurement Accuracy

Energy Measurement Error E — 0.1 — % FOUT Channel 0 swings 1:500 range,

MCP3905A, MCP3905L only

(Note 1, Note 4)

— 0.1 — % FOUT Channel 0 swings 1:1000 range,

MCP3906A only (Note 1, Note 4)

No-Load Threshold/

Minimum Load NLT — 0.0015 — % FOUT

Max Disabled when F2, F1, F0 = 0, 1, 1

(Note 5, Note 6)

Phase Delay Between

Channels — — 1/MCLK s HPF = 0 and 1, < 1 MCLK

(Note 4, Note 6, Note 7)

AC Power Supply Rejection

(output frequency variation) AC PSRR — 0.01 — % FOUT F2, F1, F0 = 0, 1, 1 (Note 3)

DC Power Supply Rejection

(output frequency

variation)

DC PSRR — 0.01 — % FOUT HPF = 1, Gain = 1 (Note 3)

System Gain Error — 3 10 % FOUT (Note 2, Note 5)

ADC/PGA Specifications

Offset Error VOS — 2 5 mV Referred to Input

Gain Error Match — 0.5 — % FOUT (Note 5)

Internal Voltage Reference

Voltage — 2.4 — V

Tolerance — ±2 — %

Tempco — 15 — ppm/°C

Note 1: Measurement error = (Energy Measured By Device - True Energy)/True Energy * 100%. Accuracy is

measured with signal (±660 mV) on Channel 1. FOUT0, FOUT1 pulse outputs. Valid from 45 Hz to 65 Hz.

See typical performance curves for higher frequencies and increased dynamic range.

2: Does not include internal VREF. Gain = 1, CH0 = 470 mVDC, CH1 = 660 mVDC, difference between

measured output frequency and expected transfer function.

3: Percent of HFOUT output frequency variation; Includes external VREF = 2.5V, CH1 = 100 mVRMS @

50 Hz, CH2 = 100 mVRMS @ 50 Hz, AVDD = 5V + 1Vpp @ 100 Hz. DC PSRR: 5V ±500 mV

4: Error applies down to 60 degree lead (PF = 0.5 capacitive) and 60 degree lag (PF = 0.5 inductive).

5: Refer to Section 4.0 “Device Overview” for complete description.

6: Specified by characterization, not production tested.

7: 1 MCLK period at 3.58 MHz is equivalent to less than <0.005 degrees at 50 or 60 Hz.

AVDD DVDD A(3ND DGND

MCP3905A/05L/06A

Reference Input

Input Range 2.2 — 2.6 V

Input Impedance 3.2 — — kΩ

Input Capacitance — — 10 pF

Analog Inputs

Maximum Signal Level — — ±1 V CH0+,CH0-,CH1+,CH1- to AGND

Differential Input Voltage

Range Channel 0 — — ±470/G mV G = PGA Gain on Channel 0

Differential Input Voltage

Range Channel 1 ——±660mV

Input Impedance 390 — — kΩProportional to 1/MCLK frequency

Bandwidth

(Notch Frequency) — 14 — kHz Proportional to MCLK frequency,

MCLK/256

Oscillator Input

Frequency Range MCLK 1 — 4 MHz

Power Specifications

Operating Voltage 4.5 — 5.5 V AVDD, DVDD

IDD,A IDD,A —2.7 3.0 mAAV

DD pin only

IDD,D IDD,D —1.2 2.0 mADV

DD pin only

TEMPERATURE CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, VDD = 4.5V – 5.5V, AGND, DGND = 0V.

Parameters Sym Min Typ Max Units Conditions

Temperature Ranges

Specified Temperature Range TA-40 — +85 °C

Operating Temperature Range TA-40 — +125 °C (Note)

Storage Temperature Range TA-65 — +150 °C

Note: The MCP3905A/05L/06A operate over this extended temperature range, but with reduced performance. In

any case, the Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C.

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 4.5V – 5.5V,

Internal VREF

, HPF turned on (AC mode), AGND, DGND = 0V, MCLK = 3.58 MHz; TA = -40°C to +85°C.

Parameter Sym Min Typ Max Units Comment

Note 1: Measurement error = (Energy Measured By Device - True Energy)/True Energy * 100%. Accuracy is

measured with signal (±660 mV) on Channel 1. FOUT0, FOUT1 pulse outputs. Valid from 45 Hz to 65 Hz.

See typical performance curves for higher frequencies and increased dynamic range.

2: Does not include internal VREF. Gain = 1, CH0 = 470 mVDC, CH1 = 660 mVDC, difference between

measured output frequency and expected transfer function.

3: Percent of HFOUT output frequency variation; Includes external VREF = 2.5V, CH1 = 100 mVRMS @

50 Hz, CH2 = 100 mVRMS @ 50 Hz, AVDD = 5V + 1Vpp @ 100 Hz. DC PSRR: 5V ±500 mV

4: Error applies down to 60 degree lead (PF = 0.5 capacitive) and 60 degree lag (PF = 0.5 inductive).

5: Refer to Section 4.0 “Device Overview” for complete description.

6: Specified by characterization, not production tested.

7: 1 MCLK period at 3.58 MHz is equivalent to less than <0.005 degrees at 50 or 60 Hz.

AGND GND OUT OUTD oun OUT

MCP3905A/05L/06A

TIMING CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 4.5V – 5.5V,

AGND, DGND = 0V, MCLK = 3.58 MHz; TA = -40°C to +85°C.

Parameter Sym Min Typ Max Units Comment

Frequency Output

FOUT0 and FOUT1 Pulse Width

(Logic Low) for MCP3905A, MCP3906A

devices

tFW —275 —ms 984376 MCLK periods

(Note 1)

HFOUT Pulse Width for MCP3905A,

MCP3906A devices tHW —90 —ms 322160 MCLK periods

(Note 2)

FOUT0 and FOUT1 Pulse Width

(Logic Low) for MCP3905L device tFW —130 —ms 465344 MCLK periods

(Note 1)

HFOUT Pulse Width for MCP3905L

device tHW —65 —ms 232672 MCLK periods

(Note 2)

FOUT0 and FOUT1 Pulse Period tFP Refer to Equation 4-1 s

HFOUT Pulse Period tHP Refer to Equation 4-2 s

FOUT0 to FOUT1 Falling-Edge Time tFS2 —0.5 tFP —

FOUT0 to FOUT1 Min Separation tFS —4/MCLK —

FOUT0 and FOUT1 Output High Voltage VOH 4.5 ——VI

OH = 10 mA, DVDD = 5.0V

FOUT0 and FOUT1 Output Low Voltage VOL ——0.5 V IOL = 10 mA, DVDD = 5.0V

HFOUT Output High Voltage VOH 4.0 ——VI

OH = 5 mA, DVDD = 5.0V

HFOUT Output Low Voltage VOL ——0.5 V IOL = 5 mA, DVDD = 5.0V

High-Level Input Voltage

(All Digital Input Pins) VIH 2.4 ——VDV

DD = 5.0V

Low Level Input Voltage

(All Digital Input Pins) VIL ——

0.85 V DVDD = 5.0V

Input Leakage Current ——±3 µA VIN = 0, VIN = DVDD

Pin Capacitance ——10 pF Note 3

Note 1: If output pulse period (tFP) falls below 984376*2 MCLK periods for MCP3905A/6A and 465344*2 MCLK

periods for MCP3905L, then tFW = 1/2 tFP

2: If output pulse period (tHP) falls below 322160*2 MCLK periods for MCP3905A/6A and 232672*2 MCLK

periods for MCP3905L, then tHW = 1/2 tHP. When F2, F1,F0 = 011, tHW is fixed to 18 µs (64 MCLK

periods).

3: Specified by characterization, not production tested.

MCP3905A/05L/06A

FIGURE 1-1: Output Timings for Pulse Outputs and Negative Power Pin.

FOUT0

tFP

FOUT1

HFOUT

tFW

tHP

tHW

tFS

tFS2

NEG

MCP3905A/05L/06A

2.0 TYPICAL PERFORMANCE CURVES

Note: Unless otherwise specified, DVDD, AVDD = 5V; AGND, DGND = 0V; VREF = Internal, HPF = 1 (AC mode),

MCLK = 3.58 MHz.

FIGURE 2-1: Measurement Error,

Gain = 8 PF = 1.

FIGURE 2-2: Measurement Error,

Gain = 16, PF = 1.

FIGURE 2-3: Measurement Error,

Gain = 32, PF = 1.

FIGURE 2-4: Measurement Error,

Gain = 8, PF = 0.5.

FIGURE 2-5: Measurement Error,

Gain = 16, PF = 0.5.

FIGURE 2-6: Measurement Error,

Gain =32, PF = 0.5.

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

0.0000 0.0001 0.0010 0.0100 0.1000

CH1 Vp-p Amplitude (V)

Measurement Error

+85°C

+25°C

-40°C

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

0.0000 0.0001 0.0010 0.0100 0.1000

CH1 Vp-p Amplitude (V)

Measurement Error

+85°C

+25°C

- 40°C

-0.5

-0.25

0.25

0.5

0.75

0.0000 0.0001 0.0010 0.0100 0.1000

CH1 Vp-p Amplitude (V)

Measurement Error

+85°C

+25°C

- 40°C

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

0.0000 0.0001 0.0010 0.0100 0.1000

CH1 Vp-p Amplitude (V)

Measurement Error

+85°C

+25°C

-40°C

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

0.0000 0.0001 0.0010 0.0100 0.1000

CH1 Vp-p Amplitude (V)

Measurement Error

+85°C

+25°C

-40°C

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

0.0000 0.0001 0.0010 0.0100 0.1000

CH1 Vp-p Amplitude (V)

Measurement Error

+85°C

+25°C

-40°C

MCP3905A/05L/06A

Note: Unless otherwise specified, DVDD, AVDD = 5V; AGND, DGND = 0V; VREF = Internal, HPF = 1 (AC mode),

MCLK = 3.58 MHz.

FIGURE 2-7: Measurement Error,

Gain = 1, PF = 1.

FIGURE 2-8: Measurement Error,

Gain = 2, PF = 1.

FIGURE 2-9: Measurement Error,

Gain = 1, PF = + 0.5.

FIGURE 2-10: Measurement Error,

Gain = 2, PF = + 0.5.

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

0.0001 0.0010 0.0100 0.1000 1.0000

CH0 Vp-p Amplitude (V)

Measurement Error

+85°C

+25°C

- 40°C

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

0.0001 0.0010 0.0100 0.1000 1.0000

CH0 Vp-p Amplitude (V)

Measurement Error

+85°C

+25°C

- 40°C

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

0.0001 0.0010 0.0100 0.1000 1.0000

CH1 Vp-p Amplitude (V)

Measurement Error

+85°C

+25°C

-40°C

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

0.0001 0.0010 0.0100 0.1000 1.0000

CH1 Vp-p Amplitude (V)

Measurement Error

+85°C

+25°C

-40°C

FIGURE 2-11: Measurement Error, Temperalure : +1251), Gain : 1. FIGURE 2-1 ' Measurement Error, Temperalure : +1251), Gain : 2. @ 200672011 Mmmcmp Technclogy Inc.

MCP3905A/05L/06A

Note: Unless otherwise specified, DVDD, AVDD = 5V; AGND, DGND = 0V; VREF = Internal, HPF = 1 (AC mode),

MCLK = 3.58 MHz.

FIGURE 2-11: Measurement Error,

Temperature = +125°C, Gain = 1.

FIGURE 2-12: Measurement Error,

Temperature = +125°C, Gain = 2.

FIGURE 2-13: Measurement Error,

Temperature = +125°C, Gain = 8.

FIGURE 2-14: Measurement Error,

Temperature = +125°C, Gain = 16.

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

0.0001 0.001 0.01 0.1 1

CH1 Vp-p Amplitude (V)

Measurement Error (%)

+25°C; PF = 1

+25°C; PF = 0.5

+125°C; PF = 0.5

+125°C; PF = 1

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

0.0001 0.001 0.01 0.1 1

CH1 Vp-p Amplitude (V)

Measurement Error (%)

+25°C; PF = 1

+25°C; PF = 0.5

+125°C; PF = 1

+125°C; PF = 0.5

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

0.0001 0.001 0.01 0.1 1

CH1 Vp-p Amplitude (V)

Measurement Error (%)

+125°C; PF = 1

+125°C; PF = 0.5

+25°C; PF = 1

+25°C; PF = 0.5

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

0.0001 0.001 0.01 0.1 1

CH1 Vp-p Amplitude (V)

Measurement Error (%)

+25°C; PF = 1

+25°C; PF = 0.5

+125°C; PF = 1

+125°C; PF = 0.5

MCP3905A/05L/06A

Note: Unless otherwise specified, DVDD, AVDD = 5V; AGND, DGND = 0V; VREF = Internal, HPF = 1 (AC mode),

MCLK = 3.58 MHz.

FIGURE 2-15: Measurement Error vs.

Input Frequency.

FIGURE 2-16: Channel 0 Offset Error

(DC Mode, HPF off), G = 1.

FIGURE 2-17: Channel 0 Offset Error

(DC Mode, HPF off), G = 8.

FIGURE 2-18: Channel 0 Offset Error

(DC Mode, HPF Off), G = 16.

FIGURE 2-19: Measurement Error vs. VDD

(G = 16).

FIGURE 2-20: Measurement Error vs. VDD,

G = 16, External VREF.

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

40 50 60 70 80

Frequency (Hz)

Measurement Error (%)

PF = 0.5

PF = 1

500

1000

1500

2000

2500

3000

-4.00E-3

-3.95E-3

-3.90E-3

-3.85E-3

-3.80E-3

-3.75E-3

-3.70E-3

-3.65E-3

-3.60E-3

-3.55E-3

-3.50E-3

-3.45E-3

Channel 0 Offset (V)

Occurance

16384 Samples

Mean = -3.76 mV

Std. Dev = 110.4 µV

500

1000

1500

2000

2500

3000

-499.6E-6

-494.1E-6

-488.6E-6

-483.1E-6

-477.6E-6

-472.6E-6

-467.1E-6

-461.6E-6

-456.1E-6

-450.6E-6

-445.6E-6

-440.1E-6

-434.6E-6

Channel 0 Offset (V)

Occurance

16384 Samples

Mean = -470.2 µV

Std. Dev = 13.8 µV

500

1000

1500

2000

2500

-251.5E-6

-249.5E-6

-248.5E-6

-246.5E-6

-243.5E-6

-240.5E-6

-237.5E-6

-234.5E-6

-231.5E-6

-229.5E-6

-226.5E-6

-223.5E-6

-220.5E-6

-217.5E-6

Channel 0 Offset (V)

Occurance

16384 Samples

Mean = - 234.7 µV

Std. dev = - 6.91 µV

-0.15

-0.1

-0.05

0.05

0.1

0.15

0.2

0.25

0.3

0.0001 0.0010 0.0100 0.1000 1.0000

CH0 Vp-p Amplitude (V)

Measurement Error

VDD=4.75V

VDD=5.0V

VDD=4.5V

VDD=5.25V

VDD=5.5V

-0.1

-0.05

0.05

0.1

0.15

0.2

0.25

0.0001 0.0010 0.0100 0.1000 1.0000

CH0 Vp-p Amplitude (V)

Measurement Error

VDD=4.5V

VDD=4.75V

VDD=5.0V

VDD=5.25V

VDD=5.5V

MCP3905A/05L/06A

Note: Unless otherwise specified, DVDD, AVDD = 5V; AGND, DGND = 0V; VREF = Internal, HPF = 1 (AC mode),

MCLK = 3.58 MHz.

FIGURE 2-21: Measurement Error

w/ External VREF

, (G = 1).

FIGURE 2-22: Measurement Error

w/ External VREF (G = 8).

FIGURE 2-23: Measurement Error

w/ External VREF (G = 16).

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.0001 0.0010 0.0100 0.1000 1.0000

CH0 Vp-p Amplitude (V)

Measurement Error

+85°C

+25°C

- 40°C

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.0000 0.0001 0.0010 0.0100 0.1000

CH1 Vp-p Amplitude (V)

Measurement Error

+85°C

+25°C

-40°C

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.0000 0.0001 0.0010 0.0100 0.1000

CH1 Vp-p Amplitude (V)

Measurement Error

+85°C +25°C

- 40°C

MCP3905A/05L/06A

NOTES:

MCP3905A/05L/06A

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

3.1 Digital VDD (DVDD)

DVDD is the power supply pin for the digital circuitry

within the MCP3905A/05L/06A devices.

This pin requires appropriate bypass capacitors and

should be maintained to 5V ±10% for specified

operation. Refer to Section 5.0 “Applications

Information”.

3.2 High-Pass Filter Input Logic Pin

(HPF)

HPF controls the state of the high-pass filter in both

input channels. A logic ‘1’ enables both filters,

removing any DC offset coming from the system or the

device. A logic ‘0’ disables both filters, allowing DC

voltages to be measured.

3.3 Analog VDD (AVDD)

AVDD is the power supply pin for the analog circuitry

within the MCP3905A/05L/06A devices.

This pin requires appropriate bypass capacitors and

should be maintained to 5V ±10% for specified

operation. Refer to Section 5.0 “Applications

Information”.

3.4 Current Channel (CH0-, CH0+)

CH0- and CH0+ are the fully differential analog voltage

input channels for the current measurement, containing

a PGA for small-signal input, such as shunt current

sensing. The linear and specified region of this channel

is dependant on the PGA gain. This corresponds to a

maximum differential voltage of ±470 mV/GAIN and

maximum absolute voltage, with respect to AGND, of

±1V. Up to ±6V can be applied to these pins without the

risk of permanent damage.

Refer to Section 1.0 “Electrical Characteristics”.

TABLE 3-1: PIN FUNCTION TABLE

Pin No. Symbol Function

1DV

DD Digital Power Supply Pin

2 HPF High-Pass Filters Control Logic Pin

3AV

DD Analog Power Supply Pin

4 NC No Connect

5 CH0+ Non-Inverting Analog Input Pin for Channel 0 (Current Channel)

6 CH0- Inverting Analog Input Pin for Channel 0 (Current Channel)

7 CH1- Inverting Analog Input Pin for Channel 1 (Voltage Channel)

8 CH1+ Non-Inverting Analog Input Pin for Channel 1 (Voltage Channel)

9MCLR

Master Clear Logic Input Pin

10 REFIN/OUT Voltage Reference Input/Output Pin

11 AGND Analog Ground Pin, Return Path for internal analog circuitry

12 F2 Frequency Control for HFOUT Logic Input Pin

13 F1 Frequency Control for FOUT0/1 Logic Input Pin

14 F0 Frequency Control for FOUT0/1 Logic Input Pin

15 G1 Gain Control Logic Input Pin

16 G0 Gain Control Logic Input Pin

17 OSC1 Oscillator Crystal Connection Pin or Clock Input Pin

18 OSC2 Oscillator Crystal Connection Pin or Clock Output Pin

19 NC No Connect

20 NEG Negative Power Logic Output Pin

21 DGND Digital Ground Pin, Return Path for Internal Digital Circuitry

22 HFOUT High-Frequency Logic Output Pin (Intended for Calibration)

23 FOUT1 Differential Mechanical Counter Logic Output Pin

24 FOUT0 Differential Mechanical Counter Logic Output Pin

MCP3905A/05L/06A

3.5 Voltage Channel (CH1-,CH1+)

CH1- and CH1+ are the fully differential analog voltage

input channels for voltage measurement. The linear

and specified region of these channels have a

maximum differential voltage of ±660 mV and a

maximum absolute voltage of ±1V, with respect to

AGND. Up to ±6V can be applied to these pins without

the risk of permanent damage.

Refer to Section 1.0 “Electrical Characteristics”.

3.6 Master Clear (MCLR)

MCLR controls the reset for both delta-sigma ADCs, all

digital registers, the SINC filters for each channel and

all accumulators post multiplier. A logic ‘0’ resets all

registers and holds both ADCs in a Reset condition.

The charge stored in both ADCs is flushed and their

output is maintained to 0x0000h. The only block

consuming power on the digital power supply during

Reset is the oscillator circuit.

3.7 Reference (REFIN/OUT)

REFIN/OUT is the output for the internal 2.4V

reference. This reference has a typical temperature

coefficient of 15 ppm/°C and a tolerance of ±2%. In

addition, an external reference can also be used by

applying voltage to this pin within the specified range.

This pin requires appropriate bypass capacitors to

AGND, even when using the internal reference only.

Refer to Section 5.0 “Applications Information”.

3.8 Analog Ground (AGND)

AGND is the ground connection to internal analog

circuitry (ADCs, PGA, band gap reference, POR). To

ensure accuracy and noise cancellation, this pin must

be connected to the same ground as DGND, preferably

with a star connection. If an analog ground plane is

available, it is recommended that this device be tied to

this plane of the PCB. This plane should also reference

all other analog circuitry in the system.

3.9 Frequency Control Logic Pins

(F2, F1, F0)

F2, F1 and F0 select the high-frequency output and

low-frequency output pin ranges by changing the

value of the constants FC and HFC used in the device

transfer function. FC and HFC are the frequency

constants that define the period of the output pulses

for the device.

3.10 Gain Control Logic Pins (G1, G0)

G1 and G0 select the PGA gain on Channel 0 from

three different values: 1, 8 and 16.

3.11 Oscillator (OSC1, OSC2)

OSC1 and OSC2 provide the master clock for the

device. A resonant crystal or clock source with a similar

sinusoidal waveform must be placed across these pins

to ensure proper operation. The typical clock frequency

specified is 3.579545 MHz. However, the clock

frequency can be with the range of 1 MHz to 4 MHz

without disturbing measurement error. Appropriate

load capacitance should be connected to these pins for

proper operation.

A full-swing, single-ended clock source may be

connected to OSC1 with proper resistors in series to

ensure no ringing of the clock source due to fast

transient edges.

3.12 Negative Power Output Logic Pin

(NEG)

NEG detects the phase difference between the two

channels and will go to a logic ‘1’ state when the phase

difference is greater than 90° (i.e., when the measured

real power is negative). The output state is synchro-

nous with the rising-edge of HFOUT and maintains the

logic ‘1’ until the real power becomes positive again

and HFOUT shows a pulse.

3.13 Ground Connection (DGND)

DGND is the ground connection to internal digital

circuitry (SINC filters, multiplier, HPF, LPF, digital-to-

frequency converter and oscillator). To ensure

accuracy and noise cancellation, DGND must be

connected to the same ground as AGND, preferably

with a star connection. If a digital ground plane is

available, it is recommended that this device be tied to

this plane of the Printed Circuit Board (PCB). This

plane should also reference all other digital circuitry in

the system.

3.14 High-Frequency Output (HFOUT)

HFOUT is the high-frequency output of the device and

supplies the instantaneous real-power information. The

output is a periodic pulse output, with its period

proportional to the measured real power, and to the

HFC constant defined by F0, F1 and F2 pin logic states.

This output is the preferred output for calibration due to

faster output frequencies, giving smaller calibration

times. Since this output gives instantaneous real

power, the 2ω ripple on the output should be noted.

However, the average period will show minimal drift.

3.15 Frequency Output (FOUT0, FOUT1)

FOUT0 and FOUT1 are the frequency outputs of the

device that supply the average real-power information.

The outputs are periodic pulse outputs, with its period

proportional to the measured real power, and to the Fc

constant, defined by F0 and F1 pin logic states. These

pins include high-output drive capability for direct use

of electromechanical counters and 2-phase stepper

motors. Since this output supplies average real power,

any 2ω ripple on the output pulse period is minimal.

MCP3905A/05L/06A

4.0 DEVICE OVERVIEW

The MCP3905A/05L/06A devices are energy metering

ICs that supply a frequency output proportional to

active (real) power, and higher frequency output

proportional to the instantaneous power for meter

calibration. Both channels use 16-bit, second-order,

delta-sigma ADCs that oversample the input at a

frequency equal to MCLK/4, allowing for wide dynamic

range input signals. A Programmable Gain Amplifier

(PGA) increases the usable range on the current input

channel (Channel 0). The calculation of the active

power, and the filtering associated with this calculation

is performed in the digital domain, ensuring better

stability and drift performance. Figure 4-1 represents

the simplified block diagram of the

MCP3905A/05L/06A, detailing its main signal

processing blocks.

Two digital high-pass filters cancel the system offset on

both channels such that the real-power calculation

does not include any circuit or system offset. After

being high-pass filtered, the voltage and current signals

are multiplied to give the instantaneous power signal.

This signal does not contain the DC offset components,

such that the averaging technique can be efficiently

used to give the desired active-power output.

The instantaneous power signal contains the real-

power information; it is the DC component of the

instantaneous power. The averaging technique can be

used with both sinusoidal and non-sinusoidal

waveforms, as well as for all power factors. The

instantaneous power is thus low-pass filtered in order

to produce the instantaneous real-power signal.

A digital-to-frequency converter accumulates the

instantaneous active real power information to produce

output pulses with a frequency proportional to the

average real power. The low-frequency pulses present

at the FOUT0 and FOUT1 outputs are designed to drive

electromechanical counters and two-phase stepper

motors displaying the real-power energy consumed.

Each pulse corresponds to a fixed quantity of real

energy, selected by the F2, F1 and F0 logic settings.

The HFOUT output has a higher frequency setting and

less integration period such that it can represent the

instantaneous real-power signal. Due to the shorter

accumulation time, it enables the user to proceed to

faster calibration under steady load conditions (see

Section 4.7 “FOUT0/1 and HFOUT Output

Frequencies”).

FIGURE 4-1: Simplified MCP3905A/05L/06A Block Diagram with Frequency Contents.

HPF

...1010..

DTF

–

ADC

–

PGA

LPF

HPF

CH0+

CH0-

CH1+

CH1-

ADC

FOUT0

FOUT1

HFOUT

0 0

MCP3905

Input Signal with

System Offset and

Line Frequency

ADC Output Code

Contains System

and ADC Offset

DC Offset

Removed by HPF

Instantaneous

Power

Instantaneous

Real Power

0 00

Frequency

Content

ANALOG DIGITAL

MCP390X

MCP3905A/05L/06A

4.1 Analog Inputs

The MCP3905A/05L/06A analog inputs can be

connected directly to the current and voltage

transducers (such as shunts or current transformers).

Each input pin is protected by specialized ESD

structures that are certified to pass 5 kV HBM and

500V MM contact charge. These structures also allow

up to ±6V continuous voltage to be present at their

inputs without the risk of permanent damage.

Both channels have fully differential voltage inputs for

better noise performance. The absolute voltage at each

pin relative to AGND should be maintained in the ±1V

range during operation in order to ensure the

measurement error performance. The common-mode

signals should be adapted to respect both the previous

conditions and the differential input voltage range. For

best performance, the common-mode signals should

be referenced to AGND.

The current channel comprises a PGA on the front-end

to allow for smaller signals to be measured without

additional signal conditioning. The maximum differen-

tial voltage specified on Channel 0 is equal to

±470 mV/Gain (see Table 4-1). The maximum peak

voltage specified on Channel 1 is equal to ±660 mV.

4.2 16-Bit Delta-Sigma A/D Converters

The ADCs used in the MCP3905A/05L/06A for both

current and voltage channel measurements are delta-

sigma ADCs. They comprise a second-order, delta-

sigma modulator using a multi-bit DAC and a third-

order SINC filter. The delta-sigma architecture is very

appropriate for the applications targeted by the

MCP3905A/05L/06A because it is a waveform-oriented

converter architecture that can offer both high linearity

and low distortion performance throughout a wide input

dynamic range. It also creates minimal requirements

for the anti-aliasing filter design. The multi-bit

architecture used in the ADC minimizes quantization

noise at the output of the converters without disturbing

the linearity.

Both ADCs have a 16-bit resolution, allowing wide input

dynamic range sensing. The oversampling ratio of both

converters is 64. Both converters are continuously

converting during normal operation. When the MCLR

pin is low, both converters will be in Reset and output

code 0x0000h. If the voltage at the inputs of the ADC is

larger than the specified range, the linearity is no longer

specified. However, the converters will continue to

produce output codes until their saturation point is

reached. The DC saturation point is around 700 mV for

Channel 0 and 1V for Channel 1, using internal voltage

reference.

The clocking signals for the ADCs are equally

distributed between the two channels in order to

minimize phase delays to less than 1 MCLK period

(see Section 3.2 “High-Pass Filter Input Logic Pin

(HPF)”). The SINC filter’s main notch is positioned at

MCLK/256 (14 kHz with MCLK = 3.58 MHz), allowing

the user to be able to measure wide harmonic content

on either channel. The magnitude response of the

SINC filter is shown in Figure 4-2.

FIGURE 4-2: SINC Filter Magnitude

Response (MCLK = 3.58 MHz).

TABLE 4-1: MCP3905A/MCP3905L GAIN

SELECTIONS

G1 G0 CH0 Gain Maximum

CH0 Voltage

00 1±470mV

01 2±235mV

10 8±60mV

11 16 ±30 mV

TABLE 4-2: MCP3906A GAIN

SELECTIONS

G1 G0 CH0 Gain Maximum

CH0 Voltage

00 1±470mV

01 32 ±15 mV

10 8±60mV

11 16 ±30 mV

-120

-100

-80

-60

-40

-20

0 5 10 15 20 25 30

Frequency (kHz)

Normal Mode Rejection (dB)

MCP3905A/05L/06A

4.3 Ultra-Low Drift VREF

The MCP3905A/05L/06A devices contain an internal

voltage reference source specially designed to mini-

mize drift over temperature. This internal VREF supplies

reference voltage to both current and voltage channel

ADCs. The typical value of this voltage reference is

2.4V ±100 mV. The internal reference has a very low

typical temperature coefficient of ±15 ppm/°C, allowing

the output frequencies to have minimal variation with

respect to temperature since they are proportional to

(1/VREF)².

The output pin for the voltage reference is REFIN/OUT.

Appropriate bypass capacitors must be connected to

the REFIN/OUT pin for proper operation (see

Section 5.0 “Applications Information”). The

voltage reference source impedance is typically 4 kΩ,

which enables this voltage reference to be overdriven

by an external voltage reference source.

If an external voltage reference source is connected to

the REFIN/OUT pin, the external voltage will be used

as the reference for both current and voltage channel

ADCs. The voltage across the source resistor will then

be the difference between the internal and external

voltage. The allowed input range for the external

voltage source goes from 2.2V to 2.6V for accurate

measurement error. A VREF value outside of this range

will cause additional heating and power consumption

due to the source resistor, which might affect measure-

ment error.

4.4 Power-On Reset (POR)

The MCP3905A/05L/06A devices contain an internal

POR circuit that monitors analog supply voltage AVDD

during operation. This circuit ensures correct device

startup at system power-up and system power-down

events. The POR circuit has built-in hysteresis and a

timer to give a high degree of immunity to potential

ripple and noise on the power supplies, allowing proper

settling of the power supply during power-up. A 0.1 µF

decoupling capacitor should be mounted as close as

possible to the AVDD pin, providing additional transient

immunity (see Section 5.0 “Applications

Information”).

The threshold voltage is typically set at 4V, with a

tolerance of about ±5%. If the supply voltage falls below

this threshold, the MCP3905A/05L/06A devices will be

held in a Reset condition (equivalent to applying logic

‘0’ on the MCLR pin). The typical hysteresis value is

approximately 200 mV in order to prevent glitches on

the power supply.

Once a power-up event has occurred, an internal timer

prevents the part from outputting any pulse for

approximately 1s (with MCLK = 3.58 MHz), thereby

preventing potential metastability due to intermittent

resets caused by an unsettled regulated power supply.

Figure 4-3 illustrates the different conditions for a

power-up and a power-down event in the typical

conditions.

FIGURE 4-3: Power-on Reset Operation.

4.5 High-Pass Filters and Multiplier

The active real-power value is extracted from the DC

instantaneous power. Therefore, any DC offset

component present on Channel 0 and Channel 1

affects the DC component of the instantaneous power

and will cause the real-power calculation to be

erroneous. In order to remove DC offset components

from the instantaneous power signal, a high-pass filter

has been introduced on each channel. Since the high-

pass filtering introduces phase delay, identical high-

pass filters are implemented on both channels. The

filters are clocked by the same digital signal, ensuring

a phase difference between the two channels of less

than one MCLK period. Under typical conditions

(MCLK = 3.58 MHz), this phase difference is less than

0.005°, with a line frequency of 50 Hz. The cut-off

frequency of the filter (4.45 Hz) has been chosen to

induce minimal gain error at typical line frequencies,

allowing sufficient settling time for the desired

applications. The two high-pass filters can be disabled

by applying logic ‘0’ to the HPF pin.

FIGURE 4-4: HPF Magnitude Response

(MCLK = 3.58 MHz).

AVDD

4.2V

DEVICE

MODE

RESET PROPER

OPERATION RESET

PULSE

OUT

Time

-40

-35

-30

-25

-20

-15

-10

-5

0.1 1 10 100 1000

Frequency (Hz)

Normal Mode Rejection (dB)

MCP3905A/05L/06A

The multiplier output gives the product of the two high-

pass filtered channels, corresponding to instantaneous

real power. Multiplying two sine wave signals by the

same ω frequency gives a DC component and a 2ω

component. The instantaneous power signal contains

the real power of its DC component, while also contain-

ing 2ω components coming from the line frequency

multiplication. These 2ω components come for the line

frequency (and its harmonics) and must be removed in

order to extract the real-power information. This is

accomplished using the low-pass filter and DTF

converter.

4.6 Low-Pass Filter and DTF

Converter

The MCP3905A/05L/06A low-pass filter is a first-order

IIR filter that extracts the active real-power information

(DC component) from the instantaneous power signal.

The magnitude response of this filter is detailed in

Figure 4-5. Due to the fact that the instantaneous power

signal has harmonic content (coming from the 2ω

components of the inputs), and since the filter is not

ideal, there will be some ripple at the output of the low-

pass filter at the harmonics of the line frequency.

The cut-off frequency of the filter (8.9 Hz) has been

chosen to have sufficient rejection for commonly-used

line frequencies (50 Hz and 60 Hz). With a standard

input clock (MCLK = 3.58 MHz) and a 50 Hz line

frequency, the rejection of the 2ω component (100 Hz)

will be more than 20 dB. This equates to a 2ω

component containing 10 times less power than the

main DC component (i.e., the average active real

power).

FIGURE 4-5: LPF Magnitude Response

(MCLK = 3.58 MHz).

The output of the low-pass filter is accumulated in the

digital-to-frequency converter. This accumulation is

compared to a different digital threshold for FOUT0/1

and HFOUT, representing a quantity of real energy mea-

sured by the part. Every time the digital threshold on

FOUT0/1 or HFOUT is crossed, the part will output a

pulse (See Section 4.7 “FOUT0/1 and HFOUT Output

Frequencies”).

The equivalent quantity of real energy required to

output a pulse is much larger for the FOUT0/1 outputs

than the HFOUT. This is such that the integration period

for the FOUT0/1 outputs is much larger. This larger

integration period acts as another low-pass filter so that

the output ripple due to the 2ω components is minimal.

However, these components are not totally removed,

since realized low-pass filters are never ideal. This will

create a small jitter in the output frequency. Averaging

the output pulses with a counter or a MCU in the

application will then remove the small sinusoidal

content of the output frequency and filter out the

remaining 2ω ripple.

HFOUT is intended to be used for calibration purposes

due to its instantaneous power content. The shorter

integration period of HFOUT demands that the 2ω

component be given more attention. Since a sinusoidal

signal average is zero, averaging the HFOUT signal in

steady-state conditions will give the proper real energy

value.

4.7 FOUT0/1 and HFOUT Output

Frequencies

The thresholds for the accumulated energy are

different for FOUT0/1 and HFOUT (i.e., they have

different transfer functions). The FOUT0/1 allowed

output frequencies are quite low in order to allow

superior integration time (see Section 4.6 “Low-Pass

Filter and DTF Converter”). The FOUT0/1 output

frequency can be calculated with the following

equation:

EQUATION 4-1: FOUT FREQUENCY

OUTPUT EQUATION

For a given DC input V, the DC and RMS values are

equivalent. For a given AC input signal with peak-to-

peak amplitude of V, the equivalent RMS value is

V/sqrt(2), assuming purely sinusoidal signals. Note

that since the real power is the product of two RMS

inputs, the output frequencies of AC signals are half of

the DC inputs ones, again assuming purely sinusoidal

AC signals. The constant FC depends on the FOUT0

and FOUT1 digital settings. Table 4-3 shows FOUT0/1

output frequencies for the different logic settings.

-40

-35

-30

-25

-20

-15

-10

-5

0.1 1 10 100 1000

Frequency (Hz)

Normal Mode Rejection (dB)

FOUT Hz() 8.06 V0

×V1

×GF

××

VREF

()

-----------------------------------------------------------=

Where:

V0 is the RMS differential voltage on Channel 0

V1 is the RMS differential voltage on Channel 1

G is the PGA gain on Channel 0 (current channel)

FC is the frequency constant selected

VREF is the voltage reference

MCP3905A/05L/06A

The high-frequency output HFOUT has lower

integration times and, thus, higher frequencies. The

output frequency value can be calculated with the

following equation:

EQUATION 4-2: HFOUT FREQUENCY

OUTPUT EQUATION

The constant HFC depends on the FOUT0 and FOUT1

digital settings with the Table 4-4.

The detailed timings of the output pulses are described

in the Timing Characteristics table (see Section 1.0

“Electrical Characteristics” and Figure 1-1).

4.7.1 MINIMAL OUTPUT FREQUENCY

FOR

NO-LOAD THRESHOLD

The MCP3905A/05L/06A devices also include, on

each output frequency, a no-load threshold circuit that

will eliminate any creep effects in the meter. The

outputs will not show any pulse if the output frequency

falls below the no-load threshold. The minimum output

frequency on FOUT0/1 and HFOUT is equal to 0.0015%

of the maximum output frequency (respectively FC and

HFC) for each of the F2, F1 and F0 selections (see

Table 4-3 and Table 4-4); except when F2, F1,

F0 = 011. In this last configuration, the no-load

threshold feature is disabled. The selection of FC will

determine the start-up current load. In order to respect

the IEC standards requirements, the meter will have to

be designed to allow start-up currents compatible with

the standards by choosing the FC value matching

these requirements. For additional applications

information on no-load threshold, startup current and

other meter design points, refer to AN994, "IEC

Compliant Active Energy Meter Design Using The

MCP3905/6”, (DS00994).

HFOUT Hz() 8.06 V0

×V1G×× HFC

VREF

()

----------------------------------------------------------------=

Where:

V0 is the RMS differential voltage on channel 0

V1 is the RMS differential voltage on channel 1

G is the PGA gain on channel 0 (current channel)

HFC is the frequency constant selected

VREF is the voltage reference

TABLE 4-3: MCP3905L OUTPUT FREQUENCY SETTINGS

F2 F1 F0 HFCHFC (Hz) HFC (Hz),

MCLK=3.58 MHz

HFOUT (Hz),

w/ full scale

AC inputs FC (Hz) FC (Hz),

MCLK=3.58 MHz

00064XFCMCLK/215 109.25 23.71 MCLK/221 1.71

00132XFCMCLK/215 109.25 23.71 MCLK/220 3.41

01016XFCMCLK/215 109.25 23.71 MCLK/219 6.83

0112048XFCMCLK/2727968.75 6070.12 MCLK/218 13.66

100 8XFCMCLK/216 54.62 11.85 MCLK/219 6.83

10164XFCMCLK/216 54.62 11.85 MCLK/222 0.85

11032XFCMCLK/216 54.62 11.85 MCLK/221 1.71

11116XFCMCLK/216 54.62 11.85 MCLK/220 3.41

TABLE 4-4: MCP3905A/06A OUTPUT FREQUENCY SETTINGS

F2 F1 F0 HFCHFC (Hz) HFC (Hz),

MCLK=3.58 MHz

HFOUT (Hz),

w/ full scale

AC inputs FC (Hz) FC (Hz),

MCLK=3.58 MHz

00064XFCMCLK/215 109.25 23.71 MCLK/221 1.71

00132XFCMCLK/215 109.25 23.71 MCLK/220 3.41

01016XFCMCLK/215 109.25 23.71 MCLK/219 6.83

0112048XFCMCLK/2727968.75 6070.12 MCLK/218 13.66

100128XFCMCLK/214 219.51 47.42 MCLK/221 1.71

10164XFCMCLK/214 219.51 47.42 MCLK/220 3.41

11032XFCMCLK/214 219.51 47.42 MCLK/219 6.83

11116XFCMCLK/214 219.51 47.42 MCLK/218 13.66

MCP3905A/05L/06A

NOTES:

MCP3905A/05L/06A

5.0 APPLICATIONS INFORMATION

5.1 Meter Design using the

MCP3905A/05L/06A

For all applications information, refer to AN994, "IEC

Compliant Active Energy Meter Design Using The

MCP3905/6” (DS00994). This application note

includes all required energy meter design information,

including the following:

• Meter rating and current sense choices

• Shunt design

• PGA selection

• F2, F1, F0 selection

• Meter calibration

• Anti-aliasing filter design

• Compensation for parasitic shunt inductance

• EMC design

• Power supply design

• No-Load threshold

• Start-up current

• Accuracy Testing Results from MCP3905-based

meter

• EMC Testing Results from MCP3905-based meter

MCP3905A/05L/06A

NOTES:

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MCP3905A/05L/06A

6.0 PACKAGING INFORMATION

6.1 Package Marking Information

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

XXXXXXXXXXX

YYWWNNN

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6WDQGRII $  ± ±

2YHUDOO:LGWK (   

0ROGHG3DFNDJH:LGWK (   

2YHUDOO/HQJWK '   

)RRW/HQJWK /   

)RRWSULQW / 5()

/HDG7KLFNQHVV F  ± 

)RRW$QJOH   

/HDG:LGWK E  ± 

NOTE 1

A1 L1 L

A2 φ

0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

24 Lead Plaslic Shrink Small Outline (SS) - 5.30 mm Body [SSOP] UHUHHHHHH \— SlLK SCREEN c o J , a A L x. E RECOMMENDED LAND PATTERN Unils MILLIMETERS Dimenslon leils MlN l NOM l MAX Comacl Pilch E 0.55 ass somael Pad Spacing c 7.20 Conlacl Pad Widlh (x24) x1 0.45 Conlact Pad Lengm (x24) Y1 «75 Dlslance Between Pads G 0.20 Notes 1. Dimenslonlrlg and toleranclrlg oer ASME Y14.5M BSC: 83le Dlmenslon. Theoretically exacl value shown without tolerances. Mlcrochlp Technology Drawing No 004-2132A

MCP3905A/05L/06A

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

MCP3905A/05L/06A

NOTES:

MCP3905A/05L/06A

APPENDIX A: REVISION HISTORY

Revision B (July 2011)

The following is the list of modifications:

1. Added Extended Temperature item to the

Features list.

2. Updated Section 2.0, Typical Performance

Curves with new extended temperature

graphics (Figures 2-11 to 2-14).

3. Updated Section 6.0, Packaging Information to

show the Land Pattern drawings.

4. Updated the Product Identification System

section with the Extended Temperature

characteristic and examples.

Revision A (September 2006)

• Original Release of this Document.

MCP3905A/05L/06A

NOTES:

PART NO. /XX

MCP3905A/05L/06A

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Device: MCP3905A: Energy Metering IC

MCP3905AT: Energy Metering IC (Tape and Reel)

MCP3905L: Energy Metering IC

MCP3905LT: Energy Metering IC (Tape and Reel)

MCP3906A: Energy Metering IC

MCP3906AT: Energy Metering IC (Tape and Reel)

Temperature Range: E = -40°C to +125°C

I = -40°C to +85°C

Package: SS = Plastic Shrink Small Outline (209 mil Body), 24-lead

PART NO. –X /XX

PackageTemperature

Range

Device

Examples:

a) MCP3905A-E/SS: Extended Temperature,

24LD SSOP.

b) MCP3905AT-E/SS: Tape and Reel,

Extended Temperature,

24LD SSOP.

c) MCP3905A-I/SS: Industrial Temperature,

24LD SSOP.

d) MCP3905AT-I/SS: Tape and Reel,

Industrial Temperature,

24LD SSOP

a) MCP3905L-E/SS: Extended Temperature,

24LD SSOP.

b) MCP3905LT-E/SS: Tape and Reel,

Extended Temperature,

24LD SSOP.

c) MCP3905L-I/SS: Industrial Temperature,

24LD SSOP.

d) MCP3905LT-I/SS: Tape and Reel,

Industrial Temperature,

24LD SSOP.

a) MCP3906A-E/SS: Extended Temperature,

24LD SSOP.

b) MCP3906AT-E/SS: Tape and Reel,

Extended Temperature,

24LD SSOP.

c) MCP3906A-I/SS: Industrial Temperature,

24LD SSOP.

d) MCP3906AT-I/SS: Tape and Reel,

Industrial Temperature,

24LD SSOP.

MCP3905A/05L/06A

NOTES:

QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV = ISO/TS 169492009:

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

PIC32 logo, rfPIC and UNI/O are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, chipKIT,

chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,

dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,

FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,

Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,

MPLINK, mTouch, Omniscient Code Generation, PICC,

PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,

rfLAB, Select Mode, Total Endurance, TSHARC,

UniWinDriver, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 978-1-61341-410-1

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

6‘ ‘MICRDCHIP

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05/02/11

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