MCP3221 Datasheet by Microchip Technology

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MICRQICHIP MCP3221 C :I I: C :I
2002-2017 Microchip Technology Inc. DS20001732E-page 1
MCP3221
Features
• 12-bit Resolution
• ±1 LSB DNL, ±2 LSB INL maximum
• 250 µA Max Conversion Current
• 5 nA Typical Standby Current, 1 µA maximum
•I
2C Compatible Serial Interface
- 100 kHz I2C Standard mode
- 400 kHz I2C Fast mode
• Up to 8 Devices on a Single 2-wire Bus
• 22.3 ksps in I2C Fast mode
• Single-Ended Analog Input Channel
• On-Chip Sample and Hold
• On-Chip Conversion Clock
• Single-Supply Specified Operation: 2.7V to 5.5V
• Temperature Range:
- Extended: -40°C to +125°C
• Small SOT-23-5 package
Applications
• Data Logging
• Multi-Zone Monitoring
• Handheld Portable Applications
• Battery-Powered Test Equipment
• Remote or Isolated Data Acquisition
General Description
Microchip’s MCP3221 is a successive approximation
A/D converter (ADC) with a 12-bit resolution. Available
in the SOT-23 package, this device provides one sin-
gle-ended input with very low-power consumption.
Based on an advanced CMOS technology, the
MCP3221 provides a low maximum conversion current
and standby current of 250 µA and 1 µA, respectively.
Low-current consumption, combined with the small
SOT-23 package, make this device ideal for battery-
powered and remote data acquisition applications.
Communication to the MCP3221 is performed using a
2-wire, I2C compatible interface. Standard (100 kHz)
and Fast (400 kHz) I2C modes are available with the
device. An on-chip conversion clock enables
independent timing for the I2C and conversion clocks.
The device is also addressable, allowing up to eight
devices on a single 2-wire bus.
The MCP3221 runs on a single-supply voltage that
operates over a broad range of 2.7V to 5.5V. This
device also provides excellent linearity of ±1 LSB
differential nonlinearity (DNL) and ±2 LSB integral
nonlinearity (INL), maximum.
Package Type
5-Pin SOT-23
SCL
AIN
MCP3221
1
2
3
5
SDA
VSS
VDD
4
Low-Power 12-Bit A/D Converter with I2C Interface
\\\\\\\\\\\
MCP3221
DS20001732E-page 2 2002-2017 Microchip Technology Inc.
Functional Block Diagram
Comparator
Sample
and
Hold
12-bit SAR
DAC
I2C Interface
AIN
VSS
VDD
SCL SDA
Clock
Control Logic
–
+
2002-2017 Microchip Technology Inc. DS20001732E-page 3
MCP3221
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
VDD...........................................................................................................................................................................+7.0V
Analog input pin w.r.t. VSS ..................................................................................................................-0.6V to VDD +0.6V
SDA and SCL pins w.r.t. VSS...............................................................................................................-0.6V to VDD +1.0V
Storage Temperature ............................................................................................................................. -65°C to +150°C
Ambient Temperature with power applied ...............................................................................................-65°C to +125°C
Maximum Junction Temperature ........................................................................................................................... +150°C
ESD protection on all pins (HBM) .......................................................................................................................... ≥4kV
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5.0V, VSS = GND, RPU = 2 k
TA = -40°C to +85°C, I2C Fast Mode Timing: fSCL = 400 kHz (Note 3).
Parameter Sym. Min. Typ. Max. Units Conditions
DC Accuracy
Resolution — 12 bits
Integral Nonlinearity INL — ±0.75 ±2 LSB
Differential Nonlinearity DNL — ±0.5 ±1 LSB No missing codes
Offset Error — — ±0.75 ±2 LSB
Gain Error — — -1 ±3 LSB
Dynamic Performance
Total Harmonic Distortion THD — -82 — dB VIN = 0.1V to 4.9V @ 1 kHz
Signal-to-Noise and Distortion SINAD — 72 — dB VIN = 0.1V to 4.9V @ 1 kHz
Spurious Free Dynamic Range SFDR — 86 — dB VIN = 0.1V to 4.9V @ 1 kHz
Analog Input
Input Voltage Range — VSS-0.3 — VDD+0.3 V 2.7V VDD 5.5V
Leakage Current — -1 — +1 µA
SDA/SCL (open-drain output)
Data Coding Format — Straight Binary —
High-Level Input Voltage VIH 0.7 VDD ——V
Low-Level Input Voltage VIL — — 0.3 VDD V
Low-Level Output Voltage VOL ——0.4VI
OL = 3 mA, RPU = 1.53 k
Hysteresis of Schmitt Trigger Inputs VHYST —0.05V
DD —Vf
SCL = 400 kHz only
Input Leakage Current ILI -1 — +1 µA VIN = 0.1 VDD and 0.9 VDD
Output Leakage Current ILO -1 — +1 µA VOUT = 0.1 VSS and
0.9 VDD
Note 1: Sample time is the time between conversions once the address byte has been sent to the converter. Refer
to Figure 5-6.
2: This parameter is periodically sampled and not 100% tested.
3: RPU = Pull-up resistor on SDA and SCL.
4: SDA and SCL = VSS to VDD at 400 kHz.
5: tACQ and tCONV are dependent on internal oscillator timing. See Figure 5-5 and Figure 5-6 in relation to
SCL.
MCP3221
DS20001732E-page 4 2002-2017 Microchip Technology Inc.
TEMPERATURE SPECIFICATIONS
Pin Capacitance
(all inputs/outputs)
CIN,
COUT
— — 10 pF TA = 25°C, f = 1 MHz;
(Note 2)
Bus Capacitance CB— — 400 pF SDA drive low, 0.4V
Power Requirements
Operating Voltage VDD 2.7 — 5.5 V
Conversion Current IDD —175250µA
Standby Current IDDS —0.005 1 µASDA, SCL = V
DD
Active Bus Current IDDA ——120µANote 4
Conversion Rate
Conversion Time tCONV —8.96—µsNote 5
Analog Input Acquisition Time tACQ —1.12—µsNote 5
Sample Rate fSAMP — — 22.3 ksps fSCL = 400 kHz (Note 1)
Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5.0V, VSS = GND.
Parameter Sym. Min. Typ. Max. Units Conditions
Temperature Ranges
Operating Temperature Range TA-40 — +125 °C
Extended Temperature Range TA-40 — +125 °C
Storage Temperature Range TA-65 — +150 °C
Thermal Package Resistances
Thermal Resistance, SOT-23 JA —256 —°C/W
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5.0V, VSS = GND, RPU = 2 k
TA = -40°C to +85°C, I2C Fast Mode Timing: fSCL = 400 kHz (Note 3).
Parameter Sym. Min. Typ. Max. Units Conditions
Note 1: Sample time is the time between conversions once the address byte has been sent to the converter. Refer
to Figure 5-6.
2: This parameter is periodically sampled and not 100% tested.
3: RPU = Pull-up resistor on SDA and SCL.
4: SDA and SCL = VSS to VDD at 400 kHz.
5: tACQ and tCONV are dependent on internal oscillator timing. See Figure 5-5 and Figure 5-6 in relation to
SCL.
2002-2017 Microchip Technology Inc. DS20001732E-page 5
MCP3221
TIMING SPECIFICATIONS
FIGURE 1-1: Standard and Fast Mode Bus Timing Data.
Electrical Characteristics: All parameters apply at VDD = 2.7V - 5.5V, VSS = GND, TA = -40°C to +85°C.
Parameter Sym. Min. Typ. Max. Units Conditions
I2C Standard Mode
Clock Frequency fSCL 0 — 100 kHz
Clock High Time THIGH 4000 — — ns
Clock Low Time TLOW 4700 — — ns
SDA and SCL Rise Time TR— — 1000 ns From VIL to VIH (Note 1)
SDA and SCL Fall Time TF— — 300 ns From VIL to VIH (Note 1)
Start Condition Hold Time THD:STA 4000 — — ns
Start Condition Setup Time TSU:STA 4700 — — ns
Data Input Setup Time TSU:DAT 250 — — ns
Stop Condition Setup Time TSU:STO 4000 — — ns
Stop Condition Hold time THD:STD 4000 — — ns
Output Valid from Clock TAA — — 3500 ns
Bus Free Time TBUF 4700 — — ns Note 2
Input Filter Spike Suppression TSP — — 50 ns SDA and SCL pins (Note 1)
I2C Fast Mode
Clock Frequency FSCL 0 — 400 kHz
Clock High Time THIGH 600 — — ns
Clock Low Time TLOW 1300 — — ns
SDA and SCL Rise Time TR20 + 0.1CB— 300 ns From VIL to VIH (Note 1)
SDA and SCL Fall Time TF20 + 0.1CB— 300 ns From VIL to VIH (Note 1)
Start Condition Hold Time THD:STA 600 — — ns
Start Condition Setup Time TSU:STA 600 — — ns
Data Input Hold Time THD:DAT 0—0.9ms
Data Input Setup Time TSU:DAT 100 — — ns
Stop Condition Setup Time TSU:STO 600 — — ns
Stop Condition Hold Time THD:STD 600 — — ns
Output Valid from Clock TAA — — 900 ns
Bus Free Time TBUF 1300 — — ns Note 2
Input Filter Spike Suppression TSP — — 50 ns SDA and SCL pins (Note 1)
Note 1: This parameter is periodically sampled and not 100% tested.
2: Time the bus must be free before a new transmission can start.
TF
THIGH VHYS TR
TSU:STA
TSP
THD:STA
TLOW THD:DAT TSU:DAT TSU:STO
TBUF
TAA
SCL
SDA
IN
SDA
OUT
MCP3221
DS20001732E-page 6 2002-2017 Microchip Technology Inc.
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion
Mode (fSAMP = 22.3 ksps), TA = +25°C.
FIGURE 2-1: INL vs. Clock Rate.
FIGURE 2-2: INL vs. VDD - I2C Standard
Mode (fSCL = 100 kHz).
FIGURE 2-3: INL vs. Code
(Representative Part).
FIGURE 2-4: INL vs. Clock Rate
(VDD =2.7V).
FIGURE 2-5: INL vs. VDD - I2C Fast Mode
(fSCL = 400 kHz).
FIGURE 2-6: INL vs. Code
(Representative Part, VDD = 2.7V).
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0 100 200 300 400
I2C Bus Rate (kHz)
INL (LSB)
Positive INL
Negative INL
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
2.533.544.555.5
VDD (V)
INL (LSB)
Positive INL
Negative INL
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
0 1024 2048 3072 4096
Digital Code
INL (LSB)
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0 100 200 300 400
I2C Bus Rate (kHz)
INL (LSB)
Positive INL
Negative INL
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
2.533.544.555.5
VDD (V)
INL (LSB)
Positive INL
Negative INL
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
0 1024 2048 3072 4096
Digital Code
INL (LSB)
2002-2017 Microchip Technology Inc. DS20001732E-page 7
MCP3221
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion
Mode (fSAMP = 22.3 ksps), TA = +25°C.
FIGURE 2-7: INL vs. Temperature.
FIGURE 2-8: DNL vs. Clock Rate.
FIGURE 2-9: DNL vs. VDD - I2C Standard
Mode (fSCL = 100 kHz).
FIGURE 2-10: INL vs. Temperature
(VDD =2.7V).
FIGURE 2-11: DNL vs. Clock Rate
(VDD =2.7V).
FIGURE 2-12: DNL vs. VDD - I2C Fast
Mode (fSCL = 400 kHz).
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
-50 -25 0 25 50 75 100 125
Temperature (°C)
INL (LSB)
Positive INL
Negative INL
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0 100 200 300 400
I2C Bus Rate (kHz)
DNL (LSB)
Positive DNL
Negative DNL
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
2.5 3 3.5 4 4.5 5 5.5
VDD (V)
DNL (LSB)
Positive DNL
Negative DNL
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
-50 -25 0 25 50 75 100 125
Temperature (°C)
INL (LSB)
Negative INL
Positive INL
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0 100 200 300 400
I2C Bus Rate (kHz)
DNL (LSB)
Negative DNL
Positive DNL
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
2.533.544.555.5
VDD (V)
DNL (LSB)
Positive DNL
Negative DNL
1m: m1)
MCP3221
DS20001732E-page 8 2002-2017 Microchip Technology Inc.
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion
Mode (fSAMP = 22.3 ksps), TA = +25°C.
FIGURE 2-13: DNL vs. Code
(Representative Part).
FIGURE 2-14: DNL vs. Temperature.
FIGURE 2-15: Gain Error vs. VDD.
FIGURE 2-16: DNL vs. Code
(Representative Part, VDD = 2.7V).
FIGURE 2-17: DNL vs. Temperature
(VDD =2.7V).
FIGURE 2-18: Offset Error vs. VDD.
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0 1024 2048 3072 4096
Digital Code
DNL (LSB)
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
-50 -25 0 25 50 75 100 125
Temperature (°C)
DNL (LSB)
Negative DNL
Positive DNL
-1
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
2.533.544.555.5
VDD (V)
Gain Error (LSB)
Fast Mode
(fSCL= 100 kHz) Standard Mode
(fSCL= 400 kHz)
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
0 1024204830724096
Digital Code
DNL (LSB)
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
-50 -25 0 25 50 75 100 125
Temperature (°C)
DNL (LSB)
Positive DNL
Negative DNL
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
2.5 3 3.5 4 4.5 5 5.5
VDD (V)
Offset Error (LSB)
fSCL = 100 kHz & 400 kHz
2002-2017 Microchip Technology Inc. DS20001732E-page 9
MCP3221
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion
Mode (fSAMP = 22.3 ksps), TA = +25°C.
FIGURE 2-19: Gain Error vs. Temperature.
FIGURE 2-20: SNR vs. Input Frequency.
FIGURE 2-21: THD vs. Input Frequency.
FIGURE 2-22: Offset Error vs.
Temperature.
FIGURE 2-23: SINAD vs. Input Frequency.
FIGURE 2-24: SINAD vs. Input Signal
Level.
-3
-2
-1
0
1
2
3
-50 -25 0 25 50 75 100 125
Temperature (°C)
Gain Error (LSB)
VDD = 5V
VDD = 2.7V
0
10
20
30
40
50
60
70
80
90
100
110
Input Frequency (kHz)
SNR (dB)
VDD = 5V
VDD = 2.7V
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
110
Input Frequency (kHz)
THD (dB)
VDD = 2.7V
VDD = 5V
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
-50 -25 0 25 50 75 100 125
Temperature (°C)
Offset Error (LSB)
VDD = 5V
VDD = 2.7V
0
10
20
30
40
50
60
70
80
90
100
110
Input Frequency (kHz)
SINAD (dB)
VDD = 5V
VDD = 2.7V
0
10
20
30
40
50
60
70
80
-40 -30 -20 -10 0
Input Signal Level (dB)
SINAD (dB)
VDD = 5V
VDD = 2.7V
MCP3221
DS20001732E-page 10 2002-2017 Microchip Technology Inc.
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion
Mode (fSAMP = 22.3 ksps), TA = +25°C.
FIGURE 2-25: ENOB vs. VDD.
FIGURE 2-26: SFDR vs. Input Frequency.
FIGURE 2-27: Spectrum Using I2C Fast
Mode (Representative Part, 1 kHz Input
Frequency).
FIGURE 2-28: ENOB vs. Input Frequency.
FIGURE 2-29: Spectrum Using I2C
Standard Mode (Representative Part, 1 kHz
Input Frequency).
FIGURE 2-30: IDD (Conversion) vs. VDD.
11.5
11.55
11.6
11.65
11.7
11.75
11.8
11.85
11.9
11.95
12
2.533.544.555.5
VDD (V)
ENOB (rms)
0
10
20
30
40
50
60
70
80
90
100
110
Input Frequency (kHz)
SFDR (dB)
VDD = 2.7V
VDD = 5V
-130
-110
-90
-70
-50
-30
-10
10
0 2000 4000 6000 8000 10000
Frequency (Hz)
Amplitude (dB)
9
9.5
10
10.5
11
11.5
12
110
Input Frequency (kHz)
ENOB (rms)
VDD = 2.7V
VDD = 5V
-130
-110
-90
-70
-50
-30
-10
10
0 500 1000 1500 2000 2500
Frequency (Hz)
Amplitude (dB)
fSAMP = 5.6 ksps
0
50
100
150
200
250
2.533.544.555.5
VDD (V)
IDD (µA)
2002-2017 Microchip Technology Inc. DS20001732E-page 11
MCP3221
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion
Mode (fSAMP = 22.3 ksps), TA = +25°C.
FIGURE 2-31: IDD (Conversion) vs. Clock
Rate.
FIGURE 2-32: IDD (Conversion) vs.
Temperature.
FIGURE 2-33: IDDA (Active Bus) vs. VDD.
FIGURE 2-34: IDDA (Active Bus) vs. Clock
Rate.
FIGURE 2-35: IDDA (Active Bus) vs.
Temperature.
FIGURE 2-36: IDDS (Standby) vs. VDD.
0
20
40
60
80
100
120
140
160
180
200
0 100 200 300 400
I2C Clock Rate (kHz)
IDD (µA)
VDD = 5V
VDD = 2.7V
0
50
100
150
200
250
-50-250 255075100125
Temperature (°C)
IDD (µA)
VDD = 5V
VDD = 2.7V
0
10
20
30
40
50
60
70
80
90
100
2.5 3 3.5 4 4.5 5 5.5
VDD (V)
IDDA (µA)
0
10
20
30
40
50
60
70
80
90
100
0 100 200 300 400
I2C Clock Rate (kHz)
IDDA (µA)
VDD = 5V
VDD = 2.7V
0
10
20
30
40
50
60
70
80
90
100
-50-250 255075100125
Temperature (°C)
IDDA (µA)
VDD = 5V
VDD = 2.7V
0
10
20
30
40
50
60
2.5 3 3.5 4 4.5 5 5.5
VDD (V)
IDDS (pA)
HW®
MCP3221
DS20001732E-page 12 2002-2017 Microchip Technology Inc.
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion
Mode (fSAMP = 22.3 ksps), TA = +25°C.
FIGURE 2-37: IDDS (Standby) vs.
Temperature.
FIGURE 2-38: Analog Input Leakage vs.
Temperature.
2.1 Test Circuits
FIGURE 2-39: Typical Test Configuration.
0.0001
0.001
0.01
0.1
1
10
100
1000
-50 -25 0 25 50 75 100 125
Temperature (°C)
IDDS (nA)
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
-50 -25 0 25 50 75 100 125
Temperature (°C)
Analog Input Leakage (nA)
0.1 µF
AIN MCP3221
VDD = 5V
VCM = 2.5V
VIN
VDD
VSS
10 µF
SDA
SCL
2k2k
2002-2017 Microchip Technology Inc. DS20001732E-page 13
MCP3221
3.0 PIN FUNCTIONS
Table 3-1 lists the function of the pins.
TABLE 3-1: PIN FUNCTION TABLE
3.1 VDD and VSS
The VDD pin, with respect to VSS, provides power to the
device as well as a voltage reference for the conversion
process. Refer to Section 6.4 “Device Power and
Layout Considerations” for tips on power and
grounding.
3.2 Analog Input (AIN)
AIN is the input pin to the sample and hold circuitry of
the Successive Approximation Register (SAR) con-
verter. Care should be taken in driving this pin. Refer to
Section 6.1 “Driving the Analog Input” for more
information. For proper conversions, the voltage on this
pin can vary from VSS to VDD.
3.3 Serial Data (SDA)
SDA is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open-drain
terminal, therefore, the SDA bus requires a pull-up
resistor to VDD (typically 10 k for 100 kHz and 2 k
for 400 kHz SCL clock speeds). Refer to Section 6.2
“Connecting to the I2C Bus” for more information.
For normal data transfer, SDA is allowed to change only
during SCL low. Changes during SCL high are reserved
for indicating the Start and Stop conditions. Refer to
Section 5.1 “I2C Bus Characteristics” for more infor-
mation.
3.4 Serial Clock (SCL)
SCL is an input pin used to synchronize the data trans-
fer to and from the device on the SDA pin and is an
open-drain terminal. Therefore, the SCL bus requires a
pull-up resistor to VDD (typically 10 k for 100 kHz and
2k for 400 kHz SCL clock speeds. Refer to
Section 6.2 “Connecting to the I2C Bus” for more
information.
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
Refer to Section 6.1 “Driving the Analog Input” for
more information.
Name Function
VDD +2.7V to 5.5V Power Supply
VSS Ground
AIN Analog Input
SDA Serial Data In/Out
SCL Serial Clock In
111, 11,, 11,1 ,111 1111 111”
MCP3221
DS20001732E-page 14 2002-2017 Microchip Technology Inc.
4.0 DEVICE OPERATION
The MCP3221 employs a classic SAR architecture.
This architecture uses an internal sample and hold
capacitor to store the analog input while the conversion
is taking place. At the end of the acquisition time, the
input switch of the converter opens and the device uses
the collected charge on the internal sample and hold
capacitor to produce a serial 12-bit digital output code.
The acquisition time and conversion is self-timed using
an internal clock. After each conversion, the results are
stored in a 12-bit register that can be read at any time.
Communication with the device is accomplished with a
2-wire, I2C interface. Maximum sample rates of
22.3 ksps are possible with the MCP3221 in a continu-
ous-conversion mode and an SCL clock rate of
400 kHz.
4.1 Digital Output Code
The digital output code produced by the MCP3221 is a
function of the input signal and power supply voltage,
VDD. As the VDD level is reduced, the LSB size is
reduced accordingly. The theoretical LSB size is shown
below.
EQUATION
The output code of the MCP3221 is transmitted serially
with MSB first. The format of the code is straight binary.
4.2 Conversion Time (tCONV)
The conversion time is the time required to obtain the
digital result once the analog input is disconnected
from the holding capacitor. With the MCP3221, the
specified conversion time is typically 8.96 µs. This time
is dependent on the internal oscillator and is
independent of SCL.
4.3 Acquisition Time (tACQ)
The acquisition time is the amount of time the sample
cap array is acquiring charge.
The acquisition time is, typically, 1.12 µs. This time is
dependent on the internal oscillator and independent of
SCL.
4.4 Sample Rate
Sample rate is the inverse of the maximum amount of
time that is required from the point of acquisition of the
first conversion to the point of acquisition of the second
conversion.
The sample rate can be measured either by single or
continuous conversions. A single conversion includes
a Start bit, Address byte, two data bytes and a Stop bit.
This sample rate is measured from one Start bit to the
next Start bit.
For continuous conversions (requested by the Master
by issuing an Acknowledge after a conversion), the
maximum sample rate is measured from conversion to
conversion or a total of 18 clocks (two data bytes and
two Acknowledge bits). Refer to Section 5.2 “Device
Addressing” for more information.
FIGURE 4-1: Transfer Function.
LSB SIZE
VDD
4096
------------
=
VDD = Supply voltage
1111 1111 1111 (4095)
1111 1111 1110 (4094)
AIN
0000 0000 0001 (1)
0000 0000 0011 (3)
Output Code
VDD-1.5 LSB
.5 LSB
1.5 LSB VDD-2.5 LSB
2.5 LSB
0000 0000 0000 (0)
0000 0000 0010 (2)
2002-2017 Microchip Technology Inc. DS20001732E-page 15
MCP3221
4.5 Differential Non-Linearity (DNL)
In the ideal A/D converter transfer function, each code
has a uniform width. That is, the difference in analog
input voltage is constant from one code transition point
to the next. Differential nonlinearity (DNL) specifies the
deviation of any code in the transfer function from an
ideal code width of 1 LSB. The DNL is determined by
subtracting the locations of successive code transition
points after compensating for any gain and offset
errors. A positive DNL implies that a code is longer than
the ideal code width, whereas a negative DNL implies
that a code is shorter than the ideal width.
4.6 Integral Non-Linearity (INL)
Integral nonlinearity (INL) is a result of cumulative DNL
errors and specifies how much the overall transfer
function deviates from a linear response. The method
of measurement used in the MCP3221 A/D converter
to determine INL is the end-point method.
4.7 Offset Error
Offset error is defined as a deviation of the code transi-
tion points that are present across all output codes.
This has the effect of shifting the entire A/D transfer
function. The offset error is measured by finding the dif-
ference between the actual location of the first code
transition and the desired location of the first transition.
The ideal location of the first code transition is located
at 1/2 LSB above VSS.
4.8 Gain Error
Gain error determines the amount of deviation from the
ideal slope of the A/D converter transfer function.
Before the gain error is determined, the offset error is
measured and subtracted from the conversion result.
The gain error can then be determined by finding the
location of the last code transition and comparing that
location to the ideal location. The ideal location of the
last code transition is 1.5 LSBs below full-scale or VDD.
4.9 Conversion Current (IDD)
Conversion current is the average amount of current
over the time required to perform a 12-bit conversion.
4.10 Active Bus Current (IDDA)
The average amount of current over the time required
to monitor the I2C bus. Any current that the device con-
sumes while it is not being addressed is referred to as
Active Bus current.
4.11 Standby Current (IDDS)
The average amount of current required while no con-
version is occurring and no data is being output (i.e.,
SCL and SDA lines are quiet).
4.12 I2C Standard Mode Timing
I2C specification where the frequency of SCL is
100 kHz.
4.13 I2C Fast Mode Timing
I2C specification where the frequency of SCL is
400 kHz.
MCP3221
DS20001732E-page 16 2002-2017 Microchip Technology Inc.
5.0 SERIAL COMMUNICATIONS
5.1 I2C Bus Characteristics
The following bus protocol are defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions are defined
(refer to Figure 5-1).
5.1.1 BUS NOT BUSY (A)
Both data and clock lines remain high.
5.1.2 START DATA TRANSFER (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
5.1.3 STOP DATA TRANSFER (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
5.1.4 DATA VALID (D)
The state of the data line represents valid data when
after a START condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of data
bytes being transferred between the Start and Stop
conditions is determined by the master device and is
unlimited.
5.1.5 ACKNOWLEDGE
Each receiving device, when addressed, is obliged to
generate an Acknowledge bit after the reception of
each byte. The master device must generate an extra
clock pulse that is associated with this Acknowledge
bit.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge-related clock pulse. Setup
and hold times must be taken into account. During
reads, a master device must signal an end of data to
the slave by not generating an Acknowledge bit on the
last byte that is clocked out of the slave (NAK). In this
case, the slave (MCP3221) releases the bus to allow
the master device to generate the Stop condition.
The MCP3221 supports a bidirectional, 2-wire bus and
data transmission protocol. The device that sends data
onto the bus is the transmitter and the device receiving
data is the receiver. The bus has to be controlled by a
master device that generates the serial clock (SCL),
controls the bus access and generates the Start and
Stop conditions, whereas the MCP3221 works as a
slave device. Both master and slave devices can oper-
ate as either transmitter or receiver, but the master
device determines which mode is activated.
FIGURE 5-1: Data Transfer Sequence on the Serial Bus.
SCL
SDA
(A) (B) (D) (D) (A)(C)
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
4% rgggkgga éfiflllfififllé
2002-2017 Microchip Technology Inc. DS20001732E-page 17
MCP3221
5.2 Device Addressing
The address byte is the first byte received following the
Start condition from the master device. The first part of
the control byte consists of a 4-bit device code, which
is set to 1001 for the MCP3221. The device code is fol-
lowed by three address bits: A2, A1 and A0. The default
address bits are 101. Contact the Microchip factory for
additional address bit options. The address bits allow
up to eight MCP3221 devices on the same bus and are
used to determine which device is accessed.
The eighth bit of the slave address determines if the
master device wants to read conversion data or write to
the MCP3221. When set to a 1, a read operation is
selected. When set to a 0, a write operation is selected.
There are no writable registers on the MCP3221, there-
fore, this bit must be set to a 1 to initiate a conversion.
The MCP3221 is a slave device that is compatible with
the 2-wire I2C serial interface protocol. A hardware
connection diagram is shown in Figure 6-2. Communi-
cation is initiated by the microcontroller (master
device), which sends a Start bit followed by the address
byte.
On completion of the conversion(s) performed by the
MCP3221, the microcontroller must send a Stop bit to
end the communication.
The last bit in the device address byte is the R/W bit.
When this bit is a logic 1, a conversion is executed. Set-
ting this bit to logic 0 also results in an Acknowledge
(ACK) from the MCP3221, with the device then releas-
ing the bus. This can be used for device polling. Refer
to Section 6.3 “Device Polling” for more information.
FIGURE 5-2: Device Addressing.
5.3 Executing a Conversion
This section describes the details of communicating
with the MCP3221 device. Initiating the sample and
hold acquisition, reading the conversion data, and
executing multiple conversions are discussed.
5.3.1 INITIATING THE SAMPLE AND
HOLD
The acquisition and conversion of the input signal
begins with the falling edge of the R/W bit of the
address byte. At this point, the internal clock initiates
the sample, hold and conversion cycle, all of which are
internal to the ADC.
FIGURE 5-3: Initiating the Conversion,
Address Byte.
FIGURE 5-4: Initiating the Conversion,
Continuous Conversions.
START READ/WRITE
SLAVE ADDRESS R/W A
1001101
Address bits(1)
Note 1: Contact Microchip for additional address bits.
Device code
123456789
SCL
SDA 1 0 0 1 A2 A1 A0 R/W
ACK
Start
bit
Address Byte
Address bits Device bits
tACQ + tCONV is
initiated here
SCL
SDA D3 D2 D2
ACK
Lower Data Byte (n)
tACQ + tCONV is
initiated here
D6 D5 D4 D0D7
ACK
D8
17 18 19 20 21 22 23 24 25 26
MCP3221
DS20001732E-page 18 2002-2017 Microchip Technology Inc.
The input signal is initially sampled with the first falling
edge of the clock following the transmission of a
logic-high R/W bit. Additionally, with the rising edge of
the SCL, the ADC transmits an Acknowledge bit (ACK
= 0). The master must release the data bus during this
clock pulse to allow the MCP3221 to pull the line low
(refer to Figure 5-3).
For consecutive samples, sampling begins on the fall-
ing edge of the LSB of the conversion result, which is
two bytes long. Refer to Figure 5-6 for the timing
diagram.
5.3.2 READING THE CONVERSION DATA
After the MCP3221 acknowledges the address byte, the
device transmits four 0 bits followed by the upper four
data bits of the conversion. The master device acknowl-
edges this byte with an ACK = Low. With the following
eight clock pulses, the MCP3221 transmits the lower
eight data bits from the conversion. The master sends
an ACK = high, indicating to the MCP3221 that no more
data is requested. The master can send a Stop bit to
end the transmission.
FIGURE 5-5: Executing a Conversion.
5.3.3 CONSECUTIVE CONVERSIONS
For consecutive samples, sampling begins on the fall-
ing edge of the LSB of the conversion result. See
Figure 5-6 for timing.
FIGURE 5-6: Continuous Conversion.
SDA
S
T
A
R
T
S
T
O
P
A
C
K
tACQ + tCONV is
initiated here
Address Byte
Address bits
Device bits
1001AR
/
W
Upper Data Byte
0000
DDDA
C
K
Lower Data Byte
N
A
K
S P
11 10
2
A
1
A
09
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
SCL
SDA
fSAMP = 22.3 ksps (fCLK = 400 kHz)
A
C
K
tACQ + tCONV is
initiated here
Address Byte
Address bits
Device bits
1 0 0 1 A2 A1 A0 R
/
W
Upper Data Byte (n)
A
C
K
Lower Data Byte (n)
A
C
K
S
tACQ + tCONV is
initiated here
0000
DDD
11 10 9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
SCL
S
T
A
R
T
0
28
2002-2017 Microchip Technology Inc. DS20001732E-page 19
MCP3221
6.0 APPLICATIONS INFORMATION
6.1 Driving the Analog Input
The MCP3221 has a single-ended analog input (AIN).
For proper conversion results, the voltage at the AIN pin
must be kept between VSS and VDD. If the converter
has no offset error, gain error, INL or DNL errors, and
the voltage level of AIN is equal to or less than
VSS + 1/2 LSB, the resultant code is 000h. Addition-
ally, if the voltage at AIN is equal to or greater than
VDD - 1.5 LSB, the output code is FFFh.
The analog input model is shown in Figure 6-1. In this
diagram, the source impedance (RSS) adds to the inter-
nal sampling switch (RS) impedance, directly affecting
the time required to charge the capacitor (CSAMPLE).
Consequently, a larger source impedance increases
the offset error, gain error and integral linearity errors of
the conversion. Ideally, the impedance of the signal
source should be near zero. This is achievable with an
operational amplifier such as the MCP6022, which has
a closed-loop output impedance of tens of ohms.
FIGURE 6-1: Analog Input Model, AIN.
6.2 Connecting to the I2C Bus
The I2C bus is an open collector bus, requiring pull-up
resistors connected to the SDA and SCL lines. This
configuration is shown in Figure 6-2.
FIGURE 6-2: Pull-up Resistors on I2C
Bus.
The number of devices connected to the bus is only
limited by the maximum bus capacitance of 400 pF. A
possible configuration using multiple devices is shown
in Figure 6-3.
FIGURE 6-3: Multiple Devices on I2C Bus.
CPIN
VA
RSS AIN
7pF
VT = 0.6V
VT = 0.6V ILEAKAGE
Sampling
Switch
SS RS = 1 k
CSAMPLE
= DAC capacitance
VSS
VDD
= 20 pF
±1 nA
Legend
VA = signal source
RSS = source impedance
AIN = analog input pad
CPIN = analog input pin capacitance
VT= threshold voltage
ILEAKAGE = leakage current at the pin
due to various junctions
SS = sampling switch
RS= sampling switch resistor
CSAMPLE = sample/hold capacitance
PIC®
SDA
SCL
VDD
RPU
RPU
RPU is typically: 10 k for fSCL = 100 kHz
2k for fSCL = 400 kHz
MCP3221
Analog
Input
Signal
Microcontroller
AIN
SDA SCL
PIC16F876
Microcontroller
MCP3221
12-bit ADC
TC74
Temperature
Sensor
24LC01
EEPROM
MCP3221
DS20001732E-page 20 2002-2017 Microchip Technology Inc.
6.3 Device Polling
In some instances, it may be necessary to test for
MCP3221 presence on the I2C bus without performing
a conversion as described in Figure 6-4 where the R/W
bit in the address byte is set to a zero. The MCP3221
acknowledges by pulling SDA low during the ACK clock
and then release the bus back to the I2C master. A Stop
or repeated Start bit can be issued from the master and
I2C communication can continue.
FIGURE 6-4: Device Polling.
6.4 Device Power and Layout
Considerations
6.4.1 POWERING THE MCP3221
VDD supplies the power to the device and the reference
voltage. A bypass capacitor value of 0.1 µF is recom-
mended. Adding a 10 µF capacitor in parallel is recom-
mended to attenuate higher frequency noise that is
present in some systems.
FIGURE 6-5: Powering the MCP3221.
6.4.2 LAYOUT CONSIDERATIONS
When laying out a printed circuit board for use with
analog components, care should be taken to reduce
noise wherever possible. A bypass capacitor from VDD
to ground must be used always with this device and
placed as close as possible to the device pin. A bypass
capacitor value of 0.1 µF is recommended.
Digital and analog traces should be separated as much
as possible on the board, with no traces running
underneath the device or the bypass capacitor. Extra
precautions should be taken to keep traces with high-
frequency signals (such as clock lines) as far as
possible from analog traces.
Use of an analog ground plane is recommended in
order to keep the ground potential the same for all
devices on the board. Providing VDD connections to
devices in a Star configuration can also reduce noise
by eliminating current return paths and associated
errors (Figure 6-6). For more information on layout tips
when using the MCP3221 or other ADC devices, refer
to the Microchip Technology Application Note, “AN688
Layout Tips for 12-Bit A/D Converter Application”
(DS00688).
FIGURE 6-6: VDD traces arranged in a
Star configuration in order to reduce errors
caused by current return paths.
Note: When power-down of the MCP3221 is
needed during applications (after power-
up), it is highly recommended to bring
down the VDD to VSS level. This can guar-
antee a Full Reset of the device for the
next power-up cycle.
123456789
SCL
SDA 100
1A2 A1A0 0
ACK
Start
bit
Address Byte
Address bits
Device bits R/W Start
bit
MCP3221 response
VDD
VDD
AIN
SCL
SDA
To
Microcontroller
10 µF
MCP3221
0.1 µF
VDD
RPU
RPU
VDD
Connection
Device 1
Device 2
Device 3
Device 4
2002-2017 Microchip Technology Inc. DS20001732E-page 21
MCP3221
6.4.3 USING A REFERENCE FOR
SUPPLY
The MCP3221 uses VDD as power and also as a refer-
ence. In some applications, it may be necessary to use
a stable reference to achieve the required accuracy.
Figure 6-7 shows an example using the MCP1541 as a
4.096V, 2% reference.
FIGURE 6-7: Stable Power and
Reference Configuration.
VDD
VDD
4.096V
Reference
1µF
0.1 µF
MCP1541 CL
AIN
To
Microcontroller
MCP3221
VDD
RPU
SCL
SDA
NNN
MCP3221
DS20001732E-page 22 2002-2017 Microchip Technology Inc.
7.0 PACKAGING INFORMATION
7.1 Package Marking Information
5-Pin SOT-23
Part Number Address Option SOT-23
MCP3221A0T-E/OT 000 GE
MCP3221A1T-E/OT 001 GH
MCP3221A2T-E/OT 010 GB
MCP3221A3T-E/OT 011 GC
MCP3221A4T-E/OT 100 GD
MCP3221A5T-E/OT 101 GA *
MCP3221A6T-E/OT 110 GF
MCP3221A7T-E/OT 111 GG
* Default option. Contact Microchip Factory for other
address options.
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
321
45
1234
2002-2017 Microchip Technology Inc. DS20001732E-page 23
MCP3221
5-Lead Plastic Small Outline Transistor (OT) (SOT-23)
1
p
D
B
n
E
E1
L
c
A2
A
A1
p1
10501050
b
Mold Draft Angle Bottom
10501050
a
Mold Draft Angle Top
0.500.430.35.020.017.014BLead Width
0.200.150.09.008.006.004
c
Lead Thickness
10501050
f
Foot Angle
0.550.450.35.022.018.014LFoot Length
3.102.952.80.122.116.110DOverall Length
1.751.631.50.069.064.059E1Molded Package Width
3.002.802.60.118.110.102EOverall Width
0.150.080.00.006.003.000A1Standoff
1.301.100.90.051.043.035A2Molded Package Thickness
1.451.180.90.057.046.035AOverall Height
1.90.075
p1
Outside lead pitch (basic)
0.95.038
p
Pitch
55
n
Number of Pins
MAXNOMMINMAXNOMMINDimension Limits
MILLIMETERSINCHES
*
Units
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
Notes:
EIAJ Equivalent: SC-74A
Drawing No. C04-091
*
Controlling Parameter
Revised 09-12-05
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
MCP3221
DS20001732E-page 24 2002-2017 Microchip Technology Inc.
NOTES:
2002-2017 Microchip Technology Inc. DS20001732E-page 25
MCP3221
APPENDIX A: REVISION HISTORY
Revision E (January 2017)
• Added a note to Section 6.4.1 “Powering the
MCP3221”.
•Fixed Section 7.1 “Package Marking Informa-
tion” format to reflect the correct package mark-
ing as “1 2 3 4” instead of “1 10 10 10”.
• Updated Temperature Specifiations table to
remove information on Industrial Temperature
Range
Revision D (January 2013)
• Added a note to each package outline drawing.
Revision C (July 2006)
• Updated Section 5.2 “Device Addressing”:
changed 4-bit device code to “1001”. Changed
three address bits to “101”.
Revision B (May 2003)
• Numerous changes throughout document.
Revision A (November 2002)
• Original Release of this Document.
MCP3221
DS20001732E-page 26 2002-2017 Microchip Technology Inc.
NOTES:
PART NO. v 41x
2002-2017 Microchip Technology Inc. DS20001732E-page 27
MCP3221
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
MCP3221
DS20001732E-page 28 2002-2017 Microchip Technology Inc.
NOTES:
YSTEM
2002-2017 Microchip Technology Inc. DS20001732E-page 11
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory,
CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ,
KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST
Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
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EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo,
CodeGuard, CryptoAuthentication, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
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ZENA are trademarks of Microchip Technology Incorporated in the
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SQTP is a service mark of Microchip Technology Incorporated in
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Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
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Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2002-2017, Microchip Technology Incorporated, All Rights
Reserved.
ISBN: 978-1-5224-1291-5
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
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are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
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and manufacture of development systems is ISO 9001:2000 certified.
QUALITYMANAGEMENTS
YSTEM
CERTIFIEDBYDNV
== ISO/TS16949==
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