SI552 Datasheet by Silicon Labs

SILIEIJN LABS £657- 1 C j C j C l T I ﬂﬂﬁ “

DUAL FREQUENCY VOLTAGE-CONTROLLED CRYSTAL

OSCILLATOR (VCXO) 10 MHZ TO 1.4 GHZ

Features

Applications

Description

The Si552 dual-frequency VCXO utilizes Silicon Laboratories’ advanced

DSPLL® circuitry to provide a very low jitter clock for all output frequencies.

The Si552 is available with any-rate output frequency from 10 to 945 MHz

and selected frequencies to 1400 MHz. Unlike traditional VCXOs, where a

different crystal is required for each output frequency, the Si552 uses one

fixed crystal frequency to provide a wide range of output frequencies. This

IC-based approach allows the crystal resonator to provide exceptional

frequency stability and reliability. In addition, DSPLL clock synthesis

provides superior supply noise rejection, simplifying the task of generating

low-jitter clocks in noisy environments typically found in communication

systems. The Si552 IC-based VCXO is factory-configurable for a wide

variety of user specifications including frequency, supply voltage, output

format, tuning slope, and temperature stability. Specific configurations are

factory programmed at time of shipment, thereby eliminating the long lead

times associated with custom oscillators.

Functional Block Diagram

Available with any-rate output

frequencies from 10–945 MHz and

selected frequencies to 1.4 GHz

Two selectable output frequencies

3rd generation DSPLL® with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

SONET/SDH

xDSL

10 GbE LAN/WAN

Low-jitter clock generation

Optical modules

Clock and data recovery

Fixed

Frequency XO

Any-rate

10–1400 MHz

DSPLL®

Clock Synthesis

VDD CLK+

CLK-

VCGND

ADC

Ordering Information:

See page 10.

Pin Assignments:

See page 9.

(Top View)

Si5602

GND

VDD

CLK+

CLK–

Si552

REVISION D

Parameter Symbol Test Condition Min Typ Max Units 1.2‘3 £2 ($9 SILICON LABS

Si552

2 Rev. 1.2

1. Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter Symbol Test Condition Min Typ Max Units

Supply Voltage1VDD 3.3 V option 2.97 3.3 3.63 V

2.5 V option 2.25 2.5 2.75 V

1.8 V option 1.71 1.8 1.89 V

Supply Current IDD Output enabled

LVPECL

CML

LVDS

CMOS

—

120

108

130

117

108

Tristate mode — 60 75 mA

Frequency Select (FS)2VIH 0.75 x VDD ——V

VIL ——0.5V

Operating Temperature Range TA–40 — 85 ºC

Notes:

1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 10 for further details.

2. FS pin includes a 17 k resistor to VDD.

Table 2. VC Control Voltage Input

Parameter Symbol Test Condition Min Typ Max Units

Control Voltage Tuning Slope1,2,3 KV10 to 90% of VDD —33

135

180

356

— ppm/V

Control Voltage Linearity4LVC BSL –5 ±1 +5 %

Incremental –10 ±5 +10 %

Modulation Bandwidth BW 9.3 10.0 10.7 kHz

VC Input Impedance ZVC 500 — — k

Nominal Control Voltage VCNOM @ fO—V

DD/2 — V

Control Voltage Tuning Range VC0V

DD V

Notes:

1. Positive slope; selectable option by part number. See Section 3. "Ordering Information" on page 10.

2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR

requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.

3. KV variation is ±10% of typical values.

4. BSL determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. Incremental slope

determined with VC ranging from 10 to 90% of VDD.

Parameter Symbol Test Condition Min Typ Max Units 1‘4 1,4 Parameter Symbol Test Condition Min TYP Max Units , . SILIEDN LABS

Si552

Rev. 1.2 3

Table 3. CLK± Output Frequency Characteristics

Parameter Symbol Test Condition Min Typ Max Units

Nominal Frequency1,2,3 fOLVDS/CML/LVPECL 10 — 945 MHz

CMOS 10 — 160 MHz

Temperature Stability1,4 TA= –40 to +85 °C –20

–50

–100

—

+20

+50

+100

ppm

Absolute Pull Range1,4 APR ±12 — ±375 ppm

Aging Frequency drift over first year. — — ±3 ppm

Frequency drift over 15 year life. — — ±10 ppm

Power up Time5tOSC ——10ms

Settling Time After FS Change tFRQ ——10ms

Notes:

1. See Section 3. "Ordering Information" on page 10 for further details.

2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.

3. Nominal output frequency set by VCNOM =V

DD/2.

4. Selectable parameter specified by part number.

5. Time from power up or tristate mode to fO (to within ±1 ppm of fO).

Table 4. CLK± Output Levels and Symmetry

Parameter Symbol Test Condition Min Typ Max Units

LVPECL Output

Option1

VOmid-level VDD – 1.42 — VDD – 1.25 V

VOD swing (diff) 1.1 —1.9 VPP

VSE swing (single-ended) 0.55 —0.95 VPP

LVDS Output Option2VOmid-level 1.125 1.20 1.275 V

VOD swing (diff) 0.5 0.7 0.9 VPP

CML Output Option2

2.5/3.3 V option mid-level — VDD – 1.30 — V

1.8 V option mid-level — VDD – 0.36 — V

VOD

2.5/3.3 V option swing (diff) 1.10 1.50 1.90 VPP

1.8 V option swing (diff) 0.35 0.425 0.50 VPP

CMOS Output Option3VOH IOH =32mA 0.8 x VDD —VDD V

VOL IOL =32mA — — 0.4 V

Rise/Fall time (20/80%) tR, tFLVPECL/LVDS/CML — — 350 ps

CMOS with CL=15pF — 1 — ns

Symmetry (duty cycle) SYM LVPECL: VDD – 1.3 V (diff)

LVDS: 1.25 V (diff)

CMOS: VDD/2

45 — 55 %

Notes:

1. 50  to VDD – 2.0 V.

2. Rterm = 100  (differential).

3. CL = 15 pF

\ v 123 d) |/\ Iv IA ($9 SILICON LABS

Si552

4 Rev. 1.2

Table 5. CLK± Output Phase Jitter

Parameter Symbol Test Condition Min Typ Max Units

Phase Jitter (RMS)1,2,3

for FOUT > 500 MHz

JKv = 33 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.26

—

Kv = 45 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.27

0.26

—

Kv = 90 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.32

0.26

—

Kv = 135 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.40

0.27

—

Kv = 180 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.49

0.28

—

Kv = 356 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.87

0.33

—

Notes:

1. Refer to AN255, AN256, and AN266 for further information.

2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR

requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.

3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply

rejection (PSR) advantage of Si55x versus SAW-based solutions.

4. Max jitter for LVPECL output with VC=1.65V, VDD=3.3V, 155.52 MHz.

5. Max offset frequencies: 80 MHz for FOUT > 250 MHz, 20 MHz for 50 MHz < FOUT <250 MHz,

2MHz for 10MHz <

FOUT <50 MHz.

1,2‘3‘45 d) |/\ Iv IA , . SILIEDN LABS

Si552

Rev. 1.2 5

Phase Jitter (RMS)1,2,3,4,5

for FOUT of 125 to 500 MHz

JKv = 33 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.37

0.33

—

Kv = 45 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.37

0.33

0.4

—

Kv = 90 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.43

0.34

—

Kv = 135 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.50

0.34

—

Kv = 180 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.59

0.35

—

Kv = 356 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

1.00

0.39

—

Table 5. CLK± Output Phase Jitter (Continued)

Parameter Symbol Test Condition Min Typ Max Units

Notes:

1. Refer to AN255, AN256, and AN266 for further information.

2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR

requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.

3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply

rejection (PSR) advantage of Si55x versus SAW-based solutions.

4. Max jitter for LVPECL output with VC=1.65V, VDD=3.3V, 155.52 MHz.

5. Max offset frequencies: 80 MHz for FOUT > 250 MHz, 20 MHz for 50 MHz < FOUT <250 MHz,

2MHz for 10MHz < FOUT <50 MHz.

1,2‘5 |/\ Iv IA ($9 SILICON LABS

Si552

6 Rev. 1.2

Phase Jitter (RMS)1,2,5

for FOUT 10 to 160 MHz

CMOS Output Only

JKv = 33 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 20 MHz

—

0.63

0.62

—

Kv = 45 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 20 MHz

—

0.63

0.62

—

Kv = 90 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 20 MHz

—

0.67

0.66

—

Kv = 135 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 20 MHz

—

0.74

0.72

—

Kv = 180 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 20 MHz

—

0.83

0.8

—

Kv = 356 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 20 MHz

—

1.26

1.2

—

Table 6. CLK± Output Period Jitter

Parameter Symbol Test Condition Min Typ Max Units

Period Jitter* JPER RMS — 2 — ps

Peak-to-Peak — 14 — ps

*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.

Table 5. CLK± Output Phase Jitter (Continued)

Parameter Symbol Test Condition Min Typ Max Units

Notes:

1. Refer to AN255, AN256, and AN266 for further information.

2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR

requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.

3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply

rejection (PSR) advantage of Si55x versus SAW-based solutions.

4. Max jitter for LVPECL output with VC=1.65V, VDD=3.3V, 155.52 MHz.

5. Max offset frequencies: 80 MHz for FOUT > 250 MHz, 20 MHz for 50 MHz < FOUT <250 MHz,

2MHz for 10MHz < FOUT <50 MHz.

, . SILIEDN LABS

Si552

Rev. 1.2 7

Table 7. CLK± Output Phase Noise (Typical)

Offset Frequency 74.25 MHz

90 ppm/V

LVPECL

491.52 MHz

45 ppm/V

LVPECL

622.08 MHz

135 ppm/V

LVPECL

Units

100 Hz

1kHz

10 kHz

100 kHz

1MHz

10 MHz

100 MHz

–87

–114

–132

–142

–148

–150

n/a

–75

–100

–116

–124

–135

–146

–147

–65

–90

–109

–121

–134

–146

–147

dBc/Hz

Table 8. Environmental Compliance

The Si552 meets the following qualification test requirements.

Parameter Conditions/Test Method

Mechanical Shock MIL-STD-883F, Method 2002.3 B

Mechanical Vibration MIL-STD-883F, Method 2007.3 A

Solderability MIL-STD-883F, Method 203.8

Gross & Fine Leak MIL-STD-883F, Method 1014.7

Resistance to Solvents MIL-STD-883F, Method 2016

Moisture Sensitivity Level J-STD-020, MSL 1

Contact Pads J-STD-020, MSL 1

Table 9. Thermal Characteristics

(Typical values TA = 25 ºC, VDD =3.3V)

Parameter Symbol Test Condition Min Typ Max Unit

Thermal Resistance Junction to Ambient JA Still Air — 84.6 — °C/W

Thermal Resistance Junction to Case JC Still Air — 38.8 — °C/W

Ambient Temperature TA–40 — 85 °C

Junction Temperature TJ——125°C

($9 SILICON LABS

Si552

8 Rev. 1.2

Table 10. Absolute Maximum Ratings1

Parameter Symbol Rating Units

Maximum Operating Temperature TAMAX 85 ºC

Supply Voltage, 1.8 V Option VDD –0.5 to +1.9 V

Supply Voltage, 2.5/3.3 V Option VDD –0.5 to +3.8 V

Input Voltage (any input pin) VI–0.5 to VDD + 0.3 V

Storage Temperature TS–55 to +125 ºC

ESD Sensitivity (HBM, per JESD22-A114) ESD 2500 V

Soldering Temperature (Pb-free profile)2TPEAK 260 ºC

Soldering Temperature Time @ TPEAK (Pb-free profile)2tP20–40 seconds

Notes:

1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional

operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for

extended periods may affect device reliability.

2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download from

www.silabs.com/VCXO for further information, including soldering profiles.

, . SILIEDN LABS

Si552

Rev. 1.2 9

2. Pin Descriptions

Table 11. Si552 Pin Descriptions

Pin Name Type Function

1 VCAnalog Input Control Voltage

2FS* Input

Frequency Select:

0 = first frequency selected

1 = second frequency selected

3GND Ground Electrical and Case Ground

4CLK+ Output Oscillator Output

5CLK–

(N/A for CMOS)

Output Complementary Output

(N/C for CMOS)

6 VDD Power Power Supply Voltage

*Note: FS includes a 17 k pullup resistor to VDD. See Section 3. "Ordering Information" on page 10 for details on frequency

select and OE polarity ordering options.

GND

VDD

CLK+

CLK–

(Top View)

Code Notes: 1 “Oman Code VDD Oulgut Formal |_ operanna Temp Ranqe (:0) —:l 6-dwgn Freguengy Designamr Code Code 1 Wm (max) 2 Ognon Code Dam/Wm) 33V 25V 1.8V ($9 SILICON LABS

Si552

10 Rev. 1.2

3. Ordering Information

The Si552 supports a variety of options including frequency, temperature stability, tuning slope, output format, and

VDD. Specific device configurations are programmed into the Si552 at time of shipment. Configurations are

specified using the Part Number Configuration chart shown below. Silicon Labs provides a web browser-based part

number configuration utility to simplify this process. Refer to www.silabs.com/VCXOPartNumber to access this tool

and for further ordering instructions. The Si552 VCXO series is supplied in an industry-standard, RoHS-compliant,

lead-free, 6-pad, 5 x 7 mm package. Tape and reel packaging is an ordering option.

Figure 1. Part Number Convention

R = Tape & Reel

Blank = Coil Tape

Operating Temp Range (°C)

G –40 to +85 °C

Device Revision Letter

552 Dual VCXO

Product Family

1st Option Code

Code VDD Output Format

A 3.3 LVPECL

B3.3LVDS

C3.3CMOS

D3.3CML

E 2.5 LVPECL

F2.5LVDS

G2.5CMOS

H2.5CML

J1.8CMOS

K1.8CML

Notes:

CMOS available to 160 MHz.

552 X X XXXXXX D G R

2nd Option Code

Temperature Tuning Slope Minimum APR

Stability Kv (±ppm) for VDD @

Code ± ppm (max) ppm/V (typ) 3.3 V 2.5 V 1.8 V

A 100 180 100 75 25

B 100 90 30 Note 6 Note 6

C 50 180 150 125 75

D5090803025

E 20 45 25 Note 6 Note 6

F 50 135 100 75 50

G 20 356 375 300 235

H 20 180 185 145 105

J 20 135 130 104 70

K 100 356 295 220 155

M 20 33 12 Note 6 Note 6

Notes:

1. For best jitter and phase noise performance , always choose the smallest Kv that meets

the application s minimum APR requirements. Unlike SAW-based solutions which

require higher higher Kv values to account for their higher temperature dependence ,

the Si55x series provides lower Kv options to minimize noise coupling and jitter in real -

world PLL designs. See AN255 and AN266 for more information.

2. APR is the ability of a VCXO to track a signal over the product lifetime . A VCXO with an

APR of ±25 ppm is able to lock to a clock with a ± 25 ppm stability over 15 years over all

operating conditions.

3. Nominal Pull range (±) = 0.5 x VDD x tuning slope.

4. Nominal Absolute Pull Range (±APR) = Pull range – stability – lifetime aging

= 0.5 x VDD x tuning slope – stability – 10 ppm

5. Minimum APR values noted above include worst case values for all parameters .

6. Combination not available.

Example Part Number: 552AF000108DGR is a 5x7mm Dual VCXO in a 6 pad package. Since the six digit code (000108) is >

000100, f0 is 644.53125 MHz (lower frequency) and f1 is 693.48299 (higher frequency), with a 3.3V supply and LVPECL output.

Temperature stability is specified as ± 50 ppm and the tuning slope is 135 ppm/V. The part is specified for a -40 to +85 C° ambient

temperature range operation and is shipped in tape and reel format .

6-digit Frequency Designator Code

Two unique frequencies can be specified within the following bands of frequencies : 10 to

945 MHz, 970 to 1134 MHz, and 1213 to 1417 MHz. A six digit code will be assigned for

the specified combination of frequencies . Codes > 000100 refer to dual XOs programmed

with the lower frequency value selected when FS = 0, and the higher value when FS = 1.

Six digit codes < 000100 refer to dual XOs programmed with the higher frequency value

selected when FS = 0, and the lower value when FS = 1.

Dimension A QWW‘ Nom 1 .65 0.60 5.00 BSC , . SILIEDN LABS

Si552

Rev. 1.2 11

4. Package Outline and Suggested Pad Layout

Figure 2 illustrates the package details for the Si552. Table 12 lists the values for the dimensions shown in the

illustration.

Figure 2. Si552 Outline Diagram

Table 12. Package Diagram Dimensions (mm)

Dimension Min Nom Max

A 1.50 1.65 1.80

b 1.30 1.40 1.50

c 0.50 0.60 0.70

D 5.00 BSC

D1 4.30 4.40 4.50

e 2.54 BSC.

E 7.00 BSC.

E1 6.10 6.20 6.30

H 0.55 0.65 0.75

L 1.17 1.27 1.37

p 1.80 — 2.60

R 0.70 REF

aaa 0.15

bbb 0.15

ccc 0.10

ddd 0.10

eee 0.50

W ($9 SILICON LABS

Si552

12 Rev. 1.2

5. 6-Pin PCB Land Pattern

Figure 3 illustrates the 6-pin PCB land pattern for the Si552. Table 13 lists the values for the dimensions shown in

the illustration.

Figure 3. Si552 PCB Land Pattern

Table 13. PCB Land Pattern Dimensions (mm)

Dimension Min Max

D2 5.08 REF

e 2.54 BSC

E2 4.15 REF

GD 0.84 —

GE 2.00 —

VD 8.20 REF

VE 7.30 REF

X1.70 TYP

Y2.15 REF

ZD — 6.78

ZE — 6.30

Notes:

1. Dimensioning and tolerancing per the ANSI Y14.5M-1994 specification.

2. Land pattern design based on IPC-7351 guidelines.

3. All dimensions shown are at maximum material condition (MMC).

4. Controlling dimension is in millimeters (mm).

, . SILIEDN LABS

Si552

Rev. 1.2 13

6. Top Marking

6.1. Si552 Top Marking

6.2. Top Marking Explanation

Line Position Description

1 1–10 “SiLabs”+ Part Family Number, 552 (First 3 characters in part number)

2 1–10 Si552: Option1+Option2+Freq(7)+Temp

Si552 w/ 8-digit resolution: Option1+Option2+ConfigNum(6)+Temp

3 Trace Code

Position 1 Pin 1 orientation mark (dot)

Position 2 Product Revision (D)

Position 3–6 Tiny Trace Code (4 alphanumeric characters per assembly release instructions)

Position 7 Year (least significant year digit), to be assigned by assembly site (ex: 2007 = 7)

Position 8–9 Calendar Work Week number (1–53), to be assigned by assembly site

Position 10 “+” to indicate Pb-Free and RoHS-compliant



($9 SILIEEIN LABS

Si552

14 Rev. 1.2

DOCUMENT CHANGE LIST

Revision 0.6 to Revision 1.0

Updated Table 4 on page 3.

Updated 2.5 V/3.3 V and 1.8 V CML output level

specifications.

Updated Table 5 on page 4.

Removed the words “Differential Modes:

LVPECL/LVDS/CML” in the footnote referring to AN256.

Added footnotes clarifying max offset frequency test

conditions.

Added CMOS phase jitter specs.

Updated Table 10 on page 8.

Separated 1.8 V, 2.5 V/3.3 V supply voltage

specifications.

Updated and clarified Table 8 on page 7

Added “Moisture Sensitivity Level” and “Contact Pads”

rows.

Updated 6. "Top Marking" on page 13 to reflect

specific marking information (previously, figure was

generic).

Updated 4. "Package Outline and Suggested Pad

Layout" on page 11.

Added cyrstal impedance pin in Figure 2 on page 11 and

Table 12 on page 11.

Reordered spec tables and back matter to conform

to data sheet quality conventions.

Revision 1.0 to Revision 1.1

Added Table 9, “Thermal Characteristics,” on

page 7.

Revision 1.1 to Revision 1.2

June, 2018

Changed “Trays” to “Coil Tape” in section

3.“Ordering Information”.

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intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"

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