SI514 Datasheet by Silicon Labs

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Si514

ANY-FREQUENCY I2C PROGRAMMABLE XO (100 kHZ TO 250 MHZ)

Features

Applications

Description

The Si514 user-programmable I

C XO utilizes Silicon Laboratories' advanced PLL

technology to provide any frequency from 100 kHz to 250 MHz with programming

resolution of 0.026 parts per billion. The Si514 uses a single integrated crystal and

Silicon Labs’ proprietary DSPLL synthesizer to generate any frequency across this

range using simple I

C commands. Ultra-fine tuning resolution replaces DACs and

VCXOs with an all-digital PLL solution that improves performance where

synchronization is necessary or in free-running reference clock applications. This

solution provides superior supply noise rejection, simplifying low jitter clock

generation in noisy environments. Crystal ESR and DLD are individually

production-tested to guarantee performance and enhance reliability.

The Si514 is factory-configurable for a wide variety of user specifications, including

startup frequency, I

C address, supply voltage, output format, and stability. Specific

configurations are factory-programmed at time of shipment, eliminating long lead

times and non-recurring engineering charges associated with custom frequency

oscillators.

Functional Block Diagram

Programmable to any frequency

from 100 kHz to 250 MHz

0.026 ppb frequency tuning

resolution

Glitch suppression on OE, power

on and frequency transitions

Low jitter operation

2- to 4-week lead times

Total stability includes 10-year

aging

Comprehensive production test

coverage includes crystal ESR and

DLD

On-chip LDO for power supply

noise filtering

3.3, 2.5, or 1.8 V operation

Differential (LVPECL, LVDS,

HCSL) or CMOS output options

Optional integrated 1:2 CMOS

fanout buffer

Industry standard 5x7, 3.2x5, and

2.5x3.2 mm packages

–40 to 85 oC operation

All-digital PLLs

DAC+ VCXO replacement

SONET/SDH/OTN

3G-SDI/HD-SDI/SDI

Datacom

Industrial automation

FPGA/ASIC clock generation

FPGA synchronization

Ordering Information:

See page 28.

Pin Assignments:

See page 27.

Si5602

5x7mm, 3.2x5mm 2.5x3.2mm

4GND

SCL

VDD

CLK+

CLK–

SDA

Section Page 659' SILIEIJN LABS

Si514

2 Rev. 1.2

TABLE OF CONTENTS

Section Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2. Solder Reflow and Rework Requirements for 2.5x3.2 mm Packages . . . . . . . . . . . . . .11

3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.1. Programming a New Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.2. Programming a Small Frequency Change (sub ±1000 ppm) . . . . . . . . . . . . . . . . . .13

3.3. Programming a Large Frequency Change (> ±1000 ppm) . . . . . . . . . . . . . . . . . . . .14

4. All-Digital PLL Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

5. User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

5.1. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

5.2. Register Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

5.3. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

6.1. Dual CMOS (1:2 Fanout Buffer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

7. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

8. Package Outline Diagram: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

9. PCB Land Pattern: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

10. Package Outline Diagram: 3.2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

11. PCB Land Pattern: 3.2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

12. Package Outline Diagram: 2.5 x 3.2 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

13. PCB Land Pattern: 2.5 x 3.2 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

14. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

14.1. Si514 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

14.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

, . SILIEDN LABS

Si514

Rev. 1.2 3

1. Electrical Specifications

Table 1. Operating Specifications

VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC

Parameter Symbol Test Condition Min Typ Max Units

Supply Voltage VDD 3.3 V option 2.97 3.3 3.63 V

2.5 V option 2.25 2.5 2.75 V

1.8 V option 1.71 1.8 1.89 V

Supply Current IDD CMOS, 100 MHz,

single-ended

—2126mA

LVDS

(output enabled)

—1923mA

LVPECL

(output enabled)

—3943mA

HCSL

(output enabled)

—4144mA

Tristate

(output disabled)

——18mA

Operating Temperature TA–40 — 85 oC

Table 2. Input Characteristics

VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC

Parameter Symbol Test Condition Min Typ Max Units

SDA, SCL Input Voltage High VIH 0.80 x VDD ——V

SDA, SCL Input Voltage Low VIL — — 0.20 x VDD V

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Si514

4 Rev. 1.2

Table 3. Output Clock Frequency Characteristics

VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC

Parameter Symbol Test Condition Min Typ Max Units

Programmable

Frequency Range

FOCMOS, Dual CMOS 0.1 — 212.5 MHz

FOLVDS/LVPECL/HCSL 0.1 — 250 MHz

Frequency

Reprogramming

Resolution

MRES — 0.026 — ppb

Frequency Range for

Small Frequency Change

(Continuous Glitchless

Output)

From center frequency –1000 — +1000 ppm

Settling time for Small

Frequency Change

<±1000 ppm from

center frequency

— — 100 µs

Settling time for Large

Frequency Change (Out-

put Squelched during Fre-

quency Transition)

>±1000 ppm from

center frequency

——10ms

Total Stability* Frequency Stability Grade C –30 — +30 ppm

Frequency Stability Grade B –50 — +50 ppm

Frequency Stability Grade A –100 — +100 ppm

Temperature Stability Frequency Stability Grade C –20 — +20 ppm

Frequency Stability Grade B –25 — +25 ppm

Frequency Stability Grade A –50 — +50 ppm

Startup Time TSU Minimum VDD until output

frequency (FO) within specification

——10ms

Disable Time TDFO < 10 MHz — — 40 µs

FO10 MHz — — 5 µs

Enable Time TEFO < 10 MHz — — 60 µs

FO10 MHz — — 20 µs

*Note: Total stability includes initial accuracy, operating temperature, supply voltage change, load change, shock and

vibration (not under operation), and 10 years aging at 40 oC.

, . SILIEDN LABS

Si514

Rev. 1.2 5

Table 4. Output Clock Levels and Symmetry

VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC

Parameter Symbol Test Condition Min Typ Max Units

CMOS Output Logic

High

VOH 0.85 x VDD ——V

CMOS Output Logic

Low

VOL — — 0.15 x VDD V

CMOS Output Logic

High Drive

IOH 3.3 V –8 — — mA

2.5 V –6 — — mA

1.8 V –4 — — mA

CMOS Output Logic

Low Drive

IOL 3.3 V 8 — — mA

2.5 V 6 — — mA

1.8 V 4 — — mA

CMOS Output

Rise/Fall Time

(20 to 80% VDD)

TR/TF0.1 to 125 MHz,

CL = 15 pF

—0.81.2ns

0.1 to 212.5 MHz,

CL = no load

—0.60.9ns

LVPECL/HCSL Out-

put Rise/Fall Time

(20 to 80% VDD)

TR/TF——565ps

LVDS Output Rise/Fall

Time (20 to 80% VDD)

TR/TF——800ps

LVPECL Output Com-

mon Mode

VOC 50  to VDD – 2 V, single-ended — VDD –

1.4 V

—V

LVPECL Output Swing VO50  to VDD – 2 V, single-ended 0.55 0.8 0.90 VPPSE

LVDS Output Common

Mode

VOC 100  line-line, 3.3/2.5 V 1.13 1.23 1.33 V

100  line-line, 1.8 V 0.83 0.92 1.00 V

LVDS Output Swing VOSingle-ended 100 differential

termination

0.25 0.35 0.45 VPPSE

HCSL Output

Common Mode

VOC 50 to ground 0.35 0.38 0.42 V

HCSL Output Swing VOSingle-ended 0.58 0.73 0.85 VPPSE

Duty Cycle DC 485052%

($9 SILICON LABS

Si514

6 Rev. 1.2

Table 5. Output Clock Jitter and Phase Noise (LVPECL)

VDD = 2.5 or 3.3 V ±10%, TA = –40 to +85 oC; Output Format = LVPECL

Parameter Symbol Test Condition Min Typ Max Units

Period Jitter (RMS) JPRMS 10 k samples1 ——1.3ps

Period Jitter (Pk-Pk) JPPKPK 10 k samples1 ——11ps

Phase Jitter (RMS) φJ 1.875 MHz to 20 MHz integration

bandwidth2 (brickwall)

— 0.31 0.5 ps

12 kHz to 20 MHz integration band-

width2

—0.81.0ps

Phase Noise,

156.25 MHz

φN 100 Hz — –86 — dBc/Hz

1 kHz — –109 — dBc/Hz

10 kHz — –116 — dBc/Hz

100 kHz — –123 — dBc/Hz

1 MHz — –136 — dBc/Hz

Additive RMS

Jitter Due to Power

Supply Noise3

JPSR 10 kHz sinusoidal noise — 3.0 — ps

100 kHz sinusoidal noise — 3.5 — ps

500 kHz sinusoidal noise — 3.5 — ps

1 MHz sinusoidal noise — 3.5 — ps

Spurious SPR LVPECL output, 156.25 MHz,

offset > 10 kHz

—–75—dBc

Notes:

1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,

212.5, 250 MHz.

2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 MHz.

3. 156.25 MHz. Increase in jitter on output clock due to sinewave noise added to VDD (2.5/3.3 V = 100 mVPP).

, . SILIEDN LABS

Si514

Rev. 1.2 7

Table 6. Output Clock Jitter and Phase Noise (LVDS)

VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC; Output Format = LVDS

Parameter Symbol Test Condition Min Typ Max Unit

Period Jitter

(RMS)

JPRMS 10k samples1 ——2.1ps

Period Jitter

(Pk-Pk)

JPPKPK 10k samples1 ——18ps

Phase Jitter

(RMS)

φJ 1.875 MHz to 20 MHz integration

bandwidth2 (brickwall)

—0.250.55ps

12 kHz to 20 MHz integration band-

width2 (brickwall)

—0.81.0ps

Phase Noise,

156.25 MHz

φN 100 Hz — –86 — dBc/Hz

1 kHz — –109 — dBc/Hz

10 kHz — –116 — dBc/Hz

100 kHz — –123 — dBc/Hz

1 MHz — –136 — dBc/Hz

Spurious SPR LVPECL output, 156.25 MHz,

offset>10 kHz

—–75—dBc

Notes:

1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,

212.5, 250 MHz.

2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 MHz.

($9 SILICON LABS

Si514

8 Rev. 1.2

Table 7. Output Clock Jitter and Phase Noise (HCSL)

VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC; Output Format = HCSL

Parameter Symbol Test Condition Min Typ Max Unit

Period Jitter

(RMS)

JPRMS 10k samples*——1.2ps

Period Jitter

(Pk-Pk)

JPPKPK 10k samples*——11ps

Phase Jitter

(RMS)

φJ 1.875 MHz to 20 MHz integration

bandwidth*(brickwall)

—0.250.30ps

12 kHz to 20 MHz integration band-

width* (brickwall)

—0.81.0ps

Phase Noise,

156.25 MHz

φN 100 Hz — –90 — dBc/Hz

1kHz — –112 — dBc/Hz

10 kHz — –120 — dBc/Hz

100 kHz — –127 — dBc/Hz

1 MHz — –140 — dBc/Hz

Spurious SPR LVPECL output, 156.25 MHz,

offset>10 kHz

—–75—dBc

*Note: Applies to an output frequency of 100 MHz.

, . SILIEDN LABS

Si514

Rev. 1.2 9

Table 8. Output Clock Jitter and Phase Noise (CMOS, Dual CMOS)

VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC; Output Format = CMOS, Dual CMOS

Parameter Symbol Test Condition Min Typ Max Unit

Phase Jitter

(RMS)

φJ 1.875 MHz to 20 MHz integration

bandwidth2 (brickwall)

—0.250.35ps

12 kHz to 20 MHz integration band-

width2 (brickwall)

—0.81.0ps

Phase Noise,

156.25 MHz

φN 100 Hz — –86 — dBc/Hz

1 kHz — –108 — dBc/Hz

10 kHz — –115 — dBc/Hz

100 kHz — –123 — dBc/Hz

1 MHz — –136 — dBc/Hz

Spurious SPR LVPECL output, 156.25 MHz,

offset>10 kHz

—–75—dBc

Notes:

1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,

212.5 MHz.

2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 MHz.

Table 9. Environmental Compliance and Package Information

Parameter Conditions/Test Method

Mechanical Shock MIL-STD-883, Method 2002

Mechanical Vibration MIL-STD-883, Method 2007

Solderability MIL-STD-883, Method 2003

Gross and Fine Leak MIL-STD-883, Method 1014

Resistance to Solder Heat MIL-STD-883, Method 2036

Contact Pads Gold over Nickel

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Si514

10 Rev. 1.2

Table 10. Thermal Characteristics

Parameter Symbol Test Condition Value Units

CLCC, Thermal Resistance Junction to Ambient*JA Still air 110 °C/W

2x5 x 3.2 mm, Thermal Resistance Junction to Ambient*JA Still air 164 °C/W

*Note: Applies to 5 x 7 and 3.2 x 5 mm packages.

Table 11. Absolute Maximum Ratings1

Parameter Symbol Rating Units

Maximum Operating Temperature TAMAX 85 oC

Storage Temperature TS–55 to +125 oC

Supply Voltage VDD –0.5 to +3.8 V

Input Voltage (any input pin) VI–0.5 to VDD + 0.3 V

ESD Sensitivity (HBM, per JESD22-A114) HBM 2 kV

Soldering Temperature (Pb-free profile)2TPEAK 260 oC

Soldering Temperature Time at TPEAK (Pb-free profile)2TP 20–40 sec

Notes:

1. Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation or

specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended

periods may affect device reliability.

2. The device is compliant with JEDEC J-STD-020E.

Heating from the top onl will cause un—even healinq of component and can lead to part inteqrit lssues. ($9 SILIEDN LABS

Si514

Rev. 1.2 11

2. Solder Reflow and Rework Requirements for 2.5x3.2 mm Packages

Reflow of Silicon Labs' components should be done in a manner consistent with the IPC/JEDEC J-STD-20E

standard. The temperature of the package is not to exceed the classification Temperature provided in the standard.

The part should not be within -5°C of the classification or peak reflow temperature (TPEAK) for longer than 30

seconds. Key to maintaining the integrity of the component is providing uniform heating and cooling of the part

during reflow and rework. Uniform heating is achieved through having a preheat soak and controlling the

temperature ramps in the process. J-STD-20E provides minimum and maximum temperatures and times for the

preheat/Soak step that need to be followed, even for rework. The entire assembly area should be heated during

rework. Hot air should be flowed from both the bottom of the board and the top of the component. Heating from the

top only will cause un-even heating of component and can lead to part integrity issues. Temperature Ramp-up rate

are not to exceed 3°C/second. Temperature ramp-down rates from peak to final temperature are not to exceed

6°C/second. Time from 25°C to peak temperature is not to exceed 8 min for Pb-free solders.

Si514 r'D'W Fi d “ Frequency *’ PFD as; + + Fm" Oscillator _, t A 4 SOL . , . . . MilnﬂSVO] LP! [3.0] HS,D|V[9:D] LS,DIV[Z:0] SDA M7FVac[28‘0] LP2[3.U] IZC Control SILIEDN LABS

Si514

12 Rev. 1.2

3. Functional Description

The Si514 offers system designers a programmable, low jitter XO solution with exceptionally fine frequency tuning

resolution. To enable designers to take full advantage of this flexibility and performance, Silicon Laboratories

provides an easy-to-use evaluation kit and intuitive suite of Windows-based software utilities to simplify the Si514

programming process.

The Si5xx-PROG-EVB kit contains the Programmable Oscillator Software suite and an EVB Driver (USBXpress®)

for use with USB-equipped PCs. Go to

http://www.silabs.com/products/clocksoscillators/Pages/DevelopmentTools.aspx for more information.

Alternatively, “3.1. Programming a New Output Frequency” provides designers a detailed description, along with

examples, of the frequency programming requirements and process for designers who are interested in learning

more about the programming algorithms implemented within the Programmable Oscillator Software suite.

3.1. Programming a New Output Frequency

The output frequency (Fout) is determined by programming the feedback multiplier (M=M_Int.M_Frac), High-

Speed Divider (HS_DIV), and Low-Speed Divider (LS_DIV) according to the following formula:

Figure 1. Block Diagram of Si514

The value of the feedback multiplier M is adjustable in the following range:

65.04065041  M  78.17385866.

This keeps the VCO frequency within the range of 2080 MHz  FVCO  2500 MHz, since the VCO frequency is the

product of the internal fixed-frequency crystal (FXO) and the high-resolution 29-bit fractional multiplier (M). This 29-

bit resolution of M allows the VCO frequency to have a frequency tuning resolution of 0.026 ppb.

The device comes from the factory with a pre-programmed center frequency within the range of

100 kHz  FOUT 250 MHz, as specified by the 6-digit code in the part number. (See section “7. Ordering

Information” for more information.) To change from the factory-programmed frequency to a different value, the user

must follow one of two algorithms based on the magnitude of the frequency change.

“Small Frequency Change.” To change the frequency by < ±1000 ppm, the user must keep the same center

frequency and only update the value of M. Refer to section "3.2. Programming a Small Frequency Change (sub

±1000 ppm)" on page 13.

“Large Frequency Change.” To change the frequency by ±1000 ppm, the user must change the center

frequency. This may require updates to the output dividers (HS_DIV and/or LS_DIV) and possibly the LP1 and

Fout

FXO M

HS_DIV LS_DIV

--------------------------------------------------

where FXO 31.98MHz=

, . SILIEDN LABS

Si514

Rev. 1.2 13

LP2 values, in addition to updating the value of M, which requires the VCO to be recalibrated. Refer to section

"3.3. Programming a Large Frequency Change (> ±1000 ppm)" on page 14. Figure 2 provides a graphic

depiction of the difference between small and large frequency changes.

Figure 2. Small vs. Large Frequency Change Illustration

3.2. Programming a Small Frequency Change (sub ±1000 ppm)

The value of the feedback multiplier, M is the only parameter that needs to be updated for output frequency

changes less than ±1000 ppm from the center frequency (recalibrating the VCO is NOT required). This enables

the output to remain continuous during the change. For example, the output frequency can be swept continuously

between 148.5 MHz and 148.352 MHz (i.e., –0.997 ppm) with no output discontinuities or glitches by changing M

in either multiple steps or in a single step. For small frequency changes, each update of M requires 100 µs to settle.

Note: It is not possible to implement a frequency change ≥ ±1000 ppm using multiple small frequency changes

without changing the center frequency and recalibrating the VCO.

Use the following procedure to make small frequency changes:

1. If the current value of M is already known, then skip to step 2; else, using the serial port, read the current M

value (Registers 5-9).

2. Calculate the new value of M as follows (all values are in decimal format):

a. Mcurrent = M_Int + M_Frac/229 (Eq 2.2)

b. Mnew = Mcurrent x Fout_new / Fout_current (Eq 2.3)

c. M_Intnew = INT[Mnew]* (Eq 2.4)

d. M_Fracnew = (Mnew – INT[Mnew]) x 229 (Eq 2.5)

*Where INT[n] rounds n down to the nearest integer (e.g., INT[3.9] = 3)

3. Using the

port, write the new value of M_Frac[23:0] (Not all registers need to be updated.)

(Registers: 5, 6, 7)

4. If necessary, write new value of M_Int[2:0] and M_Frac[28:24] register. (Register 8)

5. Write M_Int[8:3]. (Register 9) Frequency changes take effect when M_Int[8:3] is written.

Example 2.1:

An Si514 generating a 148.5 MHz clock must be reconfigured “on-the-fly” to generate a 148.352 MHz clock. This

represents a change of –0.996.633 ppm which is within the ±1000 ppm window.

1. Read the current value of M:

a. Register 5 = 0xD3 (M_Frac[7:0])

b. Register 6 = 0x65 (M_Frac[15:8])

c. Register 7 = 0x7C (M_Frac[23:16])

FVCO_MIN

(2080 MHz)

FVCO_MAX

(2500 MHz)

Range of small

frequency change

Programming a new center frequency requires a VCO

calibration and the output should be squelched

FCENTER F'CENTER

Small Frequency Change

Large Frequency Change

FCENTER

+1000 ppm

FCENTER

-1000 ppm

($9 SILICON LABS

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14 Rev. 1.2

d. Register 8 = 0x49 (M_Int[2:0],M_Frac[28:24])

e. Register 9 = 0x09 (M_Int[8:3])

f. M_Int = 0b001001010 = 0x4A = 0d74

g. M_Frac = 0x097C65D3 = 159,147,475

h. M= M_Int + M_Frac/229 = 74 + 159,147,475/229 = 74.296435272321105

2. Calculate Mnew:

a. Mnew = 74.296435272321105 x 148.352/148.5 = 74.2223889933965

b. M_Intnew = 74 = 0x4A

c. M_Fracnew = 0.2223889933965 x 229 = 119,394,181 = 0x071DCF85

3. Write Mnew to Registers 5-7:

a. Register 5 = 0x85

b. Register 6 = 0xCF

c. Register 7 = 0x1D

4. Write Mnew to Register 8:

a. Register 8 = 0x47

5. Write Mnew to Register 9:

a. Register 9 = 0x09

3.3. Programming a Large Frequency Change (> ±1000 ppm)

Large frequency changes are those that vary the FVCO frequency by an amount greater than ±1000 ppm from an

operating FCENTER. Figure 2 illustrates the difference between large and small frequency changes. Changing from

FCENTER to F'

CENTER requires a calibration cycle that resets internal circuitry to establish F'CENTER as the new

operating center frequency. The below steps are recommended when performing large frequency changes:

1. Disable the output: Write OE register bit to a 0 (Register 132, bit2)

2. If using one of the standard frequencies listed in Table 12, then write the new LP1, LP2, M_Frac, M_Int,

HS_DIV and LS_DIV register values according to the table (be sure to write M_Int[8:3] (Register 9) after writing

to the M_Frac registers (Registers 5-8)). Skip to Step 9. If the desired frequency is not in the table, then follow

steps 4-8 below.

3. Determine the minimum value of LS_DIV (minimizing LS_DIV minimizes the number of dividers on the output

stage, thus minimizing jitter) according to the following formula:

a. LS_DIV = FVCO(MIN)/(FOUT x HS_DIV(MAX)) (Eq 2.6)

b. LS_DIV = 2080/(FOUT(MHz) x 1022) (Eq 2.7)

i. Since LS_DIV is restricted to: dividing by 1,2,4,8,16,32, choose the next largest value over the

result derived in Eq 2.7 (e.g., if result is 4.135, choose LS_DIV = 8)

4. Determine the minimum value for HS_DIV (this optimizes timing margins)

a. HS_DIV(MIN) = FVCO(MIN)/(FOUT x LS_DIV) (Eq 2.8)

b. HS_DIV(MIN) = 2080/(FOUT(MHz) x LS_DIV) (Eq 2.9)

i.HS_DIV(MIN) will be the next even number greater than or equal to the result derived in Eq 2.9

(keeping in the range of 10-1022)

Note: SPEED_GRADE_MIN (Reg 48) ≤ LS_DIV x HS_DIV ≤ SPEED_GRADE_MAX (Reg 49); If outside this range, the output

will be forced to the disabled state.

5. Determine a value for M according to the following formula (all values are in decimal format):

a. M = LS_DIV x HS_DIV x FOUT/FXO (Eq 2.10)

b. M = LS_DIV x HS_DIV x FOUT(MHz)/31.98 (Eq 2.11)

c. M_Int = INT[M] (Eq 2.12)

d. M_Frac = (M – INT[M]) x 229 (Eq 2.13)

, . SILIEDN LABS

Si514

Rev. 1.2 15

Table 12. Standard Frequency Table

DEC HEX

Fout

(MHz)

M M_INT M_FRAC HSDIV LSDIV LP1 LP2 M_INTX M_FRACX HSDIVX LSDIVX LP1_X LP2_X

0.100000 65.04065041 65 21824021 650 5 2 2 41 14D0215 28A 5 2 2

1.544000 65.08167605 65 43849494 674 1 2 2 41 29D1716 2A2 1 2 2

2.048000 65.06466542 65 34716981 1016 0 2 2 41 211BD35 3F8 0 2 2

4.096000 65.06466542 65 34716981 508 0 2 2 41 211BD35 1FC 0 2 2

4.915200 65.16712946 65 89726943 424 0 2 2 41 5591FDF 1A8 0 2 2

19.440000 65.65103189 65 349520087 108 0 2 3 41 14D540D7 6C 0 2 3

24.576000 66.08930582 66 47945695 86 0 2 3 42 2DB97DF 56 0 2 3

25.000000 65.66604128 65 357578187 84 0 2 3 41 155035CB 54 0 2 3

27.000000 65.85365854 65 458304437 78 0 2 3 41 1B512BB5 4E 0 2 3

38.880000 65.65103189 65 349520087 54 0 2 3 41 14D540D7 36 0 2 3

44.736000 67.14596623 67 78365022 48 0 2 3 43 4ABC15E 30 0 2 3

54.000000 67.54221388 67 291098862 40 0 2 3 43 1159D0EE 28 0 2 3

62.500000 66.44777986 66 240399983 34 0 2 3 42 E54366F 22 0 2 3

65.536000 65.57698562 65 309766794 32 0 2 3 41 1276AA8A 20 0 2 3

74.175824 69.58332458 69 313169998 30 0 3 3 45 12AA984E 1E 0 3 3

74.250000 69.65290807 69 350527350 30 0 3 3 45 14E49F76 1E 0 3 3

77.760000 68.08255159 68 44319550 28 0 3 3 44 2A4433E 1C 0 3 3

106.250000 66.44777986 66 240399983 20 0 2 3 42 E54366F 14 0 2 3

125.000000 70.3564728 70 191379875 18 0 3 3 46 B6839A3 12 0 3 3

148.351648 74.22221288 74 119299633 16 0 3 4 4A 71C5E31 10 0 3 4

148.500000 74.29643527 74 159147475 16 0 3 4 4A 97C65D3 10 0 3 4

150.000000 65.66604128 65 357578187 14 0 2 3 41 155035CB E 0 2 3

155.520000 68.08255159 68 44319550 14 0 3 3 44 2A4433E E 0 3 3

156.250000 68.40212633 68 215889929 14 0 3 3 44 CDE3809 E 0 3 3

212.500000 66.44777986 66 240399983 10 0 2 3 42 E54366F A 0 2 3

250.000000 78.17385866 78 93339658 10 0 4 4 4E 590400A A 0 4 4

($9 SILICON LABS

Si514

16 Rev. 1.2

6. Determine values for LP1 and LP2 according to Table 13:

7. Write new LP1, LP2, M_Frac, M_Int, HS_DIV and LS_DIV register values (be sure to write M_Int[8:3] (Register

9) after writing to the M_Frac registers (Registers 5-8)

8. Write FCAL (Register 132, bit 0) to a 1 (this bit auto-resets, so it will always read as 0).

9. Enable the output: Write OE register bit to a 1.

The Si514 does not automatically detect large frequency changes. The user needs to assert the FCAL register bit

to initiate the calibration cycle required to re-center the VCO around the new frequency. Large frequency changes

are discontinuous and output may skip to intermediate frequencies or generate glitches. Resetting the OE bit

before FCAL will prevent intermediate frequencies from appearing on the output while Si514 completes a

calibration cycle and settles to F'CENTER. Settling time for large frequency changes is 10 msec maximum.

Example 2.2:

The user has a part that is programmed with SPEED_GRADE_MIN = 20 and SPEED_GRADE_MAX = 250 that is

programmed from the factory for FOUT = 50 MHz and wants to change to an STS-1 rate of 51.84 MHz. This

represents a change of +36,800 ppm which exceeds ±1000 ppm and therefore requires a large frequency change

process.

1. Write Reg 132, bit 2 to a 0 to disable the output.

2. Since 51.84 MHz is not in Table 2.1, the divider parameters must be calculated.

3. Calculate LS_DIV by using Eq 2.7:

a. LS_DIV = 2080/(51.84 x 1022) = 0.039

b. Since 0.039 < 1, use a divide-by-one (bypass), therefore LS_DIV = 0

4. Calculate HS_DIV(MIN) by using Eq 2.9:

a. HS_DIV(MIN) = 2080/(51.84 x 1) = 40.123

b. Since 40.123 > 40, use HS_DIV(MIN) = 42 = 0x2A

5. From Eq 2.11:

a. M = 1 x 42 x 51.84/31.98 = 68.08255159474

b. M_Int = 68 = 0x44

c. M_Frac = 0.08255259474 x 229 = 44,320,087 = 0x2A44557

6. From Table 2.2:

a. LP1 = 3

b. LP2 = 3

Table 13. LP1, LP2 Values

Fvco_max Fvco_min M_max M_min LP1 LP2

2500000000.00000 2425467616.18572 78.173858662 75.843265046 4 4

2425467616.18572 2332545246.89005 75.843265046 72.937624981 3 4

2332545246.89005 2170155235.53450 72.937624981 67.859763463 3 3

2170155235.53450 2087014168.27005 67.859763463 65.259980246 2 3

2087014168.27005 2080000000.00000 65.259980246 65.040650407 2 2

, . SILIEDN LABS

Si514

Rev. 1.2 17

7. Write Registers 0, 5-11:

a. Register 0 = 0x33

b. Register 5 = 0x57 (M_Frac[7:0])

c. Register 6 = 0x45 (M_Frac[15:8])

d. Register 7 = 0xA4 (M_Frac[23:16])

e. Register 8 = 0x42 (M_Int[2:0],M_Frac[28:24])

f. Register 9 = 0x05 (M_Int[8:3])

g. Register 10 = 0x2A

h. Register 11 = 0x00

8. Calibrate the VCO by writing Register 132, bit 0 to a 1.

9. Enable the output by writing Register 132, bit 2 to a 1.

[15:8] = 0000000 00 ($9 SILICON LABS

Si514

18 Rev. 1.2

4. All-Digital PLL Applications

The Si514 uses a high resolution divider M that enables fine frequency adjustments with resolution better than

0.026 parts per billion. Fine frequency adjustments are useful when making frequency corrections that compensate

for changing ambient conditions, long term aging or when locking the Si514 to an input clock reference. Figure 3

shows a typical implementation using a system IC such as an FPGA to control the output of the Si514 in a phase-

locked application. Refer to “AN575: An Introduction to FPGA-Based ADPLLs” for more information.

Figure 3. All-Digital PLL Application Using Si514 with Dual CMOS Output

Since small frequency changes must be within ±1000 ppm of the center frequency, HS_DIV and LS_DIV remain

constant. The below expression can be used to calculate a new M2 divider value based on a desired output

frequency shift, where ∆FOUT is in ppm.

Some systems, particularly those that use feedback control, can simplify the computation by implementing an

approximate frequency change based on toggling a bit position or adding/subtracting a bit to the existing M_Frac

value. Since M ranges approximately ±10% between 65.04065041 and 78.17385866, the effect of changing

M_Frac by a single bit depends only slightly on the absolute value of M.

For M=71 near the midpoint of the range, toggling M_Frac[0] changes the output frequency by 0.026 ppb. Each

higher order bit doubles the influence such that toggling M_Frac[1] is 0.052 ppb, M_Frac[2] is 0.1 ppb, etc. Figure 4

shows this trend across multiple registers generalized to M_Frac[N]. Coarse changes greater than ±1.7 ppm are

possible but most applications require finer transitions. Toggling each bit involves incrementing or decrementing

the bit position. Writing M_Int[8:3] in register 9 completes the operation.

Figure 4. Output Frequency Change When Toggling M_Frac[N], M=71

I2C Control

Any Frequency

DSPLL

CLK_OUT

Si514

FPGA

I2C

Master

Command

Conversion

Loop

Filter

÷SCL

SDA

Fin

M2M11FOUT 10 6–

–=

M_Int[8:0] = 000100111

M = 71.000000000000

M_Frac[28:0] = 00000000000000000000000000000

M_Frac[23:16] = 00000000

M_Frac[15:8] = 00000000

M_Frac[7:0] = 00000000

0.026ppb

6.7ppb

1.7ppm

, . SILIEDN LABS

Si514

Rev. 1.2 19

5. User Interface

5.1. Register Map

Table 14 displays the Si514 user register map. Registers not shown are reserved. Registers with reserved bits are

read-modify-write.

Table 14. User Register Map

Address Bit

76543210

0LP1[3:0] LP2[3:0]

5M_Frac [7:0]

6M_Frac [15:8]

7M_Frac [23:16]

8M_Int [2:0] M_Frac [28:24]

9M_Int [8:3]

10 HS_DIV [7:0]

11 LS_DIV [ 2:0] HS_DIV [9:8]

14 OE_STATE [1:0]

128 RST

132 OE FCAL

($9 SILICON LABS

Si514

20 Rev. 1.2

5.2. Register Detailed Description

Note: Registers not shown are reserved. Registers with reserved bits are read-modify-write.

Bit 76543210

Name LP1[3:0] LP2[3:0]

Type R/W R/W

Default Varies Varies

Bit Name Function

7:4 LP1[3:0] Sets loop compensation factor LP1. Value depends on VCO frequency.

3:0 LP2[3:0] Sets loop compensation factor LP2. Value depends on VCO frequency.

Bit 76543210

Name M_Frac[7:0]

Type R/W

Default Varies

Bit Name Function

7:0 M_Frac[7:0] Fractional part of feedback divider M that sets up the output frequency. Frequency

updates take effect when M_Int[8:3] is written.

Bit 76543210

Name M_Frac[15:8]

Type R/W

Default Varies

Bit Name Function

7:0 M_Frac[15:8] Fractional part of feedback divider M that sets up the output frequency. Frequency

updates take effect when M_Int[8:3] is written.

, . SILIEDN LABS

Si514

Rev. 1.2 21

Bit 76543210

Name M_Frac[23:16]

Type R/W

Default Varies

Bit Name Function

7:0 M_Frac[23:16] Fractional part of feedback divider M that sets up the output frequency. Frequency

updates take effect when M_Int[8:3] is written.

Bit 76543210

Name M_Int[2:0] M_Frac[28:24]

Type R/W R/W

Default Varies Varies

Bit Name Function

7:5 M_Int[2:0] Integer part of feedback divider M that sets the output frequency. Frequency updates

take effect when M_Int[8:3] is written.

4:0 M_Frac[28:24] Fractional part of feedback divider M that sets up the output frequency. Frequency

updates take effect when M_Int[8:3] is written.

($9 SILICON LABS

Si514

22 Rev. 1.2

Bit 76543210

Name M_Int[8:3]

Type R/W R/W R/W

Default Varies

Bit Name Function

7:6 Reserved

5:0 M_Int[8:3] Integer part of feedback divider M that sets the output frequency. Frequency updates

take effect when M_Int[8:3] is written.

Bit 76543210

Name HS_DIV[7:0]

Type R/W

Default Varies

Bit Name Function

7:0 HS_DIV[7:0] Integer divider that divides VCO frequency and provides output to LS_DIV. Follow the

large frequency change procedure when updating. The allowed values are even num-

bers in the range from 10 to 1022 (i.e., 10, 12, 14, 16, ...., 1022). The decimal value

represents the actual divide value (i.e. 12 means divide-by-12).

, . SILIEDN LABS

Si514

Rev. 1.2 23

Bit 76543210

Name LS_DIV[2:0] HS_DIV[9:8]

Type R/W R/W R/W R/W R/W

Default Varies Varies

Bit Name Function

7 Reserved

6:4 LS_DIV[2:0] Last output divider stage. Used during large frequency changes. To update, follow

large frequency change procedure. LS_DIV value updates asynchronously.

000: divide-by-1

001: divide-by-2

010: divide-by-4

011: divide-by-8

100: divide-by-16

101: divide-by-32

All others reserved.

3:2 Reserved

1:0 HS_DIV[9:8] Integer divider that divides VCO frequency and provides output to LS-DIV. Follow the

large frequency change procedure when updating. The allowed values are even num-

bers in the range from 10 to 1022 (i.e., 10, 12, 14, 16, ..., 1022). The decimal value

represents the actual divide value (i.e., 12 means divide-by-12).

Bit 76543210

Name OE_STATE[1:0]

Type R/W R/W R/W R/W R/W R/W R/W

Default 0 0

Bit Name Function

7:6 Reserved

5:4 OE_STATE[1:0] Sets logic state of output when output disabled.

00: high impedance

10: logic low when output disabled

01: logic high when output disabled

11: reserved

3:0 Reserved

($9 SILICON LABS

Si514

24 Rev. 1.2

Bit 76543210

Name RST

Type R/WR/WR/WR/WR/WR/WR/WR/W

Default 0

Bit Name Function

7RSTGlobal Reset.

Resets all register values to default values. Self-clearing.

6:0 Reserved

Bit 76543210

Name OE FCAL

Type R/W R/W R/W R/W R/W R/W R/W R/W

Default 1 0

Bit Name Function

7:3 Reserved

2OEOutput Enable.

OE can stop in high, low or high impedance state.

1: Output driver enabled.

0: Output driver powered down. OE_STATE register determines output state when dis-

abled.

1 Reserved

0 FCAL Initiates frequency calibration cycle. Necessary when making large frequency

changes. Frequency calibration cycle takes 10 msec maximum. To prevent intermedi-

ate frequencies on the output, set disable output using OE register. Self-clearing.

, . SILIEDN LABS

Si514

Rev. 1.2 25

5.3. I2C Interface

Configuration and operation of the Si514 is controlled by reading and writing to the RAM space using the

interface. The device operates in slave mode with 7-bit addressing and can operate in Standard-Mode (100 kbps)

or Fast-Mode (400 kbps). Burst data transfer with auto address increments are also supported.

The

bus consists of a bidirectional serial data line (SDA) and a serial clock input (SCL). Both the SDA and SCL

pins must be connected to the VDD supply via an external pull-up as recommended by the

specification. The

Si514 7-bit

slave address is user-customized during the part number configuration process. See "6. Pin

Descriptions" on page 27 for more details.

Data is transferred MSB first in 8-bit words as specified by the

specification. A write command consists of a 7-

bit device (slave) address + a write bit, an 8-bit register address, and 8 bits of data as shown in Figure 5.

A write burst operation is also shown where every additional data word is written using an auto-incremented

address.

Figure 5. I2C Write Operation

A read operation is performed in two stages. A data write is used to set the register address, then a data read is

performed to retrieve the data from the set address. A read burst operation is also supported. This is shown in

Figure 6.

1 – Read

0 – Write

A – Acknowledge (SDA LOW)

N – Not Acknowledge (SDA HIGH)

S – START condition

P – STOP condition

From slave to master

From master to slave

Write Operation – Single Byte

S 0 A Reg Addr [7:0]Slv Addr [6:0] AData [7:0] PA

Write Operation - Burst (Auto Address Increment)

Reg Addr +1

S 0 A Reg Addr [7:0]Slv Addr [6:0] AData [7:0] AData [7:0] PA

DD ($9 SILICON LABS

Si514

26 Rev. 1.2

Figure 6. I2C Read Operation

The timing specifications and timing diagram for the

bus is compatible with the

-Bus standard. SDA timeout

is supported for compatibility with SMBus interfaces.

The

bus can be operated at a bus voltage of 1.71 to 3.63 V and is 3.3 V tolerant.

1 – Read

0 – Write

A – Acknowledge (SDA LOW)

N – Not Acknowledge (SDA HIGH)

S – START condition

P – STOP condition

From slave to master

From master to slave

Read Operation – Single Byte

S 0 A Reg Addr [7:0]Slv Addr [6:0] A P

Read Operation - Burst (Auto Address Increment)

Reg Addr +1

S 1 ASlv Addr [6:0] Data [7:0] PN

S 0 A Reg Addr [7:0]Slv Addr [6:0] A P

S 1 ASlv Addr [6:0] Data [7:0] A PNData [7:0]

SILIEDN LABS

Si514

Rev. 1.2 27

6. Pin Descriptions

6.1. Dual CMOS (1:2 Fanout Buffer)

Dual CMOS output format ordering options support either complementary or in-phase output signals. This feature

enables replacement of multiple XOs with a single Si514 device.

Figure 7. Integrated 1:2 CMOS Buffer Supports Complementary or In-Phase Outputs

Table 15. Si514 Pin Descriptions

Pin Name Function

1SDA I2C Serial Data.

2SCL I2C Serial Clock.

3GND Electrical and Case Ground.

4CLK+ Clock Output.

5CLK- Complementary clock output (LVPECL, LVDS, HCSL, and

Complementary dual CMOS formats).

Clock output for in-phase dual CMOS format.

No connect (N/C) for single-ended CMOS format.

6 VDD Power Supply Voltage.

4GND

SCL

VDD

CLK+

CLK–

SDA

Complementary

Outputs

In-Phase

Outputs

FT? wwwsi‘abs cnmNCXOPanNumher ($9 SILICON LABS

Si514

28 Rev. 1.2

7. Ordering Information

The Si514 supports a wide variety of options including startup frequency, stability, output format, and VDD. Specific

device configurations are programmed into the Si514 at time of shipment. Configurations can be specified using

the Part Number Configuration chart below. Silicon Labs provides a web browser-based part number configuration

utility to simplify this process. To access this tool refer to www.silabs.com/oscillators and click “Customize” in the

product table. The Si514 XO series is supplied in industry-standard, RoHS-compliant, 2.5 x 3.2 mm, 3.2 x 5.0 mm,

and 5 x 7 mm packages. Tape and reel packaging is an ordering option.

Figure 8. Part Number Convention

Example orderable part number: 514ECB000107AAG supports 2.5 V LVPECL, ±30 ppm total stability, user

programmable output frequency range from 100 kHz to 170 MHz, 5x7 mm package and –40 to 85 °C temperature

range. The frequency code designates 10 MHz startup with I2C address of 0x55. Refer to www.silabs.com/VCXO

lookup to look up the attributes of any Silicon Labs orderable XO/VCXO part number.

Note: CMOS and Dual CMOS maximum frequency is 212.5 MHz.

XX514 X XXXXXXX

3rd Option Code:

Frequency Grade

1st Option Code:

Output Format

2nd Option Code:

Frequency Stability

Total Temperature

A ±100ppm ±50ppm

B ±50ppm ±25ppm

C ±30ppm ±20ppm

Package Option

Dimensions

A 5 x 7 mm

B 3.2 x 5 mm

VDD Output Format

A 3.3V LVPECL

B3.3V LVDS

C3.3V CMOS

D 3.3V HCSL

E 2.5V LVPECL

F2.5V LVDS

G2.5V CMOS

H 2.5V HCSL

J1.8V LVDS

K1.8V CMOS

L 1.8V HCSL

M 3.3V Dual CMOS (In-phase)

N 3.3V Dual CMOS (Complementary)

P 2.5V Dual CMOS (In-phase)

Q 2.5V Dual CMOS (Complementary)

R 1.8V Dual CMOS (In-phase)

S 1.8V Dual CMOS (Complementary)

Series Output Format Package

514 LVPECL, LVDS, HCSL,

CMOS, Dual CMOS 6-pin

Code Description

xxxxxx

The Si514 supports a user-defined start-up

frequency which must be in the same range as

specified by the Frequency Grade code. A

user-defined, 7-bit I2C address is supported.

Each unique start-up frequency/I2C address

combination is assigned a 6-digit code by:

www.silabs.com/VCXOPartNumber.

6-digit Frequency and Default I2C Address Code

AGR

A = Revision: A

G = Temp Range: -40°C to 85°C

R = Tape & Reel; Blank = &RLO7DSH

CMOS (MHz) LVPECL, LVDS, HCSL (MHz)

A 0.1 to 212.5 0.1 to 250

B 0.1 to 170 0.1 to 170

C 0.1 to 125 0.1 to 125

& [mm

m 1 mm mm mm\ l—I—mm c A 7' mx c \ S EAYING PLANE , . SILIEDN LABS

Si514

Rev. 1.2 29

8. Package Outline Diagram: 5 x 7 mm, 6-pin

Figure 9 illustrates the 5 x 7 mm, 6-pin package details for the Si514. Table 16 lists the values for the dimensions

shown in the illustration.

Figure 9. Si514 Outline Diagram

Table 16. Package Diagram Dimensions (mm)

Dimension Min Nom Max

A 1.50 1.65 1.80

b 1.30 1.40 1.50

c 0.50 0.60 0.70

D 5.00 BSC

D1 4.30 4.40 4.50

e 2.54 BSC

E 7.00 BSC

E1 6.10 6.20 6.30

H 0.55 0.65 0.75

L 1.17 1.27 1.37

L1 0.05 0.10 0.15

p1.80—2.60

R0.70 REF

aaa 0.15

bbb 0.15

ccc 0.10

ddd 0.10

eee 0.05

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

($9 SILICON LABS

Si514

30 Rev. 1.2

9. PCB Land Pattern: 5 x 7 mm, 6-pin

Figure 10 illustrates the 5 x 7 mm, 6-pin PCB land pattern for the Si514. Table 17 lists the values for the

dimensions shown in the illustration.

Figure 10. Si514 PCB Land Pattern

Table 17. PCB Land Pattern Dimensions (mm)

Dimension (mm)

C1 4.20

E2.54

X1 1.55

Y1 1.95

Notes:

General

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.

3. This Land Pattern Design is based on the IPC-7351 guidelines.

4. All dimensions shown are at Maximum Material Condition (MMC). Least

Material Condition (LMC) is calculated based on a Fabrication Allowance of

0.05 mm.

Solder Mask Design

5. All metal pads are to be non-solder mask defined (NSMD). Clearance

between the solder mask and the metal pad is to be 60 µm minimum, all the

way around the pad.

Stencil Design

6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls

should be used to assure good solder paste release.

7. The stencil thickness should be 0.125 mm (5 mils).

8. The ratio of stencil aperture to land pad size should be 1:1.

Card Assembly

9. A No-Clean, Type-3 solder paste is recommended.

10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020

specification for Small Body Components.

1x ‘—‘ A We CA WW’ [E] 17* +i’5 E1 ex c I 4 J HEW? a m ax H IR W L SEATING PLANE ﬂ, , . SILIEDN LABS

Si514

Rev. 1.2 31

10. Package Outline Diagram: 3.2 x 5.0 mm, 6-pin

Figure illustrates the 3.2 x 5 mm package details for the Si514. Table 18 lists the values for the dimensions shown

in the illustration.

Figure 11. Si514 Outline Diagram

Table 18. Package Diagram Dimensions (mm)

Dimension Min Nom Max

A1.061.171.33

b0.540.640.74

c0.350.450.55

D 3.20 BSC

D1 2.55 2.60 2.65

e 1.27 BSC

E 5.00 BSC

E1 4.35 4.40 4.45

H0.450.550.65

L0.800.901.00

L1 0.05 0.10 0.15

p1.171.271.37

R0.32 REF

aaa 0.15

bbb 0.15

ccc 0.10

ddd 0.10

eee 0.05

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

($9 SILICON LABS

Si514

32 Rev. 1.2

11. PCB Land Pattern: 3.2 x 5.0 mm, 6-pin

Figure 12 illustrates the 3.2 x 5.0 mm PCB land pattern for the Si514. Table 19 lists the values for the dimensions

shown in the illustration.

Figure 12. Si514 Recommended PCB Land Pattern

Table 19. PCB Land Pattern Dimensions (mm)

Dimension (mm)

C1 2.60

E1.27

X1 0.80

Y1 1.70

Notes:

General

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.

3. This Land Pattern Design is based on the IPC-7351 guidelines.

4. All dimensions shown are at Maximum Material Condition (MMC). Least Material

Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.

Solder Mask Design

5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the

solder mask and the metal pad is to be 60 µm minimum, all the way around the

pad.

Stencil Design

6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls

should be used to assure good solder paste release.

7. The stencil thickness should be 0.125 mm (5 mils).

8. The ratio of stencil aperture to land pad size should be 1:1.

Card Assembly

9. A No-Clean, Type-3 solder paste is recommended.

10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020

specification for Small Body Components.



mm mmm mun mm \ E] (A2) —_(Av) —sx L GDIOCAB 1 mm cumin INDEX m _/ E (sanmvliw) -—1[ same mu: SILIEDN LABS

Si514

Rev. 1.2 33

12. Package Outline Diagram: 2.5 x 3.2 mm, 6-pin

Figure 13 illustrates the package details for the 2.5 x 3.2 mm Si514. Table 20 lists the values for the dimensions

shown in the illustration.

Figure 13. Si514 Outline Diagram

($9 SILICON LABS

Si514

34 Rev. 1.2

Table 20. Package Diagram Dimensions (mm)

Dimension Min Nom Max

A— — 1.1

A1 0.26 REF

A2 0.7 REF

W0.65 0.7 0.75

D 3.20 BSC

e 1.25 BSC

E 2.50 BSC

M 0.30 BSC

L 0.45 0.5 0.55

D1 2.5 BSC

E1 1.65 BSC

SE 0.825 BSC

aaa 0.1

bbb 0.2

ddd 0.08

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

C1 X1 Dimension , . SILIEDN LABS

Si514

Rev. 1.2 35

13. PCB Land Pattern: 2.5 x 3.2 mm, 6-pin

Figure 14 illustrates the 2.5 x 3.2 mm PCB land pattern for the Si514. Table 21 lists the values for the dimensions

shown in the illustration.

Figure 14. Si514 Recommended PCB Land Pattern

Table 21. PCB Land Pattern Dimensions (mm)

Dimension (mm)

C1 1.9

E2.50

X1 0.70

Y1 1.05

Notes:

General

3. All dimensions shown are at Maximum Material Condition (MMC). Least Material

Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.

4. This Land Pattern Design is based on the IPC-7351 guidelines.

Solder Mask Design

5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the

solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.

Stencil Design

6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be

used to assure good solder paste release.

7. The stencil thickness should be 0.125 mm (5 mils).

8. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.

Card Assembly

9. A No-Clean, Type-3 solder paste is recommended.

10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification

for Small Body Components.

($9 SILICON LABS

Si514

36 Rev. 1.2

14. Top Marking

Use the part number configuration utility located at: www.silabs.com/VCXOpartnumber to cross-reference the mark

code to a specific device configuration.

14.1. Si514 Top Marking

14.2. Top Marking Explanation

Mark Method: Laser

Line 1 Marking: 4 = Si514

CCCCC = Mark Code

4CCCCC

Line 2 Marking: TTTTTT = Assembly Manufacturing Code TTTTTT

Line 3 Marking: Pin 1 indicator. Circle with 0.5 mm diameter;

left-justified

YY = Year.

WW = Work week.

Characters correspond to the year and

work week of package assembly.

YYWW

4CCCCC

TTTTTT

YYWW

, . SILIEDN LABS

Si514

Rev. 1.2 37

REVISION HISTORY

Revision 1.2

June, 2018

Changed “Trays” to “Coil Tape” in Ordering Guide.

Revision 1.1

December, 2017

Added new 2.5 x 3.2 mm package.

Revision 1.0

Updated Table 1 on page 3.

Updates to supply current typical and maximum values for CMOS, LVDS, LVPECL and HCSL.

CMOS frequency test condition corrected to 100 MHz.

Updates to OE VIH minimum and VIL maximum values.

Updated Table 2 on page 3.

Dual CMOS nominal frequency maximum added.

Total stability footnotes clarified for 10 year aging at 40 °C.

Disable time maximum values updated.

Enable time parameter added.

Updated Table 3 on page 4.

CMOS output rise / fall time typical and maximum values updated.

LVPECL/HCSL output rise / fall time maximum value updated.

LVPECL output swing maximum value updated.

LVDS output common mode typical and maximum values updated.

HCSL output swing maximum value updated.

Duty cycle minimum and maximum values tightened to 48/52%.

Updated Table 5 on page 6.

Phase jitter test condition and maximum value updated.

Phase noise typical values updated.

Additive RMS jitter due to external power supply noise typical values updated.

Footnote 3 updated limiting the VDD to 2.5/3.3V

Added Tables 6, 7, 8 for LVDS, HCSL, CMOS, and Dual CMOS operations.

Moved Absolute Maximum Ratings table.

Added note to Figure 8 clarifying CMOS and Dual CMOS maximum frequency.

Updated Figure 9 outline diagram to correct pinout.

Updated “14. Top Marking” section and moved to page 36.

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