ANALOG
DEVICES
1.5 Ω On Resistance,
±15 V/12 V/±5 V, 4:1, iCMOS Multiplexer
Data Sheet ADG1404
Rev. B Document Feedback
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FEATURES
1.5 Ω on resistance
0.3 Ω on-resistance flatness
0.1 Ω on-resistance match between channels
Up to 400 mA continuous current
Fully specified at +12 V, ±15 V, and ±5 V
No VL supply required
3 V logic-compatible inputs
Rail-to-rail operation
14-lead TSSOP and 4 mm × 4 mm, 16-lead LFCSP
APPLICATIONS
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Communication systems
Relay replacement
FUNCTIONAL BLOCK DIAGRAM
S1
S2 D
S3
S4
A0 A1 EN
1 OF 4
DECODER
ADG1404
06816-001
Figure 1.
GENERAL DESCRIPTION
The ADG1404 is a complementary metal-oxide semiconductor
(CMOS) analog multiplexer, comprising four single channels
designed on an iCMOS® process. iCMOS (industrial CMOS) is
a modular manufacturing process that combines high voltage
CMOS and bipolar technologies. It enables the development of
a wide range of high performance analog ICs capable of 33 V
operation in a footprint that no previous generation of high
voltage devices achieve. Unlike analog ICs using conventional
CMOS processes, iCMOS components can tolerate high supply
voltages while providing increased performance, dramatically
lower power consumption, and reduced package size.
The on-resistance profile is very flat over the full analog input
range, ensuring excellent linearity and low distortion when
switching audio signals.
iCMOS construction ensures ultralow power dissipation,
making the device ideally suited for portable and battery-
powered instruments.
The ADG1404 switches one of four inputs to a common output,
D, as determined by the 3-bit binary address lines, A0, A1, and
EN. Logic 0 on the EN pin disables the device. Each switch
conducts equally well in both directions when on and has an
input signal range that extends to the supplies. In the off condi-
tion, signal levels up to the supplies are blocked. All switches
exhibit break-before-make switching action. Inherent in the
design is low charge injection for minimum transients when
switching the digital inputs.
PRODUCT HIGHLIGHTS
1. 2.6 Ω maximum on resistance over temperature.
2. Minimum distortion.
3. Ultralow power dissipation: <0.03 μW.
4. 14-lead TSSOP and 16-lead, 4 mm × 4 mm LFCSP package.
ADG1404 Data Sheet
Rev. B | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
15 V Dual Supply .......................................................................... 3
12 V Single Supply ........................................................................ 4
5 V Dual Supply ............................................................................ 5
Continuous Current, S or D .........................................................6
Absolute Maximum Ratings ............................................................7
ESD Caution...................................................................................7
Pin Configurations and Function Descriptions ............................8
Truth Table .....................................................................................8
Typical Performance Characteristics ..............................................9
Terminology .................................................................................... 12
Test Circuits ..................................................................................... 13
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
9/2016—Rev. A to Rev. B
Changes to Figure 3 .......................................................................... 8
Updated Outline Dimensions ....................................................... 16
Changes to Ordering Guide .......................................................... 16
3/2009—Rev. 0 to Rev. A
Changes to Power Requirements, IDD, Digital Inputs = 5 V
Parameter, Table 1 ............................................................................. 3
Changes to Power Requirements, IDD, Digital Inputs = 5 V
Parameter, Table 2 ............................................................................. 4
Updated Outline Dimensions ....................................................... 16
7/2008—Revision 0: Initial Version
Table L
Data Sheet ADG1404
Rev. B | Page 3 of 16
SPECIFICATIONS
15 V DUAL SUPPLY
VDD = 15 V ± 10%, VSS = −15 V± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VDD to VSS V
On Resistance (RON) 1.5 Ω typ VS = ±10 V, IS = −10 mA; see Figure 22
1.8 2.3 2.6 Ω max VDD = +13.5 V, VSS = −13.5 V
On-Resistance Match
Between Channels (ΔRON)
0.1 Ω typ VS = ±10 V, IS = −10 mA
0.18 0.19 0.21 Ω max
On-Resistance Flatness (RFLAT(ON)) 0.3 Ω typ VS = ±10 V, IS = −10 mA
0.36 0.4 0.45 Ω max
LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V
Source Off Leakage, IS (Off) ±0.03 nA typ VS = ±10 V, Vs =
∓
10 V; see Figure 23
±0.55 ±2 ±12.5 nA max
Drain Off Leakage, ID (Off) ±0.04 nA typ VS = ±10 V, Vs =
∓
10 V; see Figure 23
±0.55 ±4 ±30 nA max
Channel On Leakage, ID, IS (On) ±0.1 nA typ VS = VD = ±10 V; see Figure 24
±2 ±4 ±30 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINLor INH 0.005 µA typ VIN = VGND or VDD
±0.1
µA max
Digital Input Capacitance, CIN 3.5 pF typ
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION 150 ns typ RL = 300 Ω, CL = 35 pF
180 220 250 ns max VS = +10 V; see Figure 29
tON (EN) 100 ns typ RL = 300 Ω, CL = 35 pF
120 145 165 ns max VS = +10 V; see Figure 31
tOFF (EN) 110 ns typ RL = 300 Ω, CL = 35 pF
135 165 185 ns max VS = +10 V; see Figure 31
Break-Before-Make Time Delay, tBBM 35 ns typ RL = 300 Ω, CL = 35 pF
10 ns min VS1 = VS2 = 10 V; see Figure 30
Charge Injection
−20
pC typ
V
S
= 0 V, R
S
= 0 Ω, C
L
= 1 nF; see Figure 32
Off Isolation
70
dB typ
R
L
= 50 Ω, C
L
= 5 pF, f = 100 kHz; see Figure 25
Channel-to-Channel Crosstalk 82 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 27
Total Harmonic Distortion + Noise 0.011 % typ
R
L
= 110 Ω, 10 V p-p, f = 20 Hz to 20 kHz; see
Figure 28
−3 dB Bandwidth 55 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 26
Insertion Loss −0.17 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 26
CS (Off) 23 pF typ f = 1 MHz, VS = 0 V
CD (Off) 90 pF typ f = 1 MHz, VS = 0 V
CD, CS (On) 170 pF typ f = 1 MHz, VS = 0 V
POWER REQUIREMENTS
V
DD
= +16.5 V, V
SS
= −16.5 V
I
DD
0.001
µA typ
Digital inputs = 0 V or V
DD
1
µA max
IDD 170 µA typ Digital inputs = 5 V
285 µA max
ISS 0.001 µA typ Digital inputs = 0 V or VDD
1 µA max
VDD/VSS ±4.5/±16.5 V min/max GND = 0 V
1 Guaranteed by design, not subject to production test.
Table 2‘
ADG1404 Data Sheet
Rev. B | Page 4 of 16
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to VDD V
On Resistance (RON) 2.8 Ω typ VS = 0 V to 10 V, IS = −10 mA; see Figure 22
3.5 4.3 4.8 Ω max VDD = 10.8 V, VSS = 0 V
On-Resistance Match
Between Channels (ΔRON)
0.13
Ω typ
V
S
= 0 V to 10 V, I
S
= −10 mA
0.21 0.23 0.25 Ω max
On-Resistance Flatness (RFLAT(ON)) 0.6 Ω typ VS = 0V to 10 V, IS = −10 mA
1.1 1.2 1.3 Ω max
LEAKAGE CURRENTS VDD = 13.2 V, VSS = 0 V
Source Off Leakage, IS (Off) ±0.02 nA typ VS = 1 V/10 V, VD = 10 V/1 V; see Figure 23
±0.55 ±2 ±12.5 nA max
Drain Off Leakage, ID (Off) ±0.03 nA typ VS = 1 V/10 V, VD = 10 V/1 V; see Figure 23
±0.55
±4
±30
nA max
Channel On Leakage, ID, IS (On) ±0.1 nA typ VS = VD = 1 V or 10 V; see Figure 24
±1.5 ±4 ±30 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH 0.001 µA typ VIN = VGND or VDD
±0.1 µA max
Digital Input Capacitance, CIN 3.5 pF typ
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION 230 ns typ RL = 300 Ω, CL = 35 pF
300 375 430 ns max VS = 8 V; see Figure 29
tON (EN) 180 ns typ RL = 300 Ω, CL = 35 pF
240
295
335
ns max
V
S
= 8 V; see Figure 31
tOFF (EN) 115 ns typ RL = 300 Ω, CL = 35 pF
160 190 220 ns max VS = 8 V; see Figure 31
Break-Before-Make Time Delay, tBBM 100 ns typ RL = 300 Ω, CL = 35 pF
10 ns min VS1 = VS2 = 8 V; see Figure 30
Charge Injection
30
pC typ
V
S
= 6 V, R
S
= 0 Ω, C
L
= 1 nF; see Figure 32
Off Isolation 80 dB typ RL = 50 Ω, CL = 5 pF, f = 100kHz; see Figure 25
Channel-to-Channel Crosstalk 82 dB typ RL = 50 Ω, CL = 5 pF, f = 100kHz; see Figure 27
−3 dB Bandwidth 35 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 26
Insertion Loss −0.3 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 26
CS (Off) 39 pF typ f = 1 MHz, VS = 6 V
CD (Off) 150 pF typ f = 1 MHz, VS = 6 V
CD, CS (On) 217 pF typ f = 1 MHz, VS = 6 V
POWER REQUIREMENTS VDD = 13.2 V
IDD 0.001 µA typ Digital inputs = 0 V or VDD
1 µA max
IDD 170 µA typ Digital inputs = 5 V
285 µA max
VDD 5/16.5 V min/max GND = 0 V, VSS = 0 V
1 Guaranteed by design, not subject to production test.
Data Sheet ADG1404
Rev. B | Page 5 of 16
5 V DUAL SUPPLY
VDD = 5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted.
Table 3.
Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VDD to VSS
V
On Resistance (RON) 3.3 Ω typ VS = ±4.5 V, IS = −10 mA; see Figure 22
4 4.9 5.4 Ω max VDD = +4.5 V, VSS = −4.5 V
On-Resistance Match
Between Channels (∆RON)
0.13
Ω typ
V
S
= ±4.5 V, I
S
= −10 mA
0.22 0.23 0.25 Ω max
On-Resistance Flatness (RFLAT(ON)) 0.9 Ω typ VS = ±4.5 V, IS = −10 mA
1.1 1.24 1.31 Ω max
LEAKAGE CURRENTS VDD = +5.5 V, VSS = −5.5 V
Source Off Leakage, IS (Off) ±0.02 nA typ VS = ±4.5 V, VD =
∓
4.5 V; see Figure 23
±0.2 ±1 ±12.5 nA max
Drain Off Leakage, ID (Off) ±0.02 nA typ VS = ±4.5 V, VD =
∓
4.5 V; see Figure 23
±0.25 ±1.2 ±15 nA max
Channel On Leakage, ID, IS (On) ±0.05 nA typ VS = VD = ±4.5 V; see Figure 24
±0.25 ±1.5 ±20 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH 0.001 µA typ VIN = VGND or VDD
±0.1 µA max
Digital Input Capacitance, CIN 3 5 pF typ
DYNAMIC CHARACTERISTICS1
Transition Time, t
TRANSITION
340
ns typ
R
L
= 300 Ω, C
L
= 35 pF
470 560 615 ns max VS = 3 V; Figure 29
tON (EN) 260 ns typ RL = 300 Ω, CL = 35 pF
355 430 480 ns max VS = 3 V; Figure 31
tOFF (EN) 220 ns typ RL = 300 Ω, CL = 35 pF
315 365 400 ns max VS = 3 V; Figure 31
Break-Before-Make Time Delay, tBBM 100 ns typ RL = 300 Ω, CL = 35 pF
50 ns min VS1 = VS2 = 3 V; see Figure 30
Charge Injection
30
pC typ
V
S
= 0 V, R
S
= 0 Ω, C
L
= 1 nF; see Figure 32
Off Isolation 80 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz;
see Figure 25
Channel-to-Channel Crosstalk 82 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz;
see Figure 27
−3 dB Bandwidth
40
MHz typ
R
L
= 50 Ω, C
L
= 5 pF; see Figure 26
Insertion Loss 0.27 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 26
Total Harmonic Distortion + Noise 0.03 % typ RL = 110 Ω, 2.5 V p-p, f = 20 Hz to 20 kHz;
see Figure 28
CS (Off) 33 pF typ VS = 0 V, f = 1 MHz
C
D
(Off)
128
pF typ
V
S
= 0 V, f = 1 MHz
CD, CS (On) 210 pF typ VS = 0 V, f = 1 MHz
POWER REQUIREMENTS VDD = 5.5 V, VSS = −5.5 V
IDD 0.001 µA typ Digital inputs = 0 V, 5 V, or VDD
1 µA max
ISS 0.001 µA typ Digital inputs = 0 V or VDD
1 µA max
VDD/VSS ±4.5/±16.5 V min/max GND = 0 V
1 Guaranteed by design, not subject to production test.
ADG1404 Data Sheet
Rev. B | Page 6 of 16
CONTINUOUS CURRENT, S OR D
Table 4.
Parameter 25°C 85°C 125°C Unit Test Conditions/Comments
CONTINUOUS CURRENT, S or D1
15 V Dual Supply
V
DD
= +13.5 V, V
SS
= −13.5 V
ADG1404 TSSOP 350 220 100 mA max
ADG1404 LFCSP 450 300 140 mA max
12 V Single Supply VDD = 10.8 V, VSS = 0 V
ADG1404 TSSOP 300 220 100 mA max
ADG1404 LFCSP 400 300 140 mA max
5 V Dual Supply VDD = +4.5 V, VSS = −4.5 V
ADG1404 TSSOP 300 220 100 mA max
ADG1404 LFCSP 400 300 140 mA max
1 Guaranteed by design, not subject to production test.
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Data Sheet ADG1404
Rev. B | Page 7 of 16
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameter Rating
VDD to VSS 35 V
VDD to GND −0.3 V to +25 V
VSS to GND +0.3 V to −25 V
Analog Inputs1 VSS − 0.3 V to VDD + 0.3 V or 30
mA, whichever occurs first
Digital Inputs GND − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
Peak Current, S or D 600 mA (pulsed at 1 ms,
10% duty cycle maximum)
Continuous Current, S or D2 Data + 15%
Operating Temperature Range
Automotive (Y Version) −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
14-Lead TSSOP, θJA Thermal
Impedance (4-layer board)
112°C/W
16-Lead LFCSP, θJA Thermal
Impedance
30.4°C/W
Reflow Soldering Peak
Temperature, Pb free
260(+0/−5)°C
1 Overvoltages at IN, S, and D are clamped by internal diodes. Current must be
limited to the maximum ratings given.
2 See data given in Table 4.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating can be applied at any
one time.
ESD CAUTION
ADG1404 Data Sheet
Rev. B | Page 8 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADG1404
NC = NO CONNECT
1
2
3
4
5
6
7
EN
V
SS
S1
NC
D
S2
A0
14
13
12
11
10
9
8
GND
V
DD
S3
NC
NC
S4
A1
TOP VIEW
(Not to Scale)
06816-002
Figure 2. TSSOP Pin Configuration
NOTES
1. EXPOSED PAD TIED TO SUBSTRATE, V
SS
.
2. NC = NO CONNECT.
0
6816-003
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
V
SS
NC
S1
S2
GND
NC
A1
A0
EN
V
DD
S3
S4
NC
D
NC
NC
ADG1404
TOP VIEW
(Not to Scale)
Figure 3. LFCSP Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
TSSOP LFCSP Mnemonic Description
1 15 A0 Logic Control Input.
2 16 EN Active High Digital Input. When this pin is low, the device is disabled and all switches are off.
When this pin is high, the Ax logic inputs determine the on switches.
3 1 VSS Most Negative Power Supply Potential.
4 3 S1 Source Terminal. Can be an input or an output.
5 4 S2 Source Terminal. Can be an input or an output.
6 6 D Drain Terminal. Can be an input or an output.
7 to 9 2, 5, 7, 8, 13 NC No Connection.
10 9 S4 Source Terminal. Can be an input or an output.
11 10 S3 Source Terminal. Can be an input or an output.
12 11 VDD Most Positive Power Supply Potential.
13 12 GND Ground (0 V) Reference.
14 14 A1 Logic Control Input.
TRUTH TABLE
Table 7.
EN A1 A0 S1 S2 S3 S4
0 X X Off Off Off Off
1 0 0 On Off Off Off
1 0 1 Off On Off Off
1 1 0 Off Off On Off
1 1 1 Off Off Off On
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Data Sheet ADG1404
Rev. B | Page 9 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
2.5
2.0
1.5
1.0
0.5
0
–16.5 –12.5 –8.5 –4.5 –0.5 3.5 7.5 15.5
ON RESISTANCE (Ω)
V
S
OR V
D
(V)
11.5
V
DD
= +16.5V,
V
SS
= –16.5V
T
A
= 25°C
I
S
= –10mA
V
DD
= +15V,
V
SS
= –15V
V
DD
= +13.5V,
V
SS
= –13.5V
V
DD
= +12V,
V
SS
= –12V
V
DD
= +10V,
V
SS
= –10V
06816-004
Figure 4. On Resistance as a Function of VD (VS), Dual Supply
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0–7 –6 –5 –3 –1–4 –2 0 1 6
ON RESISTANCE (Ω)
VS OR VD (V)
3 4 752
TA = 25°C
IS = –10mA
VDD = +7V,
VSS = –7V
VDD = +5.5V,
VSS = –5.5V
VDD = +5V,
VSS = –5V
VDD = +4.5V,
VSS = –4.5V
06816-005
Figure 5. On Resistance as a Function of VD (VS), Dual Supply
7
6
5
4
3
2
1
001412108642
ON RESISTANCE (Ω)
V
S
OR V
D
(V)
T
A
= 25°C
I
S
= –10mA
V
DD
= 15V,
V
SS
= 0V
V
DD
= 13.2V,
V
SS
= 0V
V
DD
= 12V,
V
SS
= 0V
V
DD
= 10.8V,
V
SS
= 0V
V
DD
= 8V,
V
SS
= 0V
V
DD
= 5V,
V
SS
= 0V
06816-006
Figure 6. On Resistance as a Function of VD (VS), Single Supply
3.0
2.5
2.0
1.5
1.0
0.5
0
–15 15105
0
–5
–10
ON RESISTANCE (Ω)
V
S
OR V
D
(V)
V
DD
= +15V
V
SS
= –15V
I
S
= –10mA
T
A
= +25°C
T
A
= +85°C
T
A
= +125°C
T
A
= –40°C
06816-007
Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures,
15 V Dual Supply
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0–5 –4 –3 –2 –1 0123 4 5
ON RESISTANCE (Ω)
V
S
OR V
D
(V)
V
DD
= +5V
V
SS
= –5V
I
S
= –10mA
T
A
= +25°C
T
A
= +85°C
T
A
= +125°C
T
A
= –40°C
06815-108
Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures,
5 V Dual Supply
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0012108642
ON RESISTANCE (Ω)
V
S
OR V
D
(V)
V
DD
= 12V
V
SS
= 0V
I
S
= –10mA
T
A
= +25°C
T
A
= +85°C
T
A
= +125°C
T
A
= –40°C
06815-109
Figure 9. On Resistance as a Function of VD (VS) for Different Temperatures,
Single Supply
ADG1404 Data Sheet
Rev. B | Page 10 of 16
6
4
2
0
–2
–4
–6
–8
–10
–12
–14 020 40 60 80 100 120
LEAKAGE (nA)
TEMPERATURE (°C)
06816-111
V
DD
= +15V
V
SS
= –15V
V
BIAS
= +10V/–10V
I
S
(OFF) + –
I
D
(OFF) + –
I
S
(OFF) – +
I
D
(OFF) – +
I
D
, I
S
(ON) + +
I
D
, I
S
(ON) – –
Figure 10. Leakage Currents as a Function of Temperature,15 V Dual Supply
4
–4
–3
–2
–1
0
1
2
3
020 40 60 80 100 120
LEAKAGE (nA)
TEMPERATURE (°C)
06816-112
V
DD
= +5V
V
SS
= –5V
V
BIAS
= +4.5V/–4.5V
I
S
(OFF) + –
I
D
(OFF) + –
I
S
(OFF) – +
I
D
(OFF) – +
I
D
, I
S
(ON) + +
I
D
, I
S
(ON) – –
Figure 11. Leakage Currents as a Function of Temperature, 5 V Dual Supply
14
–4
–2
0
2
4
6
8
10
12
020 40 60 80 100 120
LEAKAGE (nA)
TEMPERATURE (°C)
06816-113
V
DD
= 12V
V
SS
= 0V
V
BIAS
= 1V/10V
I
S
(OFF) + –
I
D
(OFF) + –
I
S
(OFF) – +
I
D
(OFF) – +
I
D
, I
S
(ON) + +
I
D
, I
S
(ON) – –
Figure 12. Leakage Currents as a Function of Temperature, 12 V Single Supply
80
70
60
50
40
30
20
10
001412108
64
2
I
DD
(µA)
LOGIC, Ax (V)
T
A
= 25°C
I
DD
PER LOGIC INPUT
V
DD
= +15V
V
SS
= –15V
V
DD
= +12V
V
SS
= 0V
V
DD
= +5V
V
SS
= –5V
06815-008
Figure 13. IDD vs. Logic Level
600
400
200
0
–200
–400
–600
–15 –10 –5 0 5 10 15
CHARGE INJECTION (pC)
V
S
(V)
V
DD
= +15V, V
SS
= –15V
V
DD
= +12V, V
SS
= 0V
V
DD
= +5V, V
SS
= –5V
T
A
= 25°C
06816-012
Figure 14. Charge Injection vs. Source Voltage
500
0
50
100
150
200
250
300
350
400
450
–40 –20 020 40 60 80 120
TIME (ns)
TEMPERATURE (°C)
100
V
DD
= +15V, V
SS
= –15V
V
DD
= +12V, V
SS
= 0V
V
DD
= +5V, V
SS
= –5V
06816-013
Figure 15. Transition Times vs. Temperature
umns
ans
Data Sheet ADG1404
Rev. B | Page 11 of 16
0
–100
–95
–90
–85
–80
–75
–70
–65
–60
–55
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
1k 10k 100k 1M 10M 100M
OFF ISOLATION (dB)
FREQUENCY (Hz)
T
A
= 25°C
06816-014
Figure 16. Off Isolation vs. Frequency
0
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
1k 10k 100k 1M 10M 100M
CROSSTALK (dB)
FREQUENCY (Hz)
T
A
= 25°C
06816-015
Figure 17. Crosstalk vs. Frequency
0
–7
–6
–5
–4
–3
–2
–1
1k 10k 100k 1M 10M 100M
INSERTION LOSS (dB)
FREQUENCY (Hz)
V
DD
= +15V
V
SS
= –15V
T
A
= 25°C
06816-016
Figure 18. On Response vs. Frequency
0.024
0.022
0.020
0.018
0.016
0.014
0.012
0.010
0.008
0.006
0.004
0.00210 100 1k 10k 100k
THD + N (%)
FREQUENCY (Hz)
V
DD
= +15V
V
SS
= –15V
T
A
= 25°C
V
S
= 20V p-p
V
S
= 15V p-p
06816-017
V
S
= 10V p-p
Figure 19. THD + N vs. Frequency at ±15 V
1
0.1
0.01
0.00110 100 1k 10k 100k
THD + N (%)
FREQUENCY (Hz)
V
DD
= +5V
V
SS
= –5V
T
A
= 25°C
V
S
= 10V p-p
V
S
= 5V p-p
V
S
= 2.5V p-p
06816-018
Figure 20. THD + N vs. Frequency at ±5 V
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
1k 10k 100k 1M 10M
ACPSRR (dB)
FREQUENCY (Hz)
V
DD
= +15V
V
SS
= –15V
V p-p = 0.63V
T
A
= 25°C
NO DECOUPLING
CAPACITORS
DECOUPLING
CAPACITORS
ON SUPPLIES
06815-017
Figure 21. ACPSRR vs. Frequency
ADG1404 Data Sheet
Rev. B | Page 12 of 16
TERMINOLOGY
IDD
The positive supply current.
ISS
The negative supply current.
VD (VS)
The analog voltage on Terminal D and Terminal S.
RON
The ohmic resistance between Terminal D and Terminal S.
RFLAT(ON)
Flatness that is defined as the difference between the maximum
and minimum value of on resistance measured over the
specified analog signal range.
IS (Off)
The source leakage current with the switch off.
ID (Off)
The drain leakage current with the switch off.
ID, IS (On)
The channel leakage current with the switch on.
VINL
The maximum input voltage for Logic 0.
VINH
The minimum input voltage for Logic 1.
IINL (IINH)
The input current of the digital input.
CS (Off)
The off switch source capacitance, which is measured with
reference to ground.
CD (Off)
The off switch drain capacitance, which is measured with
reference to ground.
CD, CS (On)
The on switch capacitance, which is measured with reference to
ground.
CIN
The digital input capacitance.
tTRANSITION
The delay time between the 50% and 90% points of the digital
input and switch on condition when switching from one
address state to another.
tON (EN)
The delay between applying the digital control input and the
output switching on. See Figure 29, Test Circuit 4.
tOFF (EN)
The delay between applying the digital control input and the
output switching off.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
Off Isolation
A measure of unwanted signal coupling through an off switch.
Crosstalk
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.
Bandwidth
The frequency at which the output is attenuated by 3 dB.
On Response
The frequency response of the on switch.
Insertion Loss
The loss due to the on resistance of the switch.
THD + N
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.
ACPSRR (AC Power Supply Rejection Ratio)
The ratio of the amplitude of signal on the output to the amplitude
of the modulation. This is a measure of the ability of the device
to avoid coupling noise and spurious signals that appear on the
supply voltage pin to the output of the switch. The dc voltage on the
device is modulated by a sine wave of 0.62 V p-p.
Data Sheet ADG1404
Rev. B | Page 13 of 16
TEST CIRCUITS
I
DS
Sx D
V
S
V
06816-020
Figure 22. On Resistance
Sx D
V
S
A A
V
D
I
S
(OFF) I
D
(OFF)
06816-021
Figure 23. Off Leakage
Sx D A
VD
ID (ON)
NC
NC = NO CONNECT
06816-022
Figure 24. On Leakage
V
OUT
50Ω
NETWORK
ANALYZER
R
L
50Ω
Sx
D
V
S
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
GND
50Ω
OFF ISOLATION = 20 log V
OUT
V
S
06816-027
Figure 25. Off Isolation
V
OUT
50Ω
NETWORK
ANALYZER
R
L
50Ω
Sx
D
V
S
V
DD VSS
0.1µF
VDD 0.1µF
VSS
GND
INSERTION LOSS = 20 log VOUT WITH SWITCH
VOUT WITHOUT SWITCH
06816-028
Figure 26. Bandwidth
CHANNEL-TO-CHANNEL CROSSTALK = 20 log V
OUT
GND
S1
D
S2
V
OUT
NETWORK
ANALYZER
R
L
50Ω
R
L
50Ω
V
S
V
S
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
06816-029
Figure 27. Channel-to-Channel Crosstalk
ADG1404 Data Sheet
Rev. B | Page 14 of 16
VOUT
RS
AUDIO PRECISION
RL
110Ω
IN
VIN
Sx
D
VS
V p-p
VDD VSS
0.1µF
V
DD
0.1µF
V
SS
GND
06816-030
Figure 28. THD + Noise
V
IN
S1
D
GND C
L
35pF
R
L
300Ω
V
OUT
50% 50%
90% 90%
ADDRESS
DRIVE (V
IN
)
)
V
OUT
A0
A1
S4
S3
S2
V
S1
V
S4
EN
2.4V
0V
3V
t
TRANSITION
t
TRANSITION
V
DD
0.1µF
V
SS
V
DD
V
SS
0.1µF
06816-023
Figure 29. Address to Output Switching Times
ADDRESS
DRIVE (V
IN
)
V
OUT
V
IN
S1
D
GND C
L
35pF
R
L
300Ω
300Ω
V
OUT
A0
A1
S4
S3
S2
V
S1
EN
2.4V
V
DD
0.1µF V
SS
V
DD
V
SS
0.1µF
t
BBM
80% 80%
0V
3V
06816-024
Figure 30. Break-Before-Make Time Delay
Data Sheet ADG1404
Rev. B | Page 15 of 16
ENABLE
DRIVE (V
IN
)
S1
D
GND C
L
35pF
R
L
300Ω
V
OUT
A0
A1
S4
S3
S2
V
S
EN
V
DD
0.1µF
V
SS
V
DD
V
SS
0.1µF
V
IN
300Ω
t
OFF
(EN)
t
ON (EN)
50% 50%
0.9V
OUT
0.9V
OUT
OUTPUT
0V
3V
V
OUT
0V
06816-025
Figure 31. Enable-to-Output Switching Delay
Sx D
V
S
GND
R
S
SW OFF
Q
INJ
= C
L
× ∆V
OUT
SW OFF
SW ON
SW OFF SW OFF
A2A1
EN
V
DD
V
SS
V
DD
DECODER
V
SS
V
OUT
V
OUT
V
IN
V
IN
∆V
OUT
C
L
1nF
0
6816-026
Figure 32. Charge Injection
4k:
ANALOG
DEVICES
www.analng.cnm
ADG1404 Data Sheet
Rev. B | Page 16 of 16
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
061908-A
8°
0°
4.50
4.40
4.30
14 8
7
1
6.40
BSC
PIN 1
5.10
5.00
4.90
0.65 BSC
0.15
0.05 0.30
0.19
1.20
MAX
1.05
1.00
0.80 0.20
0.09 0.75
0.60
0.45
COPLANARITY
0.10
SEATING
PLANE
Figure 33. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimension shown in millimeters
COMPLIANT
TO
JEDEC STANDARDS MO-220-WGGC.
042709-A
1
0.65
BSC
BOTTOM VIEWTOP VIEW
16
5
8
9
12
13
4
EXPOSED
PAD
PIN1
INDICATOR
4.10
4.00 SQ
3.90
0.50
0.40
0.30
SEATING
PLANE
0.80
0.75
0.70 0.05 MAX
0.02 NOM
0.20 REF
COPLANARITY
0.08
PIN 1
INDICATOR
0.35
0.30
0.25
2.60
2.50 SQ
2.40
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 34. 16-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-16-26)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADG1404YRUZ −40°C to +125°C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14
ADG1404YRUZ-REEL7 −40°C to +125°C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14
ADG1404YCPZ-REEL −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-26
ADG1404YCPZ-REEL7 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-26
1 Z = RoHS Compliant Part.
©2008–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06841-0-9/16(B)
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