CD4071BC, CD4081BC Datasheet by ON Semiconductor

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— FAIRGHlI—D — SEM‘CUNDUDTURYM
© 2002 Fairchild Semiconductor Corporation DS005977 www.fairchildsemi.com
October 1987
Revised April 2002
CD4071BC • CD4081BC Quad 2-Input OR Buffered B Series Gate • Quad 2-Input AND Buffered B Series Gate
CD4071BC CD4081BC
Quad 2-Input OR Buffered B Series Gate
Quad 2-Input AND Buffered B Series Gate
General Description
The CD4071BC and CD4081BC quad gates are monolithic
complementary MOS (CMOS) integrated circuits con-
structed with N- and P-channel enhancement mode tran-
sistors. They have equal source and sink current
capabilities and conform to standard B series output drive.
The devices also have buffered outputs which improve
transfer characteristics by providing very high gain.
All inputs protected against static discharge with diodes to
VDD and VSS.
Features
Low power TTL compatibility:
Fan out of 2 driving 74L or 1 driving 74LS
5V–10V–15V parametric ratings
Symmetrical output characteristics
Maximum input leakage 1 µA at 15V over full
temperature range
Ordering Code:
Devices are also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.
Connection Diagrams
CD4071B
Top View
CD4081B
Top View
Order Number Package Number Package Description
CD4071BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4071BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
CD4081BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4081BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
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CD4071BC CD4081BC
Schematic Diagrams
CD4071B
1/4 of device shown
J = A + B
Logical 1 = HIGH
Logical 0 = LOW
*All inputs protected by standard CMOS protection circuit.
CD4081B
1/4 of device shown
J = A B
Logical 1 = HIGH
Logical 0 = LOW
All inputs protected by standard CMOS protection circuit.
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CD4071BC CD4081BC
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Note 1: Absolute Maximum Ratings are those values beyond which the
safety of the device cannot be guaranteed. Except for Operating Tempera-
ture Range they are not meant to imply that the devices should be oper-
ated at these limits. The table of Electrical Characteristics provides
conditions for actual device operation.
Note 2: All voltages measured with respect to VSS unless otherwise speci-
fied.
DC Electrical Characteristics (Note 2)
CD4071BC/CD4081BC
Note 3: IOH and IOL are tested one output at a time.
AC Electrical Characteristics (Note 4)
CD4071BC TA = 25°C, Input tr; tf = 20 ns, CL = 50 pF, RL = 200 k, Typical temperature coefficient is 0.3%/°C
Note 4: AC Parameters are guaranteed by DC correlated testing.
Voltage at Any Pin 0.5V to VDD +0.5V
Power Dissipation (PD)
Dual-In-Line 700 mW
Small Outline 500 mW
VDD Range 0.5 VDC to +18 VDC
Storage Temperature (TS)65°C to +150°C
Lead Temperature (TL)
(Soldering, 10 seconds) 260°C
Operating Range (VDD)3 V
DC to 15 VDC
Operating Temperature Range (TA)
CD4071BC, CD4081BC 55°C to +125°C
Symbol Parameter Conditions 55°C+25°C+125°CUnits
Min Max Min Typ Max Min Max
IDD Quiescent Device VDD = 5V 0.25 0.004 0.25 7.5
µACurrent VDD = 10V 0.5 0.005 0.5 15
VDD = 15V 1.0 0.006 1.0 30
VOL LOW Level VDD = 5V 0.05 0 0.05 0.05
VOutput Voltage VDD = 10V |IO| < 1 µA 0.05 0 0.05 0.05
VDD = 15V 0.05 0 0.05 0.05
VOH HIGH Level VDD = 5V 4.95 4.95 5 4.95
VOutput Voltage VDD = 10V |IO| < 1 µA 9.95 9.95 10 9.95
VDD = 15V 14.95 14.95 15 14.95
VIL LOW Level VDD = 5V, VO = 0.5V 1.5 2 1.5 1.5
VInput Voltage VDD = 10V, VO = 1.0V 3.0 4 3.0 3.0
VDD = 15V, VO = 1.5V 4.0 6 4.0 4.0
VIH HIGH Level VDD = 5V, VO = 4.5V 3.5 3.5 3 3.5
VInput Voltage VDD = 10V, VO = 9.0V 7.0 7.0 6 7.0
VDD = 15V, VO = 13.5V 11.0 11.0 9 11.0
IOL LOW Level Output VDD = 5V, VO = 0.4V 0.64 0.51 0.88 0.36
mACurrent VDD = 10V, VO = 0.5V 1.6 1.3 2.25 0.9
(Note 3) VDD = 15V, VO = 1.5V 4.2 3.4 8.8 2.4
IOH HIGH Level Output VDD = 5V, VO = 4.6V 0.64 0.51 0.88 0.36
mACurrent VDD = 10V, VO = 9.5V 1.6 1.3 2.25 0.9
(Note 3) VDD = 15V, VO = 13.5V 4.2 3.4 8.8 2.4
IIN Input Current VDD = 15V, VIN = 0V 0.1 1050.1 1.0 µA
VDD = 15V, VIN = 15V 0.1 1050.1 1.0
Symbol Parameter Conditions Typ Max Units
tPHL Propagation Delay Time, VDD = 5V 100 250
nsHIGH-to-LOW Level VDD = 10V 40 100
VDD = 15V 30 70
tPLH Propagation Delay Time, VDD = 5V 90 250
nsLOW-to-HIGH Level VDD = 10V 40 100
VDD = 15V 30 70
tTHL, tTLH Transition Time VDD = 5V 90 200
nsVDD = 10V 50 100
VDD = 15V 40 80
CIN Average Input Capacitance Any Input 5 7.5 pF
CPD Power Dissipation Capacity Any Gate 18 pF
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CD4071BC CD4081BC
AC Electrical Characteristics (Note 5)
CD4081BC TA = 25°C, Input tr; tf = 20 ns, CL = 50 pF, RL = 200 k, Typical temperature coefficient is 0.3%/°C
Note 5: AC Parameters are guaranteed by DC correlated testing.
Typical Performance Characteristics
Typical Transfer Characteristics Typical Transfer Characteristics
Typical Transfer Characteristics Typical Transfer Characteristics
Symbol Parameter Conditions Typ Max Units
tPHL Propagation Delay Time, VDD = 5V 100 250
nsHIGH-to-LOW Level VDD = 10V 40 100
VDD = 15V 30 70
tPLH Propagation Delay Time, VDD = 5V 120 250
nsLOW-to-HIGH Level VDD = 10V 50 100
VDD = 15V 35 70
tTHL, tTLH Transition Time VDD = 5V 90 200
nsVDD = 10V 50 100
VDD = 15V 40 80
CIN Average Input Capacitance Any Input 5 7.5 pF
CPD Power Dissipation Capacity Any Gate 18 pF
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CD4071BC CD4081BC
Typical Performance Characteristics (Continued)
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CD4071BC CD4081BC
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
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CD4071BC CD4081BC Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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