PT7C4563 Datasheet by Diodes Incorporated

A Product Line of Q Diodes Incorporated IDPER/CDM‘ P1704563

Real-time Clock Module (I2C Bus)

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PT7C4563

Features

 Using external 32.768kHz quartz crystal

 Supports I2C-Bus's high speed mode (400 kHz)

 Includes time (Hour/Minute/Second) and calendar

(Year/Month/Date/Day) counter functions (BCD

code)

 Programmable square wave output signal

 Oscillator stop flag

 Low backup current: typ. 400nA at VDD=3.0V and

TA=25°C

 Operating range: 1.3V to 5.5V

Description

The PT7C4563 serial real-time clock is a low-power

clock/calendar with a programmable square-wave output.

Address and data are transferred serially via a 2-wire

bidirectional bus. The clock/calendar provides seconds,

minutes, hours, day, date, month, and year information.

The date at the end of the month is automatically

adjusted for months with fewer than 31 days, including

corrections for leap year. The clock operates in the 24-

hour format indicator.

Table 1 shows the basic functions of PT7C4563. More

details are shown in section: overview of functions.

Table 1. Basic functions of PT7C4563

Item

Function

PT7C4563

1

Oscillator

Source: Crystal: 32.768kHz



Oscillator enable/disable

-

Oscillator fail detect



2

Time

Time display

12-hour

-

24-hour



Century bit



Time count chain enable/disable

-

3

Interrupt

Alarm interrupt



4

Programmable square wave output (Hz)

1, 32, 1.024k, 32.768k

5

Communicati

on

2-wire I2C bus



Burst mode

-

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PT7C4563

Pin Configuration

SOIC-8, MSOP-8, TSSOP-8, TDFN-8

Pin Description

Pin no.

Type

Description

1

X1

I

Oscillator Circuit Input. Together with X2, 32.768kHz crystal is connected between them.

2

X2

O

Oscillator Circuit Output. Together with X1, 32.768kHz crystal is connected between them.

3

INT

O

Interrupt Output. Open drain, active low.

4

GND

P

Ground.

5

SDA

I/O

Serial Data Input/Output. SDA is the input/output pin for the 2-wire serial interface. The SDA

pin is open-drain output and requires an external pull-up resistor.

6

SCL

I

Serial Clock Input. SCL is used to synchronize data movement on the I2C serial interface.

7

SQW

O

Clock Output. Open drain. Four frequencies selectable: 32.768k, 1.024k, 32, 1Hz when SQWE

bit is set to 1.

8

VCC

P

Power.

X2

INT

GND

VCC

SQW

SCL 6

7

8

1

2

3

X1

45

SDA

PT7C4363

DIP-8

SOIC-8

TSSOP-8

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PT7C4563

Function Block

Alarm Interrupt Control

Square Wave Output Control

Comparator Alarm Register

(Min, Hour, Day, Date)

Shift Register

Address

Decoder Address

Register

INT

SCL

SDA

PT7C4363

OSC

X1

X2

CD

CG

32.768

kHz

Control Register

Counter Chain

I /O

Interface

(I2C)

SQW

Time Counter

(Sec,Min,Hour,Day,Date,Month,Year)

Note: Built in CD=CG=12pF

Maximum Ratings

Storage Temperature ............................................................................................................... -65oCto +150oC

Ambient Temperature with Power Applied ...................................................................... -40oCto +85oC

Supply Voltage to Ground Potential (Vcc to GND) ..................................................... -0.3V to +6.5V

DC Input (All Other Inputs except Vcc & GND) ........................................................... -0.3V to (Vcc+0.3V)

DC Output Voltage (SDA, /INTA, /INTB pins) .............................................................. -0.3V to +6.5V

Power Dissipation .................................................................................................................... 320mW (Depend on package)

Note:

Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of

the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect reliability.

Recommended Operating Conditions

Symbol

Description

Min.

Typ.

Max.

Unit

VCC

Power voltage

1.3

-

5.5

V

VIH

Input high level

0.7 VCC

-

VCC+0.3

VIL

Input low level

-0.3

-

0.3 VCC

TA

Operating temperature

-40

-

85

ºC

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PT7C4563

DC Electrical Characteristics

Unless otherwise specified, GND =0V, VCC = 1.3 ~ 5.5 V, TA = -40 °C to +85 °C, fOSC = 32.768kHz.

Sym.

Description

Conditions

Min.

Typ.

Max.

Unit

VCC

Supply voltage

VCC

Interface inactive. TA = 25°C 1)

1.1

-

5.5

V

Interface active. fSCL = 400kHz , TA = 25°C 1)

1.3

-

5.5

Supply voltage for clock

data integrity

VCC

-

1.1

-

5.5

ICC

Supply current

VCC

Interface active

fSCL = 400kHz

-

35

A

fSCL = 100kHz

-

15

Interface inactive (fSCL = 0Hz),

pin 7 disabled TA=-40~85°C

VCC = 5.0V

-

450

850

nA

VCC = 3.0V

-

400

650

Interface inactive (fSCL = 0Hz),

pin 7 enabled at 32kHz TA=-

40~85°C

VCC = 5.0V

-

650

1200

nA

VCC = 3.0V

-

600

850

VIL1

Low-level input voltage

SCL

-

0

-

0.3VCC

V

VIH1

High-level input voltage

SCL

-

0.7VCC

-

VCC

IOL

Low-level output voltage

SDA

VOL = 0.4V, VCC = 5V

-3

-

mA

/INT, SQW

VOL = 0.4V, VCC = 5V

-1

-

IIL

Input leakage current

SCL

-

1

A

IOZ

Output current when OFF

-

1

A

Note:

1) For reliable oscillator start-up at power-up: VCC(min)power-up = VCC(min) + 0.3 V.

AC Electrical Characteristics

Sym

Description

Value

Unit

VHM

Rising and falling threshold voltage high

0.8 VCC

V

VHL

Rising and falling threshold voltage low

0.2 VCC

V

Signal

tf

tr

VHM

VLM

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PT7C4563

Over the operating range

Symbol

Item

Min.

Typ.

Max.

Unit

fSCL

SCL clock frequency

-

400

kHz

tSU;STA

START condition set-up time

0.6

-

s

tHD;STA

START condition hold time

0.6

-

s

tSU;DAT

Data set-up time (RTC read/write)

200

-

ns

tHD;DAT1

Data hold time (RTC write)

35

-

ns

tHD;DAT2

Data hold time (RTC read)

0

-

s

tSU;STO

STOP condition setup time

0.6

-

s

tBUF

Bus idle time between a START and STOP condition

1.3

-

s

tLOW

When SCL = "L"

1.3

-

s

tHIGH

When SCL = "H"

0.6

-

s

tr

Rise time for SCL and SDA

-

0.3

s

tf

Fall time for SCL and SDA

-

0.3

s

tSP*

Allowable spike time on bus

-

50

ns

CB

Capacitance load for each bus line

-

400

pF

* Note: Only reference for design.

SSr P

tHD;STA tSP

tSU;DAT

tHD;STA tHD;DAT tSU;STA tSU;STO

SCL

SDA

tBUF

tHD;STA

tSU;STA

fSCL

tLOW tHIGH

Sr

S P

Start condition

Restart condition

Stop condition

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PT7C4563

Recommended Layout for Crystal

Built-in Capacitors Specifications and Recommended External Capacitors

Parameter

Symbol

Typ

Unit

Build-in capacitors

X1 to GND

CG

12

pF

X2 to GND

CD

12

pF

Recommended External capacitors for

crystal CL=12.5pF

X1 to GND

C1

10

pF

X2 to GND

C2

10

pF

Recommended External capacitors for

crystal CL=6pF

X1 to GND

C1

0

pF

X2 to GND

C2

0

pF

Note: The frequency of crystal can be optimized by external capacitor C1 and C2, for frequency=32.768Hz, C1 and C2 should meet the equation as below:

Cpar + [(C1+CG)*(C2+CD)]/ [(C1+CG)+(C2+CD)] =CL

Cpar is all parasitical capacitor between X1 and X2.

CL is crystal’s load capacitance.

Crystal Specifications

Parameter

Symbol

Min

Typ

Max

Unit

Nominal Frequency

fO

-

32.768

-

kHz

Series Resistance

ESR

-

70

k

Load Capacitance

CL

-

6/12.5

-

pF

Note: The crystal, traces and crystal input pins

should be isolated from RF generating signals.

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PT7C4563

Function Description

Overview of Functions

1. Clock function

CPU can read or write data including the year (last two digits), month, date, day, hour, minute, and second. Any (two-digit) year

that is a multiple of 4 is treated as a leap year and calculated automatically as such until the year 2100.

2. Alarm function

These devices have one alarm system that outputs interrupt signals from INT for PT7C4563 to CPU when the date, day of the

week, hour, minute or second correspond to the setting. Each of them may output interrupt signal separately at a specified time.

The alarm may be selectable between on and off for matching alarm or repeating alarm.

3. Programmable square wave output

A square wave output enable bit controls square wave output at pin 7. 4 frequencies are selectable: 1, 32, 1.024k, and 32.768k

Hz.

4. Interface with CPU

Data is read and written via the I2C bus interface using two signal lines: SCL (clock) and SDA (data).

Since the output of the I/O pin SDA is open drain, a pull-up resistor should be used on the circuit board if the CPU output I/O is

also open drain.

The SCL's maximum clock frequency is 400 kHz, which supports the I2C bus's high-speed mode.

5. Oscillator fail detect

When oscillator fail, OSF bit will be set.

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PT7C4563

Registers

1. Allocation of registers

Addr.

(hex) *1

Function (time range

BCD format)

Register definition

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

00

Control/status 1



01

Control/status 2



AF*2



AIE*3



02

Seconds (00-59)

OSF*4

S40

S20

S10

S8

S4

S2

S1

03

Minutes (00-59)



M40

M20

M10

M8

M4

M2

M1

04

Hours (00-23)



H20

H10

H8

H4

H2

H1

05

Dates (01-31)



D20

D10

D8

D4

D2

D1

06

Days of the week (00-06)



W4

W2

W1

07

Months (01-12)



MO10

MO8

MO4

MO2

MO1

08

Years (00-99)

Y80

Y40

Y20

Y10

Y8

Y4

Y2

Y1

09

Alarm: Minutes (00-59)

AE*5

M40

M20

M10

M8

M4

M2

M1

0A

Alarm: Hours (01-12)

AE*5



H20

H10

H8

H4

H2

H1

0B

Alarm: Dates (01-31)

AE*5



D20

D10

D8

D4

D2

D1

0C

Alarm: Weekday (00-06)

AE*5



W4

W2

W1

0D

SQW control

SQWE



RS1

RS0

Caution points:

*1. PT7C4563 uses 8 bits for address. For excess 0FH address, PT7C4563 will not respond.

*2. Alarm interrupt flag bits.

*3. Alarm interrupt enable bits.

*4. Oscillator fail indicates. Indicate clock integrity.

*5. Alarm enable bit. Alarm will be active when related time is matching if AE = 0.

*6. All bits marked with "" are not implemented.

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PT7C4563

2. Control and status register

Addr.

(hex)

Description

D7

D6

D5

D4

D3

D2

D1

D0

00

Control/status 1



(default)

0

Undefined

0

Undefined

1

Undefined

01

Control/status 2



AF



AIE



(default)

Undefined

0

Undefined

0

0D

SQW control

SQWE



RS1

RS0

(default)

1

Undefined

0

a) Alarm Interrupt

 AIE: Alarm Interrupt Enable bit.

AIE

Data

Description

Read / Write

0

Alarm interrupt disabled

Default

1

Alarm interrupt enabled

 AF: Alarm Flag

AF

Data

Description

Read

0

Alarm flag inactive

1

Alarm flag active

Write

0

Alarm flag is cleared

1

Alarm flag remains unchanged

b) SQW control

 SQWE: SQW output clock enable bit.

SQWE

Data

Description

Read / Write

0

the SQW output is inhibited and SQW output is set to high-impedance

1

the SQW output is activated

Default

 RS1, RS0: SQW output frequency select.

RS1, RS0

Data

SQW output freq. (Hz)

Read / Write

00

32.768k

Default

01

1.024k

10

32

11

1

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PT7C4563

3. Time Counter

Time digit display (in BCD code):

 Second digits: Range from 00 to 59 and carried to minute digits when incremented from 59 to 00.

 Minute digits: Range from 00 to 59 and carried to hour digits when incremented from 59 to 00.

 Hour digits: See description on the /12, 24 bit. Carried to day and day-of-the-week digits when incremented from 11 p.m. to

12 a.m. or 23 to 00.

Addr.

(hex)

Description

D7

D6

D5

D4

D3

D2

D1

D0

02

Seconds

OSF*1

S40

S20

S10

S8

S4

S2

S1

(default)

1

Undefined

03

Minutes



M40

M20

M10

M8

M4

M2

M1

(default)

0

Undefined

04

Hours



H20

H10

H8

H4

H2

H1

(default)

0

Undefined

*1 Note: Indicate clock integrity. When the bit is 1, the clock integrity is no longer guaranteed and the time need be adjusted.

4. Days of the week Counter

The day counter is a divide-by-7 counter that counts from 00 to 06 and up 06 before starting again from 00. Values that correspond

to the day of week are user defined but must be sequential (i.e., if 0 equals Sunday, then 1 equals Monday, and so on). Illogical

time and date entries result in undefined operation.

Addr.

(hex)

Description

D7

D6

D5

D4

D3

D2

D1

D0

06

Days of the week



W4

W2

W1

(default)

0

Undefined

5. Calendar Counter

The data format is BCD format.

 Day digits: Range from 1 to 31 (for January, March, May, July, August, October and December).

Range from 1 to 30 (for April, June, September and November).

Range from 1 to 29 (for February in leap years).

Range from 1 to 28 (for February in ordinary years).

Carried to month digits when cycled to 1.

 Month digits: Range from 1 to 12 and carried to year digits when cycled to 1.

 Year digits: Range from 00 to 99 and 00, 04, 08, … , 92 and 96 are counted as leap years.

Addr.

(hex)

Description

D7

D6

D5

D4

D3

D2

D1

D0

05

Dates



D20

D10

D8

D4

D2

D1

(default)

0

Undefined

07

Months



M10

M8

M4

M2

M1

(default)

Undefined

0

Undefined

08

Years

Y80

Y40

Y20

Y10

Y8

Y4

Y2

Y1

(default)

Undefined

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PT7C4563

6. Alarm Register

PT7C4563: Alarm Register

Addr.

Description

D7

D6

D5

D4

D3

D2

D1

D0

09

Alarm: Minutes

AE*1

M40

M20

M10

M8

M4

M2

M1

(default)

Undefined

0A

Alarm: Hours

AE*2



H20

H10

H8

H4

H2

H1

(default)

Undefined

0

Undefined

0B

Alarm: Dates

AE*3



D20

D10

D8

D4

D2

D1

(default)

Undefined

0

Undefined

0C

Alarm: Weekday

AE*4



W4

W2

W1

(default)

Undefined

0

Undefined

*1 Note: Minute alarm enable bit.

*2 Note: Hour alarm enable bit.

*3 Note: Date alarm enable bit.

*4 Note: Weekday alarm enable bit.

Alarm Function

Related register

A

d

r

.

(

h

e

x

)

Function

Register definition

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

01

Control/status 2



AF



AIE



02

Seconds

OSF

S40

S20

S10

S8

S4

S2

S1

03

Minutes



M40

M20

M10

M8

M4

M2

M1

04

Hours



H20

H10

H8

H4

H2

H1

05

Dates



D20

D10

D8

D4

D2

D1

06

Days of the week



W4

W2

W1

09

Alarm: Minutes

AE

M40

M20

M10

M8

M4

M2

M1

0A

Alarm: Hours

AE



H20

H10

H8

H4

H2

H1

0B

Alarm: Dates

AE



D20

D10

D8

D4

D2

D1

0C

Alarm: Weekday

AE



W4

W2

W1

When one or more of these registers are loaded with a valid minute, hour, day or weekday and its corresponding bit Alarm Enable

(AE) is logic 0, then that information will be compared with the current minute, hour, day and weekday. When all enabled

comparisons first match, the Alarm Flag (AF) is set. AF will remain set until cleared by software. Once AF has been cleared it will

only be set again when the time increments to match the alarm condition once more. Alarm registers which have their bit AE at

logic 1 will be ignored.

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PT7C4563

Communication

1. I2C Bus Interface

a) Overview of I2C-BUS

The I2C bus supports bi-directional communications via two signal lines: the SDA (data) line and SCL (clock) line. A combination

of these two signals is used to transmit and receive communication start/stop signals, data signals, acknowledge signals, and so on.

Both the SCL and SDA signals are held at high level whenever communications are not being performed. The starting and

stopping of communications is controlled at the rising edge or falling edge of SDA while SCL is at high level. During data

transfers, data changes that occur on the SDA line are performed while the SCL line is at low level, and on the receiving side the

data is captured while the SCL line is at high level. In either case, the data is transferred via the SCL line at a rate of one bit per

clock pulse. The I2C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a

chip select pin, slave addresses are allocated to each device and the receiving device responds to communications only when its

slave address matches the slave address in the received data.

b) System Configuration

All ports connected to the I2C bus must be either open drain or open collector ports in order to enable AND connections to

multiple devices.

SCL and SDA are both connected to the VDD line via a pull-up resistance. Consequently, SCL and SDA are both held at high

level when the bus is released (when communication is not being performed).

Master

MCU Slave

RTC Other Peripheral

Device

Vcc

SDA

SCL

Note: When there is only one master, the MCU is ready for driving SCL to "H" and RP of SCL may not required.

RPRP

Fig.1 System configuration

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PT7C4563

c) Starting and Stopping I2C Bus Communications

START condition, repeated START condition, and STOP condition

 START condition

SDA level changes from high to low while SCL is at high level

 STOP condition

SDA level changes from low to high while SCL is at high level

 Repeated START condition (RESTART condition)

In some cases, the START condition occurs between a previous START condition and the next STOP condition, in which

case the second START condition is distinguished as a RESTART condition. Since the required status is the same as for the

START condition, the SDA level changes from high to low while SCL is at high level.

d) Data Transfers and Acknowledge Responses during I2C-BUS Communication

 Data transfers

Data transfers are performed in 8-bit (1 byte) units once the START condition has occurred. There is no limit on the amount (bytes)

of data that are transferred between the START condition and STOP condition.

The address auto increment function operates during both write and read operations.

Updating of data on the transmitter (transmitting side)'s SDA line is performed while the SCL line is at low level.

The receiver (receiving side) captures data while the SCL line is at high level.

*Note with caution that if the SDA data is changed while the SCL line is at high level, it will be treated as a START, RESTART, or STOP condition.

Fig.2 Starting and stopping on I2C bus

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PT7C4563

 Data acknowledge response (ACK signal)

When transferring data, the receiver generates a confirmation response (ACK signal, low active) each time an 8-bit data segment

is received. If there is no ACK signal from the receiver, it indicates that normal communication has not been established. (This

does not include instances where the master device intentionally does not generate an ACK signal.)

Immediately after the falling edge of the clock pulse corresponding to the 8th bit of data on the SCL line, the transmitter releases

the SDA line and the receiver sets the SDA line to low (= acknowledge) level.

After transmitting the ACK signal, if the Master remains the receiver for transfer of the next byte, the SDA is released at the

falling edge of the clock corresponding to the 9th bit of data on the SCL line. Data transfer resumes when the Master becomes

the transmitter.

When the Master is the receiver, if the Master does not send an ACK signal in response to the last byte sent from the slave, that

indicates to the transmitter that data transfer has ended. At that point, the transmitter continues to release the SDA and awaits a

STOP condition from the Master.

e) Slave Address

The I2C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a chip select pin,

slave addresses are allocated to each device.

All communications begin with transmitting the [START condition] + [slave address (+ R/W specification)]. The receiving

device responds to this communication only when the specified slave address it has received matches its own slave address.

Slave addresses have a fixed length of 7 bits. See table for the details.

An R/W bit is added to each 7-bit slave address during 8-bit transfers.

Operation

Transfer data

Slave address

R / W bit

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Read

A3 h

1

0

1

0

1

1 (= Read)

Write

A2 h

0 (= Write)

2. I2C Bus’s Basic Transfer Format

SCL from Master 128 9

SDA from transmitter

(sending side)

SDA from receiver

(receiving side)

Release SDA

Low active

ACK signal

SStart indication PStop indication

Sr Restart indication

ARTC Acknowledge

AMaster Acknowledge

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PT7C4563

a) Write via I2C bus

b) Read via I2C bus

 Standard read

 Simplified read

Note:

1. The above steps are an example of transfers of one or two bytes only. There is no limit to the number of bytes transferred during actual communications.

2. 49H, 4AH are used as test mode address. Customer should not use the addresses.

Slave address (7 bits)

1 0 1 0 0 0 1 0

write

Addr. setting

Slave address + write specification Address

Specifies the write start address.

Abit

7 6 5 4 3 2 1 0

bit bit bit bit bit bit bit A P

Write data

S A

A

C

K

A

C

K

A

C

K

Start Stop

Slave address (7 bits)

1 0 1 0 0 0 1 0

write

Slave address + write specification Address

Specifies the read start address.

Addr. setting AS

Slave address (7 bits)

1 0 1 0 0 0 1 1

Read

Slave address + read specification Data read (1)

Data is read from the specified start

address and address auto increment.

Abit

7 6 5 4 3 2 1 0

bit bit bit bit bit bit bit /

APSr 7 6 5 4 3 2 1 0

bit bit bit bit bit bit bitbit

Data read (2)

Address auto increment to set the

address for the next data to be read.

A

C

K

N

O

A

C

K

A

C

K

A

C

K

A

C

K

A

Start

StopRestart

Data read (2)

Address register auto increment to set

the address for the next data to be

read.

Data read (1)

Data is read from the address pointed

by the internal address register and

address auto increment.

Slave address (7 bits)

1 0 1 0 0 0 1 1

Read Abit

7 6 5 4 3 2 1 0

bit bit bit bit bit bit bit /

APS 7 6 5 4 3 2 1 0

bit bit bit bit bit bit bitbit

A

C

K

N

O

A

C

K

A

C

K

A

StopStart Slave address + read specification

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2016-10-0003 PT0333-5

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PT7C4563

Mechanical Information

W (SOIC-8)

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2016-10-0003 PT0333-5

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PT7C4563

L (TSSOP-8)

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2016-10-0003 PT0333-5

18

PT7C4563

U (MSOP-8)

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2016-10-0003 PT0333-5

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PT7C4563

ZE (Lead free and Green 8-Pin TDFN)

Note: For latest package info, please check: http://www.pericom.com/support/packaging/packaging-mechanicals-and-thermal-characteristics/

Ordering Information

Part Number

Package Code

Package

PT7C4563WE

W

8-Pin, 150mil Wide (SOIC)

PT7C4563WEX

W

8-Pin, 150mil Wide (SOIC), Tape/Reel

PT7C4563UE

U

8-Pin, Mini Small Outline Package (MSOP)

PT7C4563UEX

U

8-Pin, Mini Small Outline Package (MSOP), Tape/Reel

PT7C4563LE

L

8-Pin, 173mil Wide (TSSOP)

PT7C4563LEX

L

8-Pin, 173mil Wide (TSSOP), Tape/Reel

PT7C4563ZEE

ZE

8-Pin, 2x3 (TDFN)

PT7C4563ZEEX

ZE

8-Pin, 2x3 (TDFN), Tape/Reel

Note:

 Thermal characteristics can be found on the company web site at www.pericom.com/packaging/

 E = Pb-free and Green

 Adding X Suffix= Tape/Reel

PT7C4563 Datasheet by Diodes Incorporated

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