CLRC663 plus Product Presentation Datasheet by NXP USA Inc.

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m SECURE CONNECTIONS FOR A SMARTER WORLD
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LAURENT DARDÉ
JÜRGEN SCHRODER NEXT GENERATION HIGH-PERFORMANCE
MULTI-PROTOCOL NFC FRONTEND
NFC frontend CLRC663 plus
push your design further best performance at lowest
power consumption
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NFC product portfolio
Connected NFC tag solutions
Our connected NFC tag solutions include a NFC Forum RF
interface, an EEPROM, and a field
-
detection function (NTAG F) or
a field
- detection function with an I²C interface (NTAG I²C plus).
NFC frontend solutions
Our standalone frontends, which work seamlessly with the NFC
Reader Library, are the most flexible way to add NFC to a system.
NFC controller solutions
Integrated Firmware
Our NFC controller solutions enable higher integration with fewer
components combining an NFC frontend with an advanced 32
-bit
microcontroller.
Options include integrated firmware, for an easy, standardized
interface, or a freely programmable microcontroller with the ability
to load fully
-custom applications.
Customizable Firmware
NFC
frontend
CLRC663
plus
NFC controller with
custom application
PN7462 family
NFC controller with
integrated firmware
PN7150
NP
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CLRC663 plus push your design further
best performance at lowest power consumption
extended Low Power Card Detection range with new configuration options
low supply voltage for battery support down to 2.5V
design flexibility
max. operating transmitter current of 350mA with limiting value of 500mA
broad temperature range from -40°C to +105°C
backward compatibility
pin-to-pin and software compatible to CLRC663
faster time-to-market
complete support package including EMVCo compliant NFC SW library and NFC
Cockpit with VCOM interface and easy antenna configuration
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CLRC663 plus product features
350mA maximum operating transmitter current with
limiting value of 500mA
Power supply voltage: 2.5 to 5.5V
Extended operating temperature range: -40 to +105°C
512byte FIFO buffer for highest transaction performance
Flexible and efficient power saving modes including hard
power down, standby and low-power card detection
Integrated PLL provides external system clock from
27.12MHz RF crystal
Licenses and supported standards
Includes NXP ISO/IEC14443-A, NXP MIFARE®and
Innovatron ISO/IEC14443-B licenses
Crypto 1 intellectual property licensing rights
Hardware supports for MIFARE Classic encryption
EMVCo 2.6 L1 analog compliancy on RF level and digital
compliancy with NXP NFC reader library
Characteristics
Host interfaces: SPI (10Mbit/s), I2C (1000kbit/s) and
UART (1228.8kbit/s)
SAM interface in X-mode
Up-to 8 general purpose inputs/outputs
Interfaces
Reader and Writer mode
ISO/IEC 14443A/MIFARE
ISO/IEC 14443B
JIS X 6319-4 (comparable with FeliCa1 scheme)
ISO/IEC 15693 (ICODE-SLIX, ICODE-DNA)
ISO/IEC 18000-3 mode 3/ EPC Class-1 HF (ICODE-ILT)
Peer to Peer mode
Passive-Initiator according to ISO/IEC 14443A (106kbit/s)
and FeliCa (212 and 424kbit/s)
Allows to read and write
All MIFARE®family: Ultralight, Classic 1K & 4K, DESFire
EV1 & EV2 and Plus EV1
All NTAG®family incl. NTAG I²C plus
All SmartMX®family incl. SmartMX2 P40 & P60
Supported RF protocols
HVQFN32
Wettable flanks
Packages
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CLRC663 plus target markets
ACCESS
CONTROL
PAYMENT
TERMINAL
GAMING
highest transmitter current
EMVCo 2.6 L1 analog and digital
compliant
extended Low Power Card
Detection range with new
configuration options
low supply voltage for battery support
down to 2.5V
broad temperature range from
-40°C to +105°C
pin-to-pin and software compatible to
CLRC663
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POSITIONING
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CLRC663 plus vs. other NXP NFC frontends
Dynamic
Power
Control
SW stack
ISO/IEC
18092
Target
ISO/IEC
18092
Initiator
Output
Power
(TX current)
Reader
Writer NFC tag
type
emulation
EMVCo RF
PN512
PN5180
CLRC663
plus
ISO14443(1)
Mifare, FeliCa
ISO15693(2)
5V output
stage
(350mA) L1 NFC
& EMVCo
ISO14443(1)
Mifare, FeliCa Active &
Passive Active &
Passive
3.6V output
stage
(100mA)
L1
with booster NFC
& EMVCo
ISO14443(1)
Mifare, FeliCa
ISO15693(2) 4A Active &
Passive Active &
Passive
5V output
stage
(250mA) L1 Full NFC
& EMVCo
Peer-to-Peer
2, 3, 4A(3) No
No
Yes
Passive
1. ISO/IEC14443
2. ISO/IEC15693
3. No software available for NFC tag type 2 and 3 emulation
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CLRC663 plus vs. PN5180 and PN7462
Feature CLRC663 plus PN5180 PN7462 Comment
Package HVQFN32 HVQFN40
TFBGA64 HVQFN64 CLRC663 plus is pin-to-pin compatible with
CLRC663
RF transmitter supply voltage 2.5 to 5.5V 2.7 to 5.5V 3 to 5.5V CLRC663 plus enables better support for
battery powered systems
General Purpose Input/Output pins
(e.g. to drive LEDs) 4
up-to 8 up-to 7
outputs only 12
up-to 21 PN5180 has up-to 7 general purpose outputs
on TFBGA64 package only
Max. operating transmitter current 350mA
(lim. 500mA) 250mA
with DPC 250mA
with DPC CLRC663 plus enables more flexibility in the
antenna design
Temperature range -40 to +105°C -30 to +85°C -40 to +85°CCLRC663 plus has an automotive or industrial
temperature range
Low power card detection range: very good
power: best range: best
power: good range: best
power: good CLRC663 plus offers the lowest power
consumption
Complete set of field proven
software libraries NFC &
EMVCo Full NFC
& EMVCo Full NFC
& EMVCo Full NFC forum certified library; EMVCo 2.6
Waveform Control Yes Yes
(adaptive) Yes
(adaptive) Adaptive Waveform Control improves wave
shape stability under detuned conditions
Adaptive Range Control No Yes Yes Adaptive Range Control increases sensibility
and robustness under detuned conditions
Freely programmable MCU (flash) No No Cortex M0
(160kB) PN7462 enables an 1-chip reader solution
Host interfaces SPI, I²C, UART SPI USB, HSUART,
SPI, I²C PN7462 has also two master interfaces (SPI,
I²C) and one contact reader interface
SAM Interface Yes
with X-mode No Yes The SAM interface allows to store keys in a
secure container
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CLRC663 plus
vs. CLRC663
—’7 \3 W | g
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CLRC663 plus enables better support for
battery powered systems
CLRC663
CLRC663 plus
3.0V 5.5V2.5V
CLRC663 plus vs. CLRC663
CLRC663
CLRC663 plus
250mA 500mA Maximum operating transmitter current
increases by 40% for CLRC663 plus with
2x the limiting value of the CLRC663
CLRC663
CLRC663 plus
26mm 66mm CLRC663 plus has new configuration
options(2) enabling up-to 2.5x the detection
range in LPCD(1) mode
1. Low Power Card Detection
2. New LPCD configuration options are Charge Pump (enabled/disabled) and LPCD Filter
(enabled/disabled)
CLRC663 plus has an automotive or
industrial operating temperature range:
-40 to +105°C
CLRC663
CLRC663 plus
-25°C105°C-40°C85°C
350mA
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CLRC663 plus LPCD in details
The basic idea of the LPCD(1) is to provide a function that turns off the RF field
when no card is used. This saves energy and allows battery powered NFC Reader
designs
The CLRC663 and CLRC663 plus offer a standalone LPCD function, which
replaces the normal active card polling that is triggered by the host µController
CLRC663 plus offers additional features to extend the LPCD performance
Charge Pump increases the RF field strength during the RF-on time
LPCD Filter reduces the risk of fail detections especially in case of spike noise
Card type Standard
(CLRC663)
Charge pump
enabled
LPCD_FILTER
enabled
Charge pump
+
LPCD_FILTER
enabled
MIFARE
®Ultralight 11 mm
(2)
16
mm
29
mm
25
mm
NTAG
19 mm
24
mm
37
mm
33
mm
MIFARE
DESFire®EV2
19 mm
24
mm
39
mm
35
mm
JCOP DIF
12 mm
17
mm
30
mm
27 mm
ISO
RefPICC Class 6 4
mm
7
mm
18
mm
23
mm
EMVCo
RefPICC 26
mm
29
mm
57
mm
66
mm
1. Low Power Card Detection
2. All detection ranges measured using the standard CLRC663 plus development board
(CLEV6630B) operated with external power supply at room temperature
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CLRC663 plus wettable flank package
In the case of standard HVQFN packages (e.g. CLRC663 family), there is no
exposed pin to visually determine whether or not the package is successfully
soldered onto the PCB. The package edge has exposed copper for the terminals,
these are prone to oxidation, making sidewall solder wetting difficult
The CLRC663 plus, with wettable flank HVQFN package, enables 100% automatic
visual inspection post-assembly ensuring higher quality of assembly
CLRC663 CLRC663 plus
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TECHNICAL OVERVIEW
EE ANTENNA REGISTER MN K ANALOG OONTACTLESS t INTERFACE mar F'FO SERIAL UART « BUFFER n SPI e-nwsr Izc-sus Symbol Plummet Condition: Min ma Mu um: VDD supply vantage 2 5 5 D 5 5 V VDDLPVDD) PVDD supply Vohage U 2 5 5 D VDD V VDDH’VDD] TVDD sunmy voltage 5 U 5.5 V ‘Pg puwerdown CHNEM PDDWN pm pu‘led H‘GH 8 40 nA mu supply eunem , 17 20 mA burn/DD) TVDD ww‘y cunem transminel permanent acme - «so 350 mA shod lenn (ransmmer cuvrem - - 500 mA Tm amblennemperalure device mourned an PCB whlch .40 +25 was no :flnws suflwuem hem dwsswpalmn Tsxg sloraqe lempemlure no supp‘y vonage apphed 55 .25 e150 “0
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CLRC663 plus quick references
[1] VDD(PVDD) must always be the same or lower voltage than VDD
[2] Ipd is the sum of all supply currents
The analog interface handles the modulation and demodulation of the antenna
signals for the contactless interface.
The contactless UART manages the protocol dependency of the contactless
interface settings managed by the host
The FIFO buffer ensures fast and convenient data transfer between host and the
contactless UART
The register bank contains the settings for the analog and digital functionality
SAM in|Erlace SDA IEC. FTFO EEPROM SCL LOG‘CAL 512 Bytes B kByle SPI my mterfaces RESET IFSEU LOG‘ C IFSELU _ '26 VFO 7 W I REGmERs HART ( TF2 STATEMACH‘NES TF3 ai SPI ANALOGUE FRONTEND VOLTAGE VOLTAGE TCK REGULATOR REGULATOR 3/5 V => TDT BOUNDARY 13v ms SCAN DVDD TDO FDR RNG TTMERA TX RX TIMERD 3 (WAKE>UF' TW‘ER) CDDEC DECOD ADC LFO FLL CL- COPRO ‘NTERRUPT CRC SST‘GGATJ; SIGPRO RX TX 05C CONTROLLER CONTROL RXP sz xmz DRO S‘GIN S‘GQUT VM‘D RXN T)“ XTAL1 PDOWN VDD vss PvDD TVDD TVSS AVDD DVDD CLKQUT AUM AUX2
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CLRC663 plus block diagram
terminal 1 Index area TDO/OUTO TDVOUT1 TMS/OUTZ TCK/OUT3 SlGlN/OUT7 SIGOUT DVDD VDD 66666666 @ IRQ @ IF3 @ IF2 @ IF1 @ IFD @ IFSELI/ouTs @ IFSELO/OUT4 @ PVDD heatsink O l 2 3 4 1 1 I flflflflfl N m» @@@®®®flfl AVDD E) §< 3="">< n="" x="" j=""><( n.="" x="" ii="" z="" x="" n:="" 9="" e=""> 7x2 E TVSS E Transparem lop view SDA SCL CLKOUT/OUTB PDOWN XTALZ XTAL! TVDD TXW Flu symbol me nescnpuon I mo / cum 0 IuaI dana empm for boundary m Inmaeu / generuI purpeue mupuI n 2 In I oun I I25! dara inpux boundary aean Imerlace / geneml purpase nulpul I 3 TMS I OUTZ I teeI mode neIecI boundary scan menace Ig-neml Wmcse oquuIz 4 TCK Ioura I has! elm hmndary scan inIurIueu I gunsraI purpose empuI a 5 SIGIN Ioun I CenIaeIIese eernrnunieaIien InIerIeee oquuI. l genenl pulpnse oulplfl 7 s sIeouT o cbeIucIIesa cbrnrnunreenien rnIerIuce Invut 7 DVDD PWR dig‘nnl power nuppIy puns: m a VDD PWR panel supply 9 AVDD PWR unulog power nupply buIIer m In AuxI o auxIlIaly bum: Pm Ia und in! anang Inn 991ml 11 ALIX2 0 aanl ry mulls Is used IeraneIog ues1 signnI 12 RXP I ' m pin Iorme received RF SigniL 13 RXN I reamerrnpuI pm Ierurs rimmed RF nrgnaI 14 VMID PWR InIernnI vecewer reIereeee volhge Ill Is 7x2 0 uanunIIIer 2: delivers In. modulemed 13.56 MHz carrier 15 wss PWR Ilansrmner gmund, supplies Ine qupuI sIage emu, 7x2 I7 7x1 0 uansnmer I. delivers Ine mudulatad1356 MHz carrier Is TVDD F'WR uunernIII-r vomg- “Apply 19 XTAL1 I eranaI pneiIIqur inpuI- InpuI lnlhn vem‘ng arnpmierm In. pneiIIqur nun pIn in also Ine inpul Iuren enerneIIy genenued dock «vs: 7.12 MHz) 211 XTALZ o erysIaI aseiIIaIer mIpur equumnnu inverung aranmer enne oscilamr zI PDDWN I Pwer Dawn (RESET) 22 CLKOUTI cum o clock 00wa g-null bum man s 23 SCL 0 Serial Clock Iinu 2A SDA l/O Serial DeIa Line 25 PVDD PWR pad pow supry zs IFsEm I oun I inner .nIerunc. median u l generaI purpose nurpm 4 27 IFsELI routs I m1 inIerIeee seIeeIien 1 IperneraI purpose eunnu 5 23 IF!) Iio 12:71:09 pm, nruIIIIuneIIbn Dine Can be unsigned In nesI inIerInee RS232. sPI, we, I VI. 29 IFI Iio Immune DI", nruIIIIuneIIbn Dine Can be unsigned In nesI inIerInee sPI, Re. In» an In l/O Imeiraee pm, mullIfumunn prn» Can be unsigned In nanI Int-flac- RS232, sPI, I2c, IZOVL 31 IFB Iio Irzrgrvuue DI", nruIIIIuneIIbn Dine Can be unsigned In nesI inIerInee RS232. sPI, lie, I VI. 32 IRQ 0 Imenum veguesI. bum In signal In ianm mm as vss P'WR gmund and InsaI nrnk aennemn
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CLRC663 plus pinning
[1] This pin is used for connection of a buffer capacitor.
Connection of a supply voltage might damage the device.
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PRODUCT SUPPORT
PACKAGE
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CLRC663 plus development kit and board
The OM26630FDK is a flexible and easy to use frontend development kit for
CLRC663 plus
It contains a CLEV6630B board fully supported by the NFC Cockpit and the NFC
Reader Library with a 65*65mm² antenna optimized for EMVCo applications and
a 30*50mm² antenna with matching components optimized for Access
Management applications
It also includes, 3 small antenna matching PCBs for implementation of custom
antenna matching circuit, NFC sample cards based on NTAG216F (NFC Forum
type 2 tag) and DESFire®EV2, and 10 CLRC663 plus samples in HVQFN package
up, W M khan-um m “a... MMM mum. [mum mumm|mmw M . mum wmm|muwm m mm [mm mwa‘Wka‘_wwm.-. mm. www.mmwmmlm an...“ mmrux M1Wm|mn m. mmru! MIWMm—vmxw- m..." w”. ”may...“ [mum WWW” mmu‘l Wmm‘xm mum Mxme-mwnslmm mm mm MimYMMa-ar mmw..w« [311mm WW4 m mmru! mwmwmuw... mmlmvaasmx mum! msawmwmuw... malimwuwmlmx ~ g wanmsmaml _El 7 muwlmmumm-W ‘ mam-0mm E] wwmmm
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CLRC663 plus NFC Cockpit
NFC Cockpit is an intuitive GUI that lets you configure and adapt CLRC663 plus
settings without writing a single line of software code
This Windows tool features
direct register/EEPROM read/write access and backup of EEPROM settings
RF field control and card operation (Type A, Type B, Type F, ISO15693)
control of test applications like EMVCo Loopback and test signal configuration
LPCD configuration
M m mm" mm u smimm mm W we aim unsung-rm wows mm.» ”Wm um. «mm mm m ‘Wum muum mgr . “a ,3: MW. _ "5;"; \ $ch mans: mm mm mm: Ismsn MM m w muggy- Mm. Dun-9m
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CLRC663 plus NFC Reader library
Scalability enable only required components and protocol implementations
Optimum performance built-in MCU support, interrupt-based event handling,
free RTOS support and compilers that produce highly compact and efficient code
Faster development save time and effort by using the APIs and the rich set of
sample applications for most common functions
Simpler certification get ready for certification with test applications for EMVCO
L1, NFC Forum and ISO/IEC10373-6 PICC/PCD
.com WWW. nx NFC mam Selecunn Gnugle Play sum wwwm .cnm/NFC
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NFC use cases NFC community NFC training NFC product selection guide
Use cases & products
@ NFC Everywhere
www.nxp.com/NFC
Online community & technical support
Support NXP community NFC
NXP community NFC
Recorded Webinars
Support online academy NFC
webinars
NFC webinars
NFC product selection guide app
available
Google Play
App Store
Find your NFC toolkit at www.nxp.com
www.nxp.com/products/:CLRC66303HN www.nxp.com/products/:OM2663OFDK
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Item 12NC Comment
CLRC66303HN, 551 9353 062 08551 CLRC663 plus on single tray
CLRC66303HN, 518 9353 062 08518 CLRC663 plus on reel
OM26630FDK 9353 391 51699 CLRC663 plus frontend development kit containing a CLEV6630B development board and
- an 30*50mm² antenna with matching components and 3 PCBs for individual antenna matching
- NTAG216F and MIFARE DESFire EV2 sample cards and 10 CLRC663 plus samples
CLEV6630B 9353 391 49699 CLRC663 plus frontend development board with 65*65mm² antenna
CLRC663 plus best performance at lowest power
consumption
Max. operating transmitter current: 350mA (lim. 500mA)
Enhanced LPCD performance and options
Broad temperature range from -40°C to +105°C
Low supply voltage for battery support down to 2.5V
www.nxp.com/products/:CLRC66303HN
www.nxp.com/products/:OM26630FDK
SECURE CONNECTIONS FOR A SMARTER WORLD

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