638 Series Datasheet by CTS-Frequency Controls

| Download PDF Datasheet

equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.

DOC# 008-0539-0 Rev. C Page 1 of 8

Model 638

Ultra Low Jitter LVPECL or LVDS Clock

Features

 Ceramic Surface Mount Package

 Ultra Low Phase Jitter Performance, 100fs Typical

 Fundamental or 3rd Overtone Crystal Design

 Frequency Range 80 – 170MHz *

 +2.5V or +3.3V Operation

 Output Enable Standard

 Tape and Reel Packaging, EIA-418

Applications

 SerDes

 Storage Area Networking

 Broadband Access

 SONET/SDH/DWDM

 PON

 Ethernet/GbE/SyncE

 Fiber Channel

 Test and Measurement

Description

CTS Model 638 is a low cost, high performance clock oscillator supporting differential LVPECL or LVDS outputs.

Employing the latest IC technology, M638 has excellent stability and low jitter/phase noise performance.

Ordering Information

Model

638

Code Code Code

P 6 2

L 5 3

E 3

V 2

Code Code Code

A T

Notes:

This product is specified for use only in standard commercial applications. Supplier disclaims all express and implied warranties and liability in connection with any use of this

product in any non-commercial applications or in any application that may expose the product to conditions that are outside of the tolerances provided in its specification.

Refer to document 016-1454-0, Frequency Code Tables. 3-digits for frequencies <100MHz, 4-digits for frequencies 100MHz or greater.

Consult factory for availability of 6I Stability/Temperature combination.

Not all performance combinations and frequencies may be available.

Contact your local CTS Representative or CTS Customer Service for availability.

LVPECL - Pin 2 Enable

±50ppm

-40°C to +85°C

-20°C to +70°C

LVDS - Pin 2 Enable

±100ppm

Frequency

Temp. Range

Packing

XXX or XXXX

Output Type

Frequency Code

[MHz]

Frequency

Stability

Temperature

Range

Supply

Voltage

Packaging

Output

Stability

Voltage

LVPECL - Pin 1 Enable

±20ppm

+2.5Vdc

LVDS - Pin 1 Enable

±25ppm

+3.3Vdc

Product Frequency Code

-10°C to +60°C

1k pcs./reel

Part Dimensions:

7.0 × 5.0 × 2.0mm • 178.462mg

Standard Frequencies, 100fs Maximum

- 125.00MHz - 156.25MHz

- 150.00MHz - 156.2539MHz

- 155.52MHz - 161.1328MHz

* See Page 8

for additional developed frequencies.

Check with factory for availability of frequencies

[me u www.ctscorp.com mm m [Mange [\u Mm H, mm um m man me ya- an :rs‘ cm am" h \umvahun,’uud¢. 99L mum m Ln'umev éLeu' L aw A'xun) m mt

equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.

Model 638

Ultra Low Jitter LVPECL or LVDS Clock

DOC# 008-0539-0 Rev. C Page 2 of 8

Electrical Specifications

Operating Conditions

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT

Maximum Supply Voltage

VCC --0.5 -5.0 V

2.375 2.5 2.625

3.135 3.3 3.465

Supply Current

LVPECL -55 88

LVDS -45 66

-20

+70

-40

+85

Storage Temperature

TSTG --40 -+125 °C

Frequency Stability

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT

Frequency Range

LVPECL

LVDS

Frequency Stability

[Note 1]

Δf/fO-±ppm

Aging Δf/f25 First Year @ +25°C, nominal VCC -3 - 3 ppm

Output Parameters

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT

Output Type - - -

Output Load

RLTerminated to VCC - 2.0V -50 -Ohms

VOH VCC - 1.025 - VCC - 0.880

VOL VCC - 1.810 - VCC - 1.620

VOH VCC - 1.085 - VCC - 0.880

VOL VCC - 1.830 - VCC - 1.555

Output Duty Cycle SYM @ VCC - 1.3V 45 -55 %

Rise and Fall Time TR, TF@ 20%/80% Levels, RL = 50 Ohms -0.3 0.7 ns

Output Type - - -

Output Load

RLBetween Outputs -100 -Ohms

VOH -1.43 1.60

VOL 0.90 1.10 -

Output Duty Cycle SYM @ 1.25V 45 -55 %

Differential Output Voltage VOD RL = 100 Ohms 247 330 454 mV

Offset Voltage VOS LVDS Load 1.125 1.25 1.375 V

Rise and Fall Time TR, TF@ 20%/80% Levels, RL = 100 Ohms -0.4 0.7 ns

Supply Voltage

VCC

±5%

ICC

Maximum Load

Operating Temperature

+25

°C

80 - 170

20, 25, 50 or 100

80 - 170

MHz

1.] Inclusive of initial tolerance at time of shipment, changes in supply voltage, load, temperature and 1st year aging.

LVPECL

Output Voltage Levels

PECL Load, -20°C to +70°C

PECL Load, -40°C to +85°C

LVDS

Output Voltage Levels

LVDS Load

Pinlur PinZ Pin4&Pin5 Open Output Logwc ' ngh‘mp ‘Q- a 5 ¢ \_/ ’\ n.nIuF s W] mu. . } 71M 7 E (”D —— j J1 3 ‘J x 3 ; 1 1: am: um M Om. am: W... [m] ’ m. orNC «mmumm m N.c. or Enable input [out] nmcvuz=wnmm www.ctscorp.com m 01 mt , em; mm my mum wan aw ,m meet me - man crsx (own shun Wuvmahun,’pvud4uw mm m mange [\u mm mm L‘vudqc

equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.

Model 638

Ultra Low Jitter LVPECL or LVDS Clock

DOC# 008-0539-0 Rev. C Page 3 of 8

Electrical Specifications

Enable Truth Table

Pin 1 or Pin 2

Pin 4 & Pin 5

Logic ‘1’

Output

Open

Output

Logic ‘0’

High Imp.

Test Circuit

LVPECL LVDS

Output Waveform

LVPECL or LVDS

Output Parameters

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT

Start Up Time T

Application of V

- 2 5 ms

Enable Function [Standby]

Enable Input Voltage

Pin 1 or 2 Logic '1', Output Enabled 0.7V

- - V

Disable Input Voltage V

Pin 1 or 2 Logic '0', Output Disabled - - 0.3V

Disable Time T

PLZ

Pin 1 or 2 Logic '0', Output Disabled - - 200 ns

Enable Time T

PLZ

Pin 1 or 2 Logic '1', Output Enabled - - 2 ms

80 - 124.9MHz, Bandwidth 12 kHz - 20 MHz - - 200 fs

125 - 170MHz, Bandwidth 12 kHz - 20 MHz -100 fs

Period Jitter, pk-pk pjpk-pk - - 2.6 -ps

Period Jitter, RMS pjrms - - 25 -ps

Phase Jitter, RMS

tjrms

Mus: mm m nndBlRaf .2u mam in Hz 1m Hz 1 w: an m «5.4547 1m 1m: 451.5542 1 m: -1sz.zusu s w; 452.7222 Sun 12 w: 2n IN: Canhr xu‘nuz w: "Sm-n 15.555 m 1a.. Iym Imga and mm mu An Iym my. ama mm" 1.. Nmsm 36%? a: / mas m m“ 0‘ ms ﬂag; ' 59.755 fsE: x. mm m 155.221 Hz ‘mm mm mm mm mm ISM" mm mm m». u H». ”mm mm mm sum mum ”mm m man/m nnnnnrha WW, _ “Sgyiaxsffuannm 2m: no u dE

equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.

Model 638

Ultra Low Jitter LVPECL or LVDS Clock

DOC# 008-0539-0 Rev. C Page 4 of 8

Electrical Specifications

Performance Data

Phase Noise [typical]

125.00MHz, LVPECL, VCC = 3.3V, TA = +25°C

156.25MHz, LVPECL, VCC = 3.3V, TA = +25°C

Wm. mm : M m My,“ msgmsemwds Emma/Hz WW, ’ (maamm 22mg - Ansa ﬂat/>4: 100 m .9239 am; n n 1 m ,5793 ﬂB41 in,“ arms mm [Hum 15M! www.ctscorp.com y. L m H _ u m m ”A“ L \ mm, L ",A‘Ji' k H, mm HHVMLHLL

equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.

Model 638

Ultra Low Jitter LVPECL or LVDS Clock

DOC# 008-0539-0 Rev. C Page 5 of 8

Electrical Specifications

Performance Data

Phase Noise [typical]

156.25MHz, LVDS, VCC = 3.3V, TA = +25°C

Phase Noise Tabulated

Typical, VCC = 3.3V, TA = +25°C

PARAMETER SYMBOL CONDITIONS TYP UNIT PARAMETER SYMBOL CONDITIONS TYP UNIT

LVPECL @ 125.00MHz LVPECL @ 156.25MHz

Phase Noise Single Side Band Phase Noise Single Side Band

@ 10Hz -79.62 @ 10Hz -75.60

@ 100Hz -107.25 @ 100Hz -103.54

@ 1kHz -135.31 @ 1kHz -132.26

@ 10kHz -146.45 @ 10kHz -149.09

@ 100kHz -151.59 @ 100kHz -155.26

@ 1MHz -152.31 @ 1MHz -155.33

@ 5MHz -153.73 @ 20MHz -158.39

Phase Jitter, RMS tjrms Integration Bandwidth 12kHz - 20MHz 89.77 fs Phase Jitter, RMS tjrms Integration Bandwidth 12kHz - 20MHz 77.86 fs

PARAMETER SYMBOL CONDITIONS TYP UNIT

LVDS @ 156.25MHz

Phase Noise Single Side Band

@ 10Hz -71.41

@ 100Hz -103.93

@ 1kHz -128.68

@ 10kHz -145.73

@ 100kHz -155.28

@ 1MHz -154.78

@ 20MHz -157.92

Phase Jitter, RMS tjrms Integration Bandwidth 12kHz - 20MHz 82.99 fs

dBc/Hz

l. ” , Manulacturmg Swte Code. A 5.00 M720 3.73 KEV: mm 1. JEDECtermmaUOn code(e4) Barnenptatmgts 1 EOH Or N.C. Ename [std] Or NO Connect 2 NO, or EOH NO Connector Enabte [opt] 3 GND Clrcwt & Package Ground 4 Output RF Output 5 m Commentary RF Output 5 Vcc Suppw Voltage www.ctscorp.com «:zmv :rs‘ Cuwu ouun n \uvvvvalmvv,'LVUd4J\:\ >LJ‘ELL lu theme [\u Mn, u, 'hal Lmdqel m meet me ya- DeL‘x.1'\uv\>\uvLA'UVHEV :LEU‘L aw A'xun) m ten

equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.

Model 638

Ultra Low Jitter LVPECL or LVDS Clock

DOC# 008-0539-0 Rev. C Page 6 of 8

Mechanical Specifications

Package Drawing Marking Information

Recommended Pad Layout Notes

Pin Assignments

Symbol

Function

EOH or N.C.

Enable [std] or No Connect

N.C. or EOH

No Connect or Enable [opt]

GND

Circuit & Package Ground

Output

RF Output

Output

Complimentary RF Output

VCC

Supply Voltage

1. ** - Manufacturing Site Code.

2. YYWW – Date Code; YY – year, WW – week.

3. O – Output Type; P or E = LVPECL, L or V = LVDS.

4. ST – Frequency Stability/Temperature Code.

[Refer to Ordering Information]

5. V – Voltage Code; 3 = 3.3V, 2 = 2.5V.

6. xxxx – Frequency Code.

3-digits, frequencies below 100MHz

4-digits, frequencies 100MHz or greater

[See document 016-1454-0, Frequency Code Tables.]

1. JEDEC termination code (e4). Barrier-plating is

nickel [Ni] with gold [Au] flash plate.

2. Reflow conditions per JEDEC J-STD-020; +260°C

maximum, 20 seconds.

3. MSL = 1.

CTS**YYWW

638OSTV

● xxxx

— 4.00 < ”led="" 7="" —="" 5.00=""> 1.75 LN ‘ / $ 1 E G) d :9 G) G; ‘ 7 7 m V a W V mm W“ Notes 1. name quarmtv ‘5 1k pieces mammum per 180mm ree‘. 21m www.ctscorp.com ; an :rs‘ cm am" h \umvahmv/Lmquw mm m man» [\u mu m 'nm mm. m man We :- BL‘V.1'VL‘H)‘UYLJY’JYHEY éLeu' L aw A'xun) m mt

equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.

Model 638

Ultra Low Jitter LVPECL or LVDS Clock

DOC# 008-0539-0 Rev. C Page 7 of 8

Packaging - Tape and Reel

Tape Drawing

Reel Drawing

Notes

1. Device quantity is 1k pieces maximum per 180mm reel.

2. Complete CTS part number, frequency value and date code information must appear on reel and carton labels.

CS CODE CODE CODE CODE CODE CODE CODE CODE www.ctscorp.com Emu :rs‘ Cuwu am" h \uvmahun,’uudd»l\:\ mm m meme [\u m m mm Lmqu‘ ,m man We y - u) m mt 'qu) My mum :LEU‘L aw