353 Series Datasheet by CTS-Frequency Controls

CTSJ.) ELECTRONIC COMPONENTS EE — T - 1k p§./reel R - 3k pGJreel — WWW.CTECDRP.DDM

Document No. 008-0369-0 Page 1- 3 Rev. A

www.ctscorp.com

Model 353

HCMOS VCXO

ORDERING INFORMATION

N = +2.5 Vdc, Pin 2 Enable

L = +3.3 Vdc, Pin 2 Enable

S = +5.0 Vdc, Pin 2 Enable

T = +2.5 Vdc, Pin 5 Enable

= +3.3 Vdc, Pin 5 Enable

W = +5.0 Vdc, Pin 5 Enable

SUPPLY VOLTAGE

353

PACKAGING OPTIONS

OPERATING TEMPERATURE RANGE

T - 1k pcs./reel

R - 3k pcs./reel

FRE

UENCY

Product Frequency Code 1

Contact your local CTS Representative or CTS Customer Service for availability.

BSOLUTE PULL RANGE [APR]

B = ± 50 ppm APR

FRE

UENCY STABILIT

6 = ± 20 ppm 2

3 = ± 50 ppm

5 = ± 25 ppm

A = -10°C to +60°C

C = -20°C to +70°C

I = -40°C to +85°C 2

2] Consult factory for availability of 6I Stability/Temperature combination.

3-digits required for frequencies below 100MHz and 4-digits for frequencies 100MHz or greater.

Not all performance combinations and frequencies may be available.

1] Refer to document 016-1454-0, Frequency Code Tables.

PACKAGING INFORMATION [reference]

Device quantity is 1k pcs. maximum per 180mm reel.

FEATURES

• Standard 5.0mm x 3.2mm 6-Pad Surface Mount Package

• HCMOS Output

• Low Jitter Performance

• Fundamental Crystal Designs

• Frequency Range 1 – 80 MHz

• Operating Voltages +2.5Vdc, +3.3Vdc or +5.0Vdc

• Operating Temperature to -40°C to +85°C

• Output Enable Standard

• Tape & Reel Packaging Standard, EIA-418

• RoHS/Green Compliant [6/6]

APPLICATIONS

Model 353 is ideal for applications such as broadband access, Ethernet/Gigabit Ethernet,

SONET/SDH, xDSL, PCMIA, digital video, Picocells and base stations.

CTS ELECTRDMC COMPONENYS CONDI 11 0N5 Frequency Stabihty See Nate 1 and om humus” ang Supply Voltage Model 353M, 3531, 15% Model 353L, 353v, 5% Model 3535 353w 5% @ +2.5Vdc @ +3.3Vdc +5.0Vdc Load - Control Voltage Model 353M, 3531', v“ : 2.5v Vzc w, v“ Best Stral ht Llne Flt 50% Leve‘ Modu‘atlan RON-off Enable Function Phase Jitter RMS Bandwldth 12 kHz - 20 MHZ (typical maximum) Frequency Phase Noise Frequency Phase Noise case: (and Hz) * case: (dBcl Hz) * 10 HZ 760 10k HZ 7135 100 HZ 790 100k HZ 7150 1k HZ 7120 >100k HZ 7150

Document No. 008-0369-0 Page 2 - 3 Rev. A

Model 353

5.0mm x 3.2mm HCMOS VCXO

ELECTRICAL CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT

Maximum Supply Voltage VCC --0.5-5.0V

Maximum Control Voltage VC--0.5-

VCC V

Storage Temperature TSTG - -40 - +100 °C

Frequency Range fO-MHz

Frequency Stability

(

See Note 1 and Orderin

Information

)

Δf/fO- - - 20, 25 or 50 ± ppm

Absolute Pull Ran

(See Note 2 and Ordering Information) APR - ±50 - - ppm

Aging Δf/f25 First Year @ +25°C, nominal VCC and VC-3 - 3 ppm

-10 +60

-20 +70

-40 +86

Model 353N

353T

±5% 2.38 2.5 2.63

Model 353L, 353V, ±5% 3.14 3.3 3.47

Model 353S

353W

±5% 4.75 5.0 5.25

CL = 15 pF

@ +2.5Vdc - - 25

@ +3.3Vdc - - 25

@ +5.0Vdc - - 30

Out

ut Load C

---15

Model 353N, 353T, VCC = 2.5V 0.20 1.25 2.30

Model 353L, 353V, VCC = 3.3V 0.15 1.65 3.15

Model 353S, 353W, VCC = 5.0V 0.50 2.50 4.50

Frequency Deviation Δf +25°C @ Time of Shipment, over VC range ±100 - - ppm

Linearit

L Best Strai

ht Line Fit - - 10 %

Input Impedance ZVc -10--kOhms

Transfer Function - - -

Out

ut Dut

cle SYM @ 50% Level 45 - 55 %

VOH Logic '1' Level, CMOS Load 0.9VCC --

VOL Logic '0' Level, CMOS Load - - 0.1VCC

Rise and Fall Time T

, TF @ 20%/80% Levels - 3 8.0 ns

Start Up Time TS Application of VCC -510ms

Modulation Roll-off - @ -3dB 12 - - kHz

Enable Function

Enable Input Voltage VIH Pin 2 or Pin 5 Logic '1', Output Enabled 0.7VCC --

Disable Input Voltage VIL Pin 2 or Pin 5 Logic '0', Output Disabled - - 0.3VCC

Enable Time TPLZ Pin 2 or Pin 5 Logic '1' - - 100 ns

Phase Jitter, RMS tjrms Bandwidth 12 kHz - 20 MHz - 0.5 1 ps

1. Notes:

ICC mA

TA+25-

Operating Temperature

Positive

Supply Current

1 - 80

ELECTRICAL PARAMETERS

Output Voltage Levels V

Inclusive of initial tolerance at time of shipment, changes in supply voltage, load, temperature and 1year aging.

Minimum guaranteed frequency shift from fO over variations in temperature, aging, power supply and load.

Control Voltage

VCV

°C

Supply Voltage

VCC

ENABLE TRUTH TABLE

PIN 2 or Pin 5 PIN 4

Logic ‘1’ Output

Open Output

Logic ‘0’ High Imp.

Frequency

Offset Phase Noise

(

dBc/Hz

)

* Frequency

Offset Phase Noise

(

dBc/Hz

)

10 Hz -60 10k Hz -135

100 Hz -90 100k Hz -150

1k Hz -120 >100k Hz -150

* Results may vary depending on frequency.

SINGLE SIDE BAND PHASE NOISE

(typical maximum)

GTE, ELECTHMIC CWFDNEN'S TEST CI RCUIT. CMOS LOAD NYC. or Enabie 1mm /’\ \‘2 4 alumna «v + mm; ﬁlm 7 : m m, m , [wading alone 1 J2 3 (Mum 10%, 29%,.) 5V umnf k) “I \ 7' * 1 < mum)!!!="" :="" swl="" endule="" lnpm="" or="" "l="" mmcche="{TH" “10="" ('ﬁ)="" m="" p="" (m="" «1.2)="" m="" 1="" mennner="" _="" 0.157="" 2mm="" «ﬂag—ﬂy="" if="" %="" (3,2="" my="" (2.0="" 4="" ms="" mane="" mm:="" b="" 4,="" 1="" g="" 4!="" :‘="" (1.2="" 20.2)="" ‘="" 7%="" a="" k="" 1="" m="" was="" ‘="" ‘="" l="" s="" c="">< —="" hjd="" [0="" bs]="" d.u.="" pl="" nassignments="" i=""> + + n Cmms . s s \— moss [2.10] o nss [1 4a] } > > ' L 010M254] J WWW] T

Document No. 008-0369-0 Page 3 - 3 Rev. A

Model 353

5.0mm x 3.2mm HCMOS VCXO

MECHANICAL SPECIFICATIONS

MARKING INFORMATION

1. ** - Manufacturing Site Code.

2. D – Date Code. See Table I for codes.

3. ST – Frequency stability/temperature code.

[Refer to Ordering Information.]

4. V – Voltage code. N or T = 2.5V, L or V = 3.3V,

S or W = 5.0V

5. xxx – Frequency Code.

3-digits, frequencies below 100MHz

Refer to document 016-1454-0, Frequency Code Tables.

PACKAGE DRAWING

NOTES

1. Complete CTS part number, frequency value and

date code information must appear on reel and

carton labels.

2. Termination pads [e4]. Barrier-plating is nickel [Ni]

with gold [Au] flash plate.

3. Reflow conditions per JEDEC J-STD-020; 260°C

maximum, 20 seconds.

4. MSL = 1.

CTS**D

353STV

● xxx

SUGGESTED SOLDER PAD GEOMETRY

CBYPASS should be ≥ 0.01 uF.

D.U.T. PIN ASSIGNMENTS

PIN SYMBOL DESCRIPTION

1 VC Control Voltage

2 EOH or N.C. Enable [std] or No Connect

3 GND Circuit & Package Ground

4 Output RF Output

5 N.C. or EOH No Connect or Enable [opt]

6 VCC Supply Voltage

OUTPUT WAVEFORM, CMOS

TEST CIRCUIT, CMOS LOAD

TABLE I – DATE CODE

2001 2005 2009 2013 2017 A B C D E F G H J K L M

2002 2006 2010 2014 2018 N P Q R S T U V W X Y Z

2003 2007 2011 2015 2019 a b c d e f g h j k l m

2004 2008 2012 2016 2020 n p q r s t u v w x y z

MONTH JAN FEB MAR DEC

YEAR AUG SEP OCT NOVAPR MAY JUN JUL

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