74F564 Datasheet by ON Semiconductor

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© 2000 Fairchild Semiconductor Corporation DS009563 www.fairchildsemi.com
April 1983
Revised October 2000
74F564 Octal D-Type Flip-Flop with 3-STATE Outputs
74F564
Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
The 74F564 is a high-speed, low power octal flip-flop with a
buffered common Clock (CP) and a buffered common Out-
put Enable (OE). The information presented to the D inputs
is sorted in the flip-flops on the LOW-to-HIGH Clock (CP)
transition.
This device is functionally identical to the 74F574, but has
inverted outputs.
Features
Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
Useful as input or output port for microprocessors
Functionally identical to 74F574
3-STATE outputs for bus-oriented applications
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number Package Number Package Description
74F564SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F564PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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74F564
Unit Loading/Fan Out
Functional Description
The 74F564 consists of eight edge-triggered flip-flops with
individual D-type inputs and 3-STATE true outputs. The
buffered clock and buffered Output Enable are common to
all flip-flops. The eight flip-flops will store the state of their
individual D inputs that meet the setup and hold times
requirements on the LOW-to-HIGH Clock (CP) transition.
With the Output Enable (OE) LOW, the contents of the
eight flip-flops are available at the outputs. When OE is
HIGH, the outputs go to the high impedance state. Opera-
tion of the OE input does not affect the state of the
flip-flops.
Function Table
H = HIGH Voltage Level Z = High Impedance
L = LOW Voltage Level = LOW-to-HIGH Transition
X = Immaterial NC = No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names Description U.L. Input IIH/IIL
HIGH/LOW Output IOH/IOL
D0D7Data Inputs 1.0/1.0 20 µA/0.6 mA
CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/0.6 mA
OE 3-STATE Output Enable Input (Active LOW) 1.0/1.0 20 µA/0.6 mA
O0O73-STATE Outputs 150/40 (33.3) 3 mA/24 mA (20 mA)
Inputs Internal Outputs Function
OE CP D Q O
H H L NC Z Hold
HHH NC Z Hold
HL H Z Load
HH L Z Load
LL H H Data Available
LH L L Data Available
L H L NC NC No Change in Data
L H H NC NC No Change in Data
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74F564
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Storage Temperature 65°C to +150°C
Ambient Temperature under Bias 55°C to +125°C
Junction Temperature under Bias 55°C to +150°C
VCC Pin Potential to Ground Pin 0.5V to +7.0V
Input Voltage (Note 2) 0.5V to +7.0V
Input Current (Note 2) 30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output 0.5V to VCC
3-STATE Output 0.5V to +5.5V
Current Applied to Output
in LOW State (Max) twice the rated IOL (mA)
Free Air Ambient Temperature 0°C to +70°C
Supply Voltage +4.5V to +5.5V
Symbol Parameter Min Typ Max Units VCC Conditions
VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal
VCD Input Clamp Diode Voltage 1.2 V Min IIN = 18 mA
VOH Output HIGH 10% VCC 2.5
VMin
IOH = 1 mA
Voltage 10% VCC 2.4 IOH = 3 mA
5% VCC 2.7 IOH = 1 mA
5% VCC 2.7 IOH = 3 mA
VOL Output LOW 10% VCC 0.5 V Min IOL = 24 mA
Voltage
IIH Input HIGH 5.0 µAMaxV
IN = 2.7V
Current
IBVI Input HIGH Current 7.0 µAMaxV
IN = 7.0V
Breakdown Test
ICEX Output HIGH 50 µAMaxV
OUT = VCC
Leakage Current
VID Input Leakage 4.75 V 0.0 IID = 1.9 µA
Test All Other Pins Grounded
IOD Output Leakage 3.75 µA0.0
VIOD = 150 mV
Circuit Current All Other Pins Grounded
IIL Input LOW Current 0.6 mA Max VIN = 0.5V
IOZH Output Leakage Current 50 µAMaxV
OUT = 2.7V
IOZL Output Leakage Current 50 µAMaxV
OUT = 0.5V
IOS Output Short-Circuit Current 60 150 mA Max VOUT = 0V
IZZ Bus Drainage Test 500 µA0.0VV
OUT = 5.25V
ICCZ Power Supply Current 55 86 mA Max VO = HIGH Z
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74F564
AC Electrical Characteristics
AC Operating Requirements
Symbol Parameter
TA = +25°CT
A = 0°C to +70°C
Units
VCC = +5.0V VCC = +5.0V
CL = 50 pF CL = 50 pF
Min Typ Max Min Max
fMAX Maximum Clock Frequency 100 70 MHz
tPLH Propagation Delay 2.5 5.2 8.5 2.5 8.5 ns
tPHL CP to On2.5 5.9 8.5 2.5 8.5
tPZH Output Enable Time 3.0 5.6 9.0 2.5 10.0
ns
tPZL 3.0 6.2 9.0 2.5 10.0
tPHZ Output Disable Time 1.5 3.4 5.5 1.5 6.5
tPLZ 1.5 2.7 5.5 1.5 6.5
Symbol Parameter
TA = +25°CT
A = 0°C to +70°C
UnitsVCC = +5.0V VCC = +5.0V
Min Max Min Max
tS(H) Setup Time, HIGH or LOW 2.0 2.0
ns
tS(L) Dn to CP 2.5 2.5
tH(H) Hold Time, HIGH or LOW 2.0 2.0
tH(L) Dn to CP 2.0 2.0
tW(H) CP Pulse Width 5.0 5.0 ns
tW(L) HIGH or LOW 5.0 5.0
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74F564
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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74F564 Octal D-Type Flip-Flop with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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