ATECC108A Summary Datasheet by Microchip Technology

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ATECC108A

Atmel CryptoAuthentication Device

SUMMARY DATASHEET

Features

 Crypto Element Devices with Secure Hardware-based Key Storage

 Performs High-Speed Public Key (PKI) Algorithms

– ECDSA: FIPS186-3 Elliptic Curve Digital Signature Algorithm

 NIST Standard P256, B283 and K283 Elliptic Curve Support

 SHA-256 Hash Algorithm with HMAC Option

 Host and Client Operations

 256-bit and 283-bit Key Length

 Storage for up to 16 Keys

 Guaranteed Unique 72-bit Serial Number

 Internal High-quality FIPS Random Number Generator (RNG)

 10Kb EEPROM Memory for Keys, Certificates, and Data

 Storage for up to 16 Keys

 Multiple Options for Consumption Logging and One Time Write Information

 Intrusion Latch for External Tamper Switch or Power-on Chip Enablement.

Multiple I/O Options:

– High-speed Single Pin Interface, with One GPIO Pin

– 1MHz Standard I2C Interface

 2.0V to 5.5V Supply Voltage Range

 1.8V to 5.5V IO levels

 <150nA Sleep Current

 8-pad UDFN, 8-lead SOIC, and 3-lead CONTACT Packages

Applications

 Secure Download and Boot

 Ecosystem Control

 Message Security

 Anti-Cloning

Atmel-8895BS-CryptoAuth-ATECC108A-Datasheet-Summary_012016

This is a summary document.

The complete document is

available under NDA. For more

information, please contact

your local Atmel sales office.

Secure Download and Boot

Authentication and Protect Code

In-transit

Ecosystem Control

Ensure Only OEM/Licensed

Nodes and Accessories Work

Anti-cloning

Prevent Building with Identical

BOM or Stolen Code

Message Security

Authentication, Message Integrity,

and Confidentiality of Network

Nodes (IoT)

CryptoAuthentication

Ensures Things and Code

are Real, Untampered, and

Confidential

84nd SOIC (pr View) NC El]: Nc Ell: NC El]: GND Ell: .u»_ «.an II Vac I NC I scL II SDA NC NC Nc GND B-pad UDFN (TOP View) 3-Iead Contact (Top VIew) .uu- Vu: NC scL SDA SBA GND Vac AtmeL

ATECC108A [Summary Datasheet]

Atmel-8895BS-CryptoAuth-ATECC108A-Datasheet-Summary_012016

Pin Configuration and Pinouts

Table 1. Pin Configuration

Function

No Connect

GND

Ground

SDA

Serial Data

SCL

Serial Clock Input

VCC

Power Supply

Figure 1. Pinouts

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ATECC108A [Summary Datasheet]

Atmel-8895BS-CryptoAuth-ATECC108A-Datasheet-Summary_012016

1 Introduction

1.1 Applications

The Atmel® ATECC108A is a member of the Atmel CryptoAuthentication™ family of crypto engine authentication

devices with highly secure hardware-based key storage.

The ATECC108A has a flexible command set that allows use in many applications, including the following,

among many others:

 Network/IoT Node Protection

Authenticates node IDs and ensures the integrity of messages.

 Anti-Counterfeiting

Validates that a removable, replaceable, or consumable client is authentic. Examples of clients could be

system accessories, electronic daughter cards, or other spare parts. It can also be used to validate a

software/firmware module or memory storage element.

 Protecting Firmware or Media

Validates code stored in flash memory at boot to prevent unauthorized modifications, encrypt downloaded

program files as a common broadcast, or uniquely encrypt code images to be usable on a single system

only.

 Storing Secure Data

Store secret keys for use by crypto accelerators in standard microprocessors. The ATECC108A can be

used to store small quantities of data necessary for configuration, calibration, ePurse value, consumption

data, or other secrets. Programmable protection is available using encrypted/authenticated reads and

writes.

 Checking User Password

Validates user-entered passwords without letting the expected value become known, maps memorable

passwords to a random number, and securely exchanges password values with remote systems.

1.2 Device Features

The ATECC108A includes an EEPROM array which can be used for storage of up to 16 keys, certificates,

miscellaneous read/write, read-only or secret data, consumption logging, and security configurations. Access to

the various sections of memory can be restricted in a variety of ways and then the configuration can be locked to

prevent changes.

The ATECC108A features a wide array of defense mechanisms specifically designed to prevent physical attacks

on the device itself, or logical attacks on the data transmitted between the device and the system. Hardware

restrictions on the ways in which keys are used or generated provide further defense against certain styles of

attack.

Access to the device is made through a standard I2C Interface at speeds of up to 1Mb/s. The interface is

compatible with standard Serial EEPROM I2C interface specifications. The device also supports a Single-Wire

Interface (SWI), which can reduce the number of GPIOs required on the system processor, and/or reduce the

number of pins on connectors. If the Single-Wire Interface is enabled, the remaining pin is available for use as a

GPIO, an authenticated output or tamper input.

Using either the I2C or Single-Wire Interface, multiple ATECC108A devices can share the same bus, which saves

processor GPIO usage in systems with multiple clients such as different color ink tanks or multiple spare parts,

for example.

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ATECC108A [Summary Datasheet]

Atmel-8895BS-CryptoAuth-ATECC108A-Datasheet-Summary_012016

Each ATECC108A ships with a guaranteed unique 72-bit serial number. Using the cryptographic protocols

supported by the device, a host system or remote server can verify a signature of the serial number to prove that

the serial number is authentic and not a copy. Serial numbers are often stored in a standard Serial EEPROM;

however, these can be easily copied with no way for the host to know if the serial number is authentic or if it is a

clone.

The ATECC108A can generate high-quality FIPS random numbers and employ them for any purpose, including

usage as part of the device’s crypto protocols. Because each random number is guaranteed to be essentially

unique from all numbers ever generated on this or any other device, their inclusion in the protocol calculation

ensures that replay attacks (i.e. re-transmitting a previously successful transaction) will always fail.

System integration is easy due to a wide supply voltage range (of 2.0V to 5.5V) and an ultra-low sleep current (of

<150nA). Multiple package options are available (See Sections 4, Ordering Information and Section 5, Package

Drawings).

See Section 3 for information regarding compatibility with the Atmel ATSHA204 and ATECC108.

1.3 Cryptographic Operation

The ATECC108A implements a complete asymmetric (public/private) key cryptographic signature solution based

upon Elliptic Curve Cryptography and the ECDSA signature protocol. The device features hardware acceleration

for the NIST standard P256 prime curve and supports the complete key life cycle from high quality private key

generation, to ECDSA signature generation, and ECDSA public key signature verification.

The hardware accelerator can implement such asymmetric cryptographic operations from ten to one-thousand

times faster than software running on standard microprocessors, without the usual high risk of key exposure that

is endemic to standard microprocessors.

The device is designed to securely store multiple private keys along with their associated public keys and

certificates. The signature verification command can use any stored or an external ECC public key. Public keys

stored within the device can be configured to require validation via a certificate chain to speed-up subsequent

device authentications.

Random private key generation is supported internally within the device to ensure that the private key can never

be known outside of the device. The public key corresponding to a stored private key is always returned when the

key is generated and it may optionally be computed at a later time.

The ATECC108A also supports a standard hash-based challenge-response protocol in order to simplify

programming. In its most basic instantiation, the system sends a challenge to the device, which combines that

challenge with a secret key and then sends the response back to the system. The device uses a SHA-256

cryptographic hash algorithm to make that combination so that an observer on the bus cannot derive the value of

the secret key, but preserving that ability of a recipient to verify that the response is correct by performing the

same calculation with a stored copy of the secret on the recipient’s system.

Due to the flexible command set of the ATECC108A, these basic operation sets (i.e. ECDSA signatures and

SHA-256 challenge-response) can be expanded in many ways.

In a host-client configuration where the host (for instance a mobile phone) needs to verify a client (for instance an

OEM battery), there is a need to store the secret in the host in order to validate the response from the client. The

CheckMac command allows the device to securely store the secret in the host system and hides the correct

response value from the pins, returning only a yes or no answer to the system.

All hashing functions are implemented using the industry-standard SHA-256 secure hash algorithm, which is part

of the latest set of high-security cryptographic algorithms recommended by various government agencies and

cryptographic experts. The ATECC108A employs full-sized 256 bit secret keys to prevent any kind of exhaustive

attack.

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ATECC108A [Summary Datasheet]

Atmel-8895BS-CryptoAuth-ATECC108A-Datasheet-Summary_012016

2 Electrical Characteristics

2.1 Absolute Maximum Ratings*

Operating Temperature .......................... -40°C to 85°C

Storage Temperature ........................... -65°C to 150°C

Maximum Operating Voltage................................. 6.0V

DC Output Current ................................................ 5mA

Voltage on any pin ...................... -0.5V to (VCC + 0.5V)

*Notice: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional

operation of the device at these or any other

conditions beyond those indicated in the operational

sections of this specification are not implied. Exposure

to absolute maximum rating conditions for extended

periods may affect device reliability.

2.2 Reliability

The ATECC108A is fabricated with the Atmel high reliability of the CMOS EEPROM manufacturing technology.

Table 2-1. EEPROM Reliability

Parameter

Min

Typical

Max

Units

Write Endurance (Each Byte)

400,000

Write Cycles

Data Retention (At 55C)

Years

Data Retention (At 35C)

Years

Read Endurance

Unlimited

Read Cycles

2.3 AC Parameters: All I/O Interfaces

Figure 2-1. AC Parameters: All I/O Interfaces

Parameter (1)

Symbol

Direction

Min

Typ

Max

Unit

Notes

Power-Up Delay

tPU

To Crypto

Authentication

100

—

µs

Minimum time between VCC > VCC min prior

to measurement of tWLO.

Wake Low

Duration

tWLO

To Crypto

Authentication

—

µs

Wake High

Delay to Data

Comm.

tWHI

To Crypto

Authentication

500

µs

SDA should be stable high for this entire

duration.

High Side Glitch

Filter at Active

tHIGNORE_A

To Crypto

Authentication

45(1)

Pulses shorter than this in width will be

ignored by the device, regardless of its

state when active.

Low Side Glitch

Filter at Active

tLIGNORE_A

To Crypto

Authentication

45(1)

Pulses shorter than this in width will be

ignored by the device, regardless of its

state when active.

Low Side Glitch

Filter at Sleep

tLIGNORE_S

To Crypto

Authentication

15(1)

µs

Pulses shorter than this in width will be

ignored by the device when in sleep mode.

Watchdog

Timeout

tWATCHDOG

To Crypto

Authentication

0.7

1.3

1.7

Maximum time from wake until device is

forced into sleep mode.

Note: 1. These parameters are guaranteed through characterization, but not tested.

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ATECC108A [Summary Datasheet]

Atmel-8895BS-CryptoAuth-ATECC108A-Datasheet-Summary_012016

2.3.1 AC Parameters: Single-Wire Interface

Table 2-2. AC Parameters: Single-Wire Interface

Applicable from TA = -40°C to +85°C, VCC = +2.0V to +5.5V, CL =100pF (unless otherwise noted).

Parameter

Symbol

Direction

Min

Typ

Max

Unit

Notes

Start Pulse

Duration

tSTART

To Crypto

Authentication

4.10

4.34

4.56

µs

From Crypto

Authentication

4.60

8.60

µs

Zero

Transmission

High Pulse

tZHI

To Crypto

Authentication

4.10

4.34

4.56

µs

From Crypto

Authentication

4.60

8.60

µs

Zero

Transmission

Low Pulse

tZLO

To Crypto

Authentication

4.10

4.34

4.56

µs

From Crypto

Authentication

4.60

8.60

µs

Bit Time(1)

tBIT

To Crypto

Authentication

—

µs

If the bit time exceeds tTIMEOUT then ATECC108A may

enter the sleep mode.

From Crypto

Authentication

µs

Turn Around

Delay

tTURNAROUND

From Crypto

Authentication

131

µs

ATECC108A will initiate the first low going transition

after this time interval following the initial falling edge of

the start pulse of the last bit of the transmit flag.

To Crypto

Authentication

µs

After ATECC108A transmits the last bit of a group,

system must wait this interval before sending the first bit

of a flag. It is measured from the falling edge of the start

pulse of the last bit transmitted by ATECC108A.

IO Timeout

tTIMEOUT

To Crypto

Authentication

ATECC108A may transition to the sleep mode if the bus

is inactive longer than this duration.

Note: 1. START, ZLO, ZHI, and BIT are designed to be compatible with a standard UART running at 230.4Kbaud for

both transmit and receive. The UART should be set to seven data bits, no parity and one Stop bit.

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ATECC108A [Summary Datasheet]

Atmel-8895BS-CryptoAuth-ATECC108A-Datasheet-Summary_012016

2.3.2 AC Parameters: I2C Interface

Table 2-3. AC Characteristics of I2C Interface

Applicable over recommended operating range from TA = -40°C to + 85°C, VCC = +2.0V to +5.5V,

CL = 1 TTL Gate and 100pF (unless otherwise noted).

Symbol

Parameter

Min

Max

Units

fSCK

SCK Clock Frequency

MHz

tHIGH

SCK High Time

400

tLOW

SCK Low Time

400

tSU.STA

Start Setup Time

250

tHD.STA

Start Hold Time

250

tSU.STO

Stop Setup Time

250

tSU.DAT

Data In Setup Time

100

tHD.DAT

Data In Hold Time

Input Rise Time(1)

300

Input Fall Time(1)

100

tAA

Clock Low to Data Out Valid

550

tDH

Data Out Hold Time

tTIMEOUT

SMBus Timeout Delay

tBUF

Time bus must be free before a new transmission can start. (1)

500

Note: 1. Values are based on characterization and are not tested.

AC measurement conditions:

 RL (connects between SDA and VCC): 1.2k (for VCC +2.0V to +5.0V)

 Input pulse voltages: 0.3VCC to 0.7VCC

 Input rise and fall times:  50ns

 Input and output timing reference voltage: 0.5VCC

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ATECC108A [Summary Datasheet]

Atmel-8895BS-CryptoAuth-ATECC108A-Datasheet-Summary_012016

2.4 DC Parameters: All I/O Interfaces

Table 2-4. DC Parameters on All I/O Interfaces

Parameter

Symbol

Min

Typ

Max

Unit

Notes

Ambient Operating Temperature

-40

C

Power Supply Voltage

VCC

2.0

5.5

Active Power Supply Current

ICC

Waiting for I/O during I/O transfers or execution

of non-ECC commands when ChipMode:3 is

zero.

—

During ECC command execution.

Idle Power Supply Current

IIDLE

800

µA

When device is in idle mode,

VSDA and VSCL < 0.4V or > VCC – 0.4

Sleep Current

ISLEEP

150

When device is in sleep mode, VCC  3.6V,

VSDA and VSCL < 0.4V or > VCC – 0.4, TA  55°C

µA

When device is in sleep mode.

Output Low Voltage

VOL

0.4

When device is in active mode,

VCC = 2.5 – 5.5V

Output Low Current

IOL

When device is in active mode,

VCC = 2.5 – 5.5V, VOL = 0.4V

Theta JA

ƟJA

166

C/W

SOIC (SSH)

173

C/W

UDFN (MAH)

146

C/W

RBH

2.4.2 VIH and VIL Specifications

The input voltage thresholds when in sleep or idle mode are dependent on the VCC level as shown in the graph

below. When the device is active (i.e. not in sleep or idle mode), the input voltage thresholds are different

depending upon the state of TTLenable (bit 1) within the ChipMode byte in the Configuration zone of the

EEPROM. When a common voltage is used for the ATECC108A VCC pin and the input pull-up resistor, then this

bit should be set to a one, which permits the input thresholds to track the supply.

If the voltage supplied to the VCC pin of the ATECC108A is different than the system voltage to which the input

pull-up resistor is connected, then the system designer may choose to set TTLenable to zero, which enables a

fixed input threshold according to the following table. The following applies only when the device is active:

Table 2-5. VIL, VIH on All I/O Interfaces

Parameter

Symbol

Min

Typ

Max

Unit

Notes

Input Low Voltage

VIL

-0.5

0.5

When device is active and TTLenable bit in

configuration memory is zero.

Input High Voltage

VIH

1.5

VCC + 0.5

When device is active and TTLenable bit in

configuration memory is zero.

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ATECC108A [Summary Datasheet]

Atmel-8895BS-CryptoAuth-ATECC108A-Datasheet-Summary_012016

3 Compatibility

3.1 Atmel ATSHA204

If properly configured, it can be used in all situations where the ATSHA204 or ATSHA204A is currently employed.

Because the Configuration zone is larger, the personalization procedures for the device must be updated when

personalizing the ATSHA204 or ATSHA204A.

3.2 Atmel ATECC108

ATECC108A is designed to be fully compatible with the ATECC108. If properly configured, can be used in all

situations where ATECC108 is currently employed. In many situations, the ATECC108A can also be used in an

ATECC108 application without change. The new revisions provide significant advantages as outlined below:

New Features in ATECC108A vs. ATECC108

 Intrusion Detection Capability, Including Gating Key Use

 New SHA Command, Also Computes HMAC

 X.509 Certificate Verification Capability

 Programmable Watchdog Timer Length

 Shared Random Nonce and Key Configuration Validation (Gendig Command)

Larger Slot 8 which is Extended to 416 bytes

4 Ordering Information

Atmel Ordering Code(4)

Package

Interface Configuration

ATECC108A-SSHCZ-T

8-lead SOIC, Tape and Reel(2)

Single-Wire

ATECC108A-SSHCZ-B

8-lead SOIC, Bulk in Tubes(1)

Single-Wire

ATECC108A-SSHDA-T

8-lead SOIC, Tape and Reel(2)

I2C

ATECC108A-SSHDA-B

8-lead SOIC, Bulk in Tubes(1)

I2C

ATECC108A-MAHCZ-T

8-pad UDFN, Tape and Reel(2)

Single-Wire

ATECC108A-MAHDA-T

8-pad UDFN, Tape and Reel(2)

I2C

ATECC108A-RBHCZ-T(3)

3-lead CONTACT, Tape and Reel(2)

Single-Wire

Notes: 1. B = Bulk

2. T = Tape and Reel

 SOIC = 4,000 units per reel.

 UDFN = 15,000 units per reel.

 RBH = 5,000 units per reel.

3. Please contact Atmel for availability.

4. Please contact Atmel for thinner packages.

AtmeL AtmeL

ATECC108A [Summary Datasheet]

Atmel-8895BS-CryptoAuth-ATECC108A-Datasheet-Summary_012016

5 Package Drawings

5.1 8-lead SOIC

DRAWING NO. REV.TITLE GPC

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A1 0.10 –0.25

A– – 1.75

b0.31 –0.51

C0.17 –0.25

D4.90 BSC

E6.00 BSC

E1 3.90 BSC

e1.27 BSC

L0.40 –1.27

0° –8°

TOP VIEW

END VIEW

SIDE VIEW

Package Drawing Contact:

packagedrawings@atmel.com

8S1 H

3/6/2015

Notes: This drawing is for general information only.

Refer to JEDEC Drawing MS-012, Variation AA

for proper dimensions, tolerances, datums, etc.

8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing

Small Outline (JEDEC SOIC) SWB

l [ TOP VIEW + + T T SIDE VIEW T f a E L w T: 17‘ L I j 2 E i} E i i W DT * I «b ¢ + l‘7 W Atmel AtmeL 11

ATECC108A [Summary Datasheet]

Atmel-8895BS-CryptoAuth-ATECC108A-Datasheet-Summary_012016

5.2 8-pad UDFN

DRAWING NO. REV.TITLE GPC

8MA2 H

11/2/15

8MA2, 8-pad 2 x 3 x 0.6mm Body, Thermally

Enhanced Plastic Ultra Thin Dual Flat No-Lead

Package (UDFN)

YNZ

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A 0.50 0.55 0.60

A1 0.0 0.02 0.05

A2 - - 0.55

D 1.90 2.00 2.10

D2 1.40 1.50 1.60

E 2.90 3.00 3.10

E2 1.20 1.30 1.40

b 0.18 0.25 0.30 3

C 0.152 REF

L 0.35 0.40 0.45

e 0.50 BSC

K 0.20 - -

TOP VIEW

SIDE VIEW

BOTTOM VIEW

Package Drawing Contact:

packagedrawings@atmel.com

Pin 1 ID

e (6x)

L (8x)

b (8x)

Pin#1 ID

Notes: 1. This drawing is for general information only. Refer to

Drawing MO-229, for proper dimensions, tolerances,

datums, etc.

2. The Pin #1 ID is a laser-marked feature onTop View.

3. Dimensions b applies to metallized terminal and is

measured between 0.15 mm and 0.30 mm from the

terminal tip. If the terminal has the optional radius on

the other end of the terminal, the dimension should

not be measured in that radius area.

4. The Pin #1 ID on the Bottom View is an orientation

feature on the thermal pad.

PM 1 __\ f /—Pln 1 o T —\« 'I + + J h e(3x) + Lax) *ﬂ“ ——| ~a MEAL smulm W Atmel AtmeL

ATECC108A [Summary Datasheet]

Atmel-8895BS-CryptoAuth-ATECC108A-Datasheet-Summary_012016

5.3 3-lead CONTACT

DRAWING NO. REV.TITLE GPC

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

D 2.40 2.50 2.60

E 6.40 6.50 6.60

A 0.45 0.50 0.55

e 1.60 1.70 1.80

b 1.90 2.00 2.10

L 2.10 2.20 2.30

f 0.30 0.40 0.50

g 0.05 0.15 0.25

h 2.30 2.40 2.50

j 4.30 4.40 4.50

Package Drawing Contact:

packagedrawings@atmel.com 3RB 01

1/31/11

3RB, 3-lead 2.5x6.5mm Body, 2.0 mm pitch,

CONTACT PACKAGE. (Sawn) RHB

AtmeL

ATECC108A [Summary Datasheet]

Atmel-8895BS-CryptoAuth-ATECC108A-Datasheet-Summary_012016

6 Revision History

Doc. Rev.

Date

Comments

8895BX

01/2016

Updated write endurance from write cycles of 100,000 to 400,000 minimum and the 8S1

and 8MA2 package drawings.

8895AX

02/2015

Initial summary document release. The complete document is available under NDA. For

more information, please contact your local Atmel sales office.

Security at our Core Atmel Has You Covered - Enabling Unlimited Possibiiities“ n a m & y

ATECC108A [Summary Datasheet]

Atmel-8895BS-CryptoAuth-ATECC108A-Datasheet-Summary_012016

Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 │ www.atmel.com

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