83PN148DKILF Datasheet by Renesas Electronics America Inc.
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ICS83PN148DKI REVISION A OCTOBER 11, 2012 1 ©2012 Integrated Device Technology, Inc.
Programmable FemtoClock® NG LVPECL
Oscillator Replacement
ICS83PN148I
General Description
The ICS83PN148I is a programmable LVPECL synthesizer that is
“forward” footprint compatible with standard 5mm x 7mm oscillators.
The device uses IDT’s fourth generation FemtoClock® NG
technology for an optimum of high clock frequency and low phase
noise performance. Forward footprint compatibility means that a
board designed to accommodate the crystal oscillator interface and
the optional control pins is also fully compatible with a canned
oscillator footprint - the canned oscillator will drop onto the
10-VFQFN footprint for second sourcing purposes. This capability
provides designers with programability and lead time advantages of
silicon/crystal based solutions while maintaining compatibility with
industry standard 5mm x 7mm oscillator footprints for ease of supply
chain management. Oscillator-level performance is maintained with
IDT’s 4th Generation FemtoClock® NG PLL technology, which
delivers sub 0.5ps rms phase jitter.
The ICS83PN148I defaults to 148.5MHz using a 27MHz crystal with
2 programming pins floating (pulled down/pulled up with internal
pullup or pulldown resistors) but can also be set to 4 different
frequency multiplier settings to support a wide variety of
applications. The below table shows some of the more common
application settings.
Features
•Fourth Generation FemtoClock® Next Generation (NG)
technology
•Footprint compatible with 5mm x 7mm differential oscillators
•One differential LVPECL output pair
•Crystal oscillator interface can also be overdriven by a
single-ended reference clock
•Output frequency range: 54MHz –148.5MHz
•Crystal/input frequency: 27MHz, parallel resonant crystal
•VCO range: 2GHz – 2.5GHz
•Cycle-to-cycle jitter: 10ps (maximum), 3.3V±5%
•RMS phase jitter @ 148.5MHz, 12kHz – 20MHz:
0.332ps (typical)
•Full 3.3V or 2.5V operating supply
•-40°C to 85°C ambient operating temperature
•Available in lead-free (RoHS 6) package
Common Applications and Settings
FSEL[1:0] XTAL (MHz) Output Frequency
(MHz) Application(s)
00 27 67.5 HD-SDI Video
01 27 74.25 HD Video
10 27 54 N x 27MHz
11 (default) 27 148.5 HD-SDI Video
VCC
nQ
Q
RESERVED
OE
XTAL_IN
XTAL_OUT
FSEL0
FSEL1
1
2
3
45
6
7
8
9
10
VEE
Q
nQ
Pullup
OSC
PFD
&
LPF
FemtoClock® NG
VCO
2 - 2.5GHz
÷M
÷N
XTAL_IN
XTAL_OUT
FSEL0
FSEL1
OE
Pullup
Control
Logic
Pullup
Pin Assignment
ICS83PN148I
10-Lead VFQFN
5mm x 7mm x 1mm package body
K Package
Top View
Block Diagram
ICS83PN148I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL OSCILLATOR REPLACEMENT
ICS83PN148DKI REVISION A OCTOBER 11, 2012 2 ©2012 Integrated Device Technology, Inc.
Table 1. Pin Descriptions
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Function Table
Table 3. Divider Function Table
Number Name Type Description
1 OE Input Pullup Output enable. LVCMOS/LVTTL interface levels.
2 RESERVED Reserved pin. Do not connect.
3V
EE Power Negative supply pin.
4,
5
XTAL_OUT
XTAL_IN Input Crystal oscillator interface XTAL_IN is the input, XTAL_OUT is the output. This
oscillator interface can also be driven by a single-ended reference clock.
6, 7 Q, nQ Output Differential output pair. LVPECL interface levels.
8V
CC Power Power supply pin.
9 FSEL0 Input Pullup Output divider control input. Sets the output divider value to one of four values.
See Table 3. LVCMOS/LVTTL interface levels.
10 FSEL1 Input Pullup Output divider control input. Sets the output divider value to one of four values.
See Table 3. LVCMOS/LVTTL interface levels
Symbol Parameter Test Conditions Minimum Typical Maximum Units
CIN Input Capacitance 4pF
RPULLUP Input Pullup Resistor 51 k
FSEL[1:0] M Value N Value
0 0 ÷80 ÷32
0 1 ÷88 ÷32
1 0 ÷76 ÷38
1 1 (default) ÷88 ÷16
ce, 0
39 2“
455“
50“
ICS83PN148I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL OSCILLATOR REPLACEMENT
ICS83PN148DKI REVISION A OCTOBER 11, 2012 3 ©2012 Integrated Device Technology, Inc.
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
.
Table 4B. Power Supply DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Table 4C. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Item Rating
Supply Voltage, VCC 3.63V
Inputs, VI
XTAL_IN
Other Inputs
0V to 2V
-0.5V to VCC + 0.5V
Outputs, IO
Continuos Current
Surge Current
50mA
100mA
Package Thermal Impedance, JA 39.2C/W (0 mps)
Storage Temperature, TSTG -65C to 150C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC Power Supply Voltage 3.135 3.3 3.465 V
IEE Power Supply Current 131 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC Power Supply Voltage 2.375 2.5 2.625 V
IEE Power Supply Current 124 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH Input High Voltage VCC = 3.465V 2 VCC + 0.3 V
VCC = 2.625V 1.7 VCC + 0.3 V
VIL Input Low Voltage VCC = 3.465V -0.3 0.8 V
VCC = 2.625V -0.3 0.7 V
IIH
Input High
Current
OE,
FSEL[1:0] VCC = VIN = 3.465V or 2.625V 5 µA
IIL
Input Low
Current
OE,
FSEL[1:0] VCC = 3.465V or 2.625V, VIN = 0V -150 µA
ICS83PN148I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL OSCILLATOR REPLACEMENT
ICS83PN148DKI REVISION A OCTOBER 11, 2012 4 ©2012 Integrated Device Technology, Inc.
Table 4D. LVPECL DC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, , VEE = 0V, TA = -40°C to 85°C
NOTE 1: Outputs termination with 50 to VCC – 2V.
Table 5. Crystal Characteristics
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH Output High Voltage; NOTE 1 VCC – 1.3 VCC – 0.8 V
VOL Output Low Voltage; NOTE 1 VCC – 2.0 VCC – 1.6 V
VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V
Parameter Test Conditions Minimum Typical Maximum Units
Mode of Oscillation Fundamental
Frequency 27 MHz
Equivalent Series Resistance (ESR) 50
Shunt Capacitance 7pF
ICS83PN148I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL OSCILLATOR REPLACEMENT
ICS83PN148DKI REVISION A OCTOBER 11, 2012 5 ©2012 Integrated Device Technology, Inc.
AC Electrical Characteristics
Table 6A. AC Characteristics, Vcc = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Please refer to the Phase Noise plots.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
Table 6B. AC Characteristics, Vcc = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Please refer to the Phase Noise plots.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
fMAX Output Frequency 54 148.5 MHz
tjit(Ø) RMS Phase Jitter (Random);
NOTE 1
67.5MHz,
Integration Range: 12kHz – 20MHz 0.332 0.5 ps
74.25MHz,
Integration Range: 12kHz – 20MHz 0.344 0.5 ps
54MHz,
Integration Range: 12kHz – 20MHz 0.341 0.5 ps
148.5MHz,
Integration Range: 12kHz – 20MHz 0.326 0.5 ps
tjit(cc) Cycle-to-Cycle Jitter; NOTE 2 10 ps
tR / tFOutput Rise/Fall Time 20% to 80% 100 350 ps
odc Output Duty Cycle 49 51 %
Symbol Parameter Test Conditions Minimum Typical Maximum Units
fMAX Output Frequency 54 148.5 MHz
tjit(Ø) RMS Phase Jitter (Random);
NOTE 1
67.5MHz,
Integration Range: 12kHz – 20MHz 0.335 0.5 ps
74.25MHz,
Integration Range: 12kHz – 20MHz 0.347 0.5 ps
54MHz,
Integration Range: 12kHz – 20MHz 0.341 0.5 ps
148.5MHz,
Integration Range: 12kHz – 20MHz 0.326 0.5 ps
tjit(cc) Cycle-to-Cycle Jitter; NOTE 2 20 ps
tR / tFOutput Rise/Fall Time 20% to 80% 100 350 ps
odc Output Duty Cycle 49 51 %
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ICS83PN148I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL OSCILLATOR REPLACEMENT
ICS83PN148DKI REVISION A OCTOBER 11, 2012 6 ©2012 Integrated Device Technology, Inc.
Typical Phase Noise at 54MHz (3.3V core, 3.3V output)
Typical Phase Noise at 67.5MHz (3.3V core, 3.3V output)
Offset Frequency (Hz)
Noise Power dBc
Hz
Offset Frequency (Hz)
Noise Power dBc
Hz
when Nuse 10.00am R=r0.000d0(le [Smw]
n .000
40.00
»20.00
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430.0
440.0
450.0
460.0
470.0
400.0 1
nah.“ Nnixe 10.00am Ref 0000:10de [Smo]
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420.0
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400.0 1
ICS83PN148I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL OSCILLATOR REPLACEMENT
ICS83PN148DKI REVISION A OCTOBER 11, 2012 7 ©2012 Integrated Device Technology, Inc.
Typical Phase Noise at 74.25MHz @ (3.3V core, 3.3V output)
Typical Phase Noise at 148.5MHz (3.3V core, 3.3V output)
Offset Frequency (Hz)
Noise Power dBc
Hz
Offset Frequency (Hz)
Noise Power dBc
Hz
5052 5052
50:1 50:1
IHNv-l n
"HM—l u
ICS83PN148I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL OSCILLATOR REPLACEMENT
ICS83PN148DKI REVISION A OCTOBER 11, 2012 8 ©2012 Integrated Device Technology, Inc.
Parameter Measurement Information
3.3V LVPECL Output Load AC Test Circuit
RMS Phase Jitter
Output Rise/Fall Time
2.5V LVPECL Output Load AC Test Circuit
Output Duty Cycle/Pulse Width/Period
Cycle-to-Cycle Jitter
SCOPE
Qx
nQx
VEE
VCC
2V
-1.3V ± 0.165V
Offset Frequency
f1f2
Phase Noise Plot
Area Under Curve Defined by the Offset Frequency Markers
RMS Phase Jitter =
Noise Power
2 * * ƒ
1*
20%
80% 80%
20%
tRtF
VSWING
nQ
Q
SCOPE
Qx
nQx
VEE
VCC
2V
-0.5V ± 0.125V
tPW
tPERIOD
tPW
tPERIOD
odc = x 100%
nQ
Q
➤
➤
➤
➤
tcycle n tcycle n+1
tjit(cc) =
|
tcycle n – tcycle n+1
|
1000 Cycles
nQ
Q
,%
\//
ICS83PN148I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL OSCILLATOR REPLACEMENT
ICS83PN148DKI REVISION A OCTOBER 11, 2012 9 ©2012 Integrated Device Technology, Inc.
Application Information
Recommendations for Unused Input Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pullups; additional resistance is not
required but can be added for additional protection. A 1k resistor
can be used.
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 1. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
Figure 1. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
SOLDERSOLDER PINPIN EXPOSED HEAT SLUG
PIN PAD PIN PADGROUND PLANE LAND PATTERN
(GROUND PAD)
THERMAL VIA
«H
D
H
«H
H
ICS83PN148I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL OSCILLATOR REPLACEMENT
ICS83PN148DKI REVISION A OCTOBER 11, 2012 10 ©2012 Integrated Device Technology, Inc.
Crystal Input Interface
The ICS83PN148I has been characterized with 12pF parallel
resonant crystals. The capacitor values shown in Figure 2A below
were determined using a 25MHz, 12pF parallel resonant crystal and
were chosen to minimize the ppm error. Other parallel resonant
crystal’s values can be used. For example, a crystal with a CL = 18pF
can be used, but would require the tuning capacitors to be adjusted.
Figure 2A. Crystal Input Interface, using 12pF crystal Figure 2B. Crystal Input Interface, using 18pF crystal
Overdriving the XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3A. The XTAL_OUT pin can be left floating. The
maximum amplitude of the input signal should not exceed 2V and the
input edge rate can be as slow as 10ns. This configuration requires
that the output impedance of the driver (Ro) plus the series
resistance (Rs) equals the transmission line impedance. In addition,
matched termination at the crystal input will attenuate the signal in
half. This can be done in one of two ways. First, R1 and R2 in parallel
should equal the transmission line impedance. For most 50
applications, R1 and R2 can be 100. This can also be
accomplished by removing R1 and making R2 50. By overdriving
the crystal oscillator, the device will be functional, but note, the device
performance is guaranteed by using a quartz crystal.
Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface
Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface
XTAL_IN
XTAL_OUT
X1
12pF Parallel Crystal
C1
4pF
C2
4pF
XTAL_IN
XTAL_OUT
X1
18pF Parallel Crystal
C1
16pF
C2
16pF
R2
100
R1
100
RS 43
Ro ~ 7 Ohm
Driver_LVCMOS
Zo = 50 Ohm C1
0.1uF
3.3V
3.3V
Crystal Input Interface
XTA L _ I N
XTA L _ O U T
Crystal Input Interface
XTAL_IN
XTAL_OUT
R3
50
C1
0.1uF
R2
50
R1
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
VCC=3.3V
\\\\\
ICS83PN148I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL OSCILLATOR REPLACEMENT
ICS83PN148DKI REVISION A OCTOBER 11, 2012 11 ©2012 Integrated Device Technology, Inc.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
Figure 4A. 3.3V LVPECL Output Termination Figure 4B. 3.3V LVPECL Output Termination
3.3V
VCC - 2V
R1
50Ω
R2
50Ω
RTT
Zo = 50Ω
Zo = 50Ω
+
_
RTT = * Zo
1
((VOH + VOL) / (VCC – 2)) – 2
3.3V
LVPECL Input
R1
84Ω
R2
84Ω
3.3V
R3
125Ω
R4
125Ω
Zo = 50Ω
Zo = 50Ω
LVPECL Input
3.3V
3.3V
+
_
ICS83PN148I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL OSCILLATOR REPLACEMENT
ICS83PN148DKI REVISION A OCTOBER 11, 2012 12 ©2012 Integrated Device Technology, Inc.
Termination for 2.5V LVPECL Outputs
Figure 5A and Figure 5B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating 50
to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground
level. The R3 in Figure 5B can be eliminated and the termination is
shown in Figure 5C.
Figure 5A. 2.5V LVPECL Driver Termination Example
Figure 5C. 2.5V LVPECL Driver Termination Example
Figure 5B. 2.5V LVPECL Driver Termination Example
2.5V LVPECL Driver
VCC = 2.5V
2.5V
2.5V
50Ω
50Ω
R1
250Ω
R3
250Ω
R2
62.5Ω
R4
62.5Ω
+
–
2.5V LVPECL Driver
VCC = 2.5V
2.5V
50Ω
50Ω
R1
50Ω
R2
50Ω
+
–
2.5V LVPECL Driver
VCC = 2.5V
2.5V
50Ω
50Ω
R1
50Ω
R2
50Ω
R3
18Ω
+
–
ICS83PN148I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL OSCILLATOR REPLACEMENT
ICS83PN148DKI REVISION A OCTOBER 11, 2012 13 ©2012 Integrated Device Technology, Inc.
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS83PN148I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS83PN148I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 131mA = 453.915mW
• Power (outputs)MAX = 32mW/Loaded Output pair
Total Power_MAX (3.3V, with all outputs switching) = 453.915mW + 32mW = 485.915mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 39.2°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.486W * 39.2°C/W = 104.1°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance JA for 10 Lead VFQFN, Forced Convection
JA vs. Air Flow
Meters per Second 0
Multi-Layer PCB, JEDEC Standard Test Boards 39.2°C/W
ICS83PN148I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL OSCILLATOR REPLACEMENT
ICS83PN148DKI REVISION A OCTOBER 11, 2012 14 ©2012 Integrated Device Technology, Inc.
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.
LVPECL output driver circuit and termination are shown in Figure 6.
Figure 6. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of
VCC – 2V.
• For logic high, VOUT = VOH_MAX = VCC_MAX – 0.8V
(VCC_MAX – VOH_MAX) = 0.8V
• For logic low, VOUT = VOL_MAX = VCC_MAX – 1.6V
(VCC_MAX – VOL_MAX) = 1.6V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =
[(2V – 0.8V)/50] * 0.8V = 19.2mW
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =
[(2V – 1.6V)/50] * 1.6V = 12.82mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32mW
VOUT
VCC
VCC - 2V
Q1
RL
50Ω
ICS83PN148I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL OSCILLATOR REPLACEMENT
ICS83PN148DKI REVISION A OCTOBER 11, 2012 15 ©2012 Integrated Device Technology, Inc.
Reliability Information
Table 8. JA vs. Air Flow Table for a 10 Lead VFQFN
Transistor Count
The transistor count for ICS83PN148I is: 24,932
Package Dimensions
Table 9. Package Dimensions for 10-Lead VFQFN
JA vs. Air Flow
Meters per Second 0
Multi-Layer PCB, JEDEC Standard Test Boards 39.2°C/W
VNJR-1
All Dimensions in Millimeters
Symbol Minimum Nominal Maximum
N10
A0.80 0.90 1.00
A1 0 0.02 0.05
b1 0.35 0.40 0.45
b2 1.35 1.40 1.45
D5.00 Basic
D2 1.55 1.70 1.80
E7.00 Basic
E2 3.55 3.70 3.80
e1 1.0
e2 2.54
L1 0.45 0.55 0.65
L2 1.0 1.10 1.20
N10
ND 2
NE3
aaa 0.15
bbb 0.10
ccc 0.10
INDEX AREA
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RADIUS
K“
ICS83PN148I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL OSCILLATOR REPLACEMENT
ICS83PN148DKI REVISION A OCTOBER 11, 2012 16 ©2012 Integrated Device Technology, Inc.
Package Outline
Package Outline - K Suffix for 10-Lead VFQFN
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This drawing
is not intended to convey the actual pin count or pin layout of this
device. The pin count and pinout are shown on the front page. The
package dimensions are in Table 9.
ccc C
PLANE
SEATING
0.08 C
8
A
B
C
bbb C A B
7
4
INDEX AREA
(D/2 xE/2)
(D/2 xE/2)
4
INDEX AREA
aaa C2x
TOP VIEW9
aaa C2x
SIDE VIEW
BOTTOM VIEW
PIN#1 ID
D
E
e1
e2
A1
NX b1
NX b2
bbb C A B
7
E2
D2
A
NX L1
NX L2
0.1mm→
→
0.1mm
N-1N
CHAMFER
1
2
N-1
1
2
N
RADIUS
4
4
Bottom View w/Type C IDBottom View w/Type A ID
There are 2 methods of indicating pin 1 corner at the back of the VFQFN package are:
1. Type A: Chamfer on the paddle (near pin 1)
2. Type C: Mouse bite on the paddle (near pin 1)
ICS83PN148I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL OSCILLATOR REPLACEMENT
ICS83PN148DKI REVISION A OCTOBER 11, 2012 17 ©2012 Integrated Device Technology, Inc.
Ordering Information
Table 10. Ordering Information
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
Part/Order Number Marking Package Shipping Packaging Temperature
83PN148DKILF ICS3PN148DIL “Lead-Free” 10 Lead VFQFN Tray -40C to 85C
83PN148DKILFT ICS3PN148DIL “Lead-Free” 10Lead VFQFN 2500 Tape & Reel -40C to 85C
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support
devices or critical medical instruments.
ICS83PN148I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL OSCILLATOR REPLACEMENT
ICS83PN148DKI REVISION A OCTOBER 11, 2012 18 ©2012 Integrated Device Technology, Inc.
Revision History Sheet
Rev Table Page Description of Change Date
A AMR 3 Per Errata NEN-11-03; changed AMR from 4.5V to 3.63V 10/11/12
“IDT,
www.lDT.com
ICS83PN148I Data Sheet PROGRAMMABLE FEMTOCLOCK® NG LVPECL OSCILLATOR REPLACEMENT
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
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