0N Semiconductorg
www.0nsemi.com
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documentation are available 2n www.0nsemi.com
- Funclionally Compmible wilh Exisling 3.3 v LVEL, LVER ER and
so Devices
I These are Pb—Free Devices
am
LW
VOLTAGE (130 mV/div)
15:: w ‘ ‘ ‘ F'V Wes/«1v
TIME (55 ps/divp
Figure 2. Typical Oulpul Waveform at 2.488 Gb/s with
PRBS 2234 (vmpp = 400 mV; Input Signal DDJ =14 ps)
0 Semxcunducluvcampunenls magmas. Lu: 2m |
November, 2014 — Rev. 1
© Semiconductor Components Industries, LLC, 2014
November, 2014 − Rev. 7 1Publication Order Number:
NB6N11S/D
NB6N11S
3.3 V 1:2 AnyLevelE Input
to LVDS Fanout Buffer /
Translator
Description
The NB6N11S is a differential 1:2 Clock or Data Receiver and will
accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL,
or LVDS. These signals will be translated to LVDS and two identical
copies of Clock or Data will be distributed, operating up to 2.0 GHz or
2.5 Gb/s, respectively. As such, the NB6N11S is ideal for SONET,
GigE, Fiber Channel, Backplane and other Clock or Data distribution
applications.
The NB6N11S has a wide input common mode range from
GND + 50 mV to VCC − 50 mV. Combined with the 50 W internal
termination resistors at the inputs, the NB6N11S is ideal for
translating a variety of differential or single−ended Clock or Data
signals to 350 mV typical LVDS output levels.
The NB6N11S is functionally equivalent to the EP11, LVEP11,
SG11 or 7L11M devices and is offered in a small, 3 mm X 3 mm,
16−QFN package. Application notes, models, and support
documentation are available at www.onsemi.com.
The NB6N11S is a member of the ECLinPS MAX™ family of high
performance products.
Features
•Maximum Input Clock Frequency > 2.0 GHz
•Maximum Input Data Rate > 2.5 Gb/s
•1 ps Maximum of RMS Clock Jitter
•Typically 10 ps of Data Dependent Jitter
•380 ps Typical Propagation Delay
•120 ps Typical Rise and Fall Times
•Functionally Compatible with Existing 3.3 V LVEL, LVEP, EP, and
SG Devices
•These are Pb−Free Devices
TIME (58 ps/div)
Figure 2. Typical Output Waveform at 2.488 Gb/s with
PRBS 223−1 (VINPP = 400 mV; Input Signal DDJ = 14 ps)
VOLTAGE (130 mV/div)
Device DDJ = 10 ps
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
MARKING
DIAGRAM*
QFN−16
MN SUFFIX
CASE 485G
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1
Q0
Q0
Q1
Q1
D
D
VTD
VTD
Figure 1. Logic Diagram
(Note: Microdot may be in either location)
16
NB6N
11S
ALYW G
G
1
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
LJ LJ LJ
1
OLJ
,—
|"| F'I F‘I F'I
I
NB6N11S
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2
Figure 3. NB6N11S Pinout, 16−pin QFN (Top View)
VCC NC VEE VEE
VCC
VTD
D
D
VTD
Q0
Q0
Q1
Q1
5678
16 15 14 13
12
11
10
9
1
2
3
4
NB6N11S
Exposed Pad (EP)
VCC VCC VCC
Table 1. PIN DESCRIPTION
Pin Name I/O Description
1 Q0 LVDS Output Non−inverted D output. Typically loaded with 100 W receiver termination
resistor across differential pair.
2 Q0 LVDS Output Inverted D output. Typically loaded with 10 W receiver termination resistor
across differential pair.
3 Q1 LVDS Output Non−inverted D output. Typically loaded with 100 W receiver termination
resistor across differential pair.
4 Q1 LVDS Output Inverted D output. Typically loaded with 100 W receiver termination resistor
across differential pair.
5 VCC −Positive Supply Voltage
6 NC No Connect
7 VEE Negative Supply Voltage
8 VEE Negative Supply Voltage
9 VTD −Internal 50 W termination pin for D
10 D LVPECL, CML, LVDS,
LVCMOS, LVTTL Inverted Differential Clock/Data Input (Note 1)
11 DLVPECL, CML, LVDS,
LVCMOS, LVTTL Non−inverted Differential Clock/Data Input (Note 1)
12 VTD −Internal 50 W termination pin for D
13 VCC −Positive Supply Voltage
14 VCC −Positive Supply Voltage
15 VCC −Positive Supply Voltage
16 VCC −Positive Supply Voltage
EP Exposed pad. The exposed pad (EP) on the package bottom must be
attached to a heat−sinking conduit. The exposed pad may only be
electrically connected to VEE.
1. In the differential configuration when the input termination pins (VTD/VTD) are connected to a common termination voltage or left open, and
if no signal is applied on D/D inputs, then the device will be susceptible to self oscillation.
NB6N11S
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3
Table 2. ATTRIBUTES
Characteristics Value
ESD Protection Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 200 V
> 1 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 2) Pb Pkg Pb−Free Pkg
QFN−16 − 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 225 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
VCC Positive Power Supply GND = 0 V 3.8 V
VIN Positive Input GND = 0 V VIN ≤ VCC 3.8 V
IIN Input Current Through RT (50 W Resistor) Static
Surge 35
70 mA
mA
IOSC Output Short Circuit Current
Line−to−Line (Q to Q)
Line−to−End (Q or Q to GND) Q or Q
Q to Q to GND Continuous
Continuous 12
24
mA
TAOperating Temperature Range QFN−16 −40 to +85 °C
Tstg Storage Temperature Range −65 to +150 °C
qJA Thermal Resistance (Junction−to−Ambient) (Note 3) 0 lfpm
500 lfpm QFN−16
QFN−16 41.6
35.2
°C/W
°C/W
qJC Thermal Resistance (Junction−to−Case) 1S2P (Note 3) QFN−16 4.0 °C/W
Tsol Wave Solder Pb
Pb−Free 265
265
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
3. JEDEC standard multilayer board − 1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad.
NB6N11S
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4
Table 4. DC CHARACTERISTICS, CLOCK INPUTS, LVDS OUTPUTS VCC = 3.0 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C
Symbol Characteristic Min Typ Max Unit
ICC Power Supply Current (Note 8) 35 50 mA
DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED (Figures 15, 16, 20, and 22)
Vth Input Threshold Reference Voltage Range (Note 7) GND +100 VCC − 100 mV
VIH Single−ended Input HIGH Voltage Vth + 100 VCC mV
VIL Single−ended Input LOW Voltage GND Vth − 100 mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 11, 12, 13, 14, 21, and 23)
VIHD Differential Input HIGH Voltage 100 VCC mV
VILD Differential Input LOW Voltage GND VCC − 100 mV
VCMR Input Common Mode Range (Differential Configuration) GND + 50 VCC − 50 mV
VID Differential Input Voltage (VIHD − VILD) 100 VCC mV
RTIN Internal Input Termination Resistor 40 50 60 W
LVDS OUTPUTS (Note 4)
VOD Differential Output Voltage 250 450 mV
DVOD Change in Magnitude of VOD for Complementary Output States (Note 9) 0 1 25 mV
VOS Offset Voltage (Figure 19) 1125 1375 mV
DVOS Change in Magnitude of VOS for Complementary Output States (Note 9) 0 1 25 mV
VOH Output HIGH Voltage (Note 5) 1425 1600 mV
VOL Output LOW Voltage (Note 6) 900 1075 mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. LVDS outputs require 100 W receiver termination resistor between differential pair. See Figure 18.
5. VOHmax = VOSmax + ½ VODmax.
6. VOLmax = VOSmin − ½ VODmax.
7. Vth is applied to the complementary input when operating in single−ended mode.
8. Input termination pins open, D/D at the DC level within VCMR and output pins loaded with RL = 100 W across differential.
9. Parameter guaranteed by design verification not tested in production.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
740°
5
C
25
NB6N11S
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5
Table 5. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0 V; (Note 10)
Symbo
l
Characteristic
−40°C 25°C 85°C
Uni
t
Min Typ Max Min Typ Max Min Typ Max
VOUTPP Output Voltage Amplitude (@ VINPPmin)f
in ≤ 1.0 GHz
(Figure 4) fin= 1.5 GHz
fin= 2.0 GHz
220
200
170
350
300
270
250
200
170
350
300
270
250
200
170
350
300
270
mV
fDATA Maximum Operating Data Rate 1.5 2.5 1.5 2.5 1.5 2.5 Gb/s
tPLH,
tPHL
Differential Input to Differential Output
Propagation Delay 270 370 470 270 370 470 270 370 470 ps
tSKEW Duty Cycle Skew (Note 11)
Within Device Skew (Note 16)
Device−to−Device Skew (Note 15)
8
5
30
45
25
100
8
5
30
45
25
100
8
5
30
45
25
100
ps
tJITTER RMS Random Clock Jitter (Note 13) fin = 1.0 GHz
fin = 1.5 GHz
Deterministic Jitter (Note 14) fDATA = 622 Mb/s
fDATA = 1.5 Gb/s
fDATA = 2.488 Gb/s
0.5
0.5
6
7
10
1
1
20
20
0.5
0.5
6
7
10
1
1
20
20
0.5
0.5
6
7
10
1
1
20
20
ps
VINPP Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 12) 100 VCC−
GND 100 VCC−
GND 100 VCC−
GND mV
tr
tf
Output Rise/Fall Times @ 250 MHz Q, Q
(20% − 80%) 70 120 170 70 120 170 70 120 170 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10.Measured by forcing VINPPmin with 50% duty cycle clock source and VCC − 1400 mV offset. All loading with an external RL = 100 W across
“D” and “D” of the receiver. Input edge rates 150 ps (20%−80%).
11. See Figure 17 differential measurement of tskew = |tPLH − tPHL| for a nominal 50% differential clock input waveform @ 250 MHz.
12.Input voltage swing is a single−ended measurement operating in differential mode.
13.RMS jitter with 50% Duty Cycle clock signal at 750 MHz.
14.Deterministic jitter with input NRZ data at PRBS 223−1 and K28.5.
15.Skew is measured between outputs under identical transition @ 250 MHz.
16.The worst case condition between Q0/Q0 and Q1/Q1 from D, D, when both outputs have the same transition.
INPUT CLOCK FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (VOUTPP) versus
Input Clock Frequency (fin) and Temperature (@ VCC = 3.3 V)
OUTPUT VOLTAGE AMPLITUDE (mV)
0
50
100
150
200
250
300
350
400
0.5 1 1.5 2 2.5 30
85°C
−40°C
25°C
um.
mm.“
mm
mum-wheat
m
www onsem com
NB6N11S
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6
Figure 5. Typical Phase Noise Plot at
fcarrier = 311.04 MHz Figure 6. Typical Phase Noise Plot at
fcarrier = 622.08 MHz
Figure 7. Typical Phase Noise Plot at
f
carrier
= 1.5 GHz Figure 8. Typical Phase Noise Plot at
f
carrier
= 2 GHz
The above phase noise plots captured using Agilent
E5052A show additive phase noise of the NB6N11S device
at frequencies 311.04 MHz, 622.08 MHz, 1.5 GHz and
2 GHz respectively at an operating voltage of 3.3 V in room
temperature. The RMS Phase Jitter contributed by the
device (integrated between 12 kHz and 20 MHz; as shown
in the shaded region of the plot) at each of the frequencies
is 96 fs, 40 fs, 15 fs and 14 fs respectively. The input source
used for the phase noise measurements is Agilent E8663B.
LVPECL
Dru/er
4
Figure 13. Standard 50 52 Load CML lnierface
Vcc Vcc
‘V___ __'i i’WFeNIE—‘I
I '7- D |
I | 50 {2‘ |
I LVCMOS | |
I DrIver | |
I I I 5“ 9‘ |
I | | |
I I I '5 I
I____J)___J 2.5kSlL__E__J
GND GND GND
vm = m = OPEN
Figure 15. LVCMOS lnierface
_________I
L __ _ _ _ J L _ _ _ _ _ J
vTD = Vfi = GND or VDD/z
DependIrIg on DrIver
Figure 14. HSTL Interlace
Figure 16. LV‘I'I'L lnierfac
‘RTIN. ImemaI Inpm TermInatIon neSIsIor
NB6N11S
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8
GND
V
CC
GND
LVPECL
Driver
D
50 W*
Zo = 50 W
Zo = 50 W
50 W*
D
NB6N11S
V
CC
VTD
GND
VCC
GND
CML
Driver
50 W*
Zo = 50 W
Zo = 50 W
50 W*
NB6N11S
VCC
VTD = VTD = VCC
Figure 11. LVPECL Interface Figure 12. LVDS Interface
VTD = VTD = VCC − 2.0 V
Figure 13. Standard 50 W Load CML Interface
GND
V
CC
GND
LVDS
Driver
50 W*
Zo = 50 W
Zo = 50 W
50 W*
NB6N11S
V
CC
VTD = VTD
GND
VCC
GND
HSTL
Driver
50 W*
Zo = 50 W
Zo = 50 W
50 W*
NB6N11S
VCC
VTD = VTD = GND or VDD/2
Depending on Driver.
Figure 14. HSTL Interface
GND
VCC
GND
LVCMOS
Driver
50 W*
Zo = 50 W
50 W*
NB6N11S
VCC
VTD = VTD = OPEN
Figure 15. LVCMOS Interface
GND
VCC
GND
LVTTL
Driver
50 W*
Zo = 50 W
50 W*
NB6N11S
VCC
Figure 16. LVTTL Interface
VTD
D
D
VTD
VTD
D
VTD
VTD
VCC
D
D
VTD
VTD
D
D
VTD
VTD
D
GND
D
VTD
VTD
D
*R
TIN
, Internal Input Termination Resistor.
2.5 kW
GND
1.5 kW
VTD = VTD = OPEN
NB6N11S
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9
Figure 17. AC Reference Measurement
D
D
Q
Q
tPHL
tPLH
VINPP = VIH(D) − VIL(D)
VOUTPP = VOH(Q) − VOL(Q)
Figure 18. Typical LVDS Termination for Output Driver and Device Evaluation
Driver
Device Oscilloscope
QD
Q D
LVDS 100 W
Zo = 50 W
Zo = 50 W
HI Z Probe
HI Z Probe
VOL
QN
VOH
QN
VOS VOD
Figure 19. LVDS Output
Figure 20. Differential Input Driven Single−Ended
D
Figure 21. Differential Inputs Driven Differentially
D
Vth
Vth
DD
VIH
VIL
VIHmax
VILmax
VIHmin
VILmin
VCC
Vthmax
Vthmin
GND
Vth
Figure 22. Vth Diagram
D
D
VIL
VIH(MAX)
VIH
VIL
VIH
VIL(MIN)
VCMR
GND
Figure 23. VCMR Diagram
VINPP = VIHD − VILD
VCC
ORDERING INFORMATION
Device Package Shipping†
NB6N11SMNG QFN−16, 3 X 3 mm
(Pb−Free) 123 Units / Rail
NB6N11SMNR2G QFN−16, 3 X 3 mm
(Pb−Free) 3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
,L,
51—017 1
// ’ ¢
Q \~ {
SID TA1AT¢£
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I'VE/W1” C VENUE?
#4,,5 £2 E 1 E7
1.2 1 E ; Lg+§
fiflmimflp TLD—[U‘UJ-DJ ¢
ME 4 w W *
NB6N11S
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10
PACKAGE DIMENSIONS
QFN16 3x3, 0.5P
CASE 485G−01
ISSUE E
16X
SEATING
PLANE
L
D
E
0.10 C
A
A1
e
D2
E2
b
1
4
8
9
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
B
A
0.10 C TOP VIEW
SIDE VIEW
BOTTOM VIEW
PIN 1
LOCATION
0.05 C
0.05 C
(A3)
C
NOTE 4
16X
0.10 C
0.05 C
A B
NOTE 3
K
16X
DIM MIN MAX
MILLIMETERS
A0.80 1.00
A1 0.00 0.05
A3 0.20 REF
b0.18 0.30
D3.00 BSC
D2 1.65 1.85
E3.00 BSC
E2 1.65 1.85
e0.50 BSC
K
L0.30 0.50
0.18 TYP
L1
DETAIL A
L
ALTERNATE TERMINAL
CONSTRUCTIONS
A1
A3
L
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTIONS
DETAIL A
DETAIL B
L1 0.00 0.15
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
RECOMMENDED
2X
0.50
PITCH
1.84 3.30
1
DIMENSIONS: MILLIMETERS
0.58
16X
2X
0.30
16X
OUTLINE
PACKAGE
2X
2X
0.10 C A B
e/2
SOLDERING FOOTPRINT*
ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
P
UBLICATION ORDERING INFORMATION
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
NB6N11S/D
AnyLevel and ECLinPS MAX are trademarks of Semiconductor Components Industries, LLC (SCILLC).
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
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