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Semiconductor Components Industries, LLC, 2011
October, 2011 − Rev. 5
1Publication Order Number:
NLAS7222A/D
NLAS7222A
High-Speed USB 2.0
(480 Mbps) DPDT Switch
ON Semiconductor’s NLAS7222A series of analog switch circuits
are produced using the company’s advanced sub−micron CMOS
technology, achieving industry−leading performance.
The NLAS7222A is a 2− to 1−port analog switch. Its wide
bandwidth and low bit−to−bit skew allow it to pass high−speed
differential signals with good signal integrity. The switch is
bidirectional and offers little or no attenuation of the high−speed
signals at the outputs. Industry−leading advantages include a
propagation delay of less than 250 ps, resulting from its low channel
resistance and low I/O capacitance. Its high channel−to−channel
crosstalk rejection results in minimal noise interference. Its bandwidth
is wide enough to pass High−Speed USB 2.0 differential signals
(480 Mb/s).
Features
RON is Typically 6.5 at VCC = 3 V
Low Bit−to−Bit Skew: Typically 50 ps
OVT on D+ and D− up to 3.6 V
Power OFF Protection:
When VCC = 0 V, D+ and D− Can Tolerate up to 3.6 V
Low Crosstalk: −45 dB @ 250 MHz
Low Current Consumption: 1 A
Near−Zero Propagation Delay: 250 ps
Channel On−Capacitance: 6.5 pF (Typical)
VCC Operating Range: +3.0 V to +3.6 V
> 700 MHz Bandwidth (or Data Frequency)
This is a Pb−Free Device
Typical Applications
Differential Signal Data Routing
USB 2.0 Signal Routing
Important Information
Continuous Current Rating Through Each Switch 50 mA
8 kV I/O to GND ESD Protection
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
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MARKING
DIAGRAM
XX = Specific Device Code
XX = 2A or Y
M = Date Code
G = Pb−Free Device
WQFN10
CASE 488AQ
1
Y M G
G
1
UQFN10
CASE 488AT
(Note: Microdot may be in either location)
2A M G
G
NLAS7222A
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2
Figure 1. Pin Connections and Logic Diagram
(Top View)
8
9
10
12
76
5
4
3
HSD1+ HSD2+
HSD1−HSD2−
D−
GND
D+
OE
VCC
S
CONTROL
Table 1. PIN DESCRIPTION
Pin Function
SSelect Input
OE Output Enable
HSD1+, HSD1−, HSD2+,
HSD2−, D+, D−
Data Ports
Table 2. TRUTH TABLE
OE S
HSD1+,
HSD1−
HSD2+,
HSD2−
1
0
0
X
0
1
OFF
ON
OFF
OFF
OFF
ON
MAXIMUM RATINGS
Symbol Parameter Value Unit
VCC Positive DC Supply Voltage −0.5 to +4.6 V
VIS Analog Switch Input Voltage
HSD1+, HSD1−, HSD2+, HSD2−
D+, D−
−0.5 to VCC + 0.3
−0.5 to +4.6
V
VIN Digital Select Input Voltage −0.5 to +4.6 V
IDContinuous DC Current (Through Analog Switch) 50 mA
PDPower Dissipation 0.5 W
TSStorage Temperature −65 to +150 C
ESD Human Body Model
I/O to GND
All Pins
8.0
1.5
kV
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC Positive DC Supply Voltage 3.0 3.6 V
VIS Analog I/O Voltage (HSD1+, HSD1−, HSD2+, HSD2−) GND VCC V
VOS Analog Common Output Voltage (D+, D−) GND 3.6 V
VIN Digital Select Input Voltage GND VCC V
TAOperating Temperature Range −40 +85 C
tr, tfInput Rise or Fall Time
VCC = 3.3 V 0.3 V 0 15
ns
NLAS7222A
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3
DC ELECTRICAL CHARACTERISTICS FOR USB 2.0 SWITCHING OVER OPERATIONAL RANGE
Symbol Parameter Test Conditions VCC (V)
−40C to +85C
Unit
Min
Typ
(Note 1) Max
VIH Input HIGH Voltage (VIN)3.0 to 3.6 1.3 − − V
VIL Input LOW Voltage (VIN)3.0 to 3.6 − − 0.5 V
VIK Clamp Diode Voltage IIS = −18 mA 3.0 − − −1.2 V
ICC Quiescent Supply Current VIS = VCC or GND; ID = 0 A 3.6 − − 1.0 A
ICCT Increase in ICC per
Control Voltage
VIN = 2.6 V 3.6 − − 10.0 A
IIInput Leakage Current 0 VIS VCC 3.6 − − 1.0 A
IOZ OFF State Leakage 0 VIS; VOS VCC 3.6 − − 1.0 A
IOFF Power OFF Leakage Current
(D+, D−)
0 VIS; VOS VCC 0− − 1.0 A
RON Switch On−Resistance VIS = 0 to 0.4 V; ID = 8 mA 3.0 −6.5 9.0
RFLAT(ON) On−Resistance Flatness VIS = 0 to 1.0 V; ID = 8 mA 3.0 −2.0 −
RON On−Resistance match from
center ports to any other ports
VIS = 0 to 0.4 V; ID = 8 mA 3.0 −0.35 −
1. Typical values are at VCC = 3.3 V and TA = +25C
AC ELECTRICAL CHARACTERISTICS
−405C to +855C
Symbol Parameter Test Conditions VCC (V) Min
Typ
(Note 2) Max Unit
tON Turn−ON Time VIS = 0.8 V 3.0 to 3.6 −13.0 30.0 ns
tOFF Turn−OFF Time VIS = 0.8 V 3.0 to 3.6 −12.0 25.0 ns
tBBM Break−Before−Make Delay VIS = 0.8 V 3.0 to 3.6 2.0 4.7 6.5 ns
tPD Propagation Delay CL = 10 pF 3.0 to 3.6 −0.25 −ns
OIRR OFF−Isolation f = 250 MHz; RL = 50 3.0 to 3.6 − −28 −dB
XTALK Non−Adjacent Channel Crosstalk f = 250 MHz; RL = 50 3.0 to 3.6 − −45 −dB
BW −3 dB Bandwidth RL = 50 ; CL = 0 pF
3.0 to 3.6
−700 −MHz
RL = 50 ; CL = 5 pF −500 −
AC ELECTRICAL CHARACTERISTICS FOR USB 2.0 SWITCHING OVER OPERATIONAL RANGE
tSK(O) Channel−to−Channel Skew CL = 10 pF 3.0 to 3.6 −0.05 −ns
TJITTER Total Jitter RL = 50 ; CL = 10 pF
tr = tf = 500 ps at 480 Mbps
3.0 to 3.6 −0.2 −ns
2. Typical values are at VCC = 3.3 V and TA = +25C
CAPACITANCE
−405C to +855C
Symbol Parameter Test Conditions Min
Typ
(Note 3) Max Unit
CIN Control Pin Input Capacitance VCC = 0 V −2.5 −pF
CON HSD+, HSD− ON Capacitance VCC = 3.3 V; OE = 0 V −7.0 −pF
COFF HSD+, HSD− OFF Capacitance VCC = VIS = 3.3 V; OE = 3.3 V −4.5 −pF
3. Typical values are at VCC = 3.3 V and TA = +25C
1
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NLAS7222A
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4
Figure 2. tBBM (Time Break−Before−Make)
Output
DUT
50 35 pF
VCC
Switch Select Pin
Output
Input
VCC
GND
Figure 3. tON/tOFF
50% 50%
90% 90%
tON tOFF
VOH
Output
Input
VCC
0 V
Figure 4. tON/tOFF
DUT
Open 35 pF
VCC
Input
50% 50%
10%
tON
tOFF
Output
Input
VCC
0 V
10%
50
0.1 F
tBMM
Output
VOUT
VOL
VOUT VOH
VOL
DUT
Open
VCC
Input
Output
50 35 pF
VOUT
0.1 F
50 % OF
DROOP
VOLTAGE
DROOP
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Channel swncn control/s lesl sockel is normalized. Off isolallon is measure
is me bandwidth ol an On switch. visoi Bandwidth and VONL are lndepend
VOUT
viSO : all Channel isolalion : 20 Log v lei vIN al 100 kHz
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NLAS7222A
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5
Channel switch control/s test socket is normalized. Off isolation is measured across an off channel. On loss
is the bandwidth of an On switch. VISO, Bandwidth and VONL are independent of the input signal direction.
VISO = Off Channel Isolation = 20 Log for VIN at 100 kHz
VONL = On Channel Loss = 20 Log for VIN at 100 kHz to 50 MHz
Bandwidth (BW) = the frequency 3 dB below VONL
VCT = Use VISO setup and test to all other switch analog input/outputs terminated with 50
Output
DUT
Input
50
50 Generator
Reference
Transmitted
Figure 5. Off Channel Isolation/On Channel Loss (BW)/Crosstalk
(On Channel to Off Channel)/VONL
50
ǒVOUT
VIN Ǔ
ǒVOUT
VIN Ǔ
Off On Off VOUT
VCC
GND
Output
VIN
CL
DUT
Figure 6. Charge Injection: (Q)
VIN
Open Output
J1
‘B’ receptacle
J2
‘B’ receptacle
J8
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NLAS7222A
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6
APPLICATIONS INFORMATION
The low on resistance and capacitance of the
NLAS7222A provides for a high bandwidth analog switch
suitable for applications such as USB data switching.
Results for the USB 2.0 signal quality tests will be shown in
this section, along with a description of the evaluation test
board. The data for the eye diagram signal quality and jitter
tests verifies that the NLAS7222A can be used as a data
switch in low, full and high speed USB 2.0 systems.
Figures 7, 8 and 9 provide a description of the test
evaluation board. The USB tests were conducted per the
procedures provided by the USB Implementers Forum
(www.usb.org), the industry group responsible for defining
the USB certification requirements. The test patterns were
generated by a PC and MATLAB software, and were
inputted to the analog switch through USB connectors J1
(HSD1) or J2 (HSD2). A USB certified device was plugged
into connector J4 to function as a data transceiver. The high
speed and full speed tests used a flash memory device, while
the low speed tests used a mouse. Test connectors J3 and J5
provide a direct connection of the USB device and were used
to verify that the analog switch does not distort the data
signals.
Figure 7. Schematic of the NLAS7222A USB Demo Board
MAS7222A Demo Board
NLAS7222A
Connectto a USB Device such as
a flash memory drive or mouse
Cnnnemo
PC's USB port
NLAS7222A
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7
Figure 8. Block Diagram of the NLAS7222A USB Demo Board
Figure 9. Photograph of the NLAS7222A USB Demo Board
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hme‘ ns
NLAS7222A
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8
AND8267/D – NLAS7222A USB 2.0 Signal Quality Compliance Tests
Figures 10, 11 and 12 show the test results for USB eye
diagram tests. A summary of the USB tests is provided in
Table 3. The NLAS7222A passes the low, full and high
speed signal quality, eye diagram and jitter tests.
Application note AND8267/D provides a detailed
description of the USB 2.0 test results.
Figure 10. Low Speed Signal Quality Eye Diagram Test (NLAS7222A with VCC = 3.6 V)
Figure 11. Full Speed Signal Quality Eye Diagram Test (NLAS7222A with VCC = 3.6 V)
me‘ ns
NLAS7222A
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9
Figure 12. High Speed Signal Quality Eye Diagram Test (NLAS7222A with VCC = 3.0 V)
Table 3. Summary of the USB 2.0 Signal Quality Tests Results
Compliance Test Low Speed Full Speed High Speed
Signal Quality Test Pass Pass Pass
Signal Eye Test Pass Pass Pass
EOP Width 1.29 ms 166.86 ns 7.98 bits
Measured Signal Rate 1.5140 MHz 12.0016 MHz 480.0685 MHz
Crossover Voltage Range 1.75 to 1.83 V,
mean crossover = 1.78 V
1.70 to 1.73 V,
mean crossover = 1.71 V
N/A
Connective Jitter Range −2.2 to 2.2 ns,
RMS jitter = 1.3 ns
−0.2 to 0.2 ns,
RMS jitter = 0.1 ns
−79.4 to 77.4 ps,
RMS jitter = 35.0 ps
Paired JK Jitter Range −1.4 to 2.7 ns,
RMS jitter = 1.3 ns
−0.1 to 0.1 ns,
RMS jitter = 0.1 ns
−93.2 to 78.7 ps,
RMS jitter = 24.4 ps
Paired KJ Jitter Range −1.9 to 1.1 ns,
RMS jitter = 1.0 ns
−0.2 to 0.1 ns,
RMS jitter = 0.1 ns
−72.8 to 50.9 ps,
RMS jitter = 15.6 ps
ORDERING INFORMATION
Device Package Shipping†
NLAS7222AMTR2G WQFN10
(Pb−Free)
3000 / Tape & Reel
NLAS7222AMUR2G* UQFN10
(Pb−Free)
NLAS7222AMUTAG*
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLAS72222AMUR2G and NLAS7222AMUTAG are Tape & Reel orientation options.
NLAS7222A
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10
PACKAGE DIMENSIONS
WQFN10, 1.4x1.8x0.4P
CASE 488AQ−01
ISSUE C
A
b
A3
A1
0.08 C
SEATING
PLANE
NOTE 3
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30 MM
FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
5. EXPOSED PADS CONNECTED TO DIE FLAG.
USED AS TEST CONTACTS.
DIM MIN MAX
MILLIMETERS
A
1.40 BSC
A1
0.40 BSC
A3
0.70 0.80
b
D
0.30 0.50
E
e
L
L1
0.20 REF
0.00 0.050
PIN 1 REFERENCE
D A
E
B
0.15 C
2X
0.15 C
2X
0.10 C
C
L1
10
1
35
6
0.05 C
0.10 CAB
10 X
e
e/2
L9 X
0.40 0.60
1.80 BSC
0.15 0.25
MOUNTING FOOTPRINT
10 X
PITCH
1
9 X
SCALE 20:1
0.663
0.0261
0.200
0.0079
0.400
0.0157
0.225
0.0089
2.100
0.0827
1.700
0.0669 0.563
0.0221
ǒmm
inchesǓ
M1
DETAIL A
Bottom View
(Optional)
A1
A3
DETAIL B
Side View
(Optional)
EDGE OF PACKAGE
MOLD CMPD
EXPOSED Cu
M1 0.00 0.05
Q nus C A17 6
5
NLAS7222A
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11
PACKAGE DIMENSIONS
UQFN10, 1.4x1.8, 0.4P
CASE 488AT−01
ISSUE A
A
b
A1
0.05 C
SEATING
PLANE
NOTE 3
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30 MM
FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
DIM MIN MAX
MILLIMETERS
A
1.40 BSC
A1
0.40 BSC
0.45 0.60
b
D
0.30 0.50
E
e
L
L1
0.00 0.05
PIN 1 REFERENCE
D A
E
B
0.10 C
2X
0.10 C
2X
0.05 C
C
L3
10
1
35
6
0.05 C
0.10 CAB
10 X
e
e/2
L9 X
0.00 0.15
1.80 BSC
0.15 0.25
MOUNTING FOOTPRINT
10 X
PITCH
1
9 X
SCALE 20:1
0.663
0.0261
0.200
0.0079
0.400
0.0157
0.225
0.0089
2.100
0.0827
1.700
0.0669 0.563
0.0221
ǒmm
inchesǓ
10X
L1
DETAIL A
Bottom View
(Optional)
A1
A3
DETAIL B
Side View
(Optional)
EDGE OF PACKAGE
MOLD CMPD
EXPOSED Cu
L3 0.40 0.60
0.127 REFA3
TOP VIEW
SIDE VIEW
BOTTOM VIEW
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
NLAS7222A/D
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
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