CDK3400, CDK3401 Datasheet by MaxLinear, Inc.

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CDK3400/CDK3401 10-bit, 100/150MSPS, Triple Video DACs Rev 1D
Data Sheet
CDK3400/CDK3401
10-bit, 100/150MSPS, Triple Video DACs
Exar Corporation www.exar.com
48720 Kato Road, Fremont CA 94538, USA Tel. +1 510 668-7000 - Fax. +1 510 668-7001
FEATURES
n
10-bit resolution
n
150 megapixels per second
n
±0.1% linearity error
n
Sync and blank controls
n
1.0Vpp video into 37.5Ω or 75Ω load
n
Internal bandgap voltage reference
n
Double-buffered data for low distortion
n
TTL-compatible inputs
n
Low glitch energy
n
Single +5V power supply
APPLICATIONS
n Video signal conversion
– RGB
– YCBCR
– Composite, Y, C
n Multimedia systems
n Image processing
n True-color graphics systems
(1 billion colors)
n Broadcast television equipment
n High-Definition Television (HDTV)
equipment
n Direct digital synthesis
General Description
CDK3400/3401 products are low-cost triple D/A converters that are tailored
to fit graphics and video applications where speed is critical. Two
speed
grades are available: CDK3400 at 100MSPS and CDK3401 at 150MSPS.
TTL-level inputs are converted to analog current outputs that can drive
25-37.5Ω loads corresponding to doubly-terminated 50-75Ω loads. A sync
current following SYNC input timing is added to the IOG output. BLANK
will override RGB inputs, setting IOG, IOB and IOR currents to zero when
BLANK = L. Although appropriate for many applications, the internal 1.235V
reference voltage can be overridden by the VREF input.
Few external components are required, just the current reference resistor,
current output load resistors, and decoupling capacitors.
Package is a 48-lead TQFP. Fabrication technology is CMOS. Performance is
guaranteed from 0 to 70°C.
Block Diagram
Ordering Information
Part Number Package Pb-Free RoHS Compliant Operating Temp Range Packaging Method Package Quantity
CDK3400CTQ48 TQFP-48 Yes Yes 0°C to +70°C Tray 250
CDK3401CTQ48 TQFP-48 Yes Yes 0°C to +70°C Tray 250
Moisture sensitivity level for all parts is MSL-3.
10-bit D/A
Converter
10
SYNC
CLOCK
G9-0
COMP
+1.235V
Ref
IOG
BLANK
10-bit D/A
Converter
10
B9-0 IOB
10-bit D/A
Converter
10
R9-0 IOR
REF
REF
SYNC
R
V
m S 2 x Q E
Data Sheet
CDK3400/CDK3401 10-bit, 100/150MSPS, Triple Video DACs Rev 1D
©2009-2013 Exar Corporation 2/11 Rev 1D
Pin Configuration
TQFP-48
G1
G2
G3
G4
G5
G6
G7
G8
G9
BLANK
VDD
R2
R1
NC
RREF
VREF
COMP
IOG
IOR
VDD
VDD
IOB
GND
GND
NC
G0
R9
R8
R7
R6
R5
R4
R3
NC
B0
B1
B2
B3
B4
B6
B5
NC
1
2
3
4
5
6
7
8
9
10
SYNC 11
12
36
35
34
33
32
31
30
29
28
27
CLOCK
26
25
13
14
15
16
17
18
19
20
21
22
B7
B8
B9 23
24
48
47
46
45
44
43
42
41
40
39
R038
37
TQFP
CDK3400/3401
Pin Assignments
Pin No. Pin Name Description
Clock and Pixel I/O
26 CLK
Clock Input
47-37 R9-0 Red Pixel Data Inputs
48, 9–1 G9-0 Green Pixel Data Inputs
23–14 B9-0 Blue Pixel Data Inputs
Controls
11 SYNC Sync Pulse Input
10 BLANK Blanking Input
Video Outputs
33 IOR Red Current Output
32 IOG Green Current Output
29 IOB Blue Current Output
Voltage Reference
35 VREF Voltage Reference Output/Input
36 RREF Current-Setting Resistor
34 COMP Compensation Capacitor
Power and Ground
12, 30, 31 VDD Power Supply
27, 28 GND Ground
Data Sheet
CDK3400/CDK3401 10-bit, 100/150MSPS, Triple Video DACs Rev 1D
©2009-2013 Exar Corporation 3/11 Rev 1D
Absolute Maximum Ratings
The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device
should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper device
function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the
operating conditions noted on the tables and plots.
Parameter Min Max Unit
Power Supply Voltage
VDD (Measured to GND) -0.5 7.0 V
Inputs
Applied Voltage (measured to GND)(2) -0.5 VDD + 0.5 V
Forced Current(3,4) -10.0 10.0 mA
Outputs
Applied Voltage (measured to GND)(2) -0.5 VDD + 0.5 V
Forced Current(3,4) -60.0 60.0 mA
Short Circuit Duration (single output in HIGH state to GND) Infinite sec
Temperature
Operating, Ambient -20 110 °C
Junction 150 °C
Lead Soldering (10 seconds) 300 °C
Vapor Phase Soldering (1 minute) 220 °C
Storage -65 150 °C
Notes:
1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.
Recommended Operating Conditions
Symbol Parameter Min Typ Max Unit
VDD Power Supply Voltage 4.75 5.0 5.25 V
fSConversion Rate CDK3400 100 MSPS
CDK3401 150 MSPS
tPWH CLK Pulsewidth, HIGH CDK3400 3.1 ns
CDK3401 2.5 ns
tPWL CLK Pulsewidth, LOW CDK3400 3.1 ns
CDK3401 2.5 ns
tWCLK Pulsewidth CDK3400 10 ns
CDK3401 6.6 ns
tS Input Data Setup Time 1.7 ns
th Input Date Hold Time 0 ns
VREF Reference Voltage, External 1.0 1.235 1.5 V
CC Compensation Capacitor 0.1 µF
RL Output Load 37.5 Ω
VIH Input Voltage, Logic HIGH 2.0 VDD V
VIL Input Voltage, Logic LOW GND 0.8 V
TA Ambient Temperature, Still Air 0 70 °C
Data Sheet
CDK3400/CDK3401 10-bit, 100/150MSPS, Triple Video DACs Rev 1D
©2009-2013 Exar Corporation 4/11 Rev 1D
Electrical Characteristics
(TA = 25°C, VDD = +5V, VREF = 1.235V, RL = 37.5Ω, RREF = 540Ω; unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units
IDD Power Supply Current(1) VDD = 5.25V, TA = 0°C 125 mA
PD Total Power Dissipation(1) VDD = 5.25V, TA = 0°C 655 mW
ROOutput Resistance 100 kΩ
CO Output Capacitance IOUT = 0mA 30 pF
IIH Input Current, HIGH VDD = 5.25V, VIN = 2.4V -5 µA
IIL Input Current, LOW VDD = 5.25V, VIN = 0.4V 5 µA
IREF VREF Input Bias Current 0 ±100 µA
VREF Reference Voltage Output 1.235 V
VOC Output Compliance Referred to VDD -0.4 0 +1.5 V
CDI Digital Input Capacitance 4 10 pF
Notes:
1. 100% tested at 25°C.
2. Parameter is guaranteed (but not tested) by design and characterization data.
Switching Characteristics
(TA = 25°C, VDD = +5V, VREF = 1.235V, RL = 37.5Ω, RREF = 590Ω; unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units
tDClock to Output Delay VDD = 4.75V, TA = 0°C 10 15 ns
tSKEW Output Skew 1 2 ns
tROutput Risetime 10% to 90% of Full Scale 3 ns
tFOutput Falltime 90% to 10% of Full Scale 3 ns
Notes:
1. 100% production tested at +25°C.
2. Parameter is guaranteed (but not tested) by design and characterization data.
System Performance Characteristics
(TA = 25°C, VDD = +5V, VREF = 1.235V, RL = 37.5Ω, RREF = 590Ω; unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units
INL Integral Linearity Error ±0.1 ±0.25 %/FS
DNL Differential Linearity Error ±0.1 ±0.25 %/FS
EDM DAC to DAC Matching 3 10 %
PSRR Power Supply Rejection Ratio 0.05 %/%
Notes:
1. 100% production tested at +25°C.
2. Parameter is guaranteed (but not tested) by design and characterization data.
Data Sheet
CDK3400/CDK3401 10-bit, 100/150MSPS, Triple Video DACs Rev 1D
©2009-2013 Exar Corporation 5/11 Rev 1D
RGB9-0 (MSB…LSB) BLUE AND RED D/AS GREEN D/A
SYNC BLANK VOUT SYNC BLANK VOUT
11 1111 1111 X 1 0.7140 1 1 1.0000
11 1111 1111 X 1 0.7140 0 1 0.7140
11 1111 1110 X 1 0.7134 1 1 0.9994
11 1111 1101 X 1 0.7127 1 1 0.9987
• ••••••
• ••••••
10 0000 0000 X 1 0.3843 1 1 0.6703
01 1111 1111 X 1 0.3837 1 1 0.6697
• ••••••
• ••••••
00 0000 0010 X 1 0.0553 1 1 0.3413
00 0000 0001 X 1 0.0546 1 1 0.3406
00 0000 0000 X 1 0.0540 1 1 0.3400
XX XXXX XXXX X 0 0.0000 1 0 0.2860
XX XXXX XXXX X 0 0.0000 0 0 0.0000
Table 1. Output Voltage vs. Input Code, SYNC and BLANK, VREF = 1.235V, RREF = 590Ω, RL = 37.5Ω
CLK
Pixel Data
and Controls
OUTPUT
Data N+2Data N+1Data N
t
PWL
tstH
50%
3%/FS
90%
10%
tFtR
t
PWH
1/f
s
tDtSET
Figure 1. CDK3400/3401 Timing Diagram
Data Sheet
CDK3400/CDK3401 10-bit, 100/150MSPS, Triple Video DACs Rev 1D
©2009-2013 Exar Corporation 6/11 Rev 1D
Functional Description
Within the CDK3400/3401 are three identical 10-bit D/A
converters, each with a current source output. External
loads are required to convert the current to voltage out-
puts. Data inputs RGB7-0 are overridden by the BLANK
input. SYNC = H activates, sync current from IOS for sync-
on-green video signals.
Digital Inputs
All digital inputs are TTL-compatible. Data is registered
on the rising edge of the CLK signal. Following one stage
of pipeline delay, the analog output changes tDO after the
rising edge of CLK.
Clock Input - CLK
The clock input is TTL-compatible and all pixel data is
registered on the rising edge of CLK. It is recommended
that CLK be driven by a dedicated TTL buffer to avoid
reflection induced jitter, overshoot, and undershoot.
Pixel Data Inputs - R9-0, B9-0, G9-0
TTL-compatible Red, Green and Blue Data Inputs are reg-
istered on the rising edge of CLK.
SYNC and BLANK
SYNC and BLANK inputs control the output level (Figure 2
and Table 1, on the previous page) of the D/A converters
during CRT retrace intervals. BLANK forces the D/A outputs
to the blanking level while SYNC = L turns off a current
source that is connected to the green D/A converter. SYNC
= H adds a 40 IRE sync pulse to the green output, SYNC =
L sets the green output to 0.0V during the sync tip. SYNC
and BLANK are registered on the rising edge of CLK.
Data: 660mV max.
Pedestal: 54mV
Sync: 286mV
Figure 2. Normal Output Levels
BLANK gates the D/A inputs and sets the pedestal voltage.
If BLANK = HIGH, the D/A inputs are added to a pedestal
which offsets the current output. If BLANK = Low, data
inputs and the pedestal are disabled.
Sync Pulse Input - SYNC
Bringing SYNC LOW, turns off a 40 IRE (7.62mA) current
source which forms a sync pulse on the Green D/A con-
verter output. SYNC is registered on the rising edge of
CLK with the same pipeline latency as BLANK and pixel
data. SYNC does not override any other data and should
be used only during the blanking interval.
Since this is a single-supply D/A and all signals are posi-
tive-going, sync is added to the bottom of the Green D/A
range. So turning SYNC OFF means turning the current
source ON. When a sync pulse is desired, the current
source is turned OFF. If the system does not require sync
pulses from the Green D/A converter, SYNC should con-
nected to GND.
Blanking Input - BLANK
When BLANK is LOW, pixel inputs are ignored and the
D/A converter outputs fall to the blanking level. BLANK
is registered on the rising edge of CLK and has the same
pipeline latency as SYNC.
D/A Outputs
Each D/A output is a current source. To obtain a voltage
output, a resistor must be connected to ground. Output
voltage depends upon this external resistor, the reference
voltage, and the value of the gain-setting resistor con-
nected between RREF and GND.
Normally, a source termination resistor of 75Ω is connect-
ed between the D/A current output pin and GND near the
D/A converter. A 75Ω line may then be connected with an-
other 75Ω termination resistor at the far end of the cable.
This “double termination” presents the D/A converter with
a net resistive load of 37.5Ω.
The CDK3400/3401 may also be operated with a single
75Ω terminating resistor. To lower the output voltage
swing to the desired range, the nominal value of the
resistor on RREF should be doubled.
R, G, and B Current Outputs - IOR, IOG, IOB
The R, G, and B current source outputs of the D/A
converters are capable of driving RS-343A/SMPTE-170M
compatible levels into doubly-terminated 75Ω lines. Sync
pulses may be added to the Green D/A output.
Data Sheet
CDK3400/CDK3401 10-bit, 100/150MSPS, Triple Video DACs Rev 1D
©2009-2013 Exar Corporation 7/11 Rev 1D
Current-Setting Resistor - RREF
Full-scale output current of each D/A converter is deter-
mined by the value of the resistor connected between
RREF and GND. Nominal value of RREF is found from:
RREF = 9.1 (VREF/IFS)
where IFS is the full-scale (white) output current (in amps)
from the D/A converter (without sync). Sync is 0.4 * IFS.
D/A full-scale (white) current may also be calculated from:
IFS = VFS/RL
Where VFS is the white voltage level and RL is the total
resistive load (Ω) on each D/A converter. VFS is the blank
to full-scale voltage.
Voltage Reference
All three D/A converters are supplied with a common
voltage reference. Internal bandgap voltage reference
voltage is +1.235V with a 3kΩ source resistance. An
external voltage reference may be connected to the VREF
pin, overriding the internal voltage reference.
A 0.1µF capacitor must be connected between the COMP
pin and VDD to stabilize internal bias circuitry and ensure
low-noise operation.
Voltage Reference Output/Input - VREF
An internal voltage source of +1.235V is output on the
VREF pin. An external +1.235V reference may be applied
here which overrides the internal reference. Decoupling
VREF to GND with a 0.1µF ceramic capacitor is required.
Power and Ground
Required power is a single +5.0V supply. To minimize power
supply induced noise, analog +5V should be connected
to VDD pins with 0.1µF and 0.01µF decoupling capacitors
placed adjacent to each VDD pin or pin pair.
The high slew-rate of digital data makes capacitive cou-
pling to the outputs of any D/A converter a potential
problem. Since the digital signals contain high-frequency
components of the CLK signal, as well as the video out-
put signal, the resulting data feedthrough often looks
like harmonic distortion or reduced signal-to-noise perfor-
mance. All ground pins should be connected to a common
solid ground plane for best performance.
TT TT o<>
Data Sheet
CDK3400/CDK3401 10-bit, 100/150MSPS, Triple Video DACs Rev 1D
©2009-2013 Exar Corporation 8/11 Rev 1D
Figure 3. Equivalent Digital Input Circuit Figure 4. Equivalent Analog Output Circuit
Figure 5. Equivalent Analog Input Circuit
Equivalent Circuits
Digital
Input
V
DD
p
n
GND
p
GND
R
REF
V
REF
p
VDD
pn
GND
OUT
VDD
VDD
““““““““““““““““
Data Sheet
CDK3400/CDK3401 10-bit, 100/150MSPS, Triple Video DACs Rev 1D
©2009-2013 Exar Corporation 9/11 Rev 1D
220µF
220µF
CLC3800
IN1 OUT1
IN2
IN3 OUT3
+Vs
OUT2
GND
75Ω
75Ω
75Ω
75Ω
220µF
75Ω
75Ω
75Ω
75Ω
75Ω
CDK3400/
CDK3401
IOR
IOB
IOG
AC-Coupling Caps
are Optional
DVD Player or STB
R
G
B
+3V or +5V
0.1µF1.0µF
8
7
6
5
1
2
3
4
75Ω
Video Cables
75Ω
75Ω
330Ω
330Ω
CDK3400/
CDK3401
IOR
IOB
IOG
75Ω
Video Cables
+
-
+Vs
-Vs
75Ω
1/3
CLC3605
75Ω
75Ω
330Ω
330Ω
CDK3400/
CDK3401
IOR
IOB
IOG
75Ω
Video Cables
+
-
+Vs
-Vs
75Ω
1/3
CLC3605
75Ω
75Ω
75Ω
Video Cables
75Ω
75Ω
75Ω
Video Cables
Figure 6. Standard Definition Video Output Circuit Diagram
Figure 7. Graphics Output Driver Circuit Diagram
Figure 8. Standard Definition Video Distribution Circuit Diagram
Typical Application Diagrams
Data Sheet
CDK3400/CDK3401 10-bit, 100/150MSPS, Triple Video DACs Rev 1D
©2009-2013 Exar Corporation 10/11 Rev 1D
R9-0
G9-0
B9-0
+5V
0.1µF
10µF
VDD GND
CDK3400/3401
Triple 10-bit D/A Converter
CLK
SYNC
BLANK
RED PIXEL
INPUT
GREEN PIXEL
INPUT
BLUE PIXEL
INPUT
CLOCK
SYNC
BLANK
COMP
VREF
RREF
+5V
0.1µF
0.1µF
560Ω
3.3kΩ
(not required without external reference)
LM185-1.2
(Optional)
IOR
IOG
IOB
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
Zo = 75Ω
Red
Green w/Sync
Blue
Zo = 75Ω
Zo = 75Ω
Figure 9. Typical Interface Circuit Diagram
Printed Circuit Board Layout
Designing with high-performance mixed-signal circuits
demands printed circuits with ground planes. Overall
system performance is strongly influenced by the board
layout. Capacitive coupling from digital to analog circuits
may result in poor D/A conversion. Consider the following
suggestions when doing the layout:
1. Keep the critical analog traces (VREF, IREF, COMP, IOS,
IOR, IOG) as short as possible and as far as possible
from all digital signals. The CDK3400/3401 should be
located near the board edge, close to the analog out-put
connectors.
2. Power plane for the CDK3400/3401 should be separate
from that which supplies the digital circuitry. A single
power plane should be used for all of the VDD pins. If
the power supply for the CDK3400/3401 is the same
as that of the system’s digital circuitry, power to the
CDK3400/3401 should be decoupled with 0.1µF and
0.01µF capacitors and iso-lated with a ferrite bead.
3. The ground plane should be solid, not cross-hatched.
Connections to the ground plane should have very short
leads.
4. If the digital power supply has a dedicated power plane
layer, it should not be placed under the CDK3400/3401,
the voltage reference, or the analog outputs. Capacitive
coupling of digital power supply noise from this layer
to the CDK3400/3401 and its related analog circuitry can
have an adverse effect on performance.
5. CLK should be handled carefully. Jitter and noise on this
clock will degrade performance. Terminate the clock line
carefully to eliminate overshoot and ringing.
Evaluation boards are available (CEB3400 and CEB3401),
contact Exar for more information.
Related Products
n
CDK3402/3403 Triple 8-bit 100/150MSPS DACs
n
CDK3404 Triple 8-bit 180MSPS DAC
Applications Dicussion
Figure 9 below illustrates a typical CDK3400/3401 inter-
face circuit. In this example, an optional 1.2V bandgap
reference is connected to the VREF output, overriding the
internal voltage reference source.
Grounding
It is important that the CDK3400/3401 power supply is well-
regulated and free of high-frequency noise. Careful power
supply decoupling will ensure the highest quality video
signals at the output of the circuit. The CDK3400/3401 has
separate analog and digital circuits. To keep digital system
noise from the D/A converter, it is recommended that
power supply voltages (VDD) come from the system analog
power source and all ground connections (GND) be made
to the analog ground plane. Power supply pins should be
individually decoupled at the pin.
HHHHHH HHHHHH i + \ HHHHHH HHHHHH MAX. 1.05 1.05 1.20 1.10 1.10 1.10 +.1 5/11 0 BAS‘C 1.05 ddd MAX. ccc MAX. JEDEC REFERENCE DRAWING VAR‘ATION DESIGNATOR .60 .50 .22 6—7 .00 .00 M51025 ABC 0.20 RAD. TVP. 514' 0.20 RAD. w, annoFF AI 1 am? NOTES 1 AH dwmensmns m mm. seahng wane fLfiW LEAD—E copuwm 2 mmensmn Shawn are nomma‘ w‘m «merances mdmahad 3. Font \Engm 'L‘ Is measuved at gage mane 0.25m above 4 UF' Eflec EAT Cu or equiva‘em. 0127mm (0 005") lmck & A New Direction in Mixed-Signal
Data Sheet
CDK3400/CDK3401 10-bit, 100/150MSPS, Triple Video DACs Rev 1D
For Further Assistance:
Exar Corporation Headquarters and Sales Offices
48720 Kato Road Tel.: +1 (510) 668-7000
Fremont, CA 94538 - USA Fax: +1 (510) 668-7001
www.exar.com
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage
has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
©2009-2013 Exar Corporation 11/11 Rev 1D
Mechanical Dimensions
TQFP-48 Package

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