RT9088 Datasheet by Richtek USA Inc.

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RICHTEK W
RT9088
®
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Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
DDR Termination Regulator
Applications
Notebook/Desktop/Server
Telecom/Datacom, GSM Base Station, LCD-TV/PDP-
TV, Copier/Printer, Set-Top Box
General Description
The RT9088 is a sink/source tracking termination regulator.
It is specifically designed for low-cost and low-external
component count systems. The RT9088 possesses a high
speed operating amplifier that provides fast load transient
response and only requires a minimum 30μF ceramic
output capacitor. The RT9088 supports remote sensing
functions and all features required to power the DDRIII
and Low Power DDRIII / DDRIV VTT bus termination
according to the JEDEC specification. In addition, the
RT9088 provides an open-drain PGOOD signal to monitor
the output regulation and an EN signal that can be used
to discharge VTT during S3 (suspend to RAM) for DDR
applications.
The RT9088 is available in the thermal efficient package,
WDFN-10L 3x3.
Features
VIN Input Voltage Range: 1.1V to 3.5V
VCNTL Input Voltage Range: 2.9V to 5.5V
Support Ceramic Capacitors
Power Good Indicator
10mA Source/Sink Reference Output
Meet DDRI, DDRII JEDEC Spec
Support DDRIII, Low Power DDRIII/DDRIV VTT
Applications
Soft-Start Function
UVLO and OCP Protection
Thermal Shutdown
Marking Information
Simplified Application Circuit
RT9088
REFIN
VIN
SENSE
PGND
VCNTL
PGOOD
GND
REFOUT
EN
VOUT
C2
R1
C1
C3
REFOUT
VIN
R3 C4
R2
C5
VCNTL
Power Good Indicator
VOUT
EN
63=YM
DNN
63= : Product Code
YMDNN : Date Code
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Functional Pin Description
Pin No. Pin Name Pin Function
1 REFIN Reference Input.
2 VIN Power Input of the Regulator.
3 VOUT Power Output of the Regulator.
4 PGND Power Ground of the Regulator.
5 SENSE
Voltage Sense Input for the Regulator. Connect to positive terminal of the
output capacitor or the load.
6 REFOUT Reference Output. Connect to GND through a 0.1F ceramic capacitor.
7 EN Enable Control Input. For DDR VTT application, connect EN to SLP_S3. For
other applications, use EN as the ON/OFF function.
9 PGOOD
Power Good Open-Drain Output. Connect a pull-up resistor between this pin
and VCNTL pin.
10 VCNTL
Control Voltage Input. Connect this pin to the 3.3V or 5V power supply. A
ceramic decoupling capacitor with a value 4.7F is required.
8,
11 (Exposed Pad) GND
Analog Ground. Connect to negative terminal of the output capacitor. The
exposed pad must be soldered to a large PCB and connected to GND for
maximum power dissipation.
Ordering Information
Note :
Richtek products are :
RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
Pin Configurations
(TOP VIEW)
WDFN-10L 3x3
REFIN
VIN
SENSE
PGND
VCNTL
PGOOD
GND
REFOUT
EN
VOUT
9
8
7
1
2
3
4
5
10
6
GND
11
RT9088
Package Type
QW : WDFN-10L 3x3 (W-Type)
Lead Plating System
G : Green (Halogen Free and Pb Free)
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Function Block Diagram
Operation
The RT9088 is a linear sink/source DDR termination
regulator with current capability up to 3A. The RT9088
builds in a high-side N-MOSFET which provides current
sourcing and a low-side N-MOSFET which provides current
sinking. All the control circuits are supplied by the power
VCNTL. In normal operation, the error amplifier OP adjusts
the gate driving voltage of the power MOSFET to achieve
SENSE voltage well tracking the REFIN voltage.
Both the source and sink currents are detected by the
internal sensing resistor, and the OCP function will work
to limit the current to a designed value when overload
happens. Furthermore, the current will be folded back to
be one half if VOUT is out of the power good window.
Buffer
This function provides REFOUT output equal to REFIN
with 10mA source/sink current capability.
Power Good
When the SENSE voltage is in the power good window
and lasts for a certain delay time, then the PGOOD pin
will be high impedance and the PGOOD voltage will be
pulled high by the external resistor.
Control Logic
This block includes VCNTL UVLO, REFIN UVLO and
Enable/Disable functions, and provides logic control to
the whole chip.
Thermal Protection
Both the high-side and low-side power MOSFETs will be
turned off when the junction temperature is higher than
typically 160°C, and be released to normal operation when
junction temperature falls below 120°C typically.
+
-
OCP
+
-
OCP
+
-
Thermal
Protection
Control
Logic
OP
Power
Good
Buffer
REFIN VIN
SENSE
PGND
VCNTL
PGOOD
GND
REFOUT
EN
VOUT
Driver
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Electrical Characteristics
Recommended Operating Conditions (Note 4)
Control Input Voltage, VCNTL ------------------------------------------------------------------------------------------ 2.9V to 5.5V
Supply Input Voltage, VIN ----------------------------------------------------------------------------------------------- 1.1V to 3.5V
Junction Temperature Range -------------------------------------------------------------------------------------------- 40°C to 125°C
Ambient Temperature Range -------------------------------------------------------------------------------------------- 40°C to 85°C
Absolute Maximum Ratings (Note 1)
Supply Voltage, VIN, VCNTL ------------------------------------------------------------------------------------------- 0.3V to 6V
Input Voltage, EN, REFIN, SENSE ----------------------------------------------------------------------------------- 0.3V to 6V
Output Voltage, VOUT, REFOUT, PGOOD -------------------------------------------------------------------------- 0.3V to 6V
Power Dissipation, PD @ TA = 25°C
WDFN-10L 3x3 ------------------------------------------------------------------------------------------------------------- 3.27W
Package Thermal Resistance (Note 2)
WDFN-10L 3x3, θJA ------------------------------------------------------------------------------------------------------- 30.5°C/W
WDFN-10L 3x3, θJC ------------------------------------------------------------------------------------------------------- 7.5°C/W
Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------- 260°C
Junction Temperature ----------------------------------------------------------------------------------------------------- 150°C
Storage Temperature Range -------------------------------------------------------------------------------------------- 65°C to 150°C
ESD Susceptibility (Note 3)
HBM (Human Body Model) ---------------------------------------------------------------------------------------------- 2kV
(VIN = 1.5V, VEN = VCNTL = 3.3V, VREFIN = VSENSE = 0.75V, COUT = 10μF x 3, TA = 25°C, unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
Supply Current
VCNTL Supply Current IVCNTL V
EN = VCNTL, No Load -- 0.7 1 mA
VEN = 0V, VREFIN = 0V, No Load -- 65 80 A
VCNTL Shutdown Current ISHDN_VCNTL VEN = 0V, VREFIN > 0.4V, No Load -- 200 400 A
VIN Supply Current IVIN V
EN = VCNTL, No Load -- 1 50 A
VIN Shutdown Current ISHDN_VIN V
EN = 0V, No Load -- 0.1 50 A
Output
VIN = 1.5V, VREFIN = 0.75V,
IOUT = 0A -- 0.75 -- V
VIN = 1.35V, VREFIN = 0.675V,
IOUT = 0A -- 0.675 -- V
VTT Output Voltage VOUT
VIN = 1.2V, VREFIN = 0.6V,
IOUT = 0A -- 0.6 -- V
IOUT = ±2A, VLDOIN = 1.5V,
VREFOUT = 0.75V 25-- 25
IOUT = ±2A, VLDOIN = 1.35V,
VREFOUT = 0.675V25-- 25
REFIN, VTT Output
Voltage Offset VOUT_OS
IOUT = ±2A, VLDOIN = 1.2V,
VREFOUT = 0.6V25-- 25
mV
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Parameter Symbol Test Conditions Min Typ Max Unit
VOUT Source Current Limit ILIM_VOUT_SR VOUT in PGOOD Window 3.5 -- 5.5 A
VOUT Sink Current Limit ILIM_VOUT_SK VOUT in PGOOD Window 3.5 -- 5.5 A
VOUT Discharge
Resistance RDISCHARGE VREFIN = 0V, VOUT = 0.3V,
VEN = 0V -- 18 25
Power Good Comparator
VSENSE lower threshold with
respect to REFOUT 25 20 15
VSENSE upper threshold with
respect to REFOUT 15 20 25
PGOOD Threshold VTH_PGOOD
PGOOD Hysteresis -- 5 --
%
PGOOD Start-Up Delay TPGDELAY1 Start-up rising delay, VSENSE
within PGOOD range -- 2 -- ms
Output Low Voltage VLOW_PGOOD I
PGOOD = 4mA -- -- 0.4 V
PGOOD Falling Delay TPGDELAY2 Falling delay, VSENSE is out of
PGOOD range -- 10 -- s
Leakage Current ILEAKAGE _PGOOD
VSENSE = VREFIN (PGOOD
high impedance),
VPGOOD = VIN + 0.3V
-- -- 1 A
REFIN and REFOUT
REFIN Input Current IREFIN V
EN = VCNTL -- -- 1 A
REFIN Voltage Range VREFIN 0.5 -- 1.8 V
REFIN Rising 360 390 420
REFIN Under-Voltage
Lockout VUVLO_REFIN Hysteresis -- 20 --
mV
10mA < IREFOUT < 10mA,
VREFIN = 0.75V 15 -- 15
10mA < IREFOUT < 10mA,
VREFIN = 0.675V 15 -- 15
REFOUT Voltage Tolerance
to VREFIN
VTOL_REFOUT
10mA < IREFOUT < 10mA,
VREFIN = 0.6V 15 -- 15
mV
REFOUT Source Current
Limit ILIM_REFOUT_SR V
REFOUT = 0V 10 40 -- mA
REFOUT Sink Current Limit ILIM_REFOUT_SK V
REFOUT = REFIN + 1V 10 40 -- mA
UVLO/EN
Rising 2.5 2.7 2.85 V
UVLO Threshold VUVLO_VCNTL Hysteresis -- 120 -- mV
Logic-High VIN_H 1.7 -- --
EN Input
Voltage Logic-Low VIN_L -- -- 0.3
V
Thermal Shutdown
Shutdown Temperature -- 160 --
Thermal Shutdown
Threshold TSD Hysteresis -- 15 --
°C
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Note 1. Stresses beyond those listed Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
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Typical Application Circuit
RT9088
REFIN
VIN
SENSE
PGND
VCNTL
PGOOD
GND
REFOUT
EN
VOUT
9
8, 11 (Exposed Pad)
7
1
2
3
4
5
10
6
C2
1nF
R1
10k
C1
10µF x 2
C3
0.1µF
REFOUT
VIN
R3
100k
C4
4.7µF
R2
10k
C5
10µF x 3
VCNTL
2.5V/3.3V/5V
Power Good Indicator
VOUT
EN
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Sourcing Current Limit vs. Temperature
1.0
1.5
2.0
2.5
3.0
3.5
4.0
-50 -25 0 25 50 75 100 125
Temperature (°C)
Current Limit (A)
VCNTL = 3.3V,
VIN = VDDQSNS = 1.5V, VOUT = 0.75V
Typical Operating Characteristics
Output Voltage vs. Temperature
0.5
0.6
0.7
0.8
0.9
1.0
-50 -25 0 25 50 75 100 125
Temperature (°C)
Output Voltage (V)
VCNTL = 3.3V,
VIN = VDDQSNS = 1.5V, VOUT = 0.75V
REFOUT Voltage vs. Temperature
0.5
0.6
0.7
0.8
0.9
1.0
-50 -25 0 25 50 75 100 125
Temperature (°C)
Output Voltage(V)
VCNTL = 3.3V,
VIN = VDDQSNS = 1.5V, VOUT = 0.75V
VCNTL Supply Current vs. Temperature
300.0
320.0
340.0
360.0
380.0
400.0
420.0
440.0
460.0
480.0
500.0
-50 -25 0 25 50 75 100 125
Temperature (°C)
VCNTL Supply Current (μA) 1
VIN = VDDQSNS = 1.5V, VOUT = 0.75V
VCNTL = 5V
VCNTL = 3.3V
UVLO vs. Temperature
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
-50 -25 0 25 50 75 100 125
Temperature (°C)
UVLO (V)
VIN = VDDQSNS = 1.5V,
VEN = 2V, VOUT = 0.75V
Rising
Falling
VCNTL Shutdown Current vs. Temperature
50
100
150
200
250
300
350
-50 -25 0 25 50 75 100 125
Temperature (°C)
VCNTL Shutdown Current (μA) 1
VIN = VDDQSNS = 1.5V, VOUT = 0.75V
VCNTL = 5V
VCNTL = 3.3V
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Sinking Current Limit vs. Temperature
1.0
1.5
2.0
2.5
3.0
3.5
4.0
-50 -25 0 25 50 75 100 125
Temperature (°C)
Current Limit (A)
VCNTL = 3.3V,
VIN = VDDQSNS = 1.5V, VOUT = 0.75V
Time (100μs/Div)
Power On from EN
VREFOUT
(1V/Div)
VOUT
(0.5V/Div)
IOUT
(1A/Div)
VEN
(2V/Div)
VCNTL = 3.3V, VIN = 1.5V,
VOUT = 0.75V, IOUT = 1.5A
Time (500μs/Div)
0.75VOUT @ 1.5A Transient Response
IOUT
(1A/Div)
VOUT
(10mV/Div)
Source, VIN = 1.5V
Time (10μs/Div)
Power Off from EN
VCNTL = 3.3V, VIN = 1.5V,
VOUT = 0.75V, IOUT = 1.5A
VREFOUT
(1V/Div)
VOUT
(0.5V/Div)
IOUT
(1A/Div)
VEN
(2V/Div)
Time (500μs/Div)
0.75VOUT @ 1.5A Transient Response
Sink, VIN = 1.5V
IOUT
(1A/Div)
VOUT
(10mV/Div)
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Application Information
The RT9088 is a 3.5A sink/source tracking termination
regulator. It is specifically designed for low-cost and low-
external component count system such as notebook PC
applications. The RT9088 possesses a high speed
operating amplifier that provides fast load transient response
and only requires two 10μF ceramic input capacitors and
three 10μF ceramic output capacitors.
Capacitor Selection
Good bypassing is recommended from VLDOIN to GND
to help improve AC performance. A 10μF or greater input
capacitor located as close as possible to the IC is
recommended. The input capacitor must be located at a
distance of less than 0.5 inches from the VLDOIN pin of
the IC.
Adding a 1μF ceramic capacitor close to the VIN pin and
it should be kept away from any parasitic impedance from
the supply power. For stable operation, the total
capacitance of the ceramic capacitor at the VTT output
terminal must be larger than 30μF. The RT9088 is designed
specifically to work with low ESR ceramic output capacitor
in space saving and performance consideration. Larger
output capacitance can reduce the noise and improve load
transient response, stability and PSRR. The output
capacitor should be located near the VTT output terminal
pin as close as possible.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
Figure 1. Derating Curve of Maximum Power Dissipation
WDFN-10L 3x3 package, the thermal resistance, θJA, is
30.5°C/W on a standard JEDEC 51-7 four-layer thermal
test board. The maximum power dissipation at TA = 25°C
can be calculated by the following formula :
PD(MAX) = (125°C 25°C) / (30.5°C/W) = 3.27W for
WDFN-10L 3x3 package
The maximum power dissipation depends on the operating
ambient temperature for fixed TJ(MAX) and thermal
resistance, θJA. The derating curve in Figure 1 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0 25 50 75 100 125
Ambient Temperature (°C)
Maximum Power Dissipation (W) 1
Four-Layer PCB
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Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
Outline Dimension
Dimensions In Millimeters Dimensions In Inches
Symbol Min Max Min Max
A 0.700 0.800 0.028 0.031
A1 0.000 0.050 0.000 0.002
A3 0.175 0.250 0.007 0.010
b 0.180 0.300 0.007 0.012
D 2.950 3.050 0.116 0.120
D2 2.300 2.650 0.091 0.104
E 2.950 3.050 0.116 0.120
E2 1.500 1.750 0.059 0.069
e 0.500 0.020
L 0.350 0.450
0.014 0.018
W-Type 10L DFN 3x3 Package
11
2
2
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
DETAIL A
Pin #1 ID and Tie Bar Mark Options
D
1
E
A3
A
A1
D2
E2
L
b
e
SEE DETAIL A

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