ALLEQW'SQ
The A4450 is a power management IC that can implement
either a buck or buck-boost regulator to efficiently convert
automotive battery voltages into a tightly regulated voltage. It
includes control, diagnostics, and protection functions.
An enable input to the A4450 is compatible to a high-voltage
battery level, (EN).
A diagnostic output from the A4450 includes a power-on reset
output (NPOR) signal.
Protection features include pulse-by-pulse current limit, hiccup
mode short-circuit protection, LX short-circuit protection,
missing freewheeling diode (buck diode at LX node in A4450)
protection, and thermal shutdown.
The A4450 is most suitable for applications where the input
voltage can vary from less than or greater than the regulated
output voltage.
The A4450 is supplied in 4 × 4 mm QFN (suffix “ES”) with
exposed power pad.
A4450-DS, Rev. 4
MCO-0000167
• Automotive AEC-Q100 qualified
• Wide operating range of 3 to 36 VIN, 40 VIN maximum,
covers automotive stop/start, cold crank, double battery,
and load dump
• Regulated output can operate up to 2 A DC
• Adjustable PWM switching frequency:
250 kHz to 2.2 MHz
• PWM frequency can be synchronized to external clock:
250 kHz to 2.4 MHz
• Frequency dithering helps reduce EMI/EMC
• Undervoltage protection
• Pin-to-pin and pin-to-ground tolerant at every pin
• Thermal shutdown protection
• Operating junction temperature range −40°C to 150°C
Buck-Boost Controller with Integrated Buck MOSFET
PACKAGES:
Not to scale
A4450
FEATURES AND BENEFITS DESCRIPTION
20-pin 4 × 4 mm QFN (ES) with wettable flank
APPLICATIONS
Typical Application Diagram
• Infotainment
• Instrument Clusters
• Control Modules
A4450
VBAT
VIN
AVIN
COMP
LX
LG
BOOT
EN
PGND
FSET /SYNC
NPOR
GND
FB
RNG
SS
LX
VIN
VOUT
D1
D2
Buck
Diode
Boost
Diode
VIN
July 2, 2019
“€953
Buck-Boost Controller with Integrated Buck MOSFET
A4450
2
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
SELECTION GUIDE
Part Number Temperature Range Packing
[1] Package Lead Frame
A4450KESTR-J –40°C to 150°C 1500 pieces per 7-inch reel 20-pin QFN with thermal pad and wettable flank 100% matte tin
[1] Contact Allegro for additional packing options.
ABSOLUTE MAXIMUM RATINGS
[2]
Characteristic Symbol Notes Rating Unit
VIN VIN –0.3 to 40 V
AVIN VAVIN –0.3 to 40 V
EN VEN –0.3 to VIN V
LX VLX
continuous −0.3 to VIN + 0.3 V
t < 250 ns –1.5 V
t < 50 ns VIN + 3 V
LG VLG –0.3 to 8.5 V
BOOT VBOOT VLX – 0.3 to VLX + 6 V
All other pins –0.3 to 7.5 V
Junction Temperature Range TJ–40 to 150 °C
Storage Temperature Range Tstg –55 to 150 °C
[2] Stresses beyond those listed in this table may cause permanent damage to the device. The absolute maximum ratings are stress ratings only, and functional operation of
the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability
THERMAL CHARACTERISTICS
Characteristic Symbol Test Conditions
[3] Value Unit
Junction to Ambient Thermal Resistance RθJA QFN-20 (ES) package, 4-layer PCB based on JEDEC standard 37 °C/W
[3] Additional thermal information available on the Allegro website.
ALLEGRO'
mxcrosystems
Buck-Boost Controller with Integrated Buck MOSFET
A4450
3
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Table of Contents
Features and Benefits 1
Description 1
Applications 1
Package 1
Typical Application Diagram 1
Selection Guide 2
Absolute Maximum Ratings 2
Thermal Characteristics 2
Pinout Diagram and Terminal List Table 4
Functional Block Diagram 5
Electrical Characteristics 6
Typical Performance Characteristics 9
Functional Description 11
Overview 11
Operation Modes 11
Buck Mode 11
Buck-Boost Mode 11
Reference Voltage 12
Oscillator/Switching Frequency & Synchronization 12
Frequency Dithering 13
Transconductance Err. Amp. & Compensation 14
Slope Compensation 14
Enable Input (EN) 14
Integrated Buck MOSFET 14
Current Sense Amplifier 14
Pulse-Width Modulation (PWM) Mode 15
BOOT Regulator 15
Soft-Start (Startup) and Inrush Current Control 16
Pre-Biased Startup 16
Not Powered-On Reset (NPOR) Output 16
Protection Features 17
Design and Component Selection 20
Setting the Output Voltage 20
PWM Switching Frequency (fSW, RFSET) 20
Output Inductor (LO) 21
Buck Diode (D1) & Boost Diode (D2) 21
External Boost Switch 22
Output Capacitors 22
Input Capacitors 22
Bootstrap Capacitor 23
Soft-Start and Hiccup Mode Timing (CSS) 23
Compensation Components (RZ, CZ, CP) 24
Generalized Tuning Procedure 25
Design Example Schematics 27
Input/Output Range Guidelines 30
Power Dissipation & Thermal Calculations 32
PCB Component Placement & Routing 34
Package Outline Drawing 35
__________
LLEGRO'
mxcrosystems
Buck-Boost Controller with Integrated Buck MOSFET
A4450
4
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Package ES, 20-Pin QFN Pinout Diagram
Terminal List Table
Symbol Number Function
VIN 1, 2 Input voltage; ensure decoupling capacitors are connected directly to this pin.
GND 3, 7, 12 Ground pin for decoupling and ground connection.
EN 4
Enable pin; 40 V rated and logic level compatible; can be connected to VIN or switching battery.
Used to turn the regulator on or off: set pin high to turn the regulator on or set pin low to turn the regulator off. Can be
used to set UVLO threshold with external resistor divider.
NC 5, 13 No connection.
AVIN 6 Input to internal voltage regulator and boost duty generator; must connect to VIN through a resistor (5 Ω typ) and a
capacitor is suggested to be added between AVIN pin and GND to form a RC filter.
FSET/SYNC 8
Frequency setting and synchronization input. Switching frequency is programmed by connecting a resistor from
this pin to ground. This pin can also accept a square wave switching signal that synchronizes the converter through
internal PLL.
RNG 9 Output range select pin. A resistor connected between RNG pin and GND is selected base on the target VOUT.
NPOR 10 Active-low power-on reset output signal. This pin is an open-drain regulator fault detection output that transitions from
low to high impedance after the output has maintained regulator for tdNPOR.
SS 11 A capacitor from this pin to GND sets the soft-start time. This capacitor also determines the hiccup period.
COMP 14 Error amplifier compensation network pin. Connect series RC network from this pin to ground for loop compensation to
stabilize the converter.
FB 15 Feedback pin for output. Connect a voltage divider from the output to this pin to program the output voltage.
LG 16 Gate drive output for the external boost switch. Connect a 10 kΩ resistor from this pin to PGND.
PGND 17 Power ground. Provide power ground return for drivers.
BOOT 18 Bootstrap capacitor connection. Connect a capacitor from this pin to LX pin. This pin provides supply voltage for the
high-side and low-side gate drivers.
LX 19, 20 Switching node of the regulator; the output inductor and cathode of the buck diode should be connected to this pin
with relatively wide traces. The inductor and buck diode should be placed as close as possible to this pin.
PINOUT DIAGRAM AND TERMINAL LIST TABLE
1
2
3
4
511
12
13
14
15
6
7
8
9
10 16
17
18
19
20
VIN
VIN
GND
EN
NC
AVIN
GND
FS
ET/SYNC
RNG
NPOR
SS
GND
NC
COMP
FB
LG
PGND
BOOT
LX
LX
ALLEGRO'
mwcrosystems
Buck-Boost Controller with Integrated Buck MOSFET
A4450
5
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
FUNCTIONAL BLOCK DIAGRAM
A4450
VIN
EN
CLK @ fosc
0.1 µA
LDO
AVIN
COMP BUCK-BOOST
Control
(w/ Hiccup Mode)
FB
LX
LG
SS OK
MASTER
IC POR
* indicates a
latched fault
1.9 VTYP↑
1.24 VTYP↓
CLK1MHz
OSC2
BOOT
Boot Circuit
EN
PGND
TSD
FSET/SYNC
OSC1
PLL
100 nA
BG1
ON
ON
DE-
GLITCH
tdEN(FILT)
NPOR Timing NPOR
CLK1MHz
VOUT_OV
BG_UV
VIN_UV
*D1MISSING
*ILIM(LX)
MPOR
GND
BG
BG_UV
BG
VOUT_OV
FB
FB
*D1MISSING
*ILIM(LX)
Soft Start
tSS RNG
RANGE
SS
LX
VIN
VCC
BOOT
ALLEGRO'
mxcrosystems
Buck-Boost Controller with Integrated Buck MOSFET
A4450
6
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
GENERAL SPECIFICATIONS
Operating Input Voltage VIN After VIN > VINSTART, VEN ≥ 4 V 3.0 13.5 36 V
VIN UVLO Start VINSTART VIN rising – – 4.8 V
VIN UVLO Stop VINSTOP VIN falling, when in Buck-Boost mode – – 2.9 V
Supply Quiescent Current
[1] IQVIN = 13.5 V, VEN ≥ 4 V, no load – 4.5 – mA
IQ(SLEEP) VIN = 13.5 V, VEN ≤ 1 V, no load – – 10 µA
PWM SWITCHING FREQUENCY AND DITHERING
Switching Frequency fOSC
RFSET = 7.87 kΩ 1.8 2.0 2.2 MHz
RFSET = 41.2 kΩ 343 400 457 kHz
Frequency Dithering ΔfOSC As a percent of fOSC – ±12 – %
VIN Dithering START Threshold VIN(DITHER,ON)
VIN rising, RNG = 15 kΩ, target VOUT = 5 V 7.0 [3] V
VIN falling – 16.6 – V
VIN Dithering STOP Threshold VIN(DITHER,OFF)
VIN falling, RNG = 15 kΩ, target VOUT = 5 V 7.0 [3] V
VIN rising – 18 – V
VIN Dithering Hysteresis VIN(DITHER,HYS) – 1.5 – V
THERMAL PROTECTION
Thermal Shutdown Threshold
[2] TTSD TJ rising 160 170 180 °C
Thermal Shutdown Hysteresis
[2] THYS – 20 – °C
OUTPUT VOLTAGE SPECIFICATIONS
Feedback Voltage Tolerance VFB VIN = 13.5 V, EN = high 0.788 0.800 0.812 V
PULSE-WIDTH MODULATION (PWM)
PWM Ramp Offset VPWMOFFS VCOMP for 0% duty cycle – 400 – mV
LX Rising Slew Rate
[2] LXRISE VIN = 13.5 V, 10% to 90%, ILX = 1 A – 1.5 – V/ns
LX Falling Slew Rate
[2] LXFALL VIN = 13.5 V, 10% to 90%, ILX = 1 A – 1.8 – V/ns
Buck Minimum On-Time tON(MIN,BUCK) – 85 120 ns
Buck Minimum Off-Time tOFF(MIN,BUCK) – 85 120 ns
Boost Maximum Duty Cycle DMAX(BST)
VIN = 3.5 V, VOUT = 8 V target, RNG = 25.5 kΩ, 2 MHz – 0.75 – –
VIN = 3.5 V, VOUT = 5 V target, RNG = 15 kΩ, 2 MHz – 0.57 – –
VIN = 3.5 V, VOUT = 3 V target, RNG = 9.31 kΩ, 2 MHz – 0.31 – –
COMP to LX Current Gain gmPOWER 3.5 4.7 5.9 A/V
Slope Compensation
[2] SE
fOSC = 2 MHz 1.76 2.2 2.64 A/µs
fOSC = 400 kHz 0.35 0.44 0.53 A/µs
INTERNAL MOSFET
MOSFET On Resistance RDSon
VIN = 13.5 V, TJ = –40°C (2), IDS = 0.1 A – 60 90 mΩ
VIN = 13.5 V, TJ = 25°C (2), IDS = 0.1 A – 80 110 mΩ
VIN = 13.5 V, TJ = 150°C, IDS = 0.1 A – 140 170 mΩ
MOSFET Leakage IFET(LKG)
VEN ≤ 1 V, VLX = 0 V, VIN = 13.5 V,
−40°C ≤ TJ ≤ 85°C
(2) – – 10 µA
Continued on the next page…
ELECTRICAL CHARACTERISTICS: Valid at 3 V ≤ VIN ≤ 36 V and VIN having first reached VINSTART,
‒40°C ≤ TJ ≤ 150°C, unless noted otherwise
ALLEGRO'
mxcrosystems
Buck-Boost Controller with Integrated Buck MOSFET
A4450
7
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
ERROR AMPLIFIER
Open-Loop Voltage Gain AVOL – 65 – dB
Transconductance gmEA 550 750 950 µA/V
Output Current IEA – ±75 – µA
Maximum Output Voltage,
Buck-Boost Mode VEAVO(max)BuckBoost – 1.5 – V
Maximum Output Voltage,
Buck Mode VEAVO(max)Buck – 1.2 – V
Minimum Output Voltage VEAVO(min) 150 220 290 mV
BOOST MOSFET (LG) GATE DRIVER
LG High Output Voltage VLG(ON) VIN = 7 V 5.0 – 8.0 V
LG Low Output Voltage VLG(OFF) VIN = 13.5 V – – 0.4 V
LG Source Current
[1] ILG(ON) VLG = 1 V – −265 – mA
LG Sink Current
[1] ILG(OFF) VLG = 1 V – 500 – mA
SOFT-START
SS PWM Frequency Foldback
(Linear) fSW(SS)
VFB = 0 V – 0.12 ×
fOSC
– –
VFB = 0.2 V – 0.43 ×
fOSC
– –
VFB = 0.6 V – 0.93 ×
fOSC
– –
VFB = 0.8 V – fOSC – –
Switching Frequency in SYNC Mode
with Applied Frequency fSYNC
fSW(SYNC)
0 V < VFB < 0.2 V – fSYNC/4 – –
0.2 V < VFB < 0.4 V – fSYNC/2 – –
0.4 V < VFB – fSYNC – –
HICCUP MODE
Hiccup OCP PWM Counts tHIC(OCP)
VFB < 0.4 V (typical), VCOMP = VEAVO(max) – 30 – PWM
cycles
VFB > 0.4 V (typical), VCOMP = VEAVO(max) – 120 – PWM
cycles
Hiccup Mode Recovery Time tHIC(RECOVER)
LX switching stops to LX switching starts, during
overcurrent 3.0 – 5.6 ms
CURRENT PROTECTIONS
Pulse-by-Pulse Current Limit,
Buck-Boost Mode ILIM(BuckBoost) Buck-Boost mode 3.9 4.5 5.1 A
Pulse-by-Pulse Current Limit,
Buck Mode ILIM(Buck) Buck mode 2.4 2.8 3.4 A
LX Short-Circuit Current Limit ILIM(LX) 6.3 7.4 8.5 A
MISSING BUCK DIODE (D1) PROTECTION
Detection Level
[2] VD(OPEN) −1.6 −1.4 −1.1 V
Time Filtering [2] tD(OPEN) 50 – 250 ns
ELECTRICAL CHARACTERISTICS (continued): Valid at 3 V ≤ VIN ≤ 36 V and VIN having first reached VINSTART,
‒40°C ≤ TJ ≤ 150°C, unless noted otherwise
Continued on the next page…
ALLEGRO'
mxcrosystems
Buck-Boost Controller with Integrated Buck MOSFET
A4450
8
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
ENABLE (EN) INPUT
EN Thresholds VEN(H) VEN rising – 1.9 2.25 V
VEN(L) VEN falling 1.0 1.2 – V
EN Hysteresis VEN(HYS) VEN(H) – VEN(L) – 700 – mV
EN Bias Current
[1] IEN(BIAS)
VEN = 3.5 V, TJ = 25°C (2) – 28 45 µA
VEN = 3.5 V, TJ = 150°C – 35 55 µA
EN Pulldown Resistance REN – 650 – kΩ
EN DEGLITCH
Enable Filter/Deglitch Time tdEN(FILT) 10 20 30 µs
EN SHUTDOWN DELAY
Shutdown Delay tdOFF
Measured from the falling edge of EN to the time
when LX stops switching 28 32 36 µs
FSET/SYNC INPUT
FSET/SYNC Pin Voltage VFSET/SYNC No external SYNC signal – 640 – mV
FSET/SYNC Open Circuit
(Undercurrent) Detection Time
[2] VFSET/SYNC(UC)
PWM switching frequency becomes 1 MHz upon
detection – 3 – µs
FSET/SYNC Short Circuit
(Overcurrent) Detection Time
[2] VFSET/SYNC(OC) PWM switching frequency can rise up to 3.2 MHzTYP – 3 – µs
Sync High Threshold
[2] VSYNCVIH VSYNC rising – – 2.0 V
Sync Low Threshold
[2] VSYNCVIL VSYNC falling 0.5 – – V
Sync Input Duty Cycle DCSYNC – – 80 %
Sync Input Pulse Width twSYNC 200 – – ns
Sync Input Transition Times
[2] ttSYNC – 10 15 ns
VFB THRESHOLDS
NPOR VFB Overvoltage Threshold VFBNPOROV(H) VFB rising, PWM disabled, NPOR pulled low 840 890 930 mV
NPOR VFB Overvoltage Hysteresis VFBNPOROV(HYS) – 10 – mV
VFB Overvoltage Threshold VFBOV High-side FET off, LG turns high, NPOR remains high – 840 – mV
NPOR VFB Undervoltage Thresholds VFBNPORUV(H) VFB rising – 750 – mV
VFBNPORUV(L) VFB falling 720 740 760 mV
NPOR VFB Undervoltage Hysteresis VFBNPORUV(HYS) VFBNPORUV(H) – VFBNPORUV(L) – 10 – mV
UNDERVOLTAGE/OVERVOLTAGE FILTERING/DEGLITCH
Undervoltage Filter/Deglitch Times tdUV(FILT) 20 30 40 µs
Overvoltage Filter/Deglitch Times tdOV(FILT) 20 30 40 µs
NPOR OUTPUT
NPOR Rising Delay tdNPOR Time from output in regulation to NPOR rising edge – 2.1 – ms
NPOR Low Output Voltage VNPOR(L) EN High, VIN ≥ 3 V, INPOR = 4 mA – 150 400 mV
NPOR Leakage Current INPOR(LKG) VNPOR = 5 V – – 2 µA
[1] For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin
(sinking).
[2] Ensured by design and characterization, not production tested.
[3] Threshold is adjustable following the equation RNG (kΩ) / 1.844 (V).
ELECTRICAL CHARACTERISTICS (continued): Valid at 3 V ≤ VIN ≤ 36 V and VIN having first reached VINSTART,
‒40°C ≤ TJ ≤ 150°C, unless noted otherwise
v uvLo (V)
ALLEGRO"
mlcrosystems
Buck-Boost Controller with Integrated Buck MOSFET
A4450
9
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
TYPICAL PERFORMANCE CHARACTERISTICS
Reference Voltage versus Temperature Switching Frequency fOSC versus Temperature
VIN UVLO START and STOP Thresholds versus
Temperature
Quiescent Current IQ versus Temperature
NPOR VFB Overvoltage and Undervoltage versus
Temperature
EN Rising and Falling Threshold versus Temperature
0.788
0.792
0.796
0.8
0.804
0.808
0.812
-50 -25 0 25 50 75 100 125 150
VREF (V)
Temperature (°C)
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
-50 -25 0 25 50 75 100 125 150
Frequency (MHz)
Temperature (°C)
RFSET = 7.87 kΩ
RFSET = 41.2 kΩ
2
2.25
2.5
2.75
3
3.25
3.5
3.75
4
4.25
4.5
4.75
-50 -25 0 25 50 75 100 125 150
V
IN
UVLO (V)
Temperature (°C)
VIN UVLO Start
VIN UVLO Stop
700
725
750
775
800
825
850
875
900
925
-50 -25 0 25 50 75 100 125 150
NPOR VFB (mV)
Temperature (°C)
OV Rising
OV Falling
UV Rising
UV Falling
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
2.1
2.2
-50 -25 0 25 50 75 100 125 150
EN Threshold (V)
Temperature (°C)
Rising
Falling
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
-50 -25 0 25 50 75 100 125 150
IQ(mA)
Temperature (°C)
Buck-Boost Controller with Integrated Buck MOSFET
A4450
10
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
VIN Transient Response: 18 to 4 V at 0.5 A Load for
5 VOUT, 2 MHz design example
VIN Transient Response: 4 to 18 V at 0.5 A Load for
5 VOUT, 2 MHz design example
Transient Response 0 to 0.5 A Load Step at VIN = 5 V for
5 VOUT, 2 MHz design example
Transient Response 0.5 to 1 A Load Step at VIN = 5 V for
5 VOUT, 2 MHz design example
Transient Response 0 to 0.5 A Load Step at VIN = 12 V
for 5 VOUT, 2 MHz design example
Transient Response 0.5 to 1 A Load Step at VIN = 12 V
for 5 VOUT, 2 MHz design example
(100 µs/div)
100 mV/div
VOUT = 5.0 V
VIN = 4 to 18 V
(100 µs/div)
100 mV/div
VOUT = 5.0 V
VIN = 18 to 4 V
(100 µs/div)
100 mV/div
VOUT = 5.0 V
IOUT
500 mA/div
50 mA/µs
(100 µs/div)
100 mV/div
VOUT = 5.0 V
IOUT
500 mA/div
50 mA/µs
(100 µs/div)
100 mV/div
VOUT = 5.0 V
IOUT
500 mA/div
50 mA/µs
(100 µs/div)
100 mV/div
VOUT = 5.0 V
IOUT
500 mA/div
50 mA/µs
mxcrosystems
‘ LLEGRO'
Buck-Boost Controller with Integrated Buck MOSFET
A4450
11
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
FUNCTIONAL DESCRIPTION
Overview
The A4450 features all the necessary functions to implement an
efficient buck or buck-boost regulation to convert automobile
battery voltage into a tightly regulated voltage. The regulator can
smoothly switch between Buck mode operation and Buck-Boost
mode operation, allowing the operation with input voltage greater
than or less than the output voltage. The A4450 integrates low
RDSON high-side N-MOSFET as a controlled buck switch. The
A4450 provides a gate driver output for the external boost switch.
As shown in Figure 1, the configuration of typical buck-boost
regulator consists of an external freewheeling Schottky diode
dictated as buck diode, another Schottky diode dictated as boost
diode, an external MOSFET as boost switch, inductor, and output
capacitor. The A4450 can provide regulated output up to 2 A DC
load. The A4450 employs peak current-mode control to provide
superior line and load regulation, pulse-by-pulse current limit,
fast transient response, and simple compensation.
The A4450 features include a transconductance error amplifier
for external compensation network, an enable input (EN), exter-
nally set soft-start time, a SYNC/FSET input to set PWM switch-
ing frequency or synchronize to external clock, an output voltage
range set pin (RNG), a Power-On Reset output (NPOR) pin, and
frequency dithering. Protection features of the A4450 include VIN
undervoltage lockout, pulse-by-pulse overcurrent protections in
Buck-Boost and Buck modes, BOOT capacitor protection, two
levels output overvoltage protection, hiccup mode short-circuit
protection, LX short-circuit protection, missing buck diode pro-
tection, and thermal shutdown. In addition, the A4450 provides
open-circuit, adjacent pin short-circuit, and pin-to-ground short-
circuit protection at every pin.
The A4450 is available in industry-standard QFN-20 package.
VOUT
VIN
Buck
Diode
Boost
Diode
Q1
Buck
Switch
Boost
Switch
Q2
LX
LG
A4450
Figure 1: Basic Buck-Boost Regulator Configuration
Operation Modes
A buck-boost regulator can regulate the output voltage with input
voltage greater than or less than the output voltage. However, the
buck-boost regulator is not as efficient as the buck regulator. The
A4450 is designed as a dual mode controller to resolve this chal-
lenge so that the regulator can operate efficiently under the Buck
mode when the input voltage is greater than the output voltage.
Figure 1 shows the basic buck-boost regulator configuration with
dual mode controller A4450.
BUCK MODE
In case the input voltage is high compared to the output voltage,
the regulator will enter Buck mode: buck switch Q1 turns on and
off with duty cycle, DBuck, to maintain regulation while boost
switch Q2 is off, according to the following equation:
VOUT = DBuck × VIN (1)
where DBuck is the duty cycle of buck switch.
BUCK-BOOST MODE
When the input voltage decreases toward to the output voltage,
the duty cycle of the buck switch Q1 will increase to maintain
regulation. At the same time, once the programmed boost switch
duty cycle, DBoost (shown in the equation below), is greater
than 0, the boost switch starts to turn on and off with duty cycle
DBoost. The regulator then enters Buck-Boost mode.
The boost switch duty cycle is determined by the equation below:
DBoost = max VIN × 1.844
RNG
)
0,1 –
(
(2)
where VIN is in Volts (V) and RNG (kΩ) is the resistor connected
between RNG pin and GND.
The Range resistor RNG (kΩ) programs the targeted output volt-
age, VOUT, following the equation below:
RNG = VOUT (V) × 1.844
DBUCK0
(3)
where DBUCK0 is the preferred buck duty cycle at the instant that
the boost switch starts to switch, typically set between 0.60 and
0.65.
‘ LLEGRO'
mxcrosystems
Buck-Boost Controller with Integrated Buck MOSFET
A4450
12
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Under the Buck-Boost mode operation, the buck switch duty
cycle, DBuck, is controlled through the feedback network to regu-
late VOUT, as shown in the equation below:
VOUT = DBuck / (1 – DBoost) × VIN (4)
This dual mode controller of A4450 enables smooth transition
between Buck and Buck-Boost mode over a wide range of input
voltages to maintain the regulation of output voltages.
Take as an example, VOUT = 5 V buck-boost regulator, setting
DBUCK0 = 0.61 results in RNG = 15 kΩ from equation 4. As
shown in Figure 2, when VIN is greater than ~8.5 V, the regulator
is in Buck mode and the duty cycle of Boost switch is 0; when
VIN is less than ~8.5 V, the regulator enters is in Buck-Boost
mode with both switches turning on and off. It is recommended
that the duty cycle of the buck switch should be larger than that
of the boost switch for efficient operation.
0.00
0.20
0.40
0.60
0.80
3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0
Duty Cycle
VIN (V)
Duty_Boost
Duty_Buck
Figure 2: Duty Cycles of Boost and Buck Switches vs
VIN for example above with VOUT = 5 V, RNG = 15 kΩ
Reference Voltage
The A4450 incorporates an internal precision reference at 0.8 V
(VREF) as the reference of the output voltage feedback divider.
The output voltage of the regulator is then programmed with a
resistor divider between VOUT and the FB pin of the A4450. After
VOUT is set, RNG resistor can be selected based on equation 3.
The accuracy of the internal reference is ±1.5% across a –40°C to
150°C temperature range.
Oscillator/Switching Frequency and Synchronization
The PWM switching frequency of the A4450 is adjustable from
250 kHz to 2.2 MHz and has an accuracy of about ±10% over the
operating temperature range. A resistor, RFSET, connected from
the FSET/SYNC pin to GND, sets the switching frequency. An
FSET/SYNC resistor with ±1% tolerance is recommended. A
graph of switching frequency versus FSET/SYNC resistor value
is shown in the Component Selection section of this datasheet.
The FSET/SYNC pin can also be used as a synchronization input
that accepts an external clock to switch the A4450 from 250 kHz
to 2.4 MHz; the slope compensation will be scaled according to
the applied synchronization frequency. When used as a synchro-
nization input, the applied clock pulses must satisfy the pulse-
width duty-cycle requirements shown in the Electrical Character-
istics table of this datasheet.
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Frequency Dithering
The A4450 adopts a frequency dithering technique to help reduce
EMI/EMC for demanding automotive applications. The A4450
implements the linear triangular dithering of the PWM frequency,
spreading the energy above and below the base frequency set
by RFSET. A typical fixed-frequency PWM regulator will cre-
ate distinct “spikes” of energy at fOSC, and at higher frequency
multiples of fOSC. Conversely, the A4450 spreads the spectrum
around fOSC, thus creating a lower magnitude at any comparative
frequency. Frequency dithering is disabled if FSET/SYNC pin is
used for external synchronization.
Frequency dithering of A4450 only applies in Buck mode—there
is no frequency dithering in Buck-Boost mode. Therefore, when
VIN rises from low level to be above the VIN Dithering Start
Threshold (see EC table), frequency dithering will be activated
where the A4450 enters into Buck mode from Buck-Boost mode.
This VIN Dithering Start Threshold is approximately equal to
RNG (kΩ) / 1.844 V.
If VIN continues to rise and exceeds the VIN Dithering Stop
Threshold at 18 V (typical), frequency dithering will be disabled.
Then if VIN starts to fall, frequency dithering will resume again
when VIN goes below 16.6 V (typical). When VIN continues to
drop below the VIN Dithering Stop Threshold (VIN falling) to
trigger the Buck-Boost mode operation, then frequency dithering
is disabled. The VIN Dithering Stop Threshold is approximately
equal to RNG (kΩ) / 1.844 V.
Refer to Figure 3 and Figure 4 and the PWM Switching Fre-
quency and Dithering specifications in Electrical Characteristics
table.
Dithering
No Dithering
18 V
Buck
Mode
Rising
VIN(DITHER,ON)*
Figure 3: VIN Rising Dithering Threshold
Dithering
No Dithering
Falling
V
16.6 V
Buck
Mode
VIN
IN(DITHER,OFF)*
Figure 4: VIN Falling Dithering Threshold,
where threshold is adjustable following the equation
RNG (kΩ) / 1.844 (V)
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Transconductance Error Amplifier and
Compensation Network
The transconductance error amplifier primary function is to
control the regulator output voltage. It has three-terminal inputs
with two positive inputs and one negative input (as shown in
Figure 5). The negative input is connected to the FB pin to sense
the feedback output voltage for regulation. The two positive
inputs are used for soft-start and steady-state regulation. The
error amplifier regulates to the lower value of those two positive
inputs. The error amplifier regulates the FB voltage according to
the soft-start voltage minus Soft-Start Offset during startup; when
the soft-start voltage minus Soft-Start Offset exceeds the internal
0.8 V reference, the error amplifier then “switches over” and
regulates the FB voltage to the 0.8 V reference voltage.
-
+
+
+
-
VREF 800 mV
+
Error Amp
400 mV
COMP
FB
SS
Soft-Start Offset
Figure 5: Error Amplifier
To stabilize the regulator, a series RC compensation network
(RZ and CZ) must be connected from the error amplifier output
(the COMP pin) to GND, as shown in the Typical Application
Diagram. In most instances, an additional relatively low-value
capacitor (CP) should be connected in parallel with the RZ-CZ
components to reduce the loop gain at very high frequencies.
However, if the CP capacitor is too large, the phase margin of the
converter can be reduced. A general guideline about how to select
RZ, CZ, and CP is provided in the Component Selection section of
this datasheet.
If a fault occurs or the regulator is disabled, the COMP pin is
pulled to GND via approximately 4.5 kΩ and the switching is
inhibited.
Slope Compensation
The A4450 incorporates internal slope compensation to allow
PWM duty cycles above 50% for a wide range of input/output
voltages, switching frequencies, and inductor values. The slope
compensation signal of the A4450 is actually subtracted from
COMP signal, equivalently being added into the current sense
signal. The amount of slope compensation is scaled with the
switching frequency when programming the frequency with a
resistor or with an external clock.
The value of the output inductor should be chosen such that slope
compensation rate, SE, is theoretically at least greater than half
the falling slope of the inductor current (SF). Because the A4450
will work in the Buck-Boost mode, a larger compensation slope
is preferred; refer to Output Inductor section for details.
Enable Input (EN)
An enable pin is available on the A4450. When this pin is low,
the A4450 is shut down and enters a “sleep mode”, where the
internal control circuits will be shut off and draw less current
from VIN. If EN goes high, the A4450 will turn on, and provided
there are no fault conditions, soft-start will be initiated and VOUT
will ramp to its final voltage in a time set by the soft-start capaci-
tor (CSS). To automatically enable the A4450, the EN pin may be
connected to VIN through a current-limiting resistor (1 ~10 kΩ).
For transient suppression, it is recommended that a 0.1 to 0.22 µF
capacitor is placed after the series resistor to form a low-pass
filter before the EN pin. Larger external resistance is needed if
EN signal rings below GND significantly.
Integrated Buck MOSFET
The A4450 integrates an 80 mΩTYP high-side N-channel MOS-
FET as the buck switch.
Current Sense Amplifier
The A4450 incorporates a high-bandwidth current sense amplifier
to monitor the current through the high-side MOSFET. This cur-
rent signal is used to regulate the peak current when the high-side
MOSFET is turned on. The current signal is also used by the pro-
tection circuitry for the pulse-by-pulse current limit and hiccup
mode short-circuit protection.
R (m;
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Pulse-Width Modulation (PWM) Mode
The A4450 employs peak current-mode control to provide excel-
lent load and line regulation, fast transient response, and simple
compensation.
A high-speed comparator and control logic is included in the
A4450. The inverting input of the PWM comparator is the sub-
traction of the slope compensation signal from the output of the
error amplifier. The noninverting input is connected to the sum
of the current sense signal, and a DC PWM Ramp offset voltage
(VPWMOFFS).
At the beginning of each PWM cycle, the CLK signal sets the
PWM flip-flop and the high-side buck switch is turned on. When
the voltage at the noninverting of the PWM comparator rises
above the error amplifier output, COMP, the PWM flip-flop is
reset and the high-side buck switch is turned off.
In the A4450, the duty cycle of the buck switch is controlled to
regulate the output voltage, regardless of Buck-Boost or Buck
mode. This makes control loop analysis easy, and facilitates the
compensation to design a stable system without the right-half-
plane zero introduced.
As illustrated in Figure 6, in Buck-Boost mode, both Q1 and Q2
are turned on at the beginning of each PWM cycle; Q2 operates
with the programmed duty cycle, DBoost:
DBoost = 1 – VIN (V)× 1.844
RNG (kΩ)
(5)
and the buck switch Q1 is controlled by the PWM comparator to
regulate the output voltage with the duty cycle, DBuck:
DBuck = (VOUT / VIN) × (1 – DBoost) (6)
In Buck mode, the boost switch (Q2) is off and the buck switch
(Q1) is active.
VOUT
VIN
Buck
Diode
Boost
Diode
Q1
Buck
Switch
Boost
Switch
Q2
Figure 6: Buck-Boost Regulator
When VIN rises above 18 V, the A4450 starts to linearly fold-
back the PWM switching frequency, fSW, based on VIN, from the
original frequency, fSWO, before foldback, up to about half fSWO
at 36 V. In this way, the on-time of the buck switch is relatively
extended to ensure the duty cycle regulation is within control.
The test results illustrate the foldback behavior of switching fre-
quency fSW versus VIN, in Figure 7 (where switching frequency
fSW is normalized to the original switching frequency fSWO before
foldback).
0.40
0.50
0.60
0.70
0.80
0.90
1.00
1.10
4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36
Normalized Frequency fSW /fSWO
VIN (V)
Figure 7: Normalized Switching Frequency
fSW/fSWO Foldback vs. VIN
BOOT Regulator
The A4450 includes an internal regulator to charge its boot
capacitor. The voltage across the boot capacitor is typically
5 V, which provides voltage for the gate drivers of the buck
switch and the boost switch. A 7 Ω bottom MOSFET is also also
integrated, which is turned on during minimum off-time to help
ensure the boot capacitor is always charged. When VIN is below
5 V, to ensure sufficient gate voltage, it is recommended to add an
external boot diode, which is connected to a 5 V supply, as shown
in Figure 8.
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LX
BOOT
LX
VOUT
CBOOT
D1
LO
0.22 µF
Buck Diode
5 V
A4450
Extra Boot Diode
recommended for VIN < 5 V
Figure 8: Extra Boot Diode Suggested for VIN < 5 V
If the boot capacitor is missing or shorted, the A4450 will detect
such a fault and enter hiccup mode. Also, the boot regulator has a
current limit to protect itself during a short-circuit condition.
Soft-Start (Startup) and Inrush Current Control
The soft-start function controls the inrush current at startup. The
soft-start pin, SS, is connected to GND via a capacitor. When
the A4450 is enabled and all faults are cleared, the soft-start pin
will source the charging current and the voltage on the soft-start
capacitor CSS will ramp upward from 0 V. When the voltage at
the soft-start pin exceeds the Soft-Start Offset (typical 0.4 V), the
error amplifier will ramp up its output voltage above the PWM
Ramp Offset. At that instant, PWM switching begins.
Once the A4450 begins PWM switching, the error amplifier
will regulate the voltage at the FB pin to the soft-start pin volt-
age minus the Soft-Start Offset. During the active portion of
soft-start, the regulator output voltage will rise from 0 V to the
targeted output voltage.
When the voltage of the soft-start pin minus the Soft-Start Offset
is greater than 0.8 V, the error amplifier will start to regulate the
voltage at the FB pin to the A4450 reference voltage, 800 mV.
The voltage at the soft-start pin will continue to rise to the inter-
nal LDO regulator output voltage.
During normal startup, the PWM switching frequency is linearly
scaled from 0.12 × fOSC to fOSC (depending on the FB voltage
level) as the voltage at the FB pin ramps from 0 to 800 mV (see
the details in the Electrical Characteristics table). Note if the
theoretically scaled switching frequencies are less than 100 kHz,
then 100 kHz frequency will take over. The scaled scheme is
implemented to prevent the output inductor current from climb-
ing to a level that may damage the A4450 regulator when the
input voltage is high and the output of the regulator is either
shorted or soft-starting a relatively high capacitance or very
heavy load. However, during Overcurrent Protection or Hiccup
mode, the soft-start PWM switching frequencies will become half
of the corresponding linear foldback frequencies during normal
startup.
If the A4450 is disabled or a fault occurs, the internal fault latch
is set and the capacitor at the SS pin is discharged to ground very
quickly through a 2 kΩ pull-down resistor. The A4450 will clear
the internal fault latch when the voltage at the SS pin decays to
approximately 200 mV. However, if the A4450 enters Hiccup
mode, the capacitor at the SS pin is slowly discharged through
10 µA sink current. Therefore, the soft-start capacitor CSS not
only controls the startup time but also the time between soft-start
attempts in Hiccup mode.
Pre-Biased Startup
If the output of the regulator is pre-biased at a certain output
voltage level, the A4450 will modify the normal startup routine
to prevent discharging the output capacitors. As described in the
Soft-Start (Startup) and Inrush Current Control section, the error
amplifier usually becomes active when the voltage at the soft-
start pin exceeds the Soft-Start Offset. If the output is pre-biased,
the voltage at the FB pin will be non-zero, the Boost diode blocks
reverse current from the output, and the A4450 will not start
switching until the voltage at SS pin minus the Soft-Start Offset
rises to approximately VFB. From then on, the error amplifier
becomes active, the voltage at the COMP pin rises, PWM switch-
ing starts, and the output voltage will ramp upward from the
pre-bias level.
Not Power-On Reset (NPOR) Output
The A4450 has an inverted Power-On Reset Output (NPOR) with
a fixed delay of its rising edge (tdNPOR). The NPOR output is an
open-drain output, so an external pull-up resistor must be used, as
shown in the Typical Application Diagram. NPOR transitions high
when the output voltage, sensed at the FB pin, is within regulation.
The NPOR output is immediately pulled low if either a NPOR
VFB Overvoltage or Undervoltage condition occurs, or the A4450
junction temperature exceeds the thermal shutdown threshold
(TSD). For other faults, NPOR depends on the output voltage.
At power-up, NPOR must be initialized (set to a logic low) when
VIN is relatively low. At power-down, NPOR must be held in the
logic-low state as long as possible.
m mm M
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Protection Features
The A4450 was designed to satisfy the most demanding automo-
tive and nonautomotive applications. In this section, a description
of protection features is provided.
UNDERVOLTAGE LOCKOUT PROTECTION (UVLO)
An Undervoltage Lockout (UVLO) comparator in the A4450
monitors VIN at the VIN pin and keeps the regulator disabled
either if the voltage is below the start threshold, VINSTART, while
VIN is rising, or if VIN is below the stop threshold, VINSTOP,
while VIN is falling in Buck-Boost mode. The UVLO comparator
incorporates some hysteresis to help reduce on/off cycling of the
regulator due to the resistive or inductive drops in the VIN path
during heavy loading or during startup.
OVERCURRENT PROTECTION (OCP)
The A4450 monitors the current through the high-side MOSFET. If
this current exceeds the LX Short-Circuit Current Limit, ILIM(LX),
for example when LX is hard short to ground (note: high VIN
triggers a hard short condition more easily than low VIN case), the
high-side MOSFET will be turned off and the regulator stays in the
latched-off status unless the regulator is reset. If this current is less
than ILIM(LX) but above the pulse-by-pulse current limit ILIM(Buck)
while in Buck mode or ILIM(BuckBoost) while in Buck-Boost mode,
the A4450 will enter into Hiccup mode. The A4450 includes
leading-edge blanking to prevent false triggering the overcurrent
protection when the high-side MOSFET is turned on.
An OCP (Overcurrent Pulses) counter and hiccup mode circuit
are incorporated to protect the A4450 regulator when the output
of the regulator is shorted to ground or when the load current is
too high.
If VFB is less than 400 mVTYP, the number of overcurrent pulses
is limited to 30; If VFB is greater than 400 mVTYP, the number of
overcurrent pulses is increased to 120 to accommodate the pos-
sibility of starting into a relatively high output capacitance.
If the OCP counter reaches the preset counts, a hiccup latch is
set and the COMP pin is quickly pulled down by a relatively low
resistance.
The hiccup latch also enables a small current sink connected to
the SS pin. This causes the voltage at the soft-start pin to slowly
ramp downward. When the voltage at the soft-start pin decays
to a preset low level, the hiccup latch is cleared and the small
current sink is turned off. At that instant, the SS pin will begin to
source current and the voltage at the SS pin will ramp upward.
This marks the beginning of a new, normal soft-start cycle. When
the voltage at the soft-start pin exceeds the Soft-Start Offset, the
error amplifier will force the voltage at the COMP pin to quickly
slew upward and PWM switching will resume. But the PWM
switching frequencies during the Hiccup SS upward period are
half of the SS PWM Foldback Frequency listed in Electrical
Characteristics table. Figure 9 below shows the Overcurrent Hic-
cup operation.
SS
COMP
OCP*
LX
V
OUT
f
OSC
120×
OCP
# OCP pending
on FB level
V
EAVO(MA X)
t
HIC,RECO VER
1.8 V
0.2 V
# OCP pending
on FB level
f
SW
will be half of SS
frequencies in EC table
Figure 9: Output Short Circuit to Ground Hiccup Operation
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If the short circuit at the regulator output remains, another hic-
cup cycle will occur. Hiccups will repeat until the short circuit
is removed or the converter is disabled. If the short circuit is
removed, the A4450 will soft-start normally and the output volt-
age will automatically recover to the desired level.
Thus Hiccup mode is very effective protection for the overload
condition. It can avoid false trigger for a short term overload. For
the extended overload, the average power dissipation during Hic-
cup operation is very low to keep the controller cool and enhance
reliability.
BOOT CAPACITOR PROTECTION
The A4450 monitors the voltage across the boot capacitor to
detect if the capacitor is missing or short-circuited. If the boot
capacitor is missing, the regulator will enter hiccup mode after
approximate 14 PWM cycles. If the boot capacitor is shorted to
GND, Boot Undervoltage protection will be triggered and the
regulator will enter Hiccup mode after about 32 PWM cycles.
For a boot fault, hiccup mode will operate virtually the same as
described previously for an output short-circuit fault (OCP), with
SS ramping up and down as a timer to initiate repeated soft-start
attempts. Boot faults are nonlatched conditions, so the A4450
will automatically recover when the fault is corrected.
PROTECTION OF BUCK DIODE AT LX NODE
If the buck diode at LX node is missing or damaged (open), the
LX node will be subject to unusually high negative voltages. These
negative voltages may cause the A4450 to malfunction and could
lead to damage. When the buck diode is missing, the internal ESD
diode will carry most of the freewheeling current and will cause
thermal shutdown. Also if this diode is shorted, which is hard short
of LX to ground, as described in Overcurrent Protection section,
the high-side MOSFET will be turned off and the regulator will
stay in latched-off status unless the regulator is reset.
OVERVOLTAGE PROTECTION (OVP)
The A4450 includes two levels of overvoltage comparators
that monitor the FB pin voltage, VFB. When rising VFB first
exceeds 840 mV (typical, i.e. VFBOV
, 105% of 800 mV VREF),
the high-side buck switch turns off and the boost gate driver LG
turns high, but NPOR still remains high. In this way, the further
buildup of output current is inhibited so that it cannot charge the
output capacitors further. If VFB keeps rising and exceeds the
second overvoltage threshold (VFBNPOROV(H), 110% of VREF),
NPOR will be pulled low, the high-side buck switch remains off,
and the boost gate driver LG remains high. If the duration of the
overvoltage condition is less than OV Deglitch Times, tdOV(FILT)
(30 µsTYP), no OV protection event is triggered. When VFB drops
below NPOR VFB UV Thresholds specified in Electrical Char-
acteristics table, an NPOR Undervoltage fault is triggered and
NPOR will be pulled low.
The error amplifier and its regulation voltage clamp are not
effective when the FB pin is disconnected. When the FB pin is
disconnected from the feedback resistor divider, a tiny internal
current source will force the voltage at the FB pin to rise above
the OV threshold and disables the regulator, preventing the load
from being significantly over voltage. If the conditions causing
the overvoltage are corrected, the regulator will automatically
recover.
Figure 10 below shows a timing diagram of UV/OV conditions
with respect to NPOR (refer to Electrical Characteristics table).
FB
NPOR
V
FBNPOROV(H)
V
FBNPOROV(L)
t
dOV(FILT)
t
dNPOR
t
dNPOR
t
dUV(FILT)
V
FBNPORUV(L)
V
FBNPORUV(H)
Figure 10: UV/OV Delay Timing Diagram (not scaled)
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THERMAL SHUTDOWN (TSD)
The A4450 protects itself from overheating by monitoring its
junction temperature. If the junction temperature exceeds the
Thermal Shutdown Threshold (TTSD, 170°CTYP), the A4450 will
stop PWM switching and pull NPOR low. TSD is a non-latched
fault, so the A4450 will automatically recover if the junction
temperature decreases by approximately 20°C from TTSD.
PIN-TO-GROUND AND PIN-TO-PIN SHORT PROTECTIONS
The A4450 was designed to satisfy the most demanding automo-
tive and nonautomotive applications. For example, the A4450
was carefully designed “up front” to withstand a short circuit to
ground at each pin without suffering damage.
In addition, care was taken when defining the A4450’s pinout
to optimize protection against pin-to-pin adjacent short circuits.
For example, logic pins and high-voltage pins were separated as
much as possible. Inevitably, some low-voltage pins were located
adjacent to high-voltage pins. In these instances, the low-voltage
pins were designed to withstand increased voltages, with clamps
and/or series input resistance, to prevent damage to the A4450.
D
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Setting the Output Voltage
The output voltage of the regulator is determined by a resistor
divider from the output node (VOUT) to the FB pin as shown in
Figure 11. There are tradeoffs when choosing the value of the
feedback resistors. If the series combination (RFB1 + RFB2) is
too low, then the light load efficiency of the regulator will be
reduced. To maximize efficiency, it’s best to choose higher values
of resistors. If the parallel combination (RFB1//RFB2) is too high,
then the regulator may be susceptible to noise coupling onto the
FB pin. 1% resistors are recommended to maintain the output
voltage accuracy.
R
FB1
R
FB2
FB
<<
V
OUT
Figure 11: Connecting a Feedback Divider to
Set the Output Voltage
The feedback resistors must satisfy the ratio shown in equation
below to produce a desired output voltage, VOUT.
VOUT
0.8 V (7)
RFB1
RFB2
=– 1
After the output voltage is set, the range resistor RNG (kΩ) at
RNG pin can be calculated from equation 3 found under Opera-
tion Modes in the Functional Description section, repeated
below:
RNG = VOUT (V) × 1.844
DBUCK0
(3)
where DBUCK0 is the preferred buck duty cycle at the instant
when the boost switch starts to switch, typically set at around 0.6
to 0.65.
DESIGN AND COMPONENT SELECTION
PWM Switching Frequency (fSW, RFSET)
The desired switching frequency (fSW) can be set with a resistor
RFSET connected at pin FSET/SYNC to the ground. The recom-
mended RFSET value for various switching frequencies fSW can be
obtained from either Table 1 or Figure 12:
0
500
1000
1500
2000
2500
3000
0 10 20 30 40 50 60 70 80 90
R
FSET
(kΩ)
fSW (kHz)
Figure 12: PWM Switching Frequency fSW versus RFSET
Table 1: fSW versus RFSET
fSW (kHz) RFSET (kΩ)
2500 6.04
2300 6.81
2000 7.87
1500 10.0
1250 12.7
1000 15.8
800 20.0
600 26.7
400 41.2
300 53.6
V
I.w.11 I
V ‘Xf XL
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Output Inductor (LO)
For the peak current-mode control, the priority to consider when
selecting the inductor is to prevent the subharmonic oscillations
when the duty cycle is near or above 50%. To prevent the subhar-
monic oscillations, the theorectical slope compensation ramp SE
should be at least 50% of the down slope of the inductor current.
In the A4450, the inductor value LO is suggested to start with the
equation below, because A4450 will also operate in Buck-Boost
mode:
0.5 × VOUT
SE
(8)
VOUT – VIN(MIN)
SE
,
LO ≥ 1.5 × max
( )
where VOUT is the output voltage, VIN(MIN) is the minimum input
voltage, SE is in A/µs, which scales with the switching frequency
and can be estimated by interpolating from Electrical Characteris-
tics table, and LO is in µH.
Ideally, the inductor should not saturate at the highest pulse-by-
pulse current limit. This may be too costly. At the very least, the
inductor should not saturate at the peak operating current.
In Buck-Boost mode, the peak inductor current is calculated as:
ΔIL
2
(9)
IOUT +
1 – DBOOST(MAX)
IPEAK =
× (1 – DBuck)
where
VIN(MIN) × DBoost(MAX)
fSW × LO
ΔIL = max ,VIN(MIN) × DBoost(MAX)
fSW × LO
{
VIN(MIN) – VOUT
fSW × LO
+ × (DBuck – DBoost(MAX))
}
DBoost(MAX) = 1 – VIN(MIN) × 1.844
RNG
DBuck(MAX) = (1 – DBoost(MAX)) × VOUT
VIN(MIN)
In Buck mode, the peak inductor current is:
ΔIL
2(10)IPEAK = IOUT +
where
VOUT × (VIN(MAX) – VOUT )
VIN(MAX) × fSW × LO
ΔIL =
After an inductor is chosen, it should be tested during output
short-circuit conditions. The inductor current should be moni-
tored using a current probe. A good design should ensure neither
the inductor nor the regulator are damaged when the output is
shorted to ground at the highest expected ambient temperature.
Buck Diode (D1) and Boost Diode (D2)
Schottky diodes with proper ratings should be chosen for the
buck diode (D1) and boost diode (D2), because of their low
forward voltage drop and fast reverse recovery time. The key
parameters in D1 and D2 selection are the average forward current
If(AVG) and the DC reverse voltage.
The boost diode D2 should be greater than VOUT with some
margin. The average forward current rating of the boost diode
should be above the full load current, and the peak current should
be above the peak inductor current which is calculated in previous
Output Inductor section.
The buck diode D1 must be able to withstand the input voltage
when the high-side buck switch is on. Therefore, the reverse
voltage rating should be greater than the maximum expected VIN
with some margin.
When the buck switch is off, the buck diode D1 must conduct the
output current. The average forward current rating of the buck
diode should be above the full load current.
rwaV
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VD main )
ALLEGRO'
mxcrosystems
Buck-Boost Controller with Integrated Buck MOSFET
A4450
22
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
External Boost Switch
The A4450 requires a N-channel MOSFET as the external boost
switch to form the buck-boost configuration. A suitable boost
switch should have low gate charge, small on-resistance, break-
down voltage greater than VOUT, and maximum gate driver
voltage greater than 8 V. The maximum current IDS(MAX) should
be larger than the peak inductor current calculated in Output
Inductor section. STL10N3LLH5 from STMicroelectronics and
NVTFS4823N from ON Semiconductor are good examples.
A 10 kΩTYP resistor must be added at LG pin to ground to avoid
false turn-on from coupling noise.
Output Capacitors
In Buck-Boost mode, the output capacitors must supply the entire
output current when the boost switch is on. The output capacitors
are chosen based on the Buck-Boost mode instead of the Buck
mode where the demand is much less when the application runs
through both operation modes.
The output capacitance in Buck-Boost mode is selected to limit
the output voltage ripple to meet the specification requirement,
and is calculated according to the equation below for the given
output ripple voltage ΔVOUT:
(11)
IOUT × DBoost(MAX)
fSW × ΔVOUT
COUT(MIN) =
where
DBoost(MAX) = 1 – VIN(MIN) (V) × 1.844
RNG (kΩ)
The voltage rating of the output capacitors must support the out-
put voltage with sufficient design margin.
In Buck-Boost mode, the output voltage ripple (ΔVOUT) is
mainly due to the voltage drop across the ESR of output capaci-
tors, ESRCO, and the ESR requirements can be obtained from:
(12)
ΔVOUT
IOUT
ESRCO =
The ESR requirement can usually be met by simply using mul-
tiple capacitors in parallel or by using higher quality capacitors.
Ceramic capacitors have good ESR characteristics and are good
choices for output capacitors. It should be noted that the effective
capacitance of the ceramic capacitors decrease due to the DC
bias effect.
For larger bulk values of capacitance, a high quality low ESR
electrolytic output capacitor can be used; however, electrolytic
capacitors have poor tolerance, especially over temperature. The
ESR of electrolytic capacitors usually increases significantly at
cold ambients, as much as 10×, which increases the output volt-
age ripple and, in most cases, reduces the stability of the system.
The transient response of the regulator depends on the number
and type of output capacitors. In general, minimizing the ESR of
the output capacitance will result in a better transient response. At
the instant of a fast load transient (di/dt), the output voltage will
change by the amount:
ΔVOUT=ΔILOAD × ESRCO + di/dt × ESLCO (13)
After the load transient occurs, the output voltage will deviate
from its nominal value for a short time. This time will depend on
the system bandwidth, the output inductor value, and the output
capacitance. Eventually, the error amplifier will bring the output
voltage back to its nominal value.
A higher bandwidth usually results in a shorter time to return to
the nominal voltage. However, with a higher bandwidth system
it may be more difficult to obtain acceptable gain and phase
margins.
Input Capacitors
Selection of input capacitors should meet these three require-
ments: first, they must support the maximum expected input
surge voltage with adequate design margin; second, the capaci-
tor’s RMS current rating must be higher than the expected RMS
input current to the regulator; third, they must have enough
capacitance and a low enough ESR to limit the input voltage
deviation to something much less than the VIN UVLO hysteresis
at maximum loading and minimum input voltage.
The RMS current of the input capacitors depends on the opera-
tion mode. During the Buck mode, the input capacitors must
deliver the RMS current according to:
(14)
DBuck × (1 – DBuck )IRMS = IOUT ×
where DBuck is the duty cycle of Buck switch.
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A4450
23
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
The DBuck × (1 – DBuck) term in equation 14 above has an abso-
lute maximum value of 0.25 at 50% duty cycle.
During Buck-Boost mode, the RMS current of input capacitors is:
(15)
DBuck × (1 – DBuck )IRMS = IOUT
1 – DBoost
×
Thus the RMS currents of both operation modes should be
checked to ensure the input capacitors are able to handle the
larger ripple current of the two.
The input capacitor(s) must limit the voltage deviations at the
VIN pin to a value significantly less than UVLO hysteresis dur-
ing maximum load and minimum input voltage. For Buck opera-
tion mode, the minimum input capacitance can be calculated as
follows:
CIN ≥
(16)
I× DBuck × (1 – DBuck )
OUT
0.85 × fSW × ΔVIN(MIN)
For Buck-Boost mode, the required minimum input capacitance
becomes:
CIN ≥
(17)
I× DBuck × (1 – DBuck )
OUT
(1 – DBoost ) × 0.85 × fSW × ΔVIN(MIN)
where ΔVIN(MIN) is chosen to be much less than the hysteresis
of the VIN UVLO comparator (ΔVIN(MIN) ≤ 150 mV is recom-
mended), and fSW is the nominal PWM frequency.
A good design should consider the DC bias effect on a ceramic
capacitor: as the applied voltage approaches the rated value, the
capacitance value decreases. This effect is very pronounced with
the Y5V and Z5U temperature characteristic devices (as much as
90% reduction) so these types should be avoided. The X7R type
capacitors should be the primary choices due to their stability
versus both DC bias and temperature.
For all ceramic capacitors, the DC bias effect is even more
pronounced on smaller case sizes, so a good design will use the
largest affordable case size (i.e. 1206 or 1210). Also, it is advis-
able to select input capacitors with plenty of design margin in
voltage rating to accommodate the worst-case transient input
voltage (such as a load dump as high as 40 V for automotive
applications).
Bootstrap Capacitor
A bootstrap capacitor must be connected between the BOOT
and LX pins to provide the gate drives for the buck and boost
switches. A 220 nF, 50 V, X7R ceramic capacitor is recommended
in A4450 applications.
Soft-Start and Hiccup Mode Timing (CSS)
The soft-start time of the A4450 is determined by the value of the
capacitance at the soft-start pin, CSS.
When the A4450 is enabled, the voltage at the soft-start pin will
start from 0 V and will be charged by the soft start current, ISSSU.
However, PWM switching will not begin instantly because the
voltage at the soft-start pin must rise above 400 mV (Soft-Start
Offset). The soft-start delay (tSS(DELAY)) can be calculated using
equation 18:
tSS(DELAY) SS
= C×
(18)
400 mV
ISS(SU)
()
If the A4450 is starting with a very heavy load, a very fast
soft-start time may cause the regulator to exceed the pulse-by-
pulse overcurrent threshold. This occurs because the sum of the
full load current, the inductor ripple current, and the additional
current required to charge the output capacitors (ICO = COUT ×
VOUT
/ tSS) is higher than the pulse-by-pulse current threshold.
To avoid prematurely triggering the pulse-by-pulse current limit, a
larger soft-start capacitance can be used. The soft-start capacitor,
CSS, should be calculated according to equation 19:
CSS ≥
(19)
I× VOUT × COUT
SS(SU)
0.8 V × ICO
where VOUT is the output voltage, COUT is the output capacitance,
ICO is the amount of current allowed to charge the output capaci-
tance during soft-start (recommend 0.1 A < ICO < 1 A). Higher
values of ICO result in faster soft-start times. Howewer, lower
values of ICO ensure that hiccup mode is not falsely triggered. It
is recommended to start the design with an ICO of 0.1 A and to
increase ICO only if the soft-start time is too slow.
The output voltage ramp time, tSS, can be calculated by using
either of the following methods:
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mxcrosystems
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Buck-Boost Controller with Integrated Buck MOSFET
A4450
24
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
or 0.8 V×
COUT
t= V×
SS OUT ICO
(20)
CSS
ISS(SU)
When the A4450 is in hiccup mode, the soft-start capacitor is
used as a timing capacitor and sets the hiccup period. The soft-
start pin charges the soft-start capacitor with ISS(SU) during a
startup attempt and discharges the same capacitor with smaller
current than ISS(SU) between startup attempts. Therefore, the
effective duty cycle will be very low and the junction temperature
will be kept low.
Compensation Components (RZ, CZ, CP)
To compensate the system, it is important to understand the over-
all control loop response in frequency domain. The A4450 simpli-
fied control loop, consisting of power stage and transconductance
error amplifier, is shown in Figure 13 for compensation analysis.
The error amplifier uses a Type II compensation network to
ensure system stability and to optimize transient response with
desirable phase margin and gain margin.
FB
Buck
Diode
Boost
Diode
0.8 V
Boost
Switch
Q2
LX
EA
A4450
RFB1
RFB2
VOUT
RL
ESR
-
+
COUT
RO(EA)
RZ
CZ
CP
COMP
gmEA
gmPOWER
vc
Figure 13: Simplified Overall Current-Mode Control Loop
Figure 14 is a simplified small signal model of the A4450 power
stage. The power stage is approximated as a voltage-controlled
current source to provide current to the load and output capacitor.
Because the duty cycle of boost switch Q2 is programmed with
RNG resistor at pin RNG and the inductor provides current to the
output only during off-time of Q2, the transconductance of the
voltage-controlled current source is expressed as (1 – DBoost) ×
gmPOWER.
v
O
R
L
ESR
(1-D
Boost
)gm
POWER
LX
A4450
C
OUT
vc
Figure 14: Simplified Small Signal Model of
A4450 Power Stage
where gmPOWER is COMP to LX Current Gain (see Electrical
Characteristics table), i.e. the transconductance of power stage;
DBoost is the duty cycle of boost switch,
DBoost = VIN(MIN) (V) × 1.844
RNG (kΩ)
{
0, in Buck mode
1 – , in Buck-Boost mode
The control-to-output transfer function of the power stage is
shown in equation 21 and consists of a DC gain, one dominant
pole, and one ESR zero.
(21)
vo
vc
power = GDC(power) ×
1 + s
2π × fESR(z)
1 + s
2π × fpower(p)
where
GDC(power) is the DC gain of the power stage,
GDC(power) = (1 – DBoost) × gmPOWER × RL,
fESR(z) is the ESR zero of the power stage,
fESR(z) = 1
2π × ESR × COUT
fpower(p) is the dominant pole of the power stage,
fpower(p) = 1
2π × RL × COUT
RL is the load resistance,
ESR is the equivalent series resistance of the output capacitor,
COUT is the output capacitance.
:“ LLEGRO'
mxcrosystems
Buck-Boost Controller with Integrated Buck MOSFET
A4450
25
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
For a design with very low-ESR-type output capacitors (i.e.
ceramic or OSCON output capacitors), the ESR zero is usually
at a very high frequency, so it can be ignored. If the ESR zero
falls below or near the 0 dB crossover frequency of the system
(as is the case with electrolytic output capacitors), then it should
be cancelled by the pole formed by the CP capacitor and the RZ
resistor (identified and discussed later as fEA(p2)).
The feedback loop includes a feedback output voltage divider
(RFB1 and RFB2), the error amplifier (gmEA), and the compensa-
tion network (RZ, CZ, and CP). The transfer function of the feed-
back can be derived and simplified if RO(EA) ≫ RZ, and CZ ≫ CP.
In most cases, RO(EA) > 2 MΩ, 1 kΩ < RZ < 100 kΩ, 220 pF <
CZ < 47 nF, and CP < 50 pF, so the following equations are very
accurate:
(22)
vc
vo
feedback = GDC(EA) ×
1 + s
2π × fEA(z)
1 + s
2π × fEA(p1)
( )(
1 + s
2π × fEA(p2)
)
where
GDC(EA) is the DC gain of the feedback loop,
GDC(EA) = RFB2
RFB1 + RFB2
× gmEA × RO(EA)
gmEA is the error amplifier transconductance (see EC table),
RO(EA) is the output resistance of the error amplifier (the small
output capacitance of the error amplifer is neglected), and
RO(EA) = AVOL / gmEA
AVOL is the error amplifier open-loop voltage gain (see EC
table),
fEA(z) is the low-frequency zero of the error amplifier compensa-
tion network,
fEA(z) = 1
2π × RZ × CZ
fEA(p1) is the low-frequency pole of the error amplifier compen-
sation network,
fEA(p1) = 1
2π × RO(EA) × CZ
fEA(p2) is the high-frequency pole of the error amplifier compen-
sation network,
fEA(p2) = 1
2π × RZ × CP
Placing fEA(z) just above fpower(p) will result in excellent phase
margin, but relatively slow transient recovery time.
The sum of power stage control-to-output response equation 21
and the feedback loop response equation 22, including error
amplifier, is the overall loop frequency response of the entire
system. The goal of compensation design is to shape the transfer
function of the overall loop to get a stable converter with the
desired loop gain and phase margin.
A Generalized Tuning Procedure
1. Choose the system bandwidth, fC, the frequency at which the
magnitude of the gain will cross 0 dB. Recommended values
for fC are fSW/20 < fC < fSW/7.5. A higher value of fC will gen-
erally provide a better transient response, while a lower value
of fC will be easier to obtain higher gain and phase margins.
2. Calculate the RZ resistor value to set the desired system
bandwidth (fC),
RZ = fC × RFB1 + RFB2
RFB2 ×2 × π × COUT
gmPOWER × gmEA
3. Calculate the dominant pole frequency of power stage
(fpower(p) ) formed by COUT and RL.
fpower(p) = 1
2π × RL × COUT
4. Calculate a range of values for the CZ capacitor and set the
compensation zero below the one fourth of the crossover
frequency fC,
4< CZ <
2 × π × RZ × fC
1
2 × π × RZ × 1.5 × fpower(p)
To maximize system stability (i.e. have the most gain mar-
gin), use a higher value of CZ. To optimize transient recovery
time at the expense of some phase margin, use a lower value
of CZ.
5. Calculate the frequency of the ESR zero (fESR(z)) formed by
the output capacitor(s).
fESR(z) = 1
2π × ESR × COUT
ALLEGRO'
mxcrosystems
Buck-Boost Controller with Integrated Buck MOSFET
A4450
26
Allegro MicroSystems
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A. If fESR(z) is at least 1 decade higher than the target
crossover frequency (fC), then fESR(z) can be ignored.
This is usually the case for a design using ceramic output
capacitors. Use equation below to calculate the value of
CP by setting fEA(p2) to either 5 × fC or fSW/2, whichever
is higher.
fEA(p2) = 1
2π × RZ × CP
B. If fESR(z) is near or below the target crossover frequency
(fC) then use equation above to calculate the value of CP by
setting fEA(p2) equal to fESR(z). This is usually the case for a
design using high ESR electrolytic output capacitors.
Typical design examples are provided for VOUT = 5 V and VOUT
= 8 V with fSW = 400 kHz and 2 MHz respectively.
:“ LLEGRO'
mwcrosystems
Buck-Boost Controller with Integrated Buck MOSFET
A4450
27
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Figure 15: Schematic of 5 VOUT Design Example at 400 kHz and 2 MHz
VBAT
VIN
AVIN
COMP
LX
LG
BOOT
EN
PGND
FSET/SYNC
NPOR
GND
FB
RNG
SS
LX
VIN
VOUT = 5 V
5.11 Ω
A4450
1.0 µF
+
CBCIN
Cn
RFSET
CSS
RZ
CZ
CP
Cboot
D1
D2
Q2
LO
CO1 CO2
RLG
RNG
RFB1
RFB2
RPU
VOUT
10 kΩ
10 kΩ
DBAT
RIN
<<
PDS1040L
22 nF
0.22 µF
Boost Diode
Buck Diode
Boot diode
VIN
3.3 kΩ
0.1 µF
24.9 kΩ
4.75 kΩ
Table 2: Recommended Key Components of 5 VOUT at 400 kHz and 2 MHz Designs
Reference Description Manufacturer/Part Number
Q2 – Boost Switch NFET, 20 V / 30 V, 25 mΩ and 14 nCMAX @ 4.5 VGS
ST, STL10N3LLH5
OnSemi, NVTFS4823N
D1, D2 Schottky 3 A, 40 V Vishay, SS3P4-M3/84A
CB47 µF, electrolytic capacitor, 50 V Panasonic, EEE-FK1H470XP
CIN Total ~10 µF, ceramic capacitors, X7R, ≥50 V TDK, Murata, Taiyo Yuden
2 MHz 5 VOUT (RFSET = 7.87 kΩ, RNG = 15 kΩ)
(RZ+CZ)//CP(7.32 kΩ + 2.2 nF) // 33 pF –
LO10 µH, IR = 5.2 A, ISAT = 12.5 A, 27 mΩ Wurth, 74437368100
COTotal ~20 µF, ceramic, X7R, ≥16 V TDK, Murata, Taiyo Yuden
Boot Diode BAS16 NXP, Vishay
400 kHz 5 VOUT (RFSET = 41.2 kΩ, RNG = 15 kΩ)
(RZ+CZ)//CP(9.31 kΩ + 5.6 nF) // 10 pF –
LO33 µH, IR = 4.2 A, ISAT = 5.5 A, 45 mΩ Wurth, 7447709330
COTotal ~30 µF, ceramic, X7R, ≥16 V TDK, Murata, Taiyo Yuden
Boot Diode BAS16 NXP, Vishay
:“ LLEGRO'
mwcrosystems
Buck-Boost Controller with Integrated Buck MOSFET
A4450
28
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Figure 16: Schematic of 8 VOUT Design Example at 400 kHz
VBAT
VIN
AVIN
COMP
LX
LG
BOOT
EN
PGND
FSET/SYNC
NPOR
GND
FB
RNG
SS
LX
VIN
VOUT = 8 V
5.11 Ω
A4450
1.0 µF
+
CBCIN
Cn
RFSET
CSS
RZ
CZ
CP
Cboot
D1
D2
Q2
LO
CO1 CO2
RLG
RNG
RFB1
RFB2
RPU
VAUX ≤ 5 V
10 kΩ
10 kΩ
DBAT
RIN
<<
PDS1040L
22 nF
0.22 µF
Boost Diode
Buck Diode
Boot diode
VIN
3.3 kΩ
0.1 µF
3 V Zener diode
46.4 kΩ
5.11 kΩ
Table 3: Recommended Key Components of 8 VOUT at 400 kHz Design
Reference Description Manufacturer/Part Number
400 kHz 8 VOUT (RFSET = 41.2 kΩ, RNG = 23.2 kΩ)
(RZ+CZ) // CP(20.5 kΩ + 3.3 nF) // 10 pF –
LO47 µH, IR = 3.8 A, ISAT = 4.5 A, 60 mΩ Wurth, 7447709470
COTotal ~55 µF, ceramic, X7R, ≥16 V TDK, Murata, Taiyo Yuden
Boot Diode BAS16 NXP, Vishay
Zener Diode 3 V Zener Diode BZT52C3V0T-7 Diodes Inc.
:“ LLEGRO'
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Buck-Boost Controller with Integrated Buck MOSFET
A4450
29
Allegro MicroSystems
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Figure 17: Schematics of 8 VOUT Design Example at 2 MHz
VBAT
VIN
AVIN
COMP
LX
LG
BOOT
EN
PGND
FSET/SYNC
NPOR
GND
FB
RNG
SS
LX
VIN
VOUT = 8 V
5.11 Ω
A4450
1.0 µF
+
CBCIN
Cn
RFSET
CSS
RZ
CZ
CP
Cboot
D1
D2
Q2
LO
CO1 CO2
RLG
RNG
RFB1
RFB2
RPU
VAUX ≤ 5 V
10 kΩ
10 kΩ
DBAT
RIN
<<
PDS1040L
22 nF
0.22 µF
Boost Diode
Buck Diode
VIN
3.3 kΩ
0.1 µF
46.4 kΩ
5.11 kΩ
Table 4: Recommended Key Components of 8 VOUT at 2 MHz Design
Reference Description Manufacturer/Part Number
2 MHz 8 VOUT (RFSET = 7.87 kΩ, RNG = 23.2 kΩ)
(RZ+CZ) // CP(20 kΩ + 2.2 nF) // 10 pF –
LO10 µH, IR = 5.2 A, ISAT = 12.5 A, 27 mΩ Wurth, 74437368100
COTotal ~20 µF, ceramic, X7R, ≥16 V TDK, Murata, Taiyo Yuden
1 XV” sme
1 XV” g2.5xV
N‘z
l S 1014
ALLEGRO"
microsystems
Buck-Boost Controller with Integrated Buck MOSFET
A4450
30
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
The following are some guidelines to determine the appropriate
output and input ranges.
First, when the A4450 operates under buck-boost mode, the peak
inductor current, IPEAK, which happens at minimum VIN, should
be below the Pulse-by-Pulse Current Limit at Buck-Boost Mode,
ILIM(BUCKBOOST):
)(
_
1
)1(
2
BUCKBOOSTLIM
MAXBoost
Buck
L
OUT
PEAK
I
D
D
I
I
I<
−
−×
∆
+
=
→
)1()1(
2
_)( MAXBoostBUCKBOOSTLIMBuck
L
OUT
DID
I
I−×<−×
∆
+
For practical application, some margin—for example 15% or
higher—should be added:
%85)1(
20
_
)( ×××≤−×
∆
+Buck
OUT
MININ
BUCKBOOSTLIMBuck
L
OUT D
V
V
ID
I
I
Minimum ILIM(BUCKBOOST) = 3.9 A, and it is recommended to
choose DBuck0 = 0.65 (for Buck minimum Off-Time at 2 MHz) or
DBuck0 = 0.80 or lower (for Buck minimum Off-Time at 400 kHz
and below); also choose ΔIL = 40% × IOUT. Then the outputs
should meet the following criteria:
0
_
)(
××07 ×.1
Buck
OUT
MININ
BUCKBOOSTLIMOUT
D
V
V
II ≤
for 2 MHz
0
_
)(
××04 ×.1
Buck
OUT
MININ
BUCKBOOSTLIMOUT
D
V
V
II ≤
for 400 kHz
and below
×85%
×85%
MININOUTOUT
VVI
_
×0.2× ≤
for 2 MHz
MININOUTOUT
VVI
_
×5.2× ≤
for 400 kHz and below
Second, when the A4450 operates under Buck mode, the peak
inductor current should not go beyond the Pulse-by-Pulse Current
Limit at Buck Mode, ILIM(BUCK):
)(
2
BUCKLIM
L
OUTPEAK
I
I
II ≤
∆
+=
Minimum ILIM(BUCK) = 2.4 A, and if the chosen ΔIL = 40% ×
IOUT, then:
AI
OUT
0.2≤
Thus the rated output current should not go above 2 A. At the
same time, the rated output voltage, VOUT, and rated output cur-
rent, IOUT, will also depend on the selected minimum input volt-
age, VIN_MIN. See Figure 18 and Figure 19.
Figure 18: Selection of rated IOUT versus rated VOUT for different VIN_MIN at 2 MHz
Output Limitations at 2 MHz
10 V
8 V
VIN_MIN
5 V
4 V
3 V
IOUT (A)
VOUT (V)
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0 16.0
ALLEGRO"
microsystems
Buck-Boost Controller with Integrated Buck MOSFET
A4450
31
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Figure 19: Selection of rated IOUT versus rated VOUT for different VIN_MIN at 400 kHz and below
10 V
8 V
VIN_MIN
5 V
4 V
3 V
Output Limitations at 400 kHz and below
IOUT (A)
VOUT (V)
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0 16.0
In actual application, it is important to check actual Buck duty
cycle, DBuck, at VIN_MIN to ensure that DBuck is not saturated to
avoid dropout operation. If DBuck is saturated, it is suggested to
reduce DBuck0 or increase VIN_MIN.
For example, when VOUT = 12 V and IOUT = 0.8 A at 400 kHz,
and DBuck0 = 0.8, then VIN_MIN ≥ 3.84 V. However, the actual
Buck duty cycle at VIN = 5 V is 0.95, which is close to satura-
tion; therefore, it is better to set VIN_MIN > 5.5 V, where measured
DBuck = 0.92. The other option is to choose lower DBuck0 = 0.72;
then VIN_MIN ≥ 4.3 V, and the actual Buck duty cycle at VIN =
5 V becomes 0.875. At VIN = 4.3 V, actual Buck duty cycle will
be 0.92. VIN_MIN > 5 V is suggested for some margin in the actual
application.
‘ LLEGRO'
mxcrosystems
Buck-Boost Controller with Integrated Buck MOSFET
A4450
32
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
POWER DISSIPATION AND THERMAL CALCULATIONS
The power dissipated in the A4450 is the sum of the power dis-
sipated from the VIN supply current (PIN), the switching power
dissipation of the integrated buck switch (PSW1), the conduction
power dissipation of the integrated Buck switch (PCOND1), and
the power dissipated by both gate drivers (PDRIVER).
The power dissipated from the VIN supply current can be calcu-
lated using equation 23,
PIN = VIN × IQ + (VIN – VGS1) × QG1 × fSW + PIN2 (23)
where
PIN2 =
{
0, in Buck mode
(VIN – VGS2 ) × QG2 × fSW, in Buck-Boost mode
VIN is the input voltage,
IQ is the input quiesent current drawn by the A4450 (see
Electrical Characteristics table),
VGS1 is the MOSFET gate drive voltage of high-side buck
switch (typically 5 V),
QG1 is the internal high-side buck switch gate charges
(approximately 5.7 nC),
QG2 is the external boost switch gate charges, and
fSW is the PWM switching frequency.
The switching power dissipation of the high-side buck switch can
be calculated using equation 24,
(24)P
SW1 = 2
1
× VIN × 1 – D
Boost
I
OUT × (tr + tf ) × fSW
where
VIN is the input voltage,
IOUT is the regulator output current,
DBoost is the duty cycle of the boost switch,
fSW is the PWM switching frequency, and
tr and tf are the rise and fall times measured at the SW node.
The exact rise and fall times at the LX node will depend on the
external components and PCB layout, so each design should be
measured at full load. Approximate values for both tr and tf range
from 5 to 20 ns.
The power dissipated by the high-side Buck switch while it is
conducting can be calculated using equation 25,
P= I× R=
COND1 RMS(FET) DS(ON)HS
2(25)
DBuck ΔIL
2
(1 – DBoost )212
×I+
2
OUT × RDS(ON)HS
()()
where
IOUT is the regulator output current,
ΔIL is the peak-to-peak inductor ripple current,
DBoost is the duty cycle of the boost switch,
DBuck is the duty cycle of the buck switch, and
RDS(ON)HS is the on-resistance of the high-side buck switch
MOSFET.
The RDS(ON)HS of the high-side buck switch has some initial
tolerance plus an increase from self-heating and elevated ambi-
ent temperatures. A conservative design should accomodate
an RDS(ON) with at least a 15% initial tolerance plus 0.39%/°C
increase due to temperature.
The sum of the power dissipated by both gate drivers of the inte-
grated buck switch and the external boost switch is,
PDRIVER = PG1 + PG2 (26)
where
PG1 = QG1 × VGS1 × fSW
PG2 =
{
0, in Buck mode
QG2 × VGS2 × fSW, in Buck-Boost mode
Finally, the total power dissipated by the A4450 (PTOTAL) is the
sum of the previous equations,
PTOTAL = PIN + PSW1 + PCOND1 + PDRIVER (27)
The average junction temperature can be calculated with the
equation 28,
TJ = PTOTAL × RθJA + TA (28)
ALLEGRO'
mxcrosystems
Buck-Boost Controller with Integrated Buck MOSFET
A4450
33
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
where
PTOTAL is the total power dissipated from equation 27,
RθJA is the junction-to-ambient thermal resistance of QFN-20
package (37°C/W on a 4-layer PCB), and
TA is the ambient temperature.
The maximum junction temperature will be dependent on how
efficiently heat can be transferred from the PCB to the ambient air.
It is critical that the thermal pad on the bottom of the IC should be
connected to at least one ground plane using multiple vias.
As with any regulator, there are limits to the amount of heat that
can be dissipated before risking thermal shutdown. There are trade-
offs between ambient operating temperature, input voltage, output
voltage, output current, switching frequency, PCB thermal resis-
tance, airflow, and other nearby heat sources. Even a small amount
of airflow will reduce the junction temperature considerably.
Buck-Boost Controller with Integrated Buck MOSFET
A4450
34
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
PCB COMPONENT PLACEMENT AND ROUTING
A good PCB layout is critical for the A4450 to provide clean,
stable output voltages. Follow these guidelines to ensure a good
PCB layout. Figure 20 shows a typical buck-boost converter
schematic with the critical power paths/loops.
1. Place the ceramic input capacitors CIN as close as possible to
the VIN pin and GND pins to minimize the area of the criti-
cal Loop 1 (shown in Figure 20); and the traces of the input
capacitors to VIN pin should be short and wide to minimize
the inductance. The larger input capacitor can be located
further away from VIN pin. The input capacitors and A4450
IC should be on the same side of the board with traces on the
same layer.
2. The critical Loop 2 consisting of boost diode, output capaci-
tor COUT, and the external boost switch Q2 should be mini-
mized with relatively wide traces.
3. The Loop 3 shows the external boost switch gate driver cur-
rent loop. It is supplied from the bootstrap capacitor, Cboot.
Ensure that the gate driver Loop 3 is small and place the
traces parallel with small gap.
4. Ideally, the output capacitors, output inductor, buck diode,
boost diode, boost switch, and the controller IC should be on
the same layer. Connect these components with fairly wide
traces. A solid ground plane should be used as a very low-
inductance connection to the GND.
5. Place the output inductor (LO) as close as possible to the
LX pin with short and wide traces. The LX and LXb nodes
have high dv/dt rate, which are the root cause of many noise
issues. It is suggested to minimize the copper area to mini-
mize the coupling capacitance between these nodes and other
noise-sensitive nodes; However the nodes’ area cannot be too
small in order to conduct high current. A ground copper area
can be placed beneath the node to provide additional shield-
ing. Also, keep low-level analog signals (like FB, COMP)
away from the LX and LXb polygons.
6. Place the feedback resistor divider (RFB1 and RFB2) very
close to the FB pin. Make the ground side of RFB2 as close as
possible to the A4450.
7. Place the compensation components (RZ, CZ, and CP) as
close as possible to the COMP pin. RZ should be in COMP
pin side and CZ in GND side. Also make the ground side of
CZ and CP as close as possible to the IC.
8. Place the FSET resistor as close as possible to the SYNC/
FSET pin; place the soft-start capacitor CSS as close as pos-
sible to the SS pin.
9. The output voltage sense trace (from VOUT to RFB1) should
be connected as close as possible to the load to obtain the
best load regulation.
10. Place the bootstrap capacitor (Cboot) near the BOOT pin and
keep the routing from this capacitor to the LX polygon as
short as possible.
11. When connecting the input and output ceramic capacitors,
use multiple vias to GND and place the vias as close as possi-
ble to the pads of the components. Do not use thermal reliefs
around the pads for the input and output ceramic capacitors.
12. To minimize PCB losses and improve system efficiency, the
input and output traces should be as wide as possible and be
duplicated on multiple layers, if possible.
13. The thermal pad under the IC should be connected to the
GND plane (preferably on the top and bottom layer) with
as many vias as possible. Allegro recommends vias with an
approximately 0.25 to 0.30 mm hole and a 0.13 and 0.18 mm
ring.
14. EMI/EMC issues are always a concern. Allegro recommends
having locations for an RC snubber from LX to ground. The
resistor should be 0805 or 1206 size.
VOUT
VIN
Buck
Diode
Boost
Diode
Q1
A4450
Q2
LX
LG COUT
1
CIN 2
LXb
GND
3
LOAD
Lo
BOOT
Cboot
Figure 20: Typical Buck-Boost Regulator
A single-point ground is recommended, which could be the exposed thermal pad under the IC.
For Reference Only — Not for Tooling Use
% 1 fl r
2Mini
E: g:
4 {~11 iiiiiiiiiii "'E} 5 ‘
E E
A PCB La out Reference Vxew
*
F7
1 ‘ F J J
*5 @D
Delaxl A
>l>>
LLEGRO'
mwcrosystems
Buck-Boost Controller with Integrated Buck MOSFET
A4450
35
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Figure 21: Package ES, 20-Pin QFN with Exposed Thermal Pad and Wettable Flank
PACKAGE OUTLINE DRAWING
For Reference Only –Not for Tooling Use
(Reference JEDEC MO-220WGGD)
Dimensions in millimeters
NOT TO SCALE
Exact case and lead configuration at supplier discretion within limits shown
0.95
C
SEATING
PLANE
C
0.08
21X
20
20
2
1
1
2
20
2
1
A
A
B
C
D
D
C
4.00 ±0.10
2.45 ±0.10
4.00 ±0.10
2.45 ±0.10
4.10
0.30
0.50
4.10
0.75 ±0.05
0.50 BSC
0.40 ±0.10
0.22 ±0.05
2.60
2.60
B
PCB Layout Reference View
Terminal #1 mark area
Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier
discretion)
Reference land pattern layout (reference IPC7351 QFN50P400X400X80-21BM);
all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to
meet application process requirements and PCB layout tolerances; when mounting
on a multilayer PCB, thermal vias at the exposed thermal pad land can improve
thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
Coplanarity includes exposed thermal pad and terminals
0.05 REF
0.08 REF
0.40 ±0.10
0.05 REF
0.08 REF 0.203 REF
Detail A
DETAIL A
0.20
0.25 0.10
ALLEGRO'
mxcrosystems
Buck-Boost Controller with Integrated Buck MOSFET
A4450
36
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
For the latest version of this document, visit our website:
www.allegromicro.com
Revision Table
Number Date Description
– June 29, 2016 Initial release
1 March 28, 2017 Added guidelines to determine the appropriate output and input ranges (page 29-30)
2 June 6, 2017 Added Table of Contents (page 3); updated Functional Description Overview (page 11)
3 June 20, 2018 Minor editorial updates
4 July 2, 2019 Minor editorial updates
Copyright 2019, Allegro MicroSystems.
Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor
for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
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