MB91580L Series Datasheet by Cypress Semiconductor Corp
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PERFORM
Although the document is marked
With the name ”Spansion”, the company that originally developed the specification, Cypress will
continue to offer these products to new and existing customers.
Continuity of Specifications
There is no change to this document as a result of offering the device as a Cypress product. Any
changes that have been made are the result of normal document improvements and are noted in the
document history page, where supported. Future revisions will occur when appropriate, and changes
will be noted in a document histon/ page.
Continuity of Ordering Part Numbers
Cypress continues to support existing part numbers. To order these products, please use only the
Ordering Part Numbers listed in this document.
For More Information
Please contact your local sales office for additional information about Cypress products and solutions.
About Cypress
Cypress (NASDAQ: CY) delivers high-performance, high-quality solutions at the heart oftoday’s most
advanced embedded systems from automotive industrial and networking platforms to highly
interactive consumer and mobile deVices. With a broad differentiated product portfolio that includes
NOR flash memories F- RAM'M and SRAM Traveo’” microcontrollers the industry 5 only PSoC:
programmable system- on- chip solutions analog and PMIC Power Management le CapSense®
capacitive touch- -sensing controllers and Wireless BLE Bluetootha Low- Energy and USB connectiVity
solutions Cypress is committed to providing its customers worldwide with consistent innovation pest-
in-class support and exceptional system value.
The following document contains information on Cypress products.
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MB91580L Series
32-bit Microcontroller
FR Family FR81S
MB91F585LA/F585LB/F585LC/F585LD/
MB91F586LA/F586LB/F586LC/F586LD/
MB91F587LA/F587LB/F587LC/F587LD
Data Sheet (Full Production)
Publication Number MB91F587LA_DS705-00012 Revision 2.0 Issue Date August 22, 2014
CONFIDENTIAL
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume
such that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.
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DataSheet
MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to
advise readers of product information or intended specifications throughout the product life
cycle, including development, qualification, initial production, and full production. In all cases,
however, readers are encouraged to verify that they have the latest information before
finalizing their design. The following descriptions of Spansion data sheet designations are
presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more
specific products, but has not committed any design to production. Information presented in
a document with this designation is likely to change, and in some cases, development on the
product may discontinue. Spansion Inc. therefore places the following conditions upon
Advance Information content:
“This document contains information on one or more products under development
at Spansion Inc. The information is intended to help you evaluate this product. Do
not design in this product without contacting the factory. Spansion Inc. reserves the
right to change or discontinue work on this proposed product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such
that a commitment to production has taken place. This designation covers several aspects of
the product life cycle, including product qualification, initial production, and the subsequent
phases in the manufacturing process that occur before full production is achieved. Changes
to the technical specifications presented in a Preliminary document should be expected
while keeping these aspects of production under consideration. Spansion places the
following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion
product(s) described herein. The Preliminary status of this document indicates that
product qualification has been completed, and that initial production has begun.
Due to the phases of the manufacturing process that require maintaining efficiency
and quality, this document may be revised by subsequent versions or modifications
due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance
Information, Preliminary, or Full Production). This type of document distinguishes these
products and their designations wherever necessary, typically on the first page, the ordering
information page, and pages with the DC Characteristics table and the AC Erase and
Program table (in the table notes). The disclaimer on the first page refers the reader to the
notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only
nominal changes are expected, the Preliminary designation is removed from the data sheet.
Nominal changes may include those affecting the number of ordering part numbers available,
such as the addition or deletion of a speed option, temperature range, package type, or VIO
range. Changes may also include those needed to clarify a description or to correct a
typographical error or incorrect specification. Spansion Inc. applies the following conditions
to documents in this category:
“This document states the current technical specifications regarding the Spansion
product(s) described herein. Spansion Inc. deems the products to have been in
sufficient production volume such that subsequent versions of this document are
not expected to change. However, typographical or specification corrections, or
modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
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MB91580L Series
32-bit Microcontroller
FR Family FR81S
MB91F585LA/F585LB/F585LC/F585LD/
MB91F586LA/F586LB/F586LC/F586LD/
MB91F587LA/F587LB/F587LC/F587LD
Data Sheet (Full Production)
Publication Number MB91F587LA_DS705-00012 Revision 2.0 Issue Date August 22, 2014
CONFIDENTIAL
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient
production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the
valid combinations offered may occur.
DESCRIPTION
This series has Spansion 32-bit microcontrollers for automobile motor control. They use the FR81S CPU
that is compatible with the FR family.
Note: FR is a line of products of Spansion Inc.
FEATURES
• FR81S CPU Core
• 32-bit RISC, load/store architecture, pipeline 5-stage structure
• Maximum operating frequency: 128MHz (Source oscillation= 4.0MHz, 32 multiplied ( PLL clock
multiplication system) )
• General-purpose register: 32 bits, 16 sets
• 16-bit fixed length instructions (basic instructions), 1 instruction per cycle
• Instructions appropriate to embedded applications
• Memory-to-memory transfer instructions
• Bit manipulation instructions
• Barrel shift instructions
• High-level language support instructions
• Function entry/exit instructions
• Register content multi-load and store instructions
• Bit search instructions
Logical 1 detection, 0 detection, and change-point detection
• Branch instructions with delay slot
Overhead decrement during branch process
• Register interlock function
Easy assembler writing
• Built-in multiplier and instruction level support
• Signed 32-bit multiplication: 5 cycles
• Signed 16-bit multiplication: 3 cycles
Spansion provides information facilitating product development via the following website.
The website contains information useful for customers.
http://www.spansion.com/Support/microcontrollers/
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DataSheet
2 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
• Interrupt (PC/PS saving)
6 cycles (16 priority levels)
• The Harvard architecture allows simultaneous execution of program and data access.
• Instruction compatibility with the FR family
• Built-in memory protection function (MPU)
• Eight protection areas can be specified commonly for instructions and data.
• Control access privilege in both privilege mode and user mode
• Built-in FPU (floating-point operation)
• IEEE754 compliant
• Floating-point register: 32 bits × 16 sets
• Peripheral Functions
• Clock generation (SSCG function is available)
• Main oscillation (4 to 20 MHz)
• PLL multiplication rate:1 to 32 times
• CR oscillation
• Oscillation frequency: 100kHz, with frequency accuracy ± 50% (pre-trimming)
• Trimming is enabled
• To be used as a count clock of hardware watchdog
• MB91F585LC/F586LC/F587LC/F585LD/F586LD/F587LD: Oscillation stop feature during stand-by
is not available
• MB91F585LA/F586LA/F587LA/F585LB/F586LB/F587LB: Oscillation stop feature during stand-by
is available
• Built-in program flash memory capacity
MB91F585L: 512+64 Kbytes
MB91F586L: 768+64 Kbytes
MB91F587L: 1024+64 Kbytes
• Built-in data flash (WorkFlash) 64 Kbytes
• Built-in RAM capacity
• Main RAM
MB91F585L: 48 Kbytes
MB91F586L: 64 Kbytes
MB91F587L: 96 Kbytes
• Backup RAM 8 Kbytes
• General-purpose ports:
MB91F585LA/F586LA/F587LA/F585LC/F586LC/F587LC 98 ports
MB91F585LB/F586LB/F587LB/F585LD/F586LD/F587LD 111 ports
• Including eight I2C pseudo open drain corresponding ports
• External bus interface (MB91F585LB/F586LB/F587LB/F585LD/F586LD/F587LD)
• Maximum operating frequency: 40MHz
• 22-bit address, 16-bit data
• DMA controller
• Up to 8 channels can be started simultaneously.
• 2 transfer factors (Internal peripheral request and software)
• External interrupt input: 8 channels
Level ("H" / "L") or edge detection (rising or falling) enabled
• Multi-function serial communication (built-in transmission/reception FIFO memory): 5 channels
< UART (Asynchronous serial interface) >
• Full-duplex double buffering system, 64-byte transmission FIFO memory, 64-byte reception FIFO
memory
• Parity or no parity is selectable.
• Built-in dedicated baud rate generator
• An external clock can be used as the transfer clock
• Parity, frame, and overrun error detection functions provided
• DMA transfer supported
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DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 3
CONFIDENTIAL
<CSIO (Synchronous serial interface) >
• Full-duplex double buffering system, 64-byte transmission FIFO memory, 64-byte reception FIFO
memory
• SPI supported; master and slave systems supported; 5 to 16, 20, 24, 32-bit data length can be set.
• Built-in dedicated baud rate generator (Master operation)
• An external clock can be entered. (Slave operation)
• Overrun error detection function is provided.
• Built-in chip selection function
• DMA transfer supported
<LIN interface (v2.1)>
• Full-duplex double buffering system, 64-byte transmission FIFO memory, 64-byte reception FIFO
memory
• LIN protocol revision2.1 supported.
• Master and slave systems supported
• Framing error and overrun error detection
• LIN synch break generation and detection; LIN synch delimiter generation
• Built-in dedicated baud rate generator
• An external clock can be adjusted by the reload counter.
• DMA transfer supported
< I2C >
• Supported for 4 channels: ch.0,ch.1,ch.3, and ch4.
• Full-duplex double buffering system, 64-byte transmission FIFO memory, 64-byte reception FIFO
memory
• Standard mode (Max. 100 kbps) / high-speed mode (Max. 400 kbps) supported
• DMA transfer supported (for transmission only)
• CAN controller (CAN): 3 channels
• Transfer speed: Up to 1Mbps
• 64-transmission/reception message buffering: 3 channels
• FlexRay controller: 1unit(ch.A/ch.B)
• FlexRay Specifications Version 2.1 supported
• Up to 128 message buffers
• 8K bytes of message RAM
• Variable length of message buffers
• Each message buffer can be allocated as a part of reception buffer, transmission buffer or reception
FIFO memory
• Host access to the message buffer via input and output buffers
• Filtering for slot counter, cycle counter and channels
• Maskable interrupts are supported
• PPG: 16 bits × 24 channels
• Reload timer: 16 bits × 4 channels
• A/D converter (successive approximation type)
• 12-bit resolution: 3units(24 channels)
• Conversion time: 1 µs
• Free-run timer: 16 bits × 6 channels (1 channel can be selected for input capture, and 1 channel for output
compare.)
• Input capture: 16 bits × 8 channels (linked to the free-run timer)
• Output compare: 16 bits × 12 channels (linked to the free-run timer)
• Waveform generator: 2 units (12 channels)
• R/D converter: 1 channel (MB91F585LA/F586LA/F587LA/F585LC/F586LC/F587LC)
• 10-bit D/A converter: 1 channel (MB91F585LB/F586LB/F587LB/F585LD/F586LD/F587LD)
• Calibration: The hardware watchdog for CR oscillation drive
The CR oscillation frequency can be trimmed.
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DataSheet
4 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
• Clock Supervisor
• Anomaly supervisory feature (by damaged quartz, etc.) of external main oscillation (4MHz)
• When anomaly is detected, clock is switched to CR.
• Up/ down counter: 2 channels
8/16-bit Up/ down counter
• Base timer: 2 channels
• 16-bit timer
• Any of four PWM/PPG/PWC/reload timer functions can be selected and used.
• As for the functions of PWC and reload timer, 2 channels of cascade mode can be used as 32-bit
timer..
• CRC generation
• Watchdog timer
• Hardware watchdog
• Software watchdog
• NMI
• Interrupt controller
• Interrupt request batch read
Multiple interrupts from peripherals can be read by a series of registers.
• I/O relocation
Change of pin position of peripheral functions
• Low-power consumption mode
• Sleep/Stop/Watch
• Stop (Power shut-off)/Watch (Power shut-off)
• Power-on reset
• Low-voltage detection reset (external low-voltage detection)
• Low-voltage detection reset (internal low-voltage detection)
• Device package: LQFP-144
• CMOS 90 nm technology
• Power supplies
• Single 5V power supply
• The voltage step-down circuit brings the 5.0V down to generate 1.2V internally
• I/O 5.0V
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S PA N 5 IO N
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0 Memory size
M391F585LA M391F586LA M391F587LA
M391F585LB M391 F586LB M391F587LB
M391F585LC M391F586LC MBQ1F587LC
M391F585LD M391F586LD MBQ1F587LD
Flash memory capacity (program) 51244.4 Kbytcs 768+64 Khytes 1024+64 Kby1es
Flash memory capacity (work) 64 Kbytes
RAM capacity (main) 4x Kbytes i 64 Kbytes i 96 Kbytes
RAM capacity (backup) 8 Kbytes
0 Function
M391F585LA M391F585LB MBQ1F585LC M391F585LD
M391F586LA M391F586LB MBQ1F586LC M391F586LD
M391F587LA M391F587LB MBQ1F587LC M391F587LD
()nrehip PLL clock multiplication systern
(Up to 32 times of multiplication)
Minimum instnietion execution time: 7.8 1 ns
(128MHz, source oscillation 4MHz 32 times of multiplication)
CR oscillation
Provided
Oscillation stop feature
during standby
Address: 22 bits Address: 22 bits
Data: [6 bits Data: 16 bits
DMA transfer 8 channels
lorbit base timer 2 channels
Freerrun timer 6 channels
lnput capture 8 channels
Output compare [2 channels
Waveform generator 2 units (12 channels)
lorbit reload timer 4 channels
PPG 24 channels
External intermpt 8 channels
A/D converter
3 units (24 channels)
R/D converter Provided Not provided Provided Not provided
D ’A converter Not provided Provided Not provided Provided
Up’ down counter 2 channels
Multifunction serial
interface
CAN 64 msb X 3 channels (eh.(J’ch.1/eh.2)
Flchay 128 tnsh x 1 unit (ch.A ' ch.B)
Sofiware watchdog Provided
l-lardvvarc watchdog Provided
CRC generation 1 channel
Low-voltage detection reset
(lntemal to
detection)
Low-voltage detection reset
(External 1o
detection)
Dcvicc package LQrPrlAA
Debug interface
Builtrin oer) [0n Chip Debug Unit)
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 5
CONFIDENTIAL
PRODUCT LINEUP
MB91580L Series Product Lineup Comparison
• Memory size
Items
MB91F585LA
MB91F585LB
MB91F585LC
MB91F585LD
MB91F586LA
MB91F586LB
MB91F586LC
MB91F586LD
MB91F587LA
MB91F587LB
MB91F587LC
MB91F587LD
Flash memory capacity (program)
512+64 Kbytes
768+64 Kbytes
1024+64 Kbytes
Flash memory capacity (work)
64 Kbytes
RAM capacity (main)
48 Kbytes
64 Kbytes
96 Kbytes
RAM capacity (backup)
8 Kbytes
• Function
Items
MB91F585LA
MB91F586LA
MB91F587LA
MB91F585LB
MB91F586LB
MB91F587LB
MB91F585LC
MB91F586LC
MB91F587LC
MB91F585LD
MB91F586LD
MB91F587LD
System clock
On-chip PLL clock multiplication system
(Up to 32 times of multiplication)
Minimum instruction execution time: 7.81ns
(128MHz, source oscillation 4MHz × 32 times of multiplication)
CR oscillation
Provided
Oscillation stop feature
during stand-by
Provided Provided Not provided Not provided
External bus interface Not provided
Address: 22 bits
Data: 16 bits
Not provided
Address: 22 bits
Data: 16 bits
DMA transfer
8 channels
16-bit base timer
2 channels
Free-run timer
6 channels
Input capture
8 channels
Output compare
12 channels
Waveform generator
2 units (12 channels)
16-bit reload timer
4 channels
PPG
24 channels
External interrupt
8 channels
A/D converter
3 units (24 channels)
R/D converter
Provided
Not provided
Provided
Not provided
D/A converter
Not provided
Provided
Not provided
Provided
Up/ down counter
2 channels
Multi-function serial
interface
5 channels
CAN
64 msb × 3 channels (ch.0/ch.1/ch.2)
FlexRay
128 msb × 1 unit (ch.A / ch.B)
Software watchdog
Provided
Hardware watchdog
Provided
CRC generation
1 channel
Low-voltage detection reset
(Internal low-voltage
detection)
Provided
Low-voltage detection reset
(External low-voltage
detection)
Provided
Device package
LQFP-144
Debug interface
Built-in OCD (On Chip Debug Unit)
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SPANSION
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0 Memory size
M391F583MG M391F584MG M391F585MG
M391F583MH M391F584MH M391F585MH
M391F583MJ M391F584MJ M391F585MJ
MB91F583MK MB91F584MK M391F585MK
Flash memory capacity (program) 256+64 Kbytcs 384+64 Kbytes 512+o4 Kbytes
Flash memory capacity (work) 64 Kbytes
RAM capacity (main) 32 Kbytes l 48 Kbytes l 48 Kbytes
RAM capacity (backup) 8 Kbytes
0 Function
MB91F583MG M391 F583MH M391F583MJ M391F583MK
MB91F584MG M391F584MH M391F584MJ M391F584MK
MB91F585MG M391F585MH M391F585MJ M391F585MK
Onrehip PLL clock rnuitipticatiori system
(Up to 32 times of multiplication)
Minimum instmetion cxeeution time: 7.81ns
(128MHz, source oseillalion 4MHz 32 times of multiplication)
CR oscillation
Provided
Oseillation stop
feature dn
standby
External bus interface Not provided
DMA transfer 8 channels
lorbit base timer 2 channels
Freerrun timer 6 channels
lnput capture 4 channels
Output eompare 7 channels
Waveform generator 2 unit (7ehanncls)
lorbit reload timer 4 channels
PPG 6 channels
External intermpt 8 channels
A/D converter
3 units (23 channels)
R/D converter
Not provided
D ’A converter
Provided
Up’ down counter
2 channels
Multirfunetion serial
interface
CAN (34me x 2 channels (eh.(J/chil)
lZXmsb X 1 unit lZXmsb x 1 unit
(ch.A/ch.B) (ch.A/chiB)
Sofiware watchdog Provided
Hardware watchdog Provided
CRC generation 2 channels
Low-Voltage detection reset
(Internal to
detection)
Low-Voltage detection reset
(External lo
detection)
Device package LQFPrtoo
Debug interface
Builtrin oer) (0n Chip Debug Unit)
DataSheet
6 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
MB91580M Series Product Lineup Comparison
• Memory size
Items
MB91F583MG
MB91F583MH
MB91F583MJ
MB91F583MK
MB91F584MG
MB91F584MH
MB91F584MJ
MB91F584MK
MB91F585MG
MB91F585MH
MB91F585MJ
MB91F585MK
Flash memory capacity (program)
256+64 Kbytes
384+64 Kbytes
512+64 Kbytes
Flash memory capacity (work)
64 Kbytes
RAM capacity (main)
32 Kbytes
48 Kbytes
48 Kbytes
RAM capacity (backup)
8 Kbytes
• Function
Items
MB91F583MG
MB91F584MG
MB91F585MG
MB91F583MH
MB91F584MH
MB91F585MH
MB91F583MJ
MB91F584MJ
MB91F585MJ
MB91F583MK
MB91F584MK
MB91F585MK
System clock
On-chip PLL clock multiplication system
(Up to 32 times of multiplication)
Minimum instruction execution time: 7.81ns
(128MHz, source oscillation 4MHz × 32 times of multiplication)
CR oscillation
Provided
Oscillation stop
feature during
stand-by
Provided Provided Not provided Not provided
External bus interface
Not provided
DMA transfer
8 channels
16-bit base timer
2 channels
Free-run timer
6 channels
Input capture
4 channels
Output compare
7 channels
Waveform generator
2 unit (7channels)
16-bit reload timer
4 channels
PPG
6 channels
External interrupt
8 channels
A/D converter
3 units (23 channels)
R/D converter
Not provided
D/A converter
Provided
Up/ down counter
2 channels
Multi-function serial
interface
4 channels
CAN
64msb × 2 channels (ch.0/ch.1)
FlexRay
128msb × 1 unit
(ch.A / ch.B)
Not provided
128msb × 1 unit
(ch.A / ch.B)
Not provided
Software watchdog
Provided
Hardware watchdog
Provided
CRC generation
2 channels
Low-voltage detection reset
(Internal low-voltage
detection)
Provided
Low-voltage detection reset
(External low-voltage
detection)
Provided
Device package
LQFP-100
Debug interface
Built-in OCD (On Chip Debug Unit)
Note: For details on the MB91580M series, see the "MB91580M/S Series HARDWARE MANUAL".
/'\
S PA N 5 IO N
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0 Memory size
M891F5838G M891F584SG MB91F5858G
MB91F5838H MB91F584SH M891F5858H
M891F583SJ MB91F584SJ MB91F585SJ
M891F583SK MB91F584SK MB91F5858K
Flash memory capacity (program) 256+64 Kbytcs 384+64 Kbytcs 512+64 Kbytes
Flash memory capacity (work) 64 Kbytes
RAM capacity (main) 32 Kbytes l 48 Kbytes l 48 Kbytes
RAM capacity (backup) 8 Kbytes
0 Function
MB91F5838G M891F5838H MB91F5838J M891 F5838K
MB91F584SG M891F584SH MB91F584SJ M891F584SK
MB91F5858G M891F5858H MB91F585SJ M891F5858K
()nrehip PLL clock multiplication system
(Up to 32 times of multiplication)
Minimum instniction execution time: 7.8 1 ns
(1 zle-lz, source oscillation 4MHz 32 times of multiplication)
CR oscillation
Provided
Oscillation stop feature
during standrby
External bus interface
Not provided
DMA transfer 8 channels
lorbit base timer 2 channels
Freerrun timer 6 channels
lnput capture 4 channels
()utput compare 7 channels
Waveform generator 2 unit (7channels)
lorbit reload timer 4 channels
PPG 6 channels
External intermpt 7 channels
A/D converter
3 units (1 7 channels)
R/D converter
Not provided
D ’A converter
Provided
Up’ down counter
2 channels
Multirfunetion serial
interface
CAN
64me x 1 channel (chU)
lzxmsb >< lllnit="" (ehla,="" ch.b)="" lzxmsb="">< lllnit="" (ella,="" ch.b)="" sofiware="" watchdog="" provided="" hardware="" watchdog="" provided="" crc="" generation="" 2="" channels="" low-voltage="" detection="" reset="" (lntemal="" to="" detection)="" low-voltage="" detection="" reset="" (external="" 1o="" detection)="" device="" package="" lqfproa="" debug="" interfaee="" blliltrin="" ()cd="" [0n="" chip="" debug="" unit)="">DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 7
CONFIDENTIAL
MB91580S Series Product Lineup Comparison
• Memory size
Items
MB91F583SG
MB91F583SH
MB91F583SJ
MB91F583SK
MB91F584SG
MB91F584SH
MB91F584SJ
MB91F584SK
MB91F585SG
MB91F585SH
MB91F585SJ
MB91F585SK
Flash memory capacity (program)
256+64 Kbytes
384+64 Kbytes
512+64 Kbytes
Flash memory capacity (work)
64 Kbytes
RAM capacity (main)
32 Kbytes
48 Kbytes
48 Kbytes
RAM capacity (backup)
8 Kbytes
• Function
Items
MB91F583SG
MB91F584SG
MB91F585SG
MB91F583SH
MB91F584SH
MB91F585SH
MB91F583SJ
MB91F584SJ
MB91F585SJ
MB91F583SK
MB91F584SK
MB91F585SK
System clock
On-chip PLL clock multiplication system
(Up to 32 times of multiplication)
Minimum instruction execution time: 7.81ns
(128MHz, source oscillation 4MHz × 32 times of multiplication)
CR oscillation
Provided
Oscillation stop feature
during stand-by
Provided Provided Not provided Not provided
External bus interface
Not provided
DMA transfer
8 channels
16-bit base timer
2 channels
Free-run timer
6 channels
Input capture
4 channels
Output compare
7 channels
Waveform generator
2 unit (7channels)
16-bit reload timer
4 channels
PPG
6 channels
External interrupt
7 channels
A/D converter
3 units (17 channels)
R/D converter
Not provided
D/A converter
Provided
Up/ down counter
2 channels
Multi-function serial
interface
2 channels
CAN
64msb × 1 channel (ch.0)
FlexRay
128msb × 1unit
(ch.A / ch.B)
Not provided
128msb × 1unit
(ch.A / ch.B)
Not provided
Software watchdog
Provided
Hardware watchdog
Provided
CRC generation
2 channels
Low-voltage detection reset
(Internal low-voltage
detection)
Provided
Low-voltage detection reset
(External low-voltage
detection)
Provided
Device package
LQFP-64
Debug interface
Built-in OCD (On Chip Debug Unit)
Note: For details on the MB91580S series, see the "MB91580M/S Series HARDWARE MANUAL".
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SPANSION
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o LQFP-144 Pin Assignment M891F585LA/F586LA/F587LA/F585LC/F586LC/F587LC
m
«a:
m
«:2
«25
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DataSheet
8 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
PIN ASSIGNMENT
• LQFP-144 Pin Assignment MB91F585LA/F586LA/F587LA/F585LC/F586LC/F587LC
(TOP VIEW)
VCC5
P014/TIOB1
P013/TIOA1
P012/TIOB0
P011/TIOA0
P010/RXDB
P007/TXDB
P006/SCS2/TXENB
P005/SCK2/RXDA
P004/SOT2/TXDA
P003/SIN2/TXENA/INT3
P002/SCK1
P001/SOT1
P000/SIN1/INT2
C
VSS
VCC5
P134/IN7/STOPWT/INT7/RX2
P133/ADTG2/TX2
P132/ADTG1/SCS1
P131/ADTG0
RSTX
VSS
X1
X0
MD1
MD0
P130/SCK0
P127/SOT0
P126/SIN0/INT6
P125/RTO11
P124/RTO10
DEBUGIF
VCC5
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VSS 1108 VSS
P015/TRG0 2 107 P123/RTO9
P016/TRG1 3 106 P122/RTO8
P017/TRG2 4 105 P121/RTO7/PPG23
P020/TRG3/SIN3_1 5 104 P120/RTO6/PPG22
P021/TRG4/SOT3_1 6 103 P117/RTO5/PPG21
P022/TRG5/SCK3_1 7 102 P116/RTO4/PPG20
P023/TIN0/SCS3_1 8 101 P115/RTO3/PPG19
P024/TIN1/SIN4_1 9 100 P114/RTO2/PPG18
P025/TIN2/SOT4_1 10 99 P113/RTO1/PPG17
P026/TIN3/SCK4_1 11 98 P112/RTO0/PPG16
P027/TOT0/SCS40_1 12 97 P111/RX1/INT1
P030/TOT1/SCS41_1 13 96 P110/TX1
P031/TOT2/SCS42_1 14 95 NMIX
P032/TOT3/SCS43_1 15 94 VSS
P033 16 93 VCC5
P034 17 92 P107/AN23/PPG15
VCC5 18 91 P106/AN22/PPG14
VSS 19 90 P105/AN21/PPG13
P035/AIN0/RDC_U 20 89 P104/AN20/PPG12
P036/BIN0/RDC_V 21 88 P103/AN19/PPG11
P037/ZIN0/RDC_W 22 87 P102/AN18/PPG10
P040/AIN1/RDC_A 23 86 P101/AN17/PPG9
P041/BIN1/RDC_B 24 85 P100/AN16/PPG8
P042/ZIN1/RDC_Z 25 84 AVCC3
RDC_ACT 26 83 AVRH3
MAG_OUT 27 82 AVSS3/AVRL3
MAG_PLUS 28 81 P097/IN5
MAG_MINUS 29 80 P096/RX0/INT0
COS_OUT 30 79 P095/TX0
COS_MINUS 31 78 P094/IN4
77 P093/IN3
COS_PLUS 32
SIN_PLUS 33 76 P092/IN2
SIN_MINUS 34 75 P091/IN1
SIN_OUT 35 74 P090/IN0
VCC5 36 73 VSS
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VSS
COS_IN
SIN_IN
AVCC0
AREF2
AVRH0
AVSS0/AVRL0
P060/MM
P061/IN6
P062/FRCK0/SCS40
P063/FRCK1/SCS41
P064/FRCK2/SCS42
P065/FRCK3/SCS43
P066/FRCK4/SCS3
P067/FRCK5
AVRH1
AVSS1/AVRL1
P070/AN0
P071/AN1
P072/SIN4/INT5/AN2
P073/SOT4/AN3
P074/SCK4/AN4
P075/SIN3/INT4/AN5
P076/SOT3/AN6
P077/SCK3/AN7
AVRH2
AVSS2/AVRL2
P080/PPG0/AN8
P081/PPG1/AN9
P082/PPG2/AN10
P083/PPG3/AN11
P084/PPG4/AN12
P085/PPG5/AN13
P086/PPG6/AN14
P087/PPG7/AN15
VCC5
P137/DTTI1
P136/DTTI0/MONCLK
LQFP-144
(FTP-144P-M08)
/'\
SPANSION
‘
o M391F585LB/F586LB/F587LB/F585LD/F586LD/F587LD
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 9
CONFIDENTIAL
• MB91F585LB/F586LB/F587LB/F585LD/F586LD/F587LD
(TOP VIEW)
VCC5
P014/TIOB1/D28
P013/TIOA1/D27
P012/TIOB0/D26
P011/TIOA0/D25
P010/RXDB/D24
P007/TXDB/D23
P006/SCS2/TXENB/D22
P005/SCK2/RXDA/D21
P004/SOT2/TXDA/D20
P003/SIN2/TXENA/INT3/D19
P002/SCK1/D18
P001/SOT1/D17
P000/SIN1/INT2/D16
C
VSS
VCC5
P134/IN7/STOPWT/INT7/RX2
P133/ADTG2/TX2
P132/ADTG1/SCS1
P131/ADTG0
RSTX
VSS
X1
X0
MD1
MD0
P130/SCK0
P127/SOT0
P126/SIN0/INT6
P125/RTO11
P124/RTO10
DEBUGIF
VCC5
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VSS 1108 VSS
P015/TRG0/D29 2 107P123/RTO9
P016/TRG1/D30 3 106P122/RTO8
P017/TRG2/D31 4 105P121/RTO7/PPG23
P020/TRG3/SIN3_1/ASX 5 104P120/RTO6/PPG22
P021/TRG4/SOT3_1/CS0X 6 103P117/RTO5/PPG21
P022/TRG5/SCK3_1/CS1X 7 102P116/RTO4/PPG20
P023/TIN0/SCS3_1/RDX 8 101P115/RTO3/PPG19
P024/TIN1/SIN4_1/WR0X 9 100P114/RTO2/PPG18
P025/TIN2/SOT4_1/WR1X 10 99 P113/RTO1/PPG17
P026/TIN3/SCK4_1/A00 11 98P112/RTO0/PPG16
P027/TOT0/SCS40_1/A01 12 97 P111/RX1/INT1
P030/TOT1/SCS41_1/A02 13 96P110/TX1
P031/TOT2/SCS42_1/A03 14 95 NMIX
P032/TOT3/SCS43_1/A04 15 94 VSS
P033/A05 16 93 VCC5
P034/A06 17 92P107/AN23/PPG15
VCC5 18 91 P106/AN22/PPG14
VSS19 90 P105/AN21/PPG13
P035/AIN0/A07 20 89 P104/AN20/PPG12
P036/BIN0/A08 21 88 P103/AN19/PPG11
P037/ZIN0/A09 22 87 P102/AN18/PPG10
P040/AIN1/A10 23 86 P101/AN17/PPG9
P041/BIN1/A11 24 85P100/AN16/PPG8
P042/ZIN1/A12 25 84 AVCC3
P043/A13 26 83 AVRH3
P044/DAOUT/A14 27 82 AVSS3/AVRL3
P045/A15 28 81 P097/IN5
P046/A16 29 80P096/RX0/INT0
P047/A17 30 79 P095/TX0
P050/A18 31 78P094/IN4
77P093/IN3
P051/A19 32
P052/A20 33 76 P092/IN2
P053/A21 34 75P091/IN1
P054/SYSCLK 35 74 P090/IN0
VCC5 36 73 VSS
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VSS
P055/CS2X
P056/CS3X
AVCC0
P057/RDY
AVRH0
AVSS0/AVRL0
P060/MM
P061/IN6
P062/FRCK0/SCS40
P063/FRCK1/SCS41
P064/FRCK2/SCS42
P065/FRCK3/SCS43
P066/FRCK4/SCS3
P067/FRCK5
AVRH1
AVSS1/AVRL1
P070/AN0
P071/AN1
P072/SIN4/INT5/AN2
P073/SOT4/AN3
P074/SCK4/AN4
P075/SIN3/INT4/AN5
P076/SOT3/AN6
P077/SCK3/AN7
AVRH2
AVSS2/AVRL2
P080/PPG0/AN8
P081/PPG1/AN9
P082/PPG2/AN10
P083/PPG3/AN11
P084/PPG4/AN12
P085/PPG5/AN13
P086/PPG6/AN14
P087/PPG7/AN15
VCC5
LQFP-144
P137/DTTI1
P136/DTTI0/MONCLK
(FPT-144P-M08)
/\
SPANSION
‘
- M391F585LA/F586LA/F587LA/F585LC/F586LC/F587LC
IIO circuit
type‘
11% x0 Main clock oscillation input pin
119 x1 Main clock oscillation output pin
95 NMlX B Interrupt input pin without mask
123 RSTX B External reset input pin
116 MDU C Mode pin 0 [with higlwoltage control)
117 MB] C Mode pin 1 [with higlwoltage control)
P000 (iencralrpurpose 10 port
1NT2 1NT2 external interrupt input pin
SIN] Multifunction serial cli.1 serial data input pin
P001 (iencralrpurpose 1, 0 port
Multifunction serial ch.l serial data output pin
1c ch.1 serial data 10 pin (SDA)
P002 (iencralrpurpose 10 port
Multifunction serial c11.l clock 1,0 pin/
1c ch.1 clock 1/0 pin (SCL)
P003 (iencralrpurpose 10 port
TXENA FlexRay Ch.A operation enable output pin
1NT3 1NT3 external interrupt input pin
5th Multifunction serial cli.2 serial data input pin
P004 (iencralrpurpose 10 port
TXDA FlexRay ch.A data output pin
SOTZ Multifunction serial ch.2 serial data output pin
P005 (iencralrpurpose 10 port
RXDA FlexRay Ch.A data input pin
SCKZ Multifunction serial c112 clock 1,0 pin
P006 (iencralrpurpose 10 port
TXENB FlexRay ch.B operation enable output pin
SCSZ Multifunction serial c112 serial chip select 1’0 pin
P007 (iencralrpurpose 10 port
TXDB FlexRay ch.B data output pin
P010 (iencralrpurpose 1, 0 port
RXDB FlexRay ch.B data input pin
P011 (iencralrpurpose 10 port
T1()A(J Base timer chtU T1()A 1, 0 pin
P012 (iencralrpurpose 1, 0 port
TIOBO Base timer chtU T103 [/0 pin
P013 (iencralrpurpose 1, 0 port
T1()A1 Base timer c1111 T1()A 1,0 pin
P014 (iencralrpurpose 1, 0 port
TIOBI Base timer c1111 T103 [/0 pin
P015 (iencralrpurpose 1, 0 port
TRGO PPG (31110 to clt.3 external trigger
P016 (iencralrpurpose 1, 0 port
TRGI PPG (31114 to clt.7 external trigger
DataSheet
10 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
PIN DESCRIPTION
• MB91F585LA/F586LA/F587LA/F585LC/F586LC/F587LC
Pin No. Pin name
I/O circuit
type*
Function
118
X0
A
Main clock oscillation input pin
119
X1
Main clock oscillation output pin
95
NMIX
B
Interrupt input pin without mask
123
RSTX
B
External reset input pin
116
MD0
C
Mode pin 0 (with high-voltage control)
117
MD1
C
Mode pin 1 (with high-voltage control)
131
P000
E
General-purpose I/O port
INT2
INT2 external interrupt input pin
SIN1
Multi-function serial ch.1 serial data input pin
132
P001
K
General-purpose I/O port
SOT1
Multi-function serial ch.1 serial data output pin/
I
2
C ch.1 serial data I/O pin (SDA)
133
P002
K
General-purpose I/O port
SCK1
Multi-function serial ch.1 clock I/O pin/
I
2
C ch.1 clock I/O pin (SCL)
134
P003
O
General-purpose I/O port
TXENA
FlexRay ch.A operation enable output pin
INT3
INT3 external interrupt input pin
SIN2
Multi-function serial ch.2 serial data input pin
135
P004
N
General-purpose I/O port
TXDA
FlexRay ch.A data output pin
SOT2
Multi-function serial ch.2 serial data output pin
136
P005
N
General-purpose I/O port
RXDA
FlexRay ch.A data input pin
SCK2
Multi-function serial ch.2 clock I/O pin
137
P006
N
General-purpose I/O port
TXENB
FlexRay ch.B operation enable output pin
SCS2
Multi-function serial ch2 serial chip select I/O pin
138
P007
N
General-purpose I/O port
TXDB
FlexRay ch.B data output pin
139
P010
N
General-purpose I/O port
RXDB
FlexRay ch.B data input pin
140
P011
D
General-purpose I/O port
TIOA0
Base timer ch.0 TIOA I/O pin
141
P012
D
General-purpose I/O port
TIOB0
Base timer ch.0 TIOB I/O pin
142
P013
D
General-purpose I/O port
TIOA1
Base timer ch.1 TIOA I/O pin
143
P014
D
General-purpose I/O port
TIOB1
Base timer ch.1 TIOB I/O pin
2
P015
D
General-purpose I/O port
TRG0
PPG ch.0 to ch.3 external trigger
3
P016
D
General-purpose I/O port
TRG1
PPG ch.4 to ch.7 external trigger
/'\
S PA N 5 IO N
‘
IIO circuit
type‘
P017 (icncralrpurposc 1,0 pert
TRGZ PPG ehtx to ch.11 external trigger
P020 (icncralrpurposc 1,0 pert
TRG} PPG chtlZ to 011.15 external triggcr
SINLI Multirfunction serial ch: serial data input pin (1)
P021 (icncralrpurposc 1,0 pert
TRG4 PPG [6 lo PPG [9 external triggcr
Multifunction scrial c113 serial data output pin (l)/
1 c ch.3 serial data 10 pin(l) (SDA)
P022 (icncralrpurposc 1,0 pert
TRGS PPG c1120 to 011.23 external triggcr
Multirfunction serial c113 clock 1,0 pin [1),
1c ch.3 eloek 1/0 pin (l)(SCL)
P023 (icncralrpurposc 1,0 pert
T1N0 Reload timer eh.0 cvcnt input pin
scs371 Multirfunction serial ch: serial chip select 1'0 pin ( l 1
P024 (icncralrpurposc 1,0 pert
TIN] Reload timer ch.l cvcnt input pin
SIN47| Multirfunction serial ch.4 serial data input pin (1)
P025 (icncralrpurposc 1,0 pert
TIN2 Reload timer ch.2 cvcnt input pin
Multifunction scrial ch.4 serial data output pin (l)/
1 c eh.4 serial data 10 pin (1) (SDA)
P026 (icncralrpurposc 1,0 pert
TIN3 Reload timer ch.3 cvcnt input pin
Multirfunction serial ch.4 clock 1,0 pin [1),
1c eh.4 eloek 1/0 pin (1) (SCL)
P027 (icncralrpurposc 1,0 pert
TOTO Reload timer eh.0 output pin
SCSAOJ Multirfunction serial ch.4 serial chip seleet01,0 pin ( l 1
P030 (icncralrpurposc 1,0 pert
TOTl Reload timer ch.l output pin
SCSAlil Multirfunction serial ch.4 serial chip select 1 output pin (1)
P031 (icncralrpurposc 1,0 pert
TOTZ Reload timer ch.2 output pin
SCSAZil Multirfunction serial ch.4 serial chip select 2 output pin (1)
P032 (icncralrpurposc 1,0 pert
TOT} Reload timer ch.3 output pin
SCSASJ Multirfunction serial ch.4 serial chip select 3 output pin (1)
[6 P033 D (icncralrpurposc 1,0 port
17 P034 D (icncralrpurposc 1,0 pert
P035 (icncralrpurposc 1,0 pert
Al.\l() Up/ down cottnter ch.0 AIN input pin
RDC7U RDC phase U output pin
P036 (icncralrpurposc 1,0 pert
131N0 Up/ down cottnter ch.0 BIN input pin
RDC7V RDC phase v output pin
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 11
CONFIDENTIAL
Pin No. Pin name
I/O circuit
type*
Function
4
P017
D
General-purpose I/O port
TRG2
PPG ch.8 to ch.11 external trigger
5
P020
D
General-purpose I/O port
TRG3
PPG ch.12 to ch.15 external trigger
SIN3_1
Multi-function serial ch.3 serial data input pin (1)
6
P021
K
General-purpose I/O port
TRG4
PPG16 to PPG19 external trigger
SOT3_1
Multi-function serial ch.3 serial data output pin (1)/
I
2
C ch.3 serial data I/O pin (1) (SDA)
7
P022
K
General-purpose I/O port
TRG5
PPG ch.20 to ch.23 external trigger
SCK3_1
Multi-function serial ch.3 clock I/O pin (1)/
I
2
C ch.3 clock I/O pin (1) (SCL)
8
P023
D
General-purpose I/O port
TIN0
Reload timer ch.0 event input pin
SCS3_1
Multi-function serial ch.3 serial chip select I/O pin (1)
9
P024
D
General-purpose I/O port
TIN1
Reload timer ch.1 event input pin
SIN4_1
Multi-function serial ch.4 serial data input pin (1)
10
P025
K
General-purpose I/O port
TIN2
Reload timer ch.2 event input pin
SOT4_1
Multi-function serial ch.4 serial data output pin (1)/
I
2
C ch.4 serial data I/O pin (1) (SDA)
11
P026
K
General-purpose I/O port
TIN3
Reload timer ch.3 event input pin
SCK4_1
Multi-function serial ch.4 clock I/O pin (1)/
I
2
C ch.4 clock I/O pin (1) (SCL)
12
P027
D
General-purpose I/O port
TOT0
Reload timer ch.0 output pin
SCS40_1
Multi-function serial ch.4 serial chip select 0 I/O pin (1)
13
P030
D
General-purpose I/O port
TOT1
Reload timer ch.1 output pin
SCS41_1
Multi-function serial ch.4 serial chip select 1 output pin (1)
14
P031
D
General-purpose I/O port
TOT2
Reload timer ch.2 output pin
SCS42_1
Multi-function serial ch.4 serial chip select 2 output pin (1)
15
P032
D
General-purpose I/O port
TOT3
Reload timer ch.3 output pin
SCS43_1
Multi-function serial ch.4 serial chip select 3 output pin (1)
16
P033
D
General-purpose I/O port
17
P034
D
General-purpose I/O port
20
P035
D
General-purpose I/O port
AIN0
Up/ down counter ch.0 AIN input pin
RDC_U
RDC phase U output pin
21
P036
D
General-purpose I/O port
BIN0
Up/ down counter ch.0 BIN input pin
RDC_V
RDC phase V output pin
/\
5 PA N 5 IO N
‘
IIO circuit
type‘
P037 (ieneralrpurpose 1,0 pert
ZlNO Up/ down counter eh.0 ZIN input pin
RDCiw RDC phase w output pin
P040 (ieneralrpurpose 1,0 pert
Al.\l1 Up/ down counter eh.l AIN input pin
RDCiA RDC phase A output pin
P041 (ieneralrpurpose 1,0 pert
BlNl Up/ down counter eh.l BIN input pin
RDCiB RDC phase B output pin
P042 (ieneralrpurpose 1,0 pert
ZlNl Up/ down counter eh.l ZIN input pin
RDCiz RDC phase 2 output pin
26 RDciACT J RDC operation status output pin
27 MAGiOUT 1 RDC exeitatieu signal output pin
28 MAGiPLUS 1-1 RDC exeitatieu external input pin +
29 MAGiMlNUS 1-1 RDC exeitatieu external input pin ,
30 C0870UT 1 RDC cos output pin
31 COSiMINUS 1-1 RDC cos input pin ,
32 COSJ’LUS 1-1 RDC cos input pin +
33 SlNiPLUS 1-1 RDC Sl.\l input piu +
34 SINiMINUS 1-1 RDC Sl.\l input piu ,
35 SlN7()UT 1 RDC Sl.\l output pin
38 COSJN 1-1 RDC cos eoil earth leakage detection iuput pin
39 SlNilN 1-1 RDC Sl.\l eoil earth leakage detection input pin
41 AREFZ 1 RDC Arefoutput (AVeeo/2) pin
P050 (ieneralrpurpose 1,0 pert
MM Cloek supervisor main clock missing output pin
P051 (ieneralrpurpose 1,0 pert
1N6 l6rbit input eapture eh.5 external pulse input piu
P052 (ieneralrpurpose 1,0 pert
FRCKU Freerrun timer ehtU external clock input pin
SCSAO Multirfunction serial eh.4 serial chip select 0 1,0 pin
P053 (ieneralrpurpose 1,0 pert
FRCKI Freerrun timer C1111 external clock input pin
SCSAI Multirfunction serial ch.4 serial ehip select 1 output piu
P054 (ieneralrpurpose 1,0 pert
FRCKZ Freerrun timer e112 external clock input pin
scssz Multirfunction serial ch.4 serial ehip select 2 output piu
P055 (ieneralrpurpose 1,0 pert
FRCK3 Freerrun timer e113 external clock input pin
scsu Multirfunction serial ch.4 serial ehip select 3 output piu
P055 (ieneralrpurpose 1,0 pert
FRCK4 Freerrun timer ehA external clock input pin
SCS3 Multirfunction serial e113 serial chip select 1’0 pin
P057 (ieneralrpurpose 1,0 pert
FRCKS Freerrun timer ehts external clock input pin
DataSheet
12 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Pin No. Pin name
I/O circuit
type*
Function
22
P037
D
General-purpose I/O port
ZIN0
Up/ down counter ch.0 ZIN input pin
RDC_W
RDC phase W output pin
23
P040
D
General-purpose I/O port
AIN1
Up/ down counter ch.1 AIN input pin
RDC_A
RDC phase A output pin
24
P041
D
General-purpose I/O port
BIN1
Up/ down counter ch.1 BIN input pin
RDC_B
RDC phase B output pin
25
P042
D
General-purpose I/O port
ZIN1
Up/ down counter ch.1 ZIN input pin
RDC_Z
RDC phase Z output pin
26
RDC_ACT
J
RDC operation status output pin
27
MAG_OUT
I
RDC excitation signal output pin
28
MAG_PLUS
H
RDC excitation external input pin +
29
MAG_MINUS
H
RDC excitation external input pin -
30
COS_OUT
I
RDC COS output pin
31
COS_MINUS
H
RDC COS input pin -
32
COS_PLUS
H
RDC COS input pin +
33
SIN_PLUS
H
RDC SIN input pin +
34
SIN_MINUS
H
RDC SIN input pin -
35
SIN_OUT
I
RDC SIN output pin
38
COS_IN
H
RDC COS coil earth leakage detection input pin
39
SIN_IN
H
RDC SIN coil earth leakage detection input pin
41
AREF2
I
RDC Aref output (AVcc0/2) pin
44
P060
D
General-purpose I/O port
MM
Clock supervisor main clock missing output pin
45
P061
D
General-purpose I/O port
IN6
16-bit input capture ch.6 external pulse input pin
46
P062
D
General-purpose I/O port
FRCK0
Free-run timer ch.0 external clock input pin
SCS40
Multi-function serial ch.4 serial chip select 0 I/O pin
47
P063
D
General-purpose I/O port
FRCK1
Free-run timer ch.1 external clock input pin
SCS41
Multi-function serial ch.4 serial chip select 1 output pin
48
P064
D
General-purpose I/O port
FRCK2
Free-run timer ch.2 external clock input pin
SCS42
Multi-function serial ch.4 serial chip select 2 output pin
49
P065
D
General-purpose I/O port
FRCK3
Free-run timer ch.3 external clock input pin
SCS43
Multi-function serial ch.4 serial chip select 3 output pin
50
P066
D
General-purpose I/O port
FRCK4
Free-run timer ch.4 external clock input pin
SCS3
Multi-function serial ch.3 serial chip select I/O pin
51
P067
D
General-purpose I/O port
FRCK5
Free-run timer ch.5 external clock input pin
/'\
S PA N 5 IO N
‘
IIO circuit
type‘
P070 (icncralrpurposc 1, 0 port
ANo ADC analog 0 input pin
P071 (icncralrpurposc 1, 0 port
ANl ADC analog 1 input pin
P072 (icncralrpurposc 1, 0 port
AN2 ADC analog 2 input pin
SIN4 Multifunction serial ch.4 serial data input pin
1NT5 lNTs external interrupt input pin
P073 (icncralrpurposc 1, 0 port
AN} ADC analog 3 input pin
Multifunction serial ch.4 serial data output pin
1 c eh.4 serial data 10 pin (SDA)
P074 (icncralrpurposc 1, 0 port
AN4 ADC analog 4 input pin
Multifunction serial ch.4 clock 1,0 pin/
1 c ch.4 eloek 1/0 pin (SCL)
P075 (icncralrpurposc 1,0 port
AN5 ADC analog 5 input pin
stN3 Multifunction serial en: serial data input pin
1NT4 1NT4 external interrupt input pin
P076 (icncralrpurposc 1, 0 port
ANti ADC analog 5 input pin
Multifunction serial c113 serial data output pin
1 C ch.3 serial data 1’0 pin (SDA)
P077 (icncralrpurposc 1,0 port
AN7 ADC analog 7 input pin
Multifunction serial c113 clock 1,0 pin/
1C ch.3 clock [/0 pin (SCL)
P080 (icncralrpurposc 1,0 port
AN8 ADC analog 8 input pin
PP(i0 PPG CILU output pin
P081 (icncralrpurposc 1, 0 port
AN9 ADC analog 9 input pin
PP(i1 PPG c1111 output pin
P082 (icncralrpurposc 1, 0 port
AN 10 ADC analog 10 input pin
PP(i2 PPG c1112 output pin
P083 (icncralrpurposc 1, 0 port
ANll ADC analog 11 input pin
PP(i3 PPG clij output pin
P084 (icncralrpurposc 1, 0 port
AN 12 ADC analog 12 input pin
PPG4 PPG cliA output pin
P085 (icncralrpurposc 1, 0 port
AN 13 ADC analog 13 input pin
PP(i5 PPG this output pin
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 13
CONFIDENTIAL
Pin No. Pin name
I/O circuit
type*
Function
54
P070
F
General-purpose I/O port
AN0
ADC analog 0 input pin
55
P071
F
General-purpose I/O port
AN1
ADC analog 1 input pin
56
P072
G
General-purpose I/O port
AN2
ADC analog 2 input pin
SIN4
Multi-function serial ch.4 serial data input pin
INT5
INT5 external interrupt input pin
57
P073
M
General-purpose I/O port
AN3
ADC analog 3 input pin
SOT4
Multi-function serial ch.4 serial data output pin/
I
2
C ch.4 serial data I/O pin (SDA)
58
P074
M
General-purpose I/O port
AN4
ADC analog 4 input pin
SCK4
Multi-function serial ch.4 clock I/O pin/
I
2
C ch.4 clock I/O pin (SCL)
59
P075
G
General-purpose I/O port
AN5
ADC analog 5 input pin
SIN3
Multi-function serial ch.3 serial data input pin
INT4
INT4 external interrupt input pin
60
P076
M
General-purpose I/O port
AN6
ADC analog 6 input pin
SOT3
Multi-function serial ch.3 serial data output pin/
I
2
C ch.3 serial data I/O pin (SDA)
61
P077
M
General-purpose I/O port
AN7
ADC analog 7 input pin
SCK3
Multi-function serial ch.3 clock I/O pin /
I
2
C ch.3 clock I/O pin (SCL)
64
P080
F
General-purpose I/O port
AN8
ADC analog 8 input pin
PPG0
PPG ch.0 output pin
65
P081
F
General-purpose I/O port
AN9
ADC analog 9 input pin
PPG1
PPG ch.1 output pin
66
P082
F
General-purpose I/O port
AN10
ADC analog 10 input pin
PPG2
PPG ch.2 output pin
67
P083
F
General-purpose I/O port
AN11
ADC analog 11 input pin
PPG3
PPG ch.3 output pin
68
P084
F
General-purpose I/O port
AN12
ADC analog 12 input pin
PPG4
PPG ch.4 output pin
69
P085
F
General-purpose I/O port
AN13
ADC analog 13 input pin
PPG5
PPG ch.5 output pin
/\
5 PA N 5 10 N
‘
IIO circuit
type‘
P086 (icncralrpurposc 1 0 port
AN 14 ADC analog 14 input pin
PPG6 PPG cut. output pin
P087 (icncralrpurposc 1 0 port
AN 15 ADC analog 15 input pin
PPG7 PPG c1117 output pin
P090 (icncralrpurposc 1 0 port
1N0 [67bit input eapture eh.0 external pulse input pin
P091 (icncralrpurposc 1 0 port
l.\ll [67bit input eapture eh.l external pulse input pin
P092 (icncralrpurposc 1 0 port
1N2 [67bit input eapture eh.2 external pulse input pin
P093 (icncralrpurposc 1 0 port
1N3 [67bit input eapture eh.3 external pulse input pin
P094 (icncralrpurposc 1 0 port
1N4 [67bit input eapture eh.4 external pulse input pin
P095 (icncralrpurposc 1 0 port
TXO CAN transmission data 0 output pin
P096 (icncralrpurposc 1 0 port
Rx0 CAN reception data 0 input pin
1NTO lNTU external interrupt input pin
P097 (icncralrpurposc 1 0 port
1N5 [67bit input eapture eh.5 external pulse input pin
P100 (icncralrpurposc 1 0 port
PPGx PPG c1118 output pin
AN [6 ADC analog 15 input pin
P101 (icncralrpurposc 1 0 port
PPG9 PPG c1119 output pin
AN 17 ADC analog 17 input pin
P102 (icncralrpurposc 1 0 port
PPG 10 PPG chili) oulpm pin
AN 1 8 ADC analog 18 input pin
P103 (icncralrpurposc 1 0 port
PPGll PPG c1111 1 output pin
AN 19 ADC analog 19 input pin
P104 (icncralrpurposc 1 0 port
PPG 12 PPG ch12 output pin
AN20 ADC analog 20 input pin
P105 (icncralrpurposc 1 0 port
PPG 13 PPG ch13 output pin
AN21 ADC analog 21 input pin
P106 (icncralrpurposc 1 0 port
PPG 14 PPG ch14 output pin
AN22 ADC analog 22 input pin
P107 (icncralrpurposc 1 0 port
PPG 1 5 PPG ch15 output pin
AN23 ADC analog 23 input pin
DataSheet
14 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Pin No. Pin name
I/O circuit
type*
Function
70
P086
F
General-purpose I/O port
AN14
ADC analog 14 input pin
PPG6
PPG ch.6 output pin
71
P087
F
General-purpose I/O port
AN15
ADC analog 15 input pin
PPG7
PPG ch.7 output pin
74
P090
D
General-purpose I/O port
IN0
16-bit input capture ch.0 external pulse input pin
75
P091
D
General-purpose I/O port
IN1
16-bit input capture ch.1 external pulse input pin
76
P092
D
General-purpose I/O port
IN2
16-bit input capture ch.2 external pulse input pin
77
P093
D
General-purpose I/O port
IN3
16-bit input capture ch.3 external pulse input pin
78
P094
D
General-purpose I/O port
IN4
16-bit input capture ch.4 external pulse input pin
79
P095
D
General-purpose I/O port
TX0
CAN transmission data 0 output pin
80
P096
E
General-purpose I/O port
RX0
CAN reception data 0 input pin
INT0
INT0 external interrupt input pin
81
P097
D
General-purpose I/O port
IN5
16-bit input capture ch.5 external pulse input pin
85
P100
F
General-purpose I/O port
PPG8
PPG ch.8 output pin
AN16
ADC analog 16 input pin
86
P101
F
General-purpose I/O port
PPG9
PPG ch.9 output pin
AN17
ADC analog 17 input pin
87
P102
F
General-purpose I/O port
PPG10
PPG ch.10 output pin
AN18
ADC analog 18 input pin
88
P103
F
General-purpose I/O port
PPG11
PPG ch.11 output pin
AN19
ADC analog 19 input pin
89
P104
F
General-purpose I/O port
PPG12
PPG ch.12 output pin
AN20
ADC analog 20 input pin
90
P105
F
General-purpose I/O port
PPG13
PPG ch.13 output pin
AN21
ADC analog 21 input pin
91
P106
F
General-purpose I/O port
PPG14
PPG ch.14 output pin
AN22
ADC analog 22 input pin
92
P107
F
General-purpose I/O port
PPG15
PPG ch.15 output pin
AN23
ADC analog 23 input pin
/'\
S PA N 5 IO N
‘
IIO circuit
type‘
P110 (icncralrpurposc 1, 0 pen
TXl CAN Iransm 1sion dam 1 output pin
P111 (icncralrpurposc 1, 0 pen
RX] CAN reception data I inpm pin
lNTl lNTl exmmal imcrrupl inpm pin
P112 (icncralrpurposc 1, 0 pen
RTOO Waveform gcncrmor eh.0 omput pin
PPG ]6 PPG clLlé outpm pin
P 1 13 (icncralrpurposc 1,0 pen
RTOl Waveform generamr ch.1 omput pin
PPG 1 7 PPG e11117 outpm pin
P114 (icncralrpurposc 1, 0 pen
RTOZ Waveform generamr ch.2 omput pin
PPG 1 x PPG c1111 8 outpm pin
P1 15 (icncralrpurposc 1, 0 pen
RTO3 Waveform generamr ch.3 omput pin
PPG 19 PPG e11119 outpm pin
P 1 16 (icncralrpurposc 1, 0 pen
RT04 Waveform generamr ch.4 omput pin
PPGZO PPG c1120 outpm pin
P1 17 (icncralrpurposc 1, 0 pen
RTOS Waveform generamr ch.5 omput pin
PPGZI PPG clLZl outpm pin
P120 (icncralrpurposc 1, 0 pen
RT06 Waveform generamr ch.6 omput pin
PPGZZ PPG c1122 outpm pin
P121 (icncralrpurposc 1, 0 pen
RT07 Waveform generamr ch.7 omput pin
PPGZ3 PPG e112} outpm pin
P122 (icncralrpurposc 1, 0 pen
RTOX Waveform generamr ch.8 omput pin
P123 (icncralrpurposc 1, 0 pen
RTO9 Waveform generamr ch.9 omput pin
P124 (icncralrpurposc 1, 0 pen
RTOlO Waveform gcncrmor ch. 10 output pin
P125 (icncralrpurposc 1, 0 pen
RTOll Waveform gcncrmor ch. 11 outpul pin
P126 (icncralrpurposc 1, 0 pen
SINU Muhirfunction serial c111) serial dara inpm pin
lNTfi lNTfi exmmal imcrrupl inpm pin
P127 (icncralrpurposc 1, 0 pen
Muhirfunction serial c111) serial dam output pin
1 C ch.() serial data 1’0 pin (SDA)
P130 (icncralrpurposc 1,0 port
Muhirfunction serial c111) clock 1, 0 pin/
1 c ch.() clock 1/0 pm (SCL)
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 15
CONFIDENTIAL
Pin No. Pin name
I/O circuit
type*
Function
96
P110
D
General-purpose I/O port
TX1
CAN transmission data 1 output pin
97
P111
E
General-purpose I/O port
RX1
CAN reception data 1 input pin
INT1
INT1 external interrupt input pin
98
P112
D
General-purpose I/O port
RTO0
Waveform generator ch.0 output pin
PPG16
PPG ch.16 output pin
99
P113
D
General-purpose I/O port
RTO1
Waveform generator ch.1 output pin
PPG17
PPG ch.17 output pin
100
P114
D
General-purpose I/O port
RTO2
Waveform generator ch.2 output pin
PPG18
PPG ch.18 output pin
101
P115
D
General-purpose I/O port
RTO3
Waveform generator ch.3 output pin
PPG19
PPG ch.19 output pin
102
P116
D
General-purpose I/O port
RTO4
Waveform generator ch.4 output pin
PPG20
PPG ch.20 output pin
103
P117
D
General-purpose I/O port
RTO5
Waveform generator ch.5 output pin
PPG21
PPG ch.21 output pin
104
P120
D
General-purpose I/O port
RTO6
Waveform generator ch.6 output pin
PPG22
PPG ch.22 output pin
105
P121
D
General-purpose I/O port
RTO7
Waveform generator ch.7 output pin
PPG23
PPG ch.23 output pin
106
P122
D
General-purpose I/O port
RTO8
Waveform generator ch.8 output pin
107
P123
D
General-purpose I/O port
RTO9
Waveform generator ch.9 output pin
111
P124
D
General-purpose I/O port
RTO10
Waveform generator ch.10 output pin
112
P125
D
General-purpose I/O port
RTO11
Waveform generator ch.11 output pin
113
P126
E
General-purpose I/O port
SIN0
Multi-function serial ch.0 serial data input pin
INT6
INT6 external interrupt input pin
114
P127
K
General-purpose I/O port
SOT0
Multi-function serial ch.0 serial data output pin/
I
2
C ch.0 serial data I/O pin (SDA)
115
P130
K
General-purpose I/O port
SCK0
Multi-function serial ch.0 clock I/O pin/
I
2
C ch.0 clock I/O pin (SCL)
/\
5 PA N 5 IO N
‘
IIO circuit
type‘
1>131 Generalrpurpose 1,0 port
ADTGO A/D converter clLU to ch.7 external trigger input pin
P132 Generalrpurpose 1,0 port
ADTG] A/D converter chtx to ch. 1 5 external trigger input pin
SCSI Multirfunction serial eh.l serial ehip select 1’0 pin
1>133 Generalrpurpose 1,0 port
ADTGZ A/D converter clrlé to ch23 external trigger input pin
TXZ CAN transmission data 2 output pin
P1 34 Generalrpurpose 1,0 port
STOPWT FlexRay Stopwatch input pin
RX2 CAN reception data 2 input pin
1NT7 1NT7 external interrupt input pin
l.\l7 [67bit input capture ch.7 external pulse input pin
110 DEBUGIF L DEBUG l’F pin
P1 35 Generalrpurpose 1,0 port
DTTlDataSheet
16 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Pin No. Pin name
I/O circuit
type*
Function
124
P131
D
General-purpose I/O port
ADTG0
A/D converter ch.0 to ch.7 external trigger input pin
125
P132
D
General-purpose I/O port
ADTG1
A/D converter ch.8 to ch.15 external trigger input pin
SCS1
Multi-function serial ch.1 serial chip select I/O pin
126
P133
D
General-purpose I/O port
ADTG2
A/D converter ch.16 to ch.23 external trigger input pin
TX2
CAN transmission data 2 output pin
127
P134
E
General-purpose I/O port
STOPWT
FlexRay Stopwatch input pin
RX2
CAN reception data 2 input pin
INT7
INT7 external interrupt input pin
IN7
16-bit input capture ch.7 external pulse input pin
110
DEBUGIF
L
DEBUG I/F pin
121
P136
D
General-purpose I/O port
DTTI0
Waveform generator output stop signal input pin 0
MONCLK
Clock monitor output pin
122
P137
D
General-purpose I/O port
DTTI1
Waveform generator output stop signal input pin 1
40
AV C C 0
-
R/D converter power supply
84
AV C C 3
-
A/D converter analog power supply
42
AVRH0
-
R/D converter upper limit reference voltage power supply
52
AVRH1
-
A/D converter upper limit reference voltage
62
AVRH2
-
A/D converter upper limit reference voltage
83
AVRH3
-
A/D converter upper limit reference voltage
43
AVSS0
-
R/D converter GND
AV R L 0
R/D converter lower limit reference voltage
53
AVSS1
-
A/D converter GND
AV R L 1
A/D converter lower limit reference voltage
63
AV SS2
-
A/D converter GND
AV R L 2
A/D converter lower limit reference voltage
82
AVSS3
-
A/D converter GND
AV R L 3
A/D converter lower limit reference voltage
130
C
-
External capacity connection output
18, 36,
93, 72,
109, 128,
144
VCC5 - +5.0V power supply
1, 19, 37,
73, 94,
108, 120,
129
VSS
- GND
*: For the I/O circuit types, see "■ I/O circuit type".
/'\
S PA N 5 IO N
‘
o M891F585LB/F586LB/F587LB/F585LD/F586LD/F587LD
IIO circuit
type ‘
[18 x0 Main clock oscillation input pin
119 x1 Main clock oscillation output pin
95 NMIX B Interrupt input pin without mask
123 RSTX B External resct input pin
[16 MD!) C Mode pin 0 (with highwoltage control)
117 MDl C Mode pin 1 (with highwoltage control)
P000 Generalrpurpose 1/0 port
D16 External bus data bitl 6 [/0 pin
1NT2 INTZ external internipt input pin
SlNl Multirfunction serial ch.l serial data input pin
P001 Generalrpurpose 1/0 port
Dl 7 External bus data bitl 7 [/0 pin
Multirfunction serial ch.l serial data output pin/
I C chtl serial data [/0 pin (SBA)
P002 Generalrpurpose 1/0 port
D18 External bus data bitl X [/0 pin
Multirfunction serial ch.l clock [/() pin,
1 C chtl clock 10 pin (SCL)
PUU3 Generalrpurpose 1/0 port
D19 External bus data bit] 9 [/0 pin
TXENA FlexRay eh.A operation enablc output pin
1NT3 INT} external internipt input pin
SlN2 Multirfunction serial ch.2 serial data input pin
P004 Generalrpurpose 1/0 port
D20 External bus data bit2(J [/0 pin
TXDA FlexRay eh.A data output pin
SOTZ Multirfunction serial eh.2 serial data output pin
P005 Generalrpurpose 1/0 port
D2l External bus data bitZl [/0 pin
RXDA FlexRay eh.A data input pin
SCKZ Multirfunction serial ch.2 clock [/() pin
PUUfi Generalrpurpose 1/0 port
D22 External bus data bit22 [/0 pin
TXENB FlexRay ch.B operation enable output pin
SCSZ Multirfunction serial ch.2 serial ehip select [/0 pin
P007 Generalrpurpose 1/0 port
D23 External bus data bit23 [/0 pin
TXDB FlexRay eh.B data output pin
P010 Generalrpurpose 1/0 port
D24 External bus data bit24 [/0 pin
RXDB FlexRay ch.B data input pin
P011 Generalrpurpose 1/0 port
D25 External bus data bit25 [/0 pin
TIOAU Base timer 011.0 TIOA [/() pin
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 17
CONFIDENTIAL
• MB91F585LB/F586LB/F587LB/F585LD/F586LD/F587LD
Pin No. Pin name
I/O circuit
type
*1
Function
118
X0
A
Main clock oscillation input pin
119
X1
Main clock oscillation output pin
95
NMIX
B
Interrupt input pin without mask
123
RSTX
B
External reset input pin
116
MD0
C
Mode pin 0 (with high-voltage control)
117
MD1
C
Mode pin 1 (with high-voltage control)
131
P000
E
General-purpose I/O port
D16
External bus data bit16 I/O pin
INT2
INT2 external interrupt input pin
SIN1
Multi-function serial ch.1 serial data input pin
132
P001
K
General-purpose I/O port
D17
External bus data bit17 I/O pin
SOT1
Multi-function serial ch.1 serial data output pin/
I
2
C ch.1 serial data I/O pin (SDA)
133
P002
K
General-purpose I/O port
D18
External bus data bit18 I/O pin
SCK1
Multi-function serial ch.1 clock I/O pin /
I
2
C ch.1 clock I/O pin (SCL)
134
P003
O
General-purpose I/O port
D19
External bus data bit19 I/O pin
TXENA
FlexRay ch.A operation enable output pin
INT3
INT3 external interrupt input pin
SIN2
Multi-function serial ch.2 serial data input pin
135
P004
N
General-purpose I/O port
D20
External bus data bit20 I/O pin
TXDA
FlexRay ch.A data output pin
SOT2
Multi-function serial ch.2 serial data output pin
136
P005
N
General-purpose I/O port
D21
External bus data bit21 I/O pin
RXDA
FlexRay ch.A data input pin
SCK2
Multi-function serial ch.2 clock I/O pin
137
P006
N
General-purpose I/O port
D22
External bus data bit22 I/O pin
TXENB
FlexRay ch.B operation enable output pin
SCS2
Multi-function serial ch.2 serial chip select I/O pin
138
P007
N
General-purpose I/O port
D23
External bus data bit23 I/O pin
TXDB
FlexRay ch.B data output pin
139
P010
N
General-purpose I/O port
D24
External bus data bit24 I/O pin
RXDB
FlexRay ch.B data input pin
140
P011
D
General-purpose I/O port
D25
External bus data bit25 I/O pin
TIOA0
Base timer ch.0 TIOA I/O pin
/\
5 PA N 5 10 N
‘
IIO circuit
type ‘
P012 (ieneralrpllrpose 1/0 port
D26 External bus data bitZfi [/0 pin
T1080 Base timer 011.0 TIOB 1’0 pin
P013 (ieneralrpllrpose 1/0 port
D27 External bus data bitZ7 [/0 pin
TIOAl Base timer 011.1 TIOA [/0 pin
P014 (ieneralrpllrpose 1/0 port
D28 External bus data bitZX [/0 pin
T1081 Base timer 011.1 TIOB 1’0 pin
P015 (ieneralrpllrpose 1/0 port
D29 External bus data bitZ‘) [/0 pin
TRGO PPG 0h.() to 011.3 external trigger
P016 (ieneralrpllrpose 1/0 port
D30 External bus data bit3DataSheet
18 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Pin No. Pin name
I/O circuit
type
*1
Function
141
P012
D
General-purpose I/O port
D26
External bus data bit26 I/O pin
TIOB0
Base timer ch.0 TIOB I/O pin
142
P013
D
General-purpose I/O port
D27
External bus data bit27 I/O pin
TIOA1
Base timer ch.1 TIOA I/O pin
143
P014
D
General-purpose I/O port
D28
External bus data bit28 I/O pin
TIOB1
Base timer ch.1 TIOB I/O pin
2
P015
D
General-purpose I/O port
D29
External bus data bit29 I/O pin
TRG0
PPG ch.0 to ch.3 external trigger
3
P016
D
General-purpose I/O port
D30
External bus data bit30 I/O pin
TRG1
PPG ch.4 to ch.7 external trigger
4
P017
D
General-purpose I/O port
D31
External bus data bit31 I/O pin
TRG2
PPG ch.8 to ch.11 external trigger
5
P020
D
General-purpose I/O port
ASX
External bus address strobe output pin
TRG3
PPG ch.12 to ch.15 external trigger
SIN3_1
Multi-function serial ch.3 serial data input pin (1)
6
P021
K
General-purpose I/O port
CS0X
External bus chip select 0 output pin
TRG4
PPG16 to PPG19 external trigger
SOT3_1
Multi-function serial ch.3 serial data output pin (1)/
I
2
C ch.3 serial data I/O pin (1) (SDA)
7
P022
K
General-purpose I/O port
CS1X
External bus chip select 1 output pin
TRG5
PPG ch.20 to ch.23 external trigger
SCK3_1
Multi-function serial ch.3 clock I/O pin (1)/
I
2
C ch.3 clock I/O pin (1) (SCL)
8
P023
D
General-purpose I/O port
RDX
External bus read strobe output pin
TIN0
Reload timer ch.0 event input pin
SCS3_1
Multi-function serial ch.3 serial chip select I/O pin (1)
9
P024
D
General-purpose I/O port
WR0X
External bus write strobe 0 output pin
TIN1
Reload timer ch.1 event input pin
SIN4_1
Multi-function serial ch.4 serial data input pin (1)
10
P025
K
General-purpose I/O port
WR1X
External bus write strobe 1 output pin
TIN2
Reload timer ch.2 event input pin
SOT4_1
Multi-function serial ch.4 serial data output pin (1)/
I
2
C ch.4 serial data I/O pin (1) (SDA)
/'\
S PA N 5 IO N
‘
IIO circuit
type ‘
P026 (icncralrpllrposc 1/0 port
A00 External bus address bito output pin
T1N3 Reload timer all} event input pin
Multifunction serial ch.4 clock 1/0 pin (1 )/
1 C ehl4 eloek 1'0 pin(l) (SCL)
P027 (icncralrpllrposc 1/0 port
AUl External bus address bitl output pin
T()T(J Reload timer eli.0 otttput pin
scs4071 Multifunction serial ch.4 serial chip select 0 1/0 pin (1)
P030 (icncralrpllrposc 1/0 port
A02 External bus address bit2 output pin
TOT] Reload timer ch.l output pin
SCSALI Multifunction serial ch.4 serial chip select 1 output pin ( l )
P03l (icncralrpllrposc 1/0 port
A03 External bus address bit} output pin
T()T2 Reload timer c112 output pin
SCSAZil Multifunction serial ch.4 serial chip select 2 output pin ( l )
P032 (icncralrpllrposc 1/0 port
A04 External bus address bit4 output pin
T()T3 Reload timer c113 output pin
SCSAL] Multifunction serial ch.4 serial chip select 3 output pin ( l )
P033 (icncralrpllrposc 1/0 port
A05 External bus address bitS output pin
P034 (icncralrpllrposc 1/0 port
A06 External bus address bité output pin
P035 (icncralrpllrposc 1/0 port
A07 External bus address bit7 output pin
Al.\l(J Up, down eounter elt.0A1N input piu
P036 (icncralrpllrposc 1/0 port
A08 External bus address bit8 output pin
13th) Up, down eounter elt.0 BIN input piu
P037 (icncralrpllrposc 1/0 port
A09 External bus address bit9 output pin
ZlNO Up, down eounter elt.0 ZlN input pin
P040 (icncralrpllrposc 1/0 port
A10 External bus address bitlo output pin
Al.\ll Up, down eounter elt.l AIN input piu
P04l (icncralrpllrposc 1/0 port
A11 External bus address bitll output pin
BlNl Up, down eounter elt.l BIN input piu
P042 (icncralrpllrposc 1/0 port
A12 External bus address bitlZ output pin
ZlNl Up, down eounter elt.l ZlN input pin
P043 (icncralrpllrposc 1/0 port
A13 External bus address bitl} output pin
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 19
CONFIDENTIAL
Pin No. Pin name
I/O circuit
type
*1
Function
11
P026
K
General-purpose I/O port
A00
External bus address bit0 output pin
TIN3
Reload timer ch.3 event input pin
SCK4_1
Multi-function serial ch.4 clock I/O pin (1)/
I
2
C ch.4 clock I/O pin (1) (SCL)
12
P027
D
General-purpose I/O port
A01
External bus address bit1 output pin
TOT0
Reload timer ch.0 output pin
SCS40_1
Multi-function serial ch.4 serial chip select 0 I/O pin (1)
13
P030
D
General-purpose I/O port
A02
External bus address bit2 output pin
TOT1
Reload timer ch.1 output pin
SCS41_1
Multi-function serial ch.4 serial chip select 1 output pin (1)
14
P031
D
General-purpose I/O port
A03
External bus address bit3 output pin
TOT2
Reload timer ch.2 output pin
SCS42_1
Multi-function serial ch.4 serial chip select 2 output pin (1)
15
P032
D
General-purpose I/O port
A04
External bus address bit4 output pin
TOT3
Reload timer ch.3 output pin
SCS43_1
Multi-function serial ch.4 serial chip select 3 output pin (1)
16
P033
D
General-purpose I/O port
A05
External bus address bit5 output pin
17
P034
D
General-purpose I/O port
A06
External bus address bit6 output pin
20
P035
D
General-purpose I/O port
A07
External bus address bit7 output pin
AIN0
Up/ down counter ch.0 AIN input pin
21
P036
D
General-purpose I/O port
A08
External bus address bit8 output pin
BIN0
Up/ down counter ch.0 BIN input pin
22
P037
D
General-purpose I/O port
A09
External bus address bit9 output pin
ZIN0
Up/ down counter ch.0 ZIN input pin
23
P040
D
General-purpose I/O port
A10
External bus address bit10 output pin
AIN1
Up/ down counter ch.1 AIN input pin
24
P041
D
General-purpose I/O port
A11
External bus address bit11 output pin
BIN1
Up/ down counter ch.1 BIN input pin
25
P042
D
General-purpose I/O port
A12
External bus address bit12 output pin
ZIN1
Up/ down counter ch.1 ZIN input pin
26
P043
D
General-purpose I/O port
A13
External bus address bit13 output pin
/\
5 PA N 5 IO N
‘
IIO circuit
type ‘
P044 (icneralrpllrpose [/0 port
A14 External bus address bitl4 output pin
DAOUT DAC analog output pin
P045 (icneralrpllrpose [/0 port
A15 External bus address bitlS output pin
P046 (icneralrpllrpose [/0 port
A16 External bus address bitlé output pin
P047 (icneralrpllrpose [/0 port
A17 External bus address bitl7 output pin
P050 (icneralrpllrpose [/0 port
A18 External bus address bit18 output pin
P05l (icneralrpllrpose [/0 port
A19 External bus address bit19 output pin
P052 (icneralrpllrpose [/0 port
A20 External bus address bit20 output pin
P053 (icneralrpllrpose [/0 port
A21 External bus address bit21 output pin
P054 (icneralrpllrpose [/0 port
SYSCLK External bus ' stern clock output pin
P055 (icneralrpllrpose [/0 port
CSZX External bus ehip select 2 output pin
P056 (icneralrpllrpose [/0 port
CSEX External bus ehip select 3 output pin
P057 (icneralrpllrpose [/0 port
RDY External bus ready input piu
P060 (icneralrpllrpose [/0 port
MM Clock supervisor main clock missing output pin
P06l (icneralrpllrpose [/0 port
[N6 lfirbil input eapture eh.6 external pulse input pin
P062 (icneralrpllrpose [/0 port
FRCKU Freernln timer ch.() external clock input pin
SCSAO Multirfunction serial ch.4 serial ehip select (J [/0 pin
P063 (icneralrpllrpose [/0 port
FRCKI Freermn timer ch.l external elock input pin
scs4l Multifunction serial en.4 serial enip seleet 1 output pin
P064 (icneralrpllrpose [/0 port
FRCKZ Freermn timer ch.2 external elock input pin
scs42 Multirfunction serial en.4 serial enip seleet 2 output pin
P065 (icneralrpllrpose [/0 port
FRCK3 Freermn timer 011.3 external elock input pin
scs43 Multirfunction serial en.4 serial enip seleet 3 output pin
P066 (icneralrpllrpose [/0 port
FRCK4 Freermn tinier c114 external clock input pin
SCS3 Multirfunction serial ch.3 serial ehip select [/0 pin
P067 (icneralrpllrpose [/0 port
FRCKS Freermn timer 011.5 external elock input pin
DataSheet
20 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Pin No. Pin name
I/O circuit
type
*1
Function
27
P044
P
General-purpose I/O port
A14
External bus address bit14 output pin
DAOUT
DAC analog output pin
28
P045
D
General-purpose I/O port
A15
External bus address bit15 output pin
29
P046
D
General-purpose I/O port
A16
External bus address bit16 output pin
30
P047
D
General-purpose I/O port
A17
External bus address bit17 output pin
31
P050
D
General-purpose I/O port
A18
External bus address bit18 output pin
32
P051
D
General-purpose I/O port
A19
External bus address bit19 output pin
33
P052
D
General-purpose I/O port
A20
External bus address bit20 output pin
34
P053
D
General-purpose I/O port
A21
External bus address bit21 output pin
35
P054
D
General-purpose I/O port
SYSCLK
External bus system clock output pin
38
P055
D
General-purpose I/O port
CS2X
External bus chip select 2 output pin
39
P056
D
General-purpose I/O port
CS3X
External bus chip select 3 output pin
41
P057
D
General-purpose I/O port
RDY
External bus ready input pin
44
P060
D
General-purpose I/O port
MM
Clock supervisor main clock missing output pin
45
P061
D
General-purpose I/O port
IN6
16-bit input capture ch.6 external pulse input pin
46
P062
D
General-purpose I/O port
FRCK0
Free-run timer ch.0 external clock input pin
SCS40
Multi-function serial ch.4 serial chip select 0 I/O pin
47
P063
D
General-purpose I/O port
FRCK1
Free-run timer ch.1 external clock input pin
SCS41
Multi-function serial ch.4 serial chip select 1 output pin
48
P064
D
General-purpose I/O port
FRCK2
Free-run timer ch.2 external clock input pin
SCS42
Multi-function serial ch.4 serial chip select 2 output pin
49
P065
D
General-purpose I/O port
FRCK3
Free-run timer ch.3 external clock input pin
SCS43
Multi-function serial ch.4 serial chip select 3 output pin
50
P066
D
General-purpose I/O port
FRCK4
Free-run timer ch.4 external clock input pin
SCS3
Multi-function serial ch.3 serial chip select I/O pin
51
P067
D
General-purpose I/O port
FRCK5
Free-run timer ch.5 external clock input pin
/'\
S PA N 5 IO N
‘
IIO circuit
type ‘
P070 (icncralrpurposc [/0 port
ANO ADC analog 0 input pin
P07l (icncralrpurposc [/0 port
ANl ADC analog 1 input pin
P072 (icncralrpurposc [/0 port
AN2 ADC analog 2 input pin
SlN4 Multifunction serial an serial data input pin
lNTs INTS cxternal intermpt input pin
P073 (icncralrpurposc [/0 port
AN3 ADC analog 3 input pin
Multifunction serial ch.4 serial data output pin
I C cht4 serial data [/0 pin [SDAi
P074 (icncralrpurposc [/0 port
AN4 ADC analog 4 input pin
Multifunction serial ch.4 clock [/0/
I C cliA clock 10 pin (SCL)
P075 (icncralrpurposc [/0 port
AN5 ADC analog 5 input pin
5th Multifunction serial ch.3 serial data input pin
1NT4 INT4 cxternal interrupt input pin
P076 (icncralrpurposc [/0 port
AN6 ADC analog 6 input pin
Multifunction serial ch.3 serial data output pin /
I C chi} serial data [/0 pin [SDAi
P077 (icncralrpurposc [/0 port
AN7 ADC analog 7 input pin
Multifunction serial ch.3 clock [/0 pin,
I C oligl clock 10 pin (SCL)
P080 (icncralrpurposc [/0 port
ANx ADC analog 8 input pin
PPGO PPG ch.() output pin
P08l (icncralrpurposc [/0 port
AN9 ADC analog 9 input pin
PPG] PPG ch.l output pin
P082 (icncralrpurposc [/0 port
AN [0 ADC analog to input pin
PPGZ PPG ch.2 output pin
P083 (icncralrpurposc [/0 port
A.\lll ADC analog 11 input pin
PPG3 PPG ch.3 output pin
P084 (icncralrpurposc [/0 port
AN 12 ADC analog 12 input pin
PPtiA PPG ch.4 output pin
P085 (icncralrpurposc [/0 port
AN [3 ADC analog 13 input pin
PPGS PPG ch.5 output pin
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 21
CONFIDENTIAL
Pin No. Pin name
I/O circuit
type
*1
Function
54
P070
F
General-purpose I/O port
AN0
ADC analog 0 input pin
55
P071
F
General-purpose I/O port
AN1
ADC analog 1 input pin
56
P072
G
General-purpose I/O port
AN2
ADC analog 2 input pin
SIN4
Multi-function serial ch.4 serial data input pin
INT5
INT5 external interrupt input pin
57
P073
M
General-purpose I/O port
AN3
ADC analog 3 input pin
SOT4
Multi-function serial ch.4 serial data output pin
I
2
C ch.4 serial data I/O pin (SDA)
58
P074
M
General-purpose I/O port
AN4
ADC analog 4 input pin
SCK4
Multi-function serial ch.4 clock I/O /
I
2
C ch.4 clock I/O pin (SCL)
59
P075
G
General-purpose I/O port
AN5
ADC analog 5 input pin
SIN3
Multi-function serial ch.3 serial data input pin
INT4
INT4 external interrupt input pin
60
P076
M
General-purpose I/O port
AN6
ADC analog 6 input pin
SOT3
Multi-function serial ch.3 serial data output pin /
I
2
C ch.3 serial data I/O pin (SDA)
61
P077
M
General-purpose I/O port
AN7
ADC analog 7 input pin
SCK3
Multi-function serial ch.3 clock I/O pin /
I
2
C ch.3 clock I/O pin (SCL)
64
P080
F
General-purpose I/O port
AN8
ADC analog 8 input pin
PPG0
PPG ch.0 output pin
65
P081
F
General-purpose I/O port
AN9
ADC analog 9 input pin
PPG1
PPG ch.1 output pin
66
P082
F
General-purpose I/O port
AN10
ADC analog 10 input pin
PPG2
PPG ch.2 output pin
67
P083
F
General-purpose I/O port
AN11
ADC analog 11 input pin
PPG3
PPG ch.3 output pin
68
P084
F
General-purpose I/O port
AN12
ADC analog 12 input pin
PPG4
PPG ch.4 output pin
69
P085
F
General-purpose I/O port
AN13
ADC analog 13 input pin
PPG5
PPG ch.5 output pin
/\
5 PA N 5 IO N
‘
IIO circuit
type ‘
P086 (icncmlrpurposc 1/0 port
AN 14 ADC analog 14 input pin
PPtlo PPG ch.6 output pin
P087 (icncmlrpurposc 1/0 port
AN 1 5 ADC analog 15 input pin
PPG7 PPG ch.7 output pin
P090 (icncmlrpurposc 1/0 port
[N0 lfirbil input eapture eh.0 external pulse input pin
P091 (icncmlrpurposc 1/0 port
[Nl lfirbil input eapture eh.l external pulse input pin
P092 (icncmlrpurposc 1/0 port
[N2 lfirbil input eapture eh.2 external pulse input pin
P093 (icncmlrpurposc 1/0 port
[N3 lfirbil input eapture eh.3 external pulse input pin
P094 (icncmlrpurposc 1/0 port
[N4 lfirbil input eapture eh.4 external pulse input pin
P095 (icncmlrpurposc 1/0 port
TXO CAN transtnis on data 0 output pin
P096 (icncmlrpurposc 1/0 port
RXU CAN reception data 0 input pin
[NTU INTO external internipt input pin
P097 (icncmlrpurposc 1/0 port
[N5 lfirbil input eapture eh.5 external pulse input pin
P100 (icncmlrpurposc 1/0 port
PPtlx PPG ch.8 output pin
AN [6 ADC analog 16 input pin
P101 (icncmlrpurposc 1/0 port
PPtl9 PPG ch.9 output pin
AN 1 7 ADC analog 17 input pin
P102 (icncmlrpurposc 1/0 port
PPGHJ PPG ch.1() output pin
AN 1 8 ADC analog 18 input pin
P103 (icncmlrpurposc 1/0 port
PPG] 1 PPG ch.1] output pin
AN 19 ADC analog 19 input pin
P104 (icncmlrpurposc 1/0 port
PPGIZ PPG ch.12 output pin
AN20 ADC analog 20 input pin
P105 (icncmlrpurposc 1/0 port
PPG] 3 PPG ch.13 output pin
AN21 ADC analog 21 input pin
P106 (icncmlrpurposc 1/0 port
PPGM PPG ch.14 output pin
AN22 ADC analog 22 input pin
P107 (icncmlrpurposc 1/0 port
PPG] 5 PPG ch.15 output pin
AN23 ADC analog 23 input pin
DataSheet
22 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Pin No. Pin name
I/O circuit
type
*1
Function
70
P086
F
General-purpose I/O port
AN14
ADC analog 14 input pin
PPG6
PPG ch.6 output pin
71
P087
F
General-purpose I/O port
AN15
ADC analog 15 input pin
PPG7
PPG ch.7 output pin
74
P090
D
General-purpose I/O port
IN0
16-bit input capture ch.0 external pulse input pin
75
P091
D
General-purpose I/O port
IN1
16-bit input capture ch.1 external pulse input pin
76
P092
D
General-purpose I/O port
IN2
16-bit input capture ch.2 external pulse input pin
77
P093
D
General-purpose I/O port
IN3
16-bit input capture ch.3 external pulse input pin
78
P094
D
General-purpose I/O port
IN4
16-bit input capture ch.4 external pulse input pin
79
P095
D
General-purpose I/O port
TX0
CAN transmission data 0 output pin
80
P096
E
General-purpose I/O port
RX0
CAN reception data 0 input pin
INT0
INT0 external interrupt input pin
81
P097
D
General-purpose I/O port
IN5
16-bit input capture ch.5 external pulse input pin
85
P100
F
General-purpose I/O port
PPG8
PPG ch.8 output pin
AN16
ADC analog 16 input pin
86
P101
F
General-purpose I/O port
PPG9
PPG ch.9 output pin
AN17
ADC analog 17 input pin
87
P102
F
General-purpose I/O port
PPG10
PPG ch.10 output pin
AN18
ADC analog 18 input pin
88
P103
F
General-purpose I/O port
PPG11
PPG ch.11 output pin
AN19
ADC analog 19 input pin
89
P104
F
General-purpose I/O port
PPG12
PPG ch.12 output pin
AN20
ADC analog 20 input pin
90
P105
F
General-purpose I/O port
PPG13
PPG ch.13 output pin
AN21
ADC analog 21 input pin
91
P106
F
General-purpose I/O port
PPG14
PPG ch.14 output pin
AN22
ADC analog 22 input pin
92
P107
F
General-purpose I/O port
PPG15
PPG ch.15 output pin
AN23
ADC analog 23 input pin
/'\
S PA N 5 IO N
‘
IIO circuit
type ‘
P110 (icncralrpurposc 1/0 port
TX] CAN transm,, on data 1 output pin
P111 (icncralrpurposc 1/0 port
RXl CAN reception data 1 input pin
lNTl INTI external interntpt input pin
P112 (icncralrpurposc 1/0 port
RT()(J Waveform generator ehtu output pin
PPG] 5 PPG ch.16 output pm
P113 (icncralrpurposc 1/0 port
RTol Waveform generator ehtl output pin
PPG] 7 PPG ch.17 output pm
P114 (icncralrpurposc 1/0 port
RT02 Waveform generator ch12 output pin
PPG] 8 PPG ch.18 output pm
P 1 15 (icncralrpurposc 1/0 port
RT03 Waveform generator ch13 output pin
PPG] 9 PPG ch.19 output pm
P116 (icncralrpurposc 1/0 port
RT04 Waveform generator ehA output pin
PPGZO PPG ch20 output pin
P 1 17 (icncralrpurposc 1/0 port
RT05 Waveform generator ehts output pin
PPGZ] PPG ch.21 output pm
P120 (icncralrpurposc 1/0 port
RTOfi Waveform generator ch16 output pin
PPGZZ PPG ch.22 output pm
P121 (icncralrpurposc 1/0 port
RT07 Waveform generator eht7 output pin
PPGZ3 PPG eh.23 output pm
P122 (icncralrpurposc 1/0 port
RTOX Waveform generator ehtx output pin
P123 (icncralrpurposc 1/0 port
RT09 Waveform generator eh!) output pin
P124 (icncralrpurposc 1/0 port
RT()1(J Waveform generator chtlU output pm
P125 (icncralrpurposc 1/0 port
RTUll Waveform generator eh111 output pm
P126 (icncralrpurposc 1/0 port
s1No Multifunction serial ch.(J serial data input pin
lNTfi INTé external interntpt input pin
P127 (icncralrpurposc 1/0 port
Multifunction serial eh.(J serial data output pin/
I C chtU serial data [/0 pin (SBA)
P130 (icncralrpurposc 1/0 port
Multifunction seria] ch.(J clock 1/0 [1111'
1 c chtU e1oek 10 pm (SCL)
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 23
CONFIDENTIAL
Pin No. Pin name
I/O circuit
type
*1
Function
96
P110
D
General-purpose I/O port
TX1
CAN transmission data 1 output pin
97
P111
E
General-purpose I/O port
RX1
CAN reception data 1 input pin
INT1
INT1 external interrupt input pin
98
P112
D
General-purpose I/O port
RTO0
Waveform generator ch.0 output pin
PPG16
PPG ch.16 output pin
99
P113
D
General-purpose I/O port
RTO1
Waveform generator ch.1 output pin
PPG17
PPG ch.17 output pin
100
P114
D
General-purpose I/O port
RTO2
Waveform generator ch.2 output pin
PPG18
PPG ch.18 output pin
101
P115
D
General-purpose I/O port
RTO3
Waveform generator ch.3 output pin
PPG19
PPG ch.19 output pin
102
P116
D
General-purpose I/O port
RTO4
Waveform generator ch.4 output pin
PPG20
PPG ch.20 output pin
103
P117
D
General-purpose I/O port
RTO5
Waveform generator ch.5 output pin
PPG21
PPG ch.21 output pin
104
P120
D
General-purpose I/O port
RTO6
Waveform generator ch.6 output pin
PPG22
PPG ch.22 output pin
105
P121
D
General-purpose I/O port
RTO7
Waveform generator ch.7 output pin
PPG23
PPG ch.23 output pin
106
P122
D
General-purpose I/O port
RTO8
Waveform generator ch.8 output pin
107
P123
D
General-purpose I/O port
RTO9
Waveform generator ch.9 output pin
111
P124
D
General-purpose I/O port
RTO10
Waveform generator ch.10 output pin
112
P125
D
General-purpose I/O port
RTO11
Waveform generator ch.11 output pin
113
P126
E
General-purpose I/O port
SIN0
Multi-function serial ch.0 serial data input pin
INT6
INT6 external interrupt input pin
114
P127
K
General-purpose I/O port
SOT0
Multi-function serial ch.0 serial data output pin/
I
2
C ch.0 serial data I/O pin (SDA)
115
P130
K
General-purpose I/O port
SCK0
Multi-function serial ch.0 clock I/O pin/
I
2
C ch.0 clock I/O pin (SCL)
/\
5 PA N 5 IO N
‘
IIO circuit
type ‘
P131 (ieneralrpurpose 1/0 port
ADTGO A’D eonvener ch.0 to c1117 external trigger input pin
P132 (ieneralrpurpose 1/0 port
ADTG] A’D converter ch.8 to ehtls external trigger input pin
SCSI Multifunction serial ch.l serial ehip select [/0 pin
P133 (ieneralrpurpose 1/0 port
ADTGZ A’D eonvener ch. 16 to ch23 external trigger input pin
TX2 CAN transmission data 2 output pin
P134 (ieneralrpurpose 1/0 port
STUPWT Flchay Stopwatch input pin
RXZ CAN reception data 2 input pin
INT7 INT7 external interrupt input pin
I.\l7 lfirbil input capture ch.7 external pulse input pin
110 DEBUGIF L DEBUG I/F pin
P136 (ieneralrpurpose 1/0 port
DTTlU Waveform generator output stop signal input pin (J
MONCLK Clock monitor output pin
P137 (ieneralrpurpose 1/0 port
DTTll Waveform generator output stop signal input pin 1
40 AVCCO , *2
x4 AVCC3 , A’D eonvener analog power supply
42 AVRHO , *2
52 AVRH] , A’D eonvener upper limit reference voltage
62 AVR1-12 , A’D eonvener upper limit reference voltage
83 AVR1-13 , A’D eonvener upper limit reference voltage
AVSSO *3
AVRLO *3
AVSSI A’D converter GND
AVRL] A’D converter lower limit reference voltage
AVSSZ A’D converter GND
AVRL2 A’D converter lower limit reference voltage
AVSS} A’D converter GND
AVRL3 A’D converter lower limit reference voltage
130 C , External capaeity eonnection output pin
18, 35,
3, 72,
9, 12
144
1, 19, 37,
3, 94,
X, 12
129
DataSheet
24 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Pin No. Pin name
I/O circuit
type
*1
Function
124
P131
D
General-purpose I/O port
ADTG0
A/D converter ch.0 to ch.7 external trigger input pin
125
P132
D
General-purpose I/O port
ADTG1
A/D converter ch.8 to ch.15 external trigger input pin
SCS1
Multi-function serial ch.1 serial chip select I/O pin
126
P133
D
General-purpose I/O port
ADTG2
A/D converter ch.16 to ch.23 external trigger input pin
TX2
CAN transmission data 2 output pin
127
P134
E
General-purpose I/O port
STOPWT
FlexRay Stopwatch input pin
RX2
CAN reception data 2 input pin
INT7
INT7 external interrupt input pin
IN7
16-bit input capture ch.7 external pulse input pin
110
DEBUGIF
L
DEBUG I/F pin
121
P136
D
General-purpose I/O port
DTTI0
Waveform generator output stop signal input pin 0
MONCLK
Clock monitor output pin
122
P137
D
General-purpose I/O port
DTTI1
Waveform generator output stop signal input pin 1
40
AV C C 0
-
*2
84
AV C C 3
-
A/D converter analog power supply
42
AVRH0
-
*2
52
AVRH1
-
A/D converter upper limit reference voltage
62
AVRH2
-
A/D converter upper limit reference voltage
83
AVRH3
-
A/D converter upper limit reference voltage
43
AVSS0
-
*3
AV R L 0
*3
53
AVSS1
-
A/D converter GND
AV R L 1
A/D converter lower limit reference voltage
63
AVSS2
-
A/D converter GND
AV R L 2
A/D converter lower limit reference voltage
82
AVSS3
-
A/D converter GND
AV R L 3
A/D converter lower limit reference voltage
130
C
-
External capacity connection output pin
18, 36,
93, 72,
109, 128,
144
VCC5 - +5.0V power supply
1, 19, 37,
73, 94,
108, 120,
129
VSS - GND
*1: For the I/O circuit types, see "■ I/O circuit type".
*2: The MB91F585LB/F586LB/F587LB/F585LD/F586LD/F587LD do not use this pin. Connect it with the
VCC5 pin.
*3: The MB91F585LB/F586LB/F587LB/F585LD/F586LD/F587LD do not use this pin. Connect it with the VSS
pin.
/'\
PulHAp comm
S PA N 5 IO N
\
I
Type Circuit Remarks
A Oscillation feedback rcsxstor:
B . CMOS hysmrcsis inpm
E! w» W—
C . Schmm input
1 WW
i m
77
D - (icncralrpurposc 1 0 pm
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 25
CONFIDENTIAL
I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
Clock input
X0
Standby control signal
X1
Oscillation feedback resistor:
Approx. 1 MΩ
B
Pull-up resistor
CMOS hysteresis input
• CMOS hysteresis input
• With 50 kΩ pull-up resistor
C
N-ch Mode input
High withstand voltage mode
input
High withstand voltage control
N-ch
N-ch
N-ch
• Schmitt input
• With high withstand voltage
control
D
Pull-up control
Digital output
CMOS hysteresis input
Automotive input
Standby control
P-ch P-ch
N-ch
R
• General-purpose I/O port
• CMOS level output
IOH=-2/-5mA, IOL=2/5mA
• With 50kΩ pull-up resistor control
• CMOS hysteresis input
(0.7Vcc/0.3Vcc)
• Automotive input (0.8Vcc/0.5Vcc)
/\
5 PA N 5 IO N
‘
Type Circunt Remarks
E - (icncralrpurposc 1 0 port
F . th analog mpuL generalrpurposc
rch
Pu‘lrup control
DataSheet
26 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Type
Circuit
Remarks
E
Pull-up control
Digital output
CMOS hysteresis input
Automotive input
Standby control
P-ch P-ch
N-ch
R
• General-purpose I/O port
• CMOS level output
IOH=-2/-5mA, IOL=2/5mA
• With 50 kΩ pull-up resistor control
• CMOS hysteresis input
(0.7Vcc/0.3Vcc)
During standby, the input value
retains the previous value.
• Automotive input (0.8Vcc/0.5Vcc)
During standby, the input value
retains the previous value.
F
Pull-up control
Digital output
CMOS hysteresis input
Automotive input
Standby control
Analog input
P-ch P-ch
N-ch
R
• With analog input, general-purpose
I/O port
• CMOS level output
IOH=-2/-5mA, IOL=2/5mA
• With 50 kΩ pull-up resistor control
• CMOS hysteresis input
(0.7Vcc/0.3Vcc)
• Automotive input (0.8Vcc/0.5Vcc)
/'\
S PA N 5 IO N
‘
Type Circuit Remarks
(} . th analog mpuL generalrpurposc
Pu‘lrup control
'C" i
4L
4%
‘17
H Analog input
1' Analog outpm
J CMOS lcvcl ompln
K
PuHrup comm
. wnh 13c. generalrpurposc 1/0 pon
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 27
CONFIDENTIAL
Type
Circuit
Remarks
G
Pull-up control
Digital output
CMOS hysteresis input
Automotive input
Standby control
Analog input
P-ch P-ch
N-ch
R
• With analog input, general-purpose
I/O port
• CMOS level output
IOH=-2/-5mA, IOL=2/5mA
• With 50 kΩ pull-up resistor control
• CMOS hysteresis input
(0.7Vcc/0.3Vcc)
During standby, the input value
retains the previous value.
• Automotive input (0.8Vcc/0.5Vcc)
During standby, the input value
retains the previous value.
H*
Analog input
Analog input
I*
Analog output
Analog output
J*
Digital output
P-ch
N-ch
CMOS level output
IOH=-2/-5mA, IOL=2/5mA
K
Pull-up control
Digital output
CMOS hysteresis input
Automotive input
Standby control
P-ch P-ch
N-ch
R
• With I2C, general-purpose I/O port
• CMOS level output
IOH=-3mA, IOL=3mA (at I2C
output)
IOH=-2/-5mA, IOL=2/5mA (other
than above)
• With 50 kΩ pull-up resistor control
• CMOS hysteresis input
(0.7Vcc/0.3Vcc)
• Automotive input (0.8Vcc/0.5Vcc)
/\
5 PA N 5 IO N
‘
Type Circuit Remarks
L 0an drain 1 U
M - With analog mpuL 13c,
Pu‘lrup control
N . th analog ompul,
PuIHAp control
DataSheet
28 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Type
Circuit
Remarks
L
TTL schmitt input
Digital output
Open drain I/O
M
Pull-up control
Digital output
CMOS hysteresis input
Automotive input
P-ch P-ch
N-ch
R
Analog input
Standby control
• With analog input, I2C,
general-purpose I/O port
• CMOS level output
IOH=-3mA, IOL=3mA (at I2C
output)
IOH=-2/-5mA, IOL=2/5mA (other
than above)
• With 50 kΩ pull-up resistor control
• CMOS hysteresis input
(0.7Vcc/0.3Vcc)
• Automotive input (0.8Vcc/0.5Vcc)
N
Pull-up control
Digital output
FlexRay input
Automotive input
Standby control
P-ch P-ch
N-ch
R
Analog output
• With analog output,
general-purpose I/O port
• CMOS level output
IOH=-2/-4mA, IOL=2/4mA
• With 50 kΩ pull-up resistor control
• FlexRay input (0.7Vcc/0.3Vcc)
• Automotive input (0.8Vcc/0.5Vcc)
/'\
S PA N 5 IO N
‘
Type Circuit Remarks
0 . th analog ompul,
Pulkup control
P . th D/A converter oulpm,
PuHrup comm
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 29
CONFIDENTIAL
Type
Circuit
Remarks
O
Pull-up control
Digital output
FlexRay input
Automotive input
Standby control
P-ch P-ch
N-ch
R
Analog output
• With analog output,
general-purpose I/O port
• CMOS level output
IOH=-2/-4mA, IOL=2/4mA
• With 50 kΩ pull-up resistor control
• FlexRay input (0.7Vcc/0.3Vcc)
During standby, the input value
retains the previous value.
• Automotive input (0.8Vcc/0.5Vcc)
During standby, the input value
retains the previous value.
P
Pull-up control
Digital output
CMOS hysteresis input
Automotive input
Standby control
P-ch P-ch
N-ch
R
D/A converter output
• With D/A converter output,
general-purpose I/O port
• CMOS level output
IOH=-2/-5mA, IOL=2/5mA
• With 50 kΩ pull-up resistor control
• CMOS hysteresis input
(0.7Vcc/0.3Vcc)
• Automotive input (0.8Vcc/0.5Vcc)
*: MB91F585LA/F586LA/F587LA/F585LC/F586LC/F587LC only
/\
SPANSION’
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DataSheet
30 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
HANDLING PRECAUTIONS
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly
affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This
page describes precautions that must be observed to minimize the chance of failure and to obtain higher
reliability from your Spansion semiconductor devices.
1. Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
• Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.
• Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the
device's electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data
sheet. Users considering application outside the listed conditions are advised to contact their sales
representative beforehand.
• Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power
supply and input/output functions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause
deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to
prevent such overvoltage or over-current conditions at the design stage.
(2) Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can
cause large current flows. Such conditions if present for extended periods of time can damage the
device.
Therefore, avoid this type of connection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation.
Such pins should be connected through an appropriate resistance to a power supply pin or ground pin.
• Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When
subjected to abnormally high-voltages, internal parasitic PNPN junctions (called thyristor structures) may
be formed, causing large current levels in excess of several hundred mA to flow continuously at the power
supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but
can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the
following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should
include attention to abnormal noise, surge levels, etc.
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
Code: DS00-00004-1Ea
/‘\
SPANSION
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DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 31
CONFIDENTIAL
• Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from
electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards
in the design of products.
• Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury,
damage or loss from such failures by incorporating safety design measures into your facility and equipment
such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions.
• Precautions Related to Usage of Devices
Spansion semiconductor devices are intended for use in standard applications (computers, office automation
and other office equipment, industrial, communications, and measurement equipment, personal or
household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or
abnormal operation may directly affect human lives or cause physical injury or property damage, or where
extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea
floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult
with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
2. Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance
during soldering, you should only mount under Spansion's recommended conditions. For detailed
information about mount conditions, contact your sales representative.
• Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct
soldering on the board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the
board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the
soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for
storage temperature. Mounting processes should conform to Spansion recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can
lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment
of socket contacts and IC leads be verified before mounting.
• Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are
more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in
increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Spansion Inc. recommends the solder reflow method, and
has established a ranking of mounting conditions for each product. Users are advised to mount packages in
accordance with Spansion ranking of recommended conditions.
/\
SPANSION’
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DataSheet
32 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
• Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic
soldering, junction strength may be reduced under some conditions of use.
• Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions
will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed
moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent,
do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product.
Store products in locations where temperature changes are slight.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at
temperatures between 5°C and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
(3) When necessary, Spansion Inc. packages semiconductor devices in highly moisture-resistant
aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum
laminate bags for storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
• Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion
recommended conditions for baking.
Condition: 125°C/24 h
• Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take
the following precautions:
(1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus
for ion generation may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high
resistance (on the level of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to
minimize shock loads is recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board
assemblies.
/‘\
SPANSION
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DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 33
CONFIDENTIAL
3. Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described
above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high
humidity levels are anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal
operation. In such cases, use anti-static measures or processing to prevent discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will
adversely affect the device. If you use devices in such conditions, consider ways to prevent such
exposure or to protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation.
Users should provide shielding as appropriate.
(5) Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible
substances. If devices begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Spansion products in other special environmental conditions should
consult with sales representatives.
Please check the latest handling precautions at the following URL.
http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf
/\
SPANSION
‘
Power Supply Input Pins
0E
0C
E
L v»:
Vss
DataSheet
34 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
HANDLING DEVICES
The latch-up prevention and pin processing are explained below.
• For latch-up prevention
If a voltage higher than VCC or a voltage lower than VSS is applied to an I/O pin, or if a voltage exceeding
the ratings is applied between VCC and VSS pins, a latch-up may occur in CMOS IC. If the latch-up occurs,
the power supply current increases excessively and device elements may be damaged by heat. Take care to
prevent any voltage from exceeding the maximum ratings in device application.
Also, the analog power supplies (AVCC0*, AVCC3, AVRH0*, AVRH1, AVRH2, AVRH3) and analog input
must not exceed the digital power supply (VCC5) when the power supply to the analog system is turned on
or off.
In the correct power-on sequence, turn on the digital power supply voltage (VCC5) and analog power
supply voltages (AVCC0*, AVCC3, AVRH0*, AVRH1, AVRH2, AVRH3) simultaneously. Alternatively,
turn on the digital power supply voltage (VCC5) first, and then turn on the analog power supplies (AVCC0*,
AVCC3, AVRH0*, AVRH1, AVRH2, AVRH3).
*: MB91F585LA/F586LA/F587LA/F585LC/F586LC/F587LC only
• Treatment of unused pins
If unused input pins are left open, they may cause a permanent damage to the device due to device
malfunction or latch-up. Connect a 2kΩ or higher resistor to each of unused input pins for pull-up or
pull-down processing.
Also, if I/O pins are not used, they must be set to the output state for releasing or they must be set to the
input state and treated in the same way as for the input pins.
• Power supply pins
The device is designed to ensure that if the device contains multiple VCC or VSS pins, the pins that should
be at the same potential are interconnected to prevent latch-up or other malfunctions. Further, connect these
pins to an external power supply or ground to reduce unwanted radiation, prevent strobe signals from
malfunctioning due to a raised ground level, and fulfill the total output current standard, etc. As shown
below, all VSS power supply pins must be treated in the similar way. If multiple VCC or VSS systems are
connected, the device cannot operate correctly even within the guaranteed operating range.
Power Supply Input Pins
The power supply pins should be connected to VCC and VSS of this device at the low impedance from the
power supply source.
In the area close to this device, a ceramic capacitor having the capacitance larger than the capacitor of C pin
is recommended to use as a bypass capacitor between VCC and VSS pins.
VSS
/‘\
SPANSION
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DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 35
CONFIDENTIAL
• Crystal oscillation circuit
An external noise to the X0 or X1 pin may cause a device malfunction. The printed circuit board must be
designed to lay out X0 and X1 pins, crystal oscillator (or ceramic resonator), and the bypass capacitor to be
grounded to the close position to the device.
The printed circuit board artwork is recommended to surround the X0 and X1 pins by ground circuits.
• Mode pin (MD[1:0])
Connect the MD[1:0] mode pin to the VCC or VSS pin directly. To prevent an erroneous selection of test
mode caused by the noise, reduce the pattern length between each mode pin and VCC or VSS pin on the
printed circuit board. Also, use the low-impedance pin connection.
• During power-on
To prevent a malfunction of the voltage step-down circuit built in the device, set the voltage rising time to
have 50µs or longer (between 0.2V and 2.7V) during power-on.
• Notes during PLL clock operation
When the PLL clock is selected and if the oscillator is disconnected or if the input is stopped, this clock
may continue to operate at the free running frequency of the self oscillator circuit built in the PLL. This
operation is not guaranteed.
• Treatment of R/D converter* and A/D converter power supply pins
Connect the pins to have AVCC0 = AVCC3 = AVRH0 = AVRH1=AVRH2=AVRH3=VCC and
AV S S 0 / AV R L 0 =AV S S 1 / AV R L 1 = AV S S 2 / AV R L 2 = AV S S3/AVRL3=VSS even if the R/D converter* and
the A/D converter are not used.
• Note on using external clock
The external clock is unsupported.
External direct clock input cannot use.
• Power-on sequence of R/D converter* and A/D converter power supply analog inputs
Be sure to turn on the digital power supply (VCC5) first, and then turn on the R/D converter* and A/D
converter power supplies (AVCC0*, AVCC3, AVRH0*, AVRH1, AVRH2, AVRH3, AVRL0*, AVRL1,
AVRL2, AVRL3) and analog inputs (MAG_PLUS*, MAG_MINUS*, COS_PLUS*, COS_MINUS*,
SIN_PLUS*, SIN_MINUS*, COS_IN*, SIN_IN*, AN0 to AN23). Also, turn off the R/D converter* and
A/D converter power supplies (AVCC0*, AVCC3, AVRH0*, AVRH1, AVRH2, AVRH3, AVRL0*, AVRL1,
AVRL2, AVRL3) and analog inputs (MAG_PLUS*, MAG_MINUS*, COS_PLUS*, COS_MINUS*,
SIN_PLUS*, SIN_MINUS*, COS_IN*, SIN_IN*, AN0 to AN23) first, and then turn off the digital power
supply (VCC5). When the AVRH0*, AVRH1, AVRH2, and AVRH3 pin voltages are turned on or off, they
must not exceed AVCC0* and AVCC3. Even if a common analog input pin is used as an input port, its input
voltage must not exceed AVCC0* or AVCC3. (However, the analog power supply voltage and digital power
supply voltage can be turned on or off simultaneously.)
• Treatment of C pin
This device contains a voltage step-down circuit. A capacitor must always be connected to the C pin to
assure the internal stabilization of the device. For the standard values, see the "Recommended Operating
Conditions" of the latest data sheet.
*: MB91F585LA/F586LA/F587LA/F585LC/F586LC/F587LC only
/\
SPANSION’
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DataSheet
36 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
APPLICATION NOTES
• Function Switching of a Multiplexed Port
To switch between the port function and the multiplexed pin function, use the PFR (port function register).
However, if a pin is also used for an external bus, its function is switched by the external bus setting. For
details, see "I/O PORTS" in Hardware Manual.
*: MB91F585LB/F586LB/F587LB/F585LD/F586LD/F587LD only
• Low-power Consumption Mode
To transit to the sleep mode, watch mode, stop mode, watch mode(power-off) or stop mode(power-off),
follow the procedure explained in the "Activating the sleep mode, watch mode, or stop mode" or the
"Activating the watch mode (power-off) or stop mode(power-off)" of "POWER CONSUMPTION
CONTROL" in Hardware Manual.
Take the following notes when using a monitor debugger.
• Do not set a break point for the low-power consumption transition program.
• Do not execute an operation step for the low-power consumption transition program.
• Notes When Writing Data in a Register Having the Status Flag
When writing data in the register that has a status flag (especially, an interrupt request flag) to control
function, take care not to clear its status flag erroneously.
The program must be written not to clear the flag to the status bit, and to set the control bits to have the
desired value.
Especially, if multiple control bits are used, the bit instruction cannot be used. (The bit instruction can
access to a single bit only.) The Byte, Half-word, or Word access must be used to write data in the control
bits and status flag simultaneously. During this time, take care not to clear other bits (in this case, the bits of
status flag) erroneously.
Note: These points can be ignored because the bit instructions already take the points into consideration
for registers that support read-modify-write (RMW) operations. These points must be considered
when using the bit instructions for registers that do not support RMW operations.
/'\
SPANSION
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o M391F585LA/F586LA/F587LA/F585LC/F586LC/F587LC
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 37
CONFIDENTIAL
BLOCK DIAGRAM
• MB91F585LA/F586LA/F587LA/F585LC/F586LC/F587LC
F ro m M a s te r
T o S l a ve
F ro m M a s te r
T o S l a ve
M D0,M D 1,P127
SOT0-4,SIN0-4,
DTTI0-1,RTO0-11
IN0-7
ADTG0-2,A N0-23
NMIX
MO NCLK
RX0-2,
TX0-2
A IN0-1, B IN0-1,
Z IN0-1
I / O P ort
XBS C rossbar S w itch
F R 81s C P U core
In s truc tio n
On-chip bus Layer 2
Peripheral bus bridge
FlexRay/RDC clock control
CR oscillation (trimming)
NMI
1 6 3 2
Wild register
I / O P ort
On-chip bus Layer 1
Debug In te rfa ce
Regulator
Delay interrupt
Interrupt controller Regulator control
On-chip bus XBS
M P U
32-bit peripheral bus
Clock Supervisor
Bus
performance
counter
16-bit peripheral bus
BackUp
RAM
Shutdown control
External interrupt input (8ch)
Watchdog timer (SW and HW)
PPG (24ch)
Interrupt request batch read
Generation/clear of DMA transfer request
Clock Monitor
DMAC
RAMECC
/
Operating
mode register
Power-on reset
CR oscillator
CAN prescaler
F la sh
RA M
D ata
Clock control
(clock setting, main timer, PLL timer)
Bus bridge
(32-bit 16-bit)
CRC
Waveform generator (12ch)
Output compare (12ch)
A/D converter
Free-run timer (6ch)
Input capture (8ch)
R/D converter
Multi-function serial interface (5ch)
Asynchronous bus bridge
(PCLK1 PCLK2)
INT0-7
Input cut-off
inhibiting signal
MM
SIN_PLUS,SIN_MINUS,
COS_PLUS,COS_MINUS,
MAG_PLUS,MAG_MINUS,
SIN_IN,COS_IN,AREF2,
SIN_OUT,COS_OUT,MAG_OUT,
RDC_ACT,RDC_U,RDC_V,RDC_W,
RDC_A,RDC_B,RDC_Z
FRCK0-5
SCK0-4,
SCS1-3, SCS3_1,
SCS40-43,
SCS40_1-SCS43_1
Clock control register
(frequency dividing setting)
Reset control register
Low-power consumption setting register
RSTX
Asynchronous bus bridge
(PCLK1 PCLK2)
Diagnosis
Bus bridge
FlexRay (1unit)
CAN (3ch)
Bus diagnosis register
Flash control register
RAMECC/Diagnosis
(XBS-RAM)
RX DA-B,TXDA-B,
TX ENA-B,STOPWT
I/O port setting
Base timer (2ch)
Reload timer (4ch)
U/D counter (2ch)
TIOA0-1, TIOB0-1
TIN0-3, TOT0-3
TRG0-5, PPG0-23
WDT1 calibration
Main Flash/WorkFlash
Low-voltage detection (internal
power supply low-voltage detection)
Low-voltage detection (external
power supply low-voltage detection)
/\
SPANSION“
‘
o M391F585LB/F586LB/F587LB/F585LD/F586LD/F587LD
|:|
Exlnnm w. W
m
mm
db
mm mm
Dwm ‘ mow
Anmn 1 mm
DataSheet
38 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
• MB91F585LB/F586LB/F587LB/F585LD/F586LD/F587LD
F ro m Ma s te r
T o S l a ve
F ro m Ma s te r
T o S l a ve
M D0,M D1 ,P127
SOT0-4,SIN0-4,
DTTI0-1,RTO0-11
IN0-7
ADTG0-2,A N0-23
NMIX
MO NCLK
RX0-2,
TX0-2
External bus pin
D16-31
, A 00-21 ,
ASX, CS0-3,
RDX ,
W R0X ,W R1X ,
SY SCLK
A IN0-1, BIN0-1,
Z IN0-1
I / O P o rt
XBS C rossbar S w itch
F R 81s C P U core
In s truc tio n
On-chip bus Layer 2
External bus
I / F
Peripheral bus bridge
FlexRay clock control
CR oscillation (trimming)
NMI
1 6 3 2
Wild register
I / O P o rt
Debug In te rfa ce
Regulator
Delay interrupt
Interrupt controller
Regulator control
On-chip bus XBS
M P U
32-bit peripheral bus
Clock Supervisor
Bus
performance
counter
16-bit peripheral bus
BackUp
RAM
Shutdown control
External interrupt input (8ch)
Watchdog timer (SW and HW)
PPG (24ch)
Interrupt request batch read
Generation/clear of DMA transfer request
Clock Monitor
DMAC
RAMECC
/
Operating
mode register
CR oscillator
CAN prescaler
F la sh
RA M
D ata
Clock control
(clock setting, main timer, PLL timer)
Bus bridge
(32-bit 16-bit)
CRC
Waveform generator (12ch)
Output compare (12ch)
A/D converter
Free-run timer (6ch)
Input capture (8ch)
D/A converter
Multi-function serial interface (5ch)
Asynchronous bus bridge
(PCLK1 PCLK2)
INT0-7
Input cut-off
inhibiting signal
MM
DAOUT
FRCK0-5
SCK0-4,
SCS1-3,SCS3_1,
SCS40-43,
SCS40_1-SCS43_1
Clock control register
(frequency dividing setting)
Reset control register
Low-power consumption setting register
RSTX
Asynchronous bus bridge
(PCLK1 PCLK2)
Diagnosis
Bus bridge
FlexRay (1unit)
CAN (3ch)
Bus diagnosis register
Flash control register
RAMECC/Diagnosis
(XBS-RAM)
RXDA-B,TXDA-B,
TXENA-B,STOPWT
I/O port setting
Base timer (2ch)
Reload timer (4ch)
U/D counter (2ch)
TIOA0-1, TIOB0-1
TIN0-3, TOT0-3
TRG0-5, PPG0-23
WDT1 calibration
Main Flash/WorkFlash
On-chip bus Layer 1
Power-on reset
Low-voltage detection (internal
power supply low-voltage detection)
Low-voltage detection (external
power supply low-voltage detection)
/'\
SPANSION”
‘
o M391F585LA/F586LA/F587LAIF585LC/F586LC/F587LC
M BQ1F585LAIF585LC MBS1F586LA/F586LC M 591F587LA/F587LC
BackUp RAM(8KEI) BackUp RAM(8KB) BackUp RAM(SKEI)
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 39
CONFIDENTIAL
MEMORY MAP
• MB91F585LA/F586LA/F587LA/F585LC/F586LC/F587LC
M B 91F585LA/F585LC M B 91F586LA/F586LC M B 91F587LA/F587LC
0000_0000
H
0000_0000
H
0000_0000
H
0000_4000
H
BackUp RAM(8KB) 0000_4000
H
BackUp RAM(8KB) 0000_4000
H
BackUp RAM(8KB)
0000_6000
H
0000_6000
H
0000_6000
H
0001_0000
H
0001_0000
H
0001_0000
H
0001_C000
H
0002_0000
H
0002_8000
H
0007_0000
H
0007_0000
H
0007_0000
H
0010_0000
H
0014_0000
H
0018_0000
H
Reserved
0033_0000
H
0033_0000
H
0033_0000
H
0034_0000
H
0034_0000
H
0034_0000
H
FFFF_FFFF
H
FFFF_FFFF
H
FFFF_FFFF
H
Reserved
Reserved
Reserved
WorkFlash
(64KB)
WorkFlash
(64KB)
WorkFlash
(64KB)
Flash memory Flash memory Flash memory
(512+64)KB (768+64)KB (1024+64)KB
Reserved
Reserved
RAM(48KB)
RAM(64KB)
RAM(96KB)
Reserved Reserved
Reserved
I/O area I/O areaI/O area
I/O area I/O areaI/O area
Interrupt vector table
Reset vector table
000F_FC00
H
0010_0000
H
Interrupt vector table
Reset vector table
000F_FC00
H
Flash memory 0010_0000
H
Interrupt vector table
Reset vector table
000F_FC00
H
Flash memory
/‘\
SPANSION'
‘
o MB91F585LB/F586LB/F587LB/F585LD/F586LD/F587LD
M BMFSBSLBIFSSSLD
BackUp RAM(8KB)
M BB1F586LEIIF536LD
BackUp RAM(8KB)
M BB1F587LEIIF537LD
BackUp RAM(8KB)
DataSheet
40 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
• MB91F585LB/F586LB/F587LB/F585LD/F586LD/F587LD
M B 91F585LB/F585LD MB91F586LB/F586LD M B 91F587LB/F587LD
0000_0000
H
0000_0000
H
0000_0000
H
0000_4000
H
BackUp RAM(8KB) 0000_4000
H
BackUp RAM(8KB) 0000_4000
H
BackUp RAM(8KB)
0000_6000
H
0000_6000
H
0000_6000
H
0001_0000
H
0001_0000
H
0001_0000
H
0001_C000
H
0002_0000
H
0002_8000
H
0007_0000
H
0007_0000
H
0007_0000
H
0010_0000
H
0014_0000
H
0018_0000
H
Reserved
0033_0000
H
0033_0000
H
0033_0000
H
0034_0000
H
0034_0000
H
0034_0000
H
FFFF_FFFF
H
FFFF_FFFF
H
FFFF_FFFF
H
External bus area
WorkFlash
(64KB)
WorkFlash
(64KB)
WorkFlash
(64KB)
Flash memory Flash memory Flash memory
(512+64)KB(768+64)KB (1024+64)KB
Reserved
Reserved
RAM(48KB)
RAM(64KB)
RAM(96KB)
Reserved Reserved
Reserved
I/O area I/O areaI/O area
I/O area I/O areaI/O area
Interrupt vector table
Reset vector table
000F_FC00
H
0010_0000
H
Interrupt vector table
Reset vector table
000F_FC00
H
Flash memory 0010_0000
H
Interrupt vector table
Reset vector table
000F_FC00
H
Flash memory
Reserved
0040_0000
H
External bus area
Reserved
0040_0000
H
External bus area
Reserved
0040_0000
H
/‘\
SPANSION
‘
)
Address ufiset va‘ue/Reglsier name
Address muck
BTWMR R] H BT1TMCR[R/W]B.H.W
, ansTc [RNV] B 7 ,
BT1PCSR/BT1 PRLL [R/W] H BT1FDUT/BT1PRLH/BT1DTBF [RNV] H 5352 ”“9"
BTSEL [RNV] B , BTSSSR [W] 5‘ H
7 41
ADERH [WW] 3. H, w ADERL [Fr/W] 5‘ H. w
ADCSI [R/W] B.H,w ADCSO[R/W]B‘H.W ADCFH [R15 H‘W ADCRD [R15 H‘W
uooouuou
ADCT1 [RNV] B H‘W Aucm [RNV] BM w ADSCH [RNV] B HW ADECH [Fr/W] B.H.W
AID convener
Dam access annbule
-wo
W, Word
(Note)
mum regwster value alter resel
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 41
CONFIDENTIAL
I/O MAP
The following I/O map shows the relationship between memory space and registers for peripheral
resources.
• Legend of I/O Map
The initial register values after reset are indicated as follows:
"1": Initial value "1"
"0": Initial value "0"
"X": Initial value undefined
"-": Reserved bit/Undefined bit
"*": Initial value "0" or "1" according to the setting
Note:
It is prohibited to access addresses not described here.
Read/Write attribute (R: Read W: Write)
Data access attribute
B: Byte
H: Half
-word
W: Word
(Note)
The access by the data access attribute
not described
is disabled.
Initial register value after reset
Address
Address offset value/Register name
Block
Base timer 1
A/D converter
000090H
000094H
000098H
00009CH
0000A0H
0000A4H
0000A8H
+ 0 + 1 + 2 + 3
BT1TMR [R] H
00000000 00000000
BT1TMCR [R/W] B,H,W
00000000 00000000
BT1STC [R/W] B
00000000
-
-
-
-
BT1PCSR/BT1PRLL [R/W] H
00000000 00000000
BT1PDUT/BT1PRLH/BT1DTBF [R/W] H
00000000 00000000
BTSEL [R/W] B
----0000
ADERH [R/W] B, H, W
00000000 00000000
BTSSSR [W] B, H
--------------11
ADERL [R/W] B, H, W
00000000 00000000
ADCS1 [R/W] B,H,W
00000000
ADCS0 [R/W] B,H,W
00000000
ADCR1 [R] B,H,W
------XX
ADCR0 [R] B,H,W
XXXXXXXX
ADCT1 [R/W] B,H,W
00010000
ADCT0 [R/W] B,H,W
00101100
ADSCH [R/W] B,H,W
---00000
ADECH [R/W] B,H,W
---00000
/\
SPANSION
‘
o M391F585LA/F586LA/F587LA/F585LC/F586LC/F587LC
5 Address offset value/Register name
+0 +1 +2 +3
PDRUO[K w] PDRU l [R w] PDRDataSheet
42 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
• MB91F585LA/F586LA/F587LA/F585LC/F586LC/F587LC
Address
Address offset value/Register name
Block
+0
+1
+2
+3
000000H
PDR00[R/W]
B,H,W
XXXXXXXX
PDR01[R/W]
B,H,W
XXXXXXXX
PDR02[R/W]
B,H,W
XXXXXXXX
PDR03[R/W]
B,H,W
XXXXXXXX
Port data register
000004H
PDR04[R/W]
B,H,W
-----XXX
-
PDR06[R/W]
B,H,W
XXXXXXXX
PDR07[R/W]
B,H,W
XXXXXXXX
000008H
PDR08[R/W]
B,H,W
XXXXXXXX
PDR09[R/W]
B,H,W
XXXXXXXX
PDR10[R/W]
B,H,W
XXXXXXXX
PDR11[R/W]
B,H,W
XXXXXXXX
00000CH
PDR12[R/W]
B,H,W
XXXXXXXX
PDR13[R/W]
B,H,W
XX-XXXXX
- -
000010
H
|
000038H
- - - - Reserved
00003CH
WDTCR0[R/W]
B,H,W
-0--0000
WDTCPR0[W]
B,H,W
00000000
WDTCR1[R]
B,H,W
----0010
WDTCPR1[W]
B,H,W
00000000
Watchdog timer
[S]
000040H
-
-
-
Reserved
000044H
DICR[R/W] B
-------0
- - - Delay interrupt
000048
H
|
00005CH
- - Reserved
000060H
TMRLRA0[R/W] H
XXXXXXXX XXXXXXXX
TMR0[R] H
XXXXXXXX XXXXXXXX
Reload timer 0
000064H
TMRLRB0[R/W] H
XXXXXXXX XXXXXXXX
TMCSR0[R/W] B,H,W
00000000 0-000000
000068
H
|
00007CH
- - - - Reserved
000080H
BT0TMR[R] H
00000000 00000000
BT0TMCR[R/W] H
-0000000 00000000
Base timer 0
000084H
BT0TMCR2[R/W]
B
-------0
BT0STC[R/W] B
-0-0-0-0 - -
000088H
BT0PCSR/BT0PRLL[R/W] H
00000000 00000000
BT0PDUT/BT0PRLH/BT0DTBF
[R/W] H
00000000 00000000
00008CH
-
-
-
-
000090H
BT1TMR[R] H
00000000 00000000
BT1TMCR[R/W] H
-0000000 00000000
Base timer 1
000094H
BT1TMCR2[R/W]
B
-------0
BT1STC[R/W] B
-0-0-0-0 - -
000098H
BT1PCSR/BT1PRLL[R/W] H
00000000 00000000
BT1PDUT/BT1PRLH/BT1DTBF[R/W]
H
00000000 00000000
00009CH
BTSEL01[R/W] B
----0000
-
BTSSSR[W] B,H
-------- ------11
Base timer 0,1
/'\
S PA N 5 IO N
‘
5 Address offset value/Register name
+0 +1 +2 +3
0000A0
\
0000FCH
TMRLRAI[R w] H TMR][R] H
XXXXXXXX xxxxxxxx XXXXXXXX XXXXXXXX
TMRLRBI [R’W] H TMCSRI [R w] B,H,W
XXXXXXXX xxxxxxxx 00000000 07000000
TMRLRA2[R w] H TMR2[R] H
XXXXXXXX xxxxxxxx XXXXXXXX XXXXXXXX
TMRLRBZUUW] H TMCSR2[R w] B,H,W
XXXXXXXX xxxxxxxx 00000000 07000000
TMRLRA3[R w] H TMR3[R] H
XXXXXXXX xxxxxxxx XXXXXXXX XXXXXXXX
TMRLRBSUUW] H TMCSR3[R w] B,H,W
XXXXXXXX xxxxxxxx 00000000 07000000
0001 1 x
\
0001 lCH
IRPRUH[R] BHW
007" , 007"
IRPROL[R] B,H,w lRPRlH[R] B,H,w
00m
lRPR1L[R] BHW
IRPR2H[R] BHW
00007 ,
IRPR2L[R] B H,w lRPR3H[R] B,H,w
UUr
IRPR4H[R] BHW
IRPR4L[R] B H,w lRPR5H[R] B,H,w
()0 , 000000"
00 777777 000000" 00 777777
IRPR6H[R]B.H,W IRPR6L[R]B,H,W 1RPR7H[R]B,H,w lRPR7L[R]B.H,W
000000" 000000" 000000" 000000"
IRPRxH[R]B.H,w IRPR8L[R]B,H,W 1RPR9H[R]B,H,W lRPR9L[R]B.H,W
000000" 00 777777 00 777777 00 777777
lRPRlUH[R] IRPRIOL[R] lRPRllH[R] lRPRllL[R]
B,H,w B,H,w B, w BHW
00 , 00 007 0000000
lRPR12H[R] IRPRIZL[R] IRPR13H[R] IRPR13L[R]
B,H,w B,H,w B,H,w BHW
00000007 00000000 00000000 00000000
lRPRl4H[R] IRPR14L[R] IRPR15H[R] IRPR15L[R]
B,H,w B,H,w B,H,w BHW
00 , 00 00000000 000007"
lRPR16H[R] IRPR16L[R] IRPR17H[R]
B,H,w B,H,w B, w
00 , 00 007
lRPRlXH[R] lRPRlXL[R]
B,H,w B,H,w
s!
000148
\
000 1 FCH
PCNO[K w] B.H,w
00000000 00000070
PCSR()[W] H,w
xxxxxxxx xxxxxxxx
PDUT()[W] H,w
xxxxxxxx xxxxxxxx
PTMRO[R] H,w
1111111111111111
PCN l [R w] B.H,w
00000000 00000070
PCSR1[W] H,w
xxxxxxxx xxxxxxxx
PDUT1[W] H,w
xxxxxxxx xxxxxxxx
PTMRI[R] H,w
1111111111111111
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 43
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
0000A0
H
|
0000FCH
- - - - Reserved
000100H
TMRLRA1[R/W] H
XXXXXXXX XXXXXXXX
TMR1[R] H
XXXXXXXX XXXXXXXX
Reload timer 1
000104H
TMRLRB1[R/W] H
XXXXXXXX XXXXXXXX
TMCSR1[R/W] B,H,W
00000000 0-000000
000108H
TMRLRA2[R/W] H
XXXXXXXX XXXXXXXX
TMR2[R] H
XXXXXXXX XXXXXXXX
Reload timer 2
00010CH
TMRLRB2[R/W] H
XXXXXXXX XXXXXXXX
TMCSR2[R/W] B,H,W
00000000 0-000000
000110H
TMRLRA3[R/W] H
XXXXXXXX XXXXXXXX
TMR3[R] H
XXXXXXXX XXXXXXXX
Reload timer 3
000114H
TMRLRB3[R/W] H
XXXXXXXX XXXXXXXX
TMCSR3[R/W] B,H,W
00000000 0-000000
000118
H
|
00011CH
- - - - Reserved
000120H
IRPR0H[R] B,H,W
00------
IRPR0L[R] B,H,W
00------
IRPR1H[R] B,H,W
00------
IRPR1L[R] B,H,W
--------
Interrupt request
batch read
register
000124H
IRPR2H[R] B,H,W
--------
IRPR2L[R] B,H,W
0000----
IRPR3H[R] B,H,W
00------
IRPR3L[R] B,H,W
00------
000128H
IRPR4H[R] B,H,W
00------
IRPR4L[R] B,H,W
000000--
IRPR5H[R] B,H,W
00------
IRPR5L[R] B,H,W
00------
00012CH
IRPR6H[R] B,H,W
000000--
IRPR6L[R] B,H,W
000000--
IRPR7H[R] B,H,W
000000--
IRPR7L[R] B,H,W
000000--
000130H
IRPR8H[R] B,H,W
000000--
IRPR8L[R] B,H,W
00------
IRPR9H[R] B,H,W
00------
IRPR9L[R] B,H,W
00------
000134H
IRPR10H[R]
B,H,W
00------
IRPR10L[R]
B,H,W
00------
IRPR11H[R]
B,H,W
00------
IRPR11L[R]
B,H,W
0000000-
000138H
IRPR12H[R]
B,H,W
0000000-
IRPR12L[R]
B,H,W
00000000
IRPR13H[R]
B,H,W
00000000
IRPR13L[R]
B,H,W
00000000
00013CH
IRPR14H[R]
B,H,W
00------
IRPR14L[R]
B,H,W
00------
IRPR15H[R]
B,H,W
00000000
IRPR15L[R]
B,H,W
00000---
000140 H
IRPR16H[R]
B,H,W
00------
IRPR16L[R]
B,H,W
00------
IRPR17H[R]
B,H,W
00------
IRPR17L[R]B,H,W
00------
000144 H
IRPR18H[R]
B,H,W
00------
IRPR18L[R]
B,H,W
000000--
- -
000148
H
|
0001FCH
- - - - Reserved
000200H
PCN0[R/W] B,H,W
00000000 000000-0
PCSR0[W] H,W
XXXXXXXX XXXXXXXX
PPG0
000204H
PDUT0[W] H,W
XXXXXXXX XXXXXXXX
PTMR0[R] H,W
11111111 11111111
000208H
PCN1[R/W] B,H,W
00000000 000000-0
PCSR1[W] H,W
XXXXXXXX XXXXXXXX
PPG1
00020CH
PDUT1[W] H,W
XXXXXXXX XXXXXXXX
PTMR1[R] H,W
11111111 11111111
/\
SPANSION
‘
Address offset value/Register name
+0 ‘ +1
+2 ‘ +3
PCN2[R w] BJ—LW
00000000 0000000
PCSRZ[W] H,w
xxxxxxxx xxxxxxxx
PDUTZ[W] H,w
xxxxxxxx xxxxxxxx
PTMR2[R] H,w
1111111111111111
PCN3[R w] BJ—LW
00000000 0000000
PCSR3[W] H,w
xxxxxxxx xxxxxxxx
PDUT3[W] H,w
xxxxxxxx xxxxxxxx
PTMR3[R] H,w
1111111111111111
PCN4[K w] BJ—LW
00000000 0000000
PCSR4[W] H,w
xxxxxxxx xxxxxxxx
PDUT4[W] H,w
xxxxxxxx xxxxxxxx
PTMR4[R] H,w
1111111111111111
PCN5[K w] BJ—LW
00000000 0000000
PCSRS[W] H,w
xxxxxxxx xxxxxxxx
PDUTS[W] H,w
xxxxxxxx xxxxxxxx
PTMR5[R] H,w
1111111111111111
PCN6[K w] BJ—LW
00000000 0000000
PCSR6[W] H,w
xxxxxxxx xxxxxxxx
PDUT6[W] H,w
xxxxxxxx xxxxxxxx
PTMR6[R] H,w
1111111111111111
PCN7[K w] BJ—LW
00000000 0000000
PCSR7[W] H,w
xxxxxxxx xxxxxxxx
PDUT7[W] H,w
xxxxxxxx xxxxxxxx
PTMR7[R] H,w
1111111111111111
PCN8[K w] BJ—LW
00000000 0000000
PCSR8[W] H,w
xxxxxxxx xxxxxxxx
PDUT8[W] H,w
xxxxxxxx xxxxxxxx
PTMR8[R] H,w
1111111111111111
PCN9[K w] BJ—LW
00000000 0000000
PCSR9[W] H,w
xxxxxxxx xxxxxxxx
PDUT9[W] H,w
xxxxxxxx xxxxxxxx
PTMR9[R] H,w
1111111111111111
PCNl()[R/W] BJ—Lw
00000000 0000000
PCSR10[W] H,w
xxxxxxxx xxxxxxxx
PDUT1(J[W] H,w
xxxxxxxx xxxxxxxx
PTMR10[R] H,w
1111111111111111
PCN11[R’W]B.H,W
00000000 00000070
PCSRll[W] H,w
xxxxxxxx xxxxxxxx
PDUT11[W] H,w
xxxxxxxx xxxxxxxx
PTMR]1[R] H,w
1111111111111111
PCNlZ[R/W] BJ—Lw
00000000 0000000
PCSR12[W] H,w
xxxxxxxx xxxxxxxx
PDUT12[W] H,w
xxxxxxxx xxxxxxxx
PTMRIZ[R] H,w
1111111111111111
PCNI3[R/W] B,H,W
00000000 0000000
PCSR13[W] H,w
xxxxxxxx xxxxxxxx
PDUT13[W] H,w
xxxxxxxx xxxxxxxx
PTMR13[R] H,w
1111111111111111
PCN14[R/W] BJ—Lw
00000000 0000000
PCSR14[W] H,w
xxxxxxxx xxxxxxxx
PDUT14[W] H,w
xxxxxxxx xxxxxxxx
PTMR14[R] H,w
1111111111111111
DataSheet
44 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
000210H
PCN2[R/W] B,H,W
00000000 000000-0
PCSR2[W] H,W
XXXXXXXX XXXXXXXX
PPG2
000214H
PDUT2[W] H,W
XXXXXXXX XXXXXXXX
PTMR2[R] H,W
11111111 11111111
000218H
PCN3[R/W] B,H,W
00000000 000000-0
PCSR3[W] H,W
XXXXXXXX XXXXXXXX
PPG3
00021CH
PDUT3[W] H,W
XXXXXXXX XXXXXXXX
PTMR3[R] H,W
11111111 11111111
000220H
PCN4[R/W] B,H,W
00000000 000000-0
PCSR4[W] H,W
XXXXXXXX XXXXXXXX
PPG4
000224H
PDUT4[W] H,W
XXXXXXXX XXXXXXXX
PTMR4[R] H,W
11111111 11111111
000228H
PCN5[R/W] B,H,W
00000000 000000-0
PCSR5[W] H,W
XXXXXXXX XXXXXXXX
PPG5
00022CH
PDUT5[W] H,W
XXXXXXXX XXXXXXXX
PTMR5[R] H,W
11111111 11111111
000230H
PCN6[R/W] B,H,W
00000000 000000-0
PCSR6[W] H,W
XXXXXXXX XXXXXXXX
PPG6
000234H
PDUT6[W] H,W
XXXXXXXX XXXXXXXX
PTMR6[R] H,W
11111111 11111111
000238H
PCN7[R/W] B,H,W
00000000 000000-0
PCSR7[W] H,W
XXXXXXXX XXXXXXXX
PPG7
00023CH
PDUT7[W] H,W
XXXXXXXX XXXXXXXX
PTMR7[R] H,W
11111111 11111111
000240H
PCN8[R/W] B,H,W
00000000 000000-0
PCSR8[W] H,W
XXXXXXXX XXXXXXXX
PPG8
000244H
PDUT8[W] H,W
XXXXXXXX XXXXXXXX
PTMR8[R] H,W
11111111 11111111
000248H
PCN9[R/W] B,H,W
00000000 000000-0
PCSR9[W] H,W
XXXXXXXX XXXXXXXX
PPG9
00024CH
PDUT9[W] H,W
XXXXXXXX XXXXXXXX
PTMR9[R] H,W
11111111 11111111
000250H
PCN10[R/W] B,H,W
00000000 000000-0
PCSR10[W] H,W
XXXXXXXX XXXXXXXX
PPG10
000254H
PDUT10[W] H,W
XXXXXXXX XXXXXXXX
PTMR10[R] H,W
11111111 11111111
000258H
PCN11[R/W] B,H,W
00000000 000000-0
PCSR11[W] H,W
XXXXXXXX XXXXXXXX
PPG11
00025CH
PDUT11[W] H,W
XXXXXXXX XXXXXXXX
PTMR11[R] H,W
11111111 11111111
000260H
PCN12[R/W] B,H,W
00000000 000000-0
PCSR12[W] H,W
XXXXXXXX XXXXXXXX
PPG12
000264H
PDUT12[W] H,W
XXXXXXXX XXXXXXXX
PTMR12[R] H,W
11111111 11111111
000268H
PCN13[R/W] B,H,W
00000000 000000-0
PCSR13[W] H,W
XXXXXXXX XXXXXXXX
PPG13
00026CH
PDUT13[W] H,W
XXXXXXXX XXXXXXXX
PTMR13[R] H,W
11111111 11111111
000270H
PCN14[R/W] B,H,W
00000000 000000-0
PCSR14[W] H,W
XXXXXXXX XXXXXXXX
PPG14
000274H
PDUT14[W] H,W
XXXXXXXX XXXXXXXX
PTMR14[R] H,W
11111111 11111111
/'\
S PA N 5 IO N
\
5 Address offset value/Register name
+0 \ +1 +2 ‘ +3
PCNIS[R/W] BJ—Lw PCSR15[W] H,w
00000000 0000000 XXXXXXXX xxxxxxxx
PDUT15[W] H,w PTMRIS[R] H,w
XXXXXXXXXXXXXXXX 1111111111111111
PCNI6[R/W] BJ—Lw PCSR16[W] H,w
00000000 0000000 XXXXXXXX xxxxxxxx
PDUT16[W] H,w PTMR16[R] H,w
XXXXXXXXXXXXXXXX 1111111111111111
PCNl7[R/W] BJ—Lw PCSR17[W] H,w
00000000 0000000 XXXXXXXX xxxxxxxx
PDUT17[W] H,w PTMRI7[R] H,w
XXXXXXXXXXXXXXXX 1111111111111111
PCN18[R/W] BJ—Lw PCSR18[W] H,w
00000000 0000000 XXXXXXXX xxxxxxxx
PDUT18[W] H,w PTMR18[R] H,w
XXXXXXXXXXXXXXXX 1111111111111111
PCNI9[R/W] BJ—Lw PCSR19[W] H,w
00000000 0000000 XXXXXXXX xxxxxxxx
PDUT19[W] H,w PTMR19[R] H,w
XXXXXXXXXXXXXXXX 1111111111111111
PCN2()[R/W] BJ—Lw PCSRZ()[W] H,w
00000000 0000000 XXXXXXXX xxxxxxxx
PDUTZ(J[W] H,w PTMR20[R] H,w
XXXXXXXXXXXXXXXX 1111111111111111
PCN21[R/W] BJ—Lw PCSR21[W] H,w
00000000 0000000 XXXXXXXX xxxxxxxx
PDUTZ][W] H,w PTMR21[R] H,w
XXXXXXXXXXXXXXXX 1111111111111111
PCN22[R/W] BJ—Lw PCSRZZ[W] H,w
00000000 0000000 XXXXXXXX xxxxxxxx
PDUT22[W] H,w PTMR22[R] H,w
XXXXXXXXXXXXXXXX 1111111111111111
PCN23[R/W] BJ—Lw PCSRZ3[W] H,w
00000000 0000000 XXXXXXXX xxxxxxxx
PDUTZ3[W] H,w PTMR23[R] H,w
XXXXXXXXXXXXXXXX 1111111111111111
GTRS()[R/W] B,H,w GTRS l [R w] BJ—LW
70000000 0000000 0000000 0000000
GTRSZ[R/W] B,H,w GTRS}[K w] BJ—LW
70000000 0000000 0000000 0000000
GTRquR/w] B,H,w GTRSS[K w] BJ—LW
70000000 0000000 0000000 0000000
GTRS6[R/W] B,H,w GTRS7[K w] BJ—LW
70000000 0000000 0000000 0000000
GTRSx[R/w] B,H,w GTRS‘)[K w] BJ—LW
70000000 0000000 0000000 0000000
GTRSI()[R/W] BJ—Lw (iTRSll[R’W] B,H.w
70000000 0000000 0000000 0000000
GTREN()[R/W] H,w GTREN l [R w] H.W
00000000 00000000 W 00000000
0002DCH , , Reserved
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 45
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
000278H
PCN15[R/W] B,H,W
00000000 000000-0
PCSR15[W] H,W
XXXXXXXX XXXXXXXX
PPG15
00027CH
PDUT15[W] H,W
XXXXXXXX XXXXXXXX
PTMR15[R] H,W
11111111 11111111
000280H
PCN16[R/W] B,H,W
00000000 000000-0
PCSR16[W] H,W
XXXXXXXX XXXXXXXX
PPG16
000284H
PDUT16[W] H,W
XXXXXXXX XXXXXXXX
PTMR16[R] H,W
11111111 11111111
000288H
PCN17[R/W] B,H,W
00000000 000000-0
PCSR17[W] H,W
XXXXXXXX XXXXXXXX
PPG17
00028CH
PDUT17[W] H,W
XXXXXXXX XXXXXXXX
PTMR17[R] H,W
11111111 11111111
000290H
PCN18[R/W] B,H,W
00000000 000000-0
PCSR18[W] H,W
XXXXXXXX XXXXXXXX
PPG18
000294H
PDUT18[W] H,W
XXXXXXXX XXXXXXXX
PTMR18[R] H,W
11111111 11111111
000298H
PCN19[R/W] B,H,W
00000000 000000-0
PCSR19[W] H,W
XXXXXXXX XXXXXXXX
PPG19
00029CH
PDUT19[W] H,W
XXXXXXXX XXXXXXXX
PTMR19[R] H,W
11111111 11111111
0002A0H
PCN20[R/W] B,H,W
00000000 000000-0
PCSR20[W] H,W
XXXXXXXX XXXXXXXX
PPG20
0002A4H
PDUT20[W] H,W
XXXXXXXX XXXXXXXX
PTMR20[R] H,W
11111111 11111111
0002A8H
PCN21[R/W] B,H,W
00000000 000000-0
PCSR21[W] H,W
XXXXXXXX XXXXXXXX
PPG21
0002ACH
PDUT21[W] H,W
XXXXXXXX XXXXXXXX
PTMR21[R] H,W
11111111 11111111
0002B0H
PCN22[R/W] B,H,W
00000000 000000-0
PCSR22[W] H,W
XXXXXXXX XXXXXXXX
PPG22
0002B4H
PDUT22[W] H,W
XXXXXXXX XXXXXXXX
PTMR22[R] H,W
11111111 11111111
0002B8H
PCN23[R/W] B,H,W
00000000 000000-0
PCSR23[W] H,W
XXXXXXXX XXXXXXXX
PPG23
0002BCH
PDUT23[W] H,W
XXXXXXXX XXXXXXXX
PTMR23[R] H,W
11111111 11111111
0002C0H
GTRS0[R/W] B,H,W
-0000000 -0000000
GTRS1[R/W] B,H,W
-0000000 -0000000
PPG Control
0002C4H
GTRS2[R/W] B,H,W
-0000000 -0000000
GTRS3[R/W] B,H,W
-0000000 -0000000
0002C8H
GTRS4[R/W] B,H,W
-0000000 -0000000
GTRS5[R/W] B,H,W
-0000000 -0000000
0002CCH
GTRS6[R/W] B,H,W
-0000000 -0000000
GTRS7[R/W] B,H,W
-0000000 -0000000
0002D0H
GTRS8[R/W] B,H,W
-0000000 -0000000
GTRS9[R/W] B,H,W
-0000000 -0000000
0002D4H
GTRS10[R/W] B,H,W
-0000000 -0000000
GTRS11[R/W] B,H,W
-0000000 -0000000
0002D8H
GTREN0[R/W] H,W
00000000 00000000
GTREN1[R/W] H,W
-------- 00000000
0002DCH
-
-
Reserved
/\
5 PA N 5 IO N
‘
5 Address offset value/Register name
+0 +1 +2 +3
GATEC0[R/w] GATEC2[R’W]
B H,w BJ—LW
, 00 ,, )0
GATEC4[R/W] GATECX[R’W]
H,w BJ—LW
, 00 ,, ~00
GATECI U[R/W] GATEC12[K w]
B H,w BJ—LW
0002ECH , , , , Reserved
UDCRLU[R]
BJ—LW
00000000
CCR0[R/w] 3,1-1 CSR0[R] B
00000000 7000 1000 00000000
UDCRLI [R]
BJ—LW
00000000
CCR1[R/w] 3,1-1 CSR] [R] B
00000000 7000 1000 00000000
000300H , Reserved
000304H , \ , , \ , Reserved
00030er ,
00030CH , , , \ ,
MPUCR[R/w] H
00000070 ""0100
000314H , , , \ ,
000310H ,
0003 [CH , , \ ,
DPVAR[R] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
DPVSR[R/W] H
00000~0
DEAR[R] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
DESR[R w] H
, 00000~0
PABR(J[R/W] w
XXXXXXXX XXXXXXXX XXXXXXXX XXXXOOOO
PACR0[R/w] H
0000000 00000770
PABR] [R/W] w
XXXXXXXX XXXXXXXX XXXXXXXX XXXXOOOO
PAC R 1 [WW] H
0000000 00000770
PABR2[R/W] w
XXXXXXXX XXXXXXXX XXXXXXXX XXXXOOOO
PAC R2 [R/W] H
0000000 00000770
PABR3[R/W] w
XXXXXXXX XXXXXXXX XXXXXXXX XXXXOOOO
PAC R3 [R/W] H
0000000 00000770
PAB R4[R/w] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000
DataSheet
46 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
0002E0H -
GATEC0[R/W]
B,H,W
------00
-
GATEC2[R/W]
B,H,W
------00
PPG GATE
Control
0002E4H -
GATEC4[R/W]
B,H,W
------00
-
GATEC8[R/W]
B,H,W
------00
0002E8H -
GATEC10[R/W]
B,H,W
------00
-
GATEC12[R/W]
B,H,W
------00
0002ECH
-
-
-
-
Reserved
0002F0H
RCRH0[W] H,W
00000000
RCRL0[W] B,H,W
00000000
UDCRH0[R] H,W
00000000
UDCRL0[R]
B,H,W
00000000
U/D counter 0
0002F4H
CCR0[R/W] B,H
00000000 -0001000
-
CSR0[R] B
00000000
0002F8H
RCRH1[W] H,W
00000000
RCRL1[W] B,H,W
00000000
UDCRH1[R] H,W
00000000
UDCRL1[R]
B,H,W
00000000
U/D counter 1
0002FCH
CCR1[R/W] B,H
00000000 -0001000
-
CSR1[R] B
00000000
000300H
-
Reserved
000304H
-
-
-
-
Reserved
000308H
-
Reserved
00030CH
-
-
-
-
000310H - -
MPUCR[R/W] H
000000-0 ----0100
MPU [S]
(Only the CPU
can access this
area)
000314H
-
-
-
-
000318H
-
00031CH
-
-
-
000320H
DPVAR[R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000324H - -
DPVSR[R/W] H
-------- 00000--0
000328H
DEAR[R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00032CH - -
DESR[R/W] H
-------- 00000--0
000330H
PABR0[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
000334H - -
PACR0[R/W] H
000000-0 00000--0
000338H
PABR1[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
00033CH - -
PACR1[R/W] H
000000-0 00000--0
000340H
PABR2[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
000344H - -
PACR2[R/W] H
000000-0 00000--0
000348H
PABR3[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
00034CH - -
PACR3[R/W] H
000000-0 00000--0
000350H
PABR4[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
/'\
5 PA N 5 IO N
‘
5 Address offset value/Register name
+0 +1 +2 ‘ +3
PACR4[R/W] H
0000000 0000040
PABR5[R/W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxoooo
PACRS[R/W] H
0000000 0000040
PABR6[R/W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxoooo
PACR6[R/W] H
0000000 0000040
PABR7[R/W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxoooo
PACR7[R/W] H
0000000 0000040
000370H ,
000374H , \ , \ ,
000378H ,
00037cH , \ , \ ,
000380H ,
000384H , \ , \ ,
000388H ,
UOOZXCH , \ , \ ,
000390H ,
000394H , \ , \ ,
000398H ,
00039cH , \ , \ ,
()003A0H ,
0003MH , \ , \ ,
()(J(J3AXH ,
0003AcH , , ,
0003B0
\
000qu
ICSEL()[R/W] ICSEL1[R/W] ICSEL2[R’W] lCSEL3[R/W]
B,H,w B H,w B,H w BJ-Lw
, 4J00 , 4) , 70 , "4)
ICSEL4[R/W] ICSELS[R/W] ICSEL6[R’W] lCSEL7[R/W]
H,w H,w B, w BJ-Lw
4) , 4) , 70 000
ICSEL8[R/W] ICSEL9[R/W] lCSELlU[R’W] lCSELll[RW] nd
B H,w B H,w B,H,w BJ-Lw A
4) , 4) ,, 7000 ""7000
ICSELlZ[R/W] ICSEL13[R/W] lCSELl4[R’W] lCSEL]5[R/W]
B,H,w B,H,w B,H,w BJ-Lw
, 4J00 , 4J00 ,, 7000 , "4)
ICSEL16[R/W] ICSEL17[R/W] lCSELlX[R’W] lCSELl9[R/W]
H,w H,w w
4) 4)
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 47
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
000354H - -
PACR4[R/W] H
000000-0 00000--0
MPU [S]
(Only the CPU
can access this
area)
000358H
PABR5[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
00035CH - -
PACR5[R/W] H
000000-0 00000--0
000360H
PABR6[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
000364H - -
PACR6[R/W] H
000000-0 00000--0
000368H
PABR7[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
00036CH - -
PACR7[R/W] H
000000-0 00000--0
000370H
-
Reserved [S]
000374H
-
-
-
000378H
-
00037CH
-
-
-
000380H
-
000384H
-
-
-
000388H
-
00038CH
-
-
-
000390H
-
000394H
-
-
-
Reserved [S]
000398H
-
00039CH
-
-
-
0003A0H
-
0003A4H
-
-
-
0003A8H
-
0003ACH
-
-
-
0003B0
H
|
0003FCH
- - - - Reserved [S]
000400H
ICSEL0[R/W]
B,H,W
-----000
ICSEL1[R/W]
B,H,W
-------0
ICSEL2[R/W]
B,H,W
-------0
ICSEL3[R/W]
B,H,W
-------0
Generation and
clearing of DMA
transfer requests
000404H
ICSEL4[R/W]
B,H,W
-------0
ICSEL5[R/W]
B,H,W
-------0
ICSEL6[R/W]
B,H,W
-------0
ICSEL7[R/W]
B,H,W
-----000
000408H
ICSEL8[R/W]
B,H,W
-------0
ICSEL9[R/W]
B,H,W
-------0
ICSEL10[R/W]
B,H,W
-----000
ICSEL11[R/W]
B,H,W
-----000
00040CH
ICSEL12[R/W]
B,H,W
-----000
ICSEL13[R/W]
B,H,W
-----000
ICSEL14[R/W]
B,H,W
-----000
ICSEL15[R/W]
B,H,W
-------0
000410H
ICSEL16[R/W]
B,H,W
-------0
ICSEL17[R/W]
B,H,W
-------0
ICSEL18[R/W]
B,H,W
-------0
ICSEL19[R/W]
B,H,W
-------0
/\
5 PA N 5 IO N
‘
5 Address offset value/Register name
+0 +1 +2 +3
ICSELZ()[R/W] ICSELZ 1 [R/W] lCSEL22[R’W] lCSEL23[R/W]
H,w B,H,w B,H,w BJ—LW
4) , r000 ,, 7000 ""7000
ICSEL24[R/w] ICSELZS[R/W] 1cSEL26[R/w] lCSEL27[R/W] "“1
B,H,w H,w w BJ—LW A
""7000 ""7000 , "0
0004ch , , , ,
000420H , , , ,
000424
\
00043cH
[CR00[K w] ICROI [R w] ICRUZ[R’W] lCR()3[R/W]
B,H,w B,H,w B,H,w BJ—LW
"711111 "711111 "711111 "711111
[CR04[K w] [CR05[K w] [CR06[R/w] lCR()7[R/W]
B,H,w B,H,w B,H,w BJ—LW
"711111 "711111 "711111 "711111
[CR08[K w] [CR09[K w] ICRlU[R’W] ICRll[R w]
B,H,w B,H,w B,H,w BJ—LW
"711111 "711111 "711111 "711111
ICRlZ[K w] [CR13[K w] [CR14[R’W] lCRl S[R/W]
B,H,w B,H,w B,H,w BJ—LW
"711111 "711111 "711111 "711111
[CR16[R w] ICRl7[K w] [CRIXUUW] lCRl9[R/W]
B,H,w B,H,w B,H,w BJ—LW
"711111 "711111 "711111 "711111
[CR20[K w] [CR2 1 [R w] [CR22[R/w] lCRZ3[R/W]
B,H,w B,H,w B,H,w BJ—LW
"711111 "711111 "711111 "711111
[CR24[K w] [CR25[K w] [CR26[R’W] lCRZ7[R/W]
B,H,w B,H,w B,H,w BJ—LW
"711111 "711111 "711111 "711111
[CR28[K w] [CR29[K w] ICR30[R’W] lCR31[R/W]
B,H,w B,H,w B,H,w BJ—LW
"711111 "711111 "711111 "711111
[CR32[K w] [CR33[K w] ICR34[R’W] lCR3S[R/W]
B,H,w B,H,w B,H,w BJ—LW
"711111 "711111 "711111 "711111
[CR36[K w] [CR37[K w] ICR38[R’W] lCR39[R/W]
B,H,w B,H,w B,H,w BJ—LW
"711111 "711111 "711111 "711111
ICR40[K w] ICR4I [R w] ICR42[R’W] 1CR43[R/w]
B,H,w B,H,w B,H,w BJ—LW
"711111 "711111 "711111 "711111
ICR44[K w] ICR45[K w] ICR46[R’W] 1CR47[R/w]
B,H,w B,H,w B,H,w BJ—LW
"711111 "711111 "711111 "711111
000470
\
00047cH
DataSheet
48 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
000414H
ICSEL20[R/W]
B,H,W
-------0
ICSEL21[R/W]
B,H,W
-----000
ICSEL22[R/W]
B,H,W
-----000
ICSEL23[R/W]
B,H,W
-----000
Generation and
clearing of DMA
transfer requests
000418H
ICSEL24[R/W]
B,H,W
-----000
ICSEL25[R/W]
B,H,W
-----000
ICSEL26[R/W]
B,H,W
-------0
ICSEL27[R/W]
B,H,W
-------0
00041CH
-
-
-
-
000420H
-
-
-
-
000424
H
|
00043CH
- - - - Reserved
000440H
ICR00[R/W]
B,H,W
---11111
ICR01[R/W]
B,H,W
---11111
ICR02[R/W]
B,H,W
---11111
ICR03[R/W]
B,H,W
---11111
Interrupt
controller [S]
000444H
ICR04[R/W]
B,H,W
---11111
ICR05[R/W]
B,H,W
---11111
ICR06[R/W]
B,H,W
---11111
ICR07[R/W]
B,H,W
---11111
000448H
ICR08[R/W]
B,H,W
---11111
ICR09[R/W]
B,H,W
---11111
ICR10[R/W]
B,H,W
---11111
ICR11[R/W]
B,H,W
---11111
00044CH
ICR12[R/W]
B,H,W
---11111
ICR13[R/W]
B,H,W
---11111
ICR14[R/W]
B,H,W
---11111
ICR15[R/W]
B,H,W
---11111
000450H
ICR16[R/W]
B,H,W
---11111
ICR17[R/W]
B,H,W
---11111
ICR18[R/W]
B,H,W
---11111
ICR19[R/W]
B,H,W
---11111
000454H
ICR20[R/W]
B,H,W
---11111
ICR21[R/W]
B,H,W
---11111
ICR22[R/W]
B,H,W
---11111
ICR23[R/W]
B,H,W
---11111
000458H
ICR24[R/W]
B,H,W
---11111
ICR25[R/W]
B,H,W
---11111
ICR26[R/W]
B,H,W
---11111
ICR27[R/W]
B,H,W
---11111
00045CH
ICR28[R/W]
B,H,W
---11111
ICR29[R/W]
B,H,W
---11111
ICR30[R/W]
B,H,W
---11111
ICR31[R/W]
B,H,W
---11111
000460H
ICR32[R/W]
B,H,W
---11111
ICR33[R/W]
B,H,W
---11111
ICR34[R/W]
B,H,W
---11111
ICR35[R/W]
B,H,W
---11111
000464H
ICR36[R/W]
B,H,W
---11111
ICR37[R/W]
B,H,W
---11111
ICR38[R/W]
B,H,W
---11111
ICR39[R/W]
B,H,W
---11111
000468H
ICR40[R/W]
B,H,W
---11111
ICR41[R/W]
B,H,W
---11111
ICR42[R/W]
B,H,W
---11111
ICR43[R/W]
B,H,W
---11111
00046CH
ICR44[R/W]
B,H,W
---11111
ICR45[R/W]
B,H,W
---11111
ICR46[R/W]
B,H,W
---11111
ICR47[R/W]
B,H,W
---11111
000470
H
|
00047CH
- - - - Reserved [S]
/'\
S PA N 5 IO N
‘
5 Address offset value/Register name
+0 +1 +2 +3
Reset eomrol [S]
Power
consumplion
comml [s]
* Wrifing m
STBCR by
DMA is
disabled.
000484H , , , , Reserved [S]
DIVRO[R w] DIVR2[R/W]
B,H,w B,H,W
(xx 001 1
UOOAXCH , , , , Reserved [S]
I()RR()[R/W] IURR1[R/W] I<)rr2[r w]="" 10rr3[r/w]="" b,h,w="" b,h,w="" b,h,w="" bj—lw="" 70000000="" 70000000="" 70000000="" 70000000="" iurr4[r/w]="" iurrs[r/w]="" i()rr6[k="" w]="" 10rr7[r/w]="" b,h,w="" b,h,w="" b,h,w="" bj—lw="" 70000000="" 70000000="" 70000000="" 70000000="" 00049er="" ,="" ,="" ,="" ,="" 00049ch="" ,="" ,="" ,="" ,="" 0004a0h="" ,="" ,="" ,="" ,="" reserved="" canpre[r’w]="" b,h,w="" ""0000="" 0004ax="" [="" 0004ach="" 000480h="" ,="" ,="" ,="" ,="" reserved="" 000484="" [="" 0004c0h="" cucr]="" [r/w]="" b,h,w="" cutd]="" [r/w]="" b,h,w="" 777777="" "70700="" 11000011="" 01010000="" cutri[r]="" b,h,w="" 77777777="" 00000000="" 00000000="" 00000000="" 0004cc="" [="" 00040ch="" cscfg[r'w]="" cmcfg[r’w]="" b,h="" w="" bj—lw="" 00000000="" 0004e4h="" ,="" ,="" ,="" ,="" pllzdivm[r’w]="" pll2d1vn[r/w]="" pll2d1v(;[r="" w]="" pllzmulg[k="" w]="" b,h,w="" b,h,w="" b,h,w="" bj—lw="" ""0000="" 70000000="" ""0000="" 00000000="" pll2ctrl[r/w]="" pllzdivk[r/w]="" clkr2[r/w]="" b,h,w="" b="" h,w="" b,h,w="" ""0000="" ,="" 000~000="" 0004f0="" [="" 0004fch="" 000500h="" ,="" reserved="" 000504h="" ,="" reserved="">DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 49
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
000480H
RSTRR[R]
B,H,W
XXXX--XX
RSTCR[R/W]
B,H,W
111----0
STBCR[R/W]
B,H,W*
000---11
-
Reset control [S]
Power
consumption
control [S]
* Writing to
STBCR by
DMA is
disabled.
000484H
-
-
-
-
Reserved [S]
000488H
DIVR0[R/W]
B,H,W
000-----
-
DIVR2[R/W]
B,H,W
0011----
- Clock control
[S]
00048CH
-
-
-
-
Reserved [S]
000490H
IORR0[R/W]
B,H,W
-0000000
IORR1[R/W]
B,H,W
-0000000
IORR2[R/W]
B,H,W
-0000000
IORR3[R/W]
B,H,W
-0000000
DMA transfer
request from a
peripheral [S]
000494H
IORR4[R/W]
B,H,W
-0000000
IORR5[R/W]
B,H,W
-0000000
IORR6[R/W]
B,H,W
-0000000
IORR7[R/W]
B,H,W
-0000000
000498H
-
-
-
-
00049CH
-
-
-
-
0004A0H
-
-
-
-
Reserved
0004A4H
CANPRE[R/W]
B,H,W
----0000
- - - CAN prescaler
0004A8
H
|
0004ACH
- - - - Reserved
0004B0H
-
-
-
-
Reserved
0004B4
H
|
0004C0H
- - - - Reserved
0004C4H
CUCR1[R/W] B,H,W
-------- ---0--00
CUTD1[R/W] B,H,W
11000011 01010000
WDT1
calibration
0004C8H
CUTR1[R] B,H,W
-------- 00000000 00000000 00000000
0004CC
H
|
0004DCH
- - - - Reserved
0004E0H - -
CSCFG[R/W]
B,H,W
---0----
CMCFG[R/W]
B,H,W
00000000
Clock monitor
0004E4H
-
-
-
-
0004E8H
PLL2DIVM[R/W]
B,H,W
----0000
PLL2DIVN[R/W]
B,H,W
-0000000
PLL2DIVG[R/W]
B,H,W
----0000
PLL2MULG[R/W]
B,H,W
00000000
FlexRay/RDC
clock control
0004ECH
PLL2CTRL[R/W]
B,H,W
----0000
PLL2DIVK[R/W]
B,H,W
-------0
CLKR2[R/W]
B,H,W
000--000
-
0004F0
H
|
0004FCH
- - - - Reserved
000500H
-
Reserved
000504H
-
Reserved
/\
5 PA N 5 IO N
‘
5 Address offset value/Register name
+0 +1 +2 +3
000508
1
00050CH
CSELR[R/W] CM()NR[R] MTMCR[R/W]
B,1—1,w B,1—1,w B,H,W
70 00 70177700 00001111
CSTBR[R’W] PTMCR[R/W]
B,H,W B.1-1,W
""0000 007
CPUAR[R/W]
B,H,W
UWXXXX
00051CH , , , , Reserved [S]
CCPSSELRUUW] CCPSDIVR[R’W]
B 1-1,w B.1-1,W
0 70007000
CCPLLFBR[R/W] CCSSFBR()[R/W] CCSSFBRI[R/W]
B,1—1,w B,H,W B.1-1,W
70000000 "000000 "700000
CCSSCCRU[R’W] CCSSCCR] [R/W]
B,1—1,w 1-1,w
0000 000"" ,,
CL((;RCRU[R’W] CCC(1RCR1[R/W] LL GRCR2[K w]
B,1—1,w B,H,W B.1-1,W
00~~00 00000000 00000000
CCPMUCR(J[R/W] CCPMUCRMKW]
B,H,W B.1-1,W
07700000
000534H , , , ,
000530H , , , ,
UOOSZCH , , , ,
000540
1
00054CH
E1RRO[R/w] ENIRU[R’W] External
B,1—1,w B,1—1,w intcmlp!
xxxxxxxx 00000000 [lNTU 10 7)
000554
1
000558H
CSVCR[K w] B
707170
WDT1
calibration
(trimming)
000574
1
00057CH
RE(}SEL[K w]
B,1—1,w
01771107
LVD5R[R/W] LVD5F[R/W] LVD[R/W]
B,1—1,w B,H,W
07010771 010004)
DataSheet
50 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
000508
H
|
00050CH
- - - - Reserved
000510H
CSELR[R/W]
B,H,W
-0----00
CMONR[R]
B,H,W
-01---00
MTMCR[R/W]
B,H,W
00001111
-
Clock control
[S]
000514H
PLLCR[R/W] B,H,W
00-00000 11110000
CSTBR[R/W]
B,H,W
----0000
PTMCR[R/W]
B,H,W
00------
000518H - -
CPUAR[R/W]
B,H,W
0---XXXX
- Reset [S]
00051CH
-
-
-
-
Reserved [S]
000520H
CCPSSELR[R/W]
B,H,W
-------0
- -
CCPSDIVR[R/W]
B,H,W
-000-000
Clock control 2
000524H -
CCPLLFBR[R/W]
B,H,W
-0000000
CCSSFBR0[R/W]
B,H,W
--000000
CCSSFBR1[R/W]
B,H,W
---00000
000528H -
CCSSCCR0[R/W]
B,H,W
----0000
CCSSCCR1[R/W]
H,W
000----- --------
00052CH -
CCCGRCR0[R/W]
B,H,W
00----00
CCCGRCR1[R/W]
B,H,W
00000000
CCCGRCR2[R/W]
B,H,W
00000000
000530H - -
CCPMUCR0[R/W]
B,H,W
0-----00
CCPMUCR1[R/W]
B,H,W
0--00000
000534H
-
-
-
-
000538H
-
-
-
-
00053CH
-
-
-
-
000540
H
|
00054CH
- - - - Reserved
000550H
EIRR0[R/W]
B,H,W
XXXXXXXX
ENIR0[R/W]
B,H,W
00000000
ELVR0[R/W] B,H,W
00000000 00000000
External
interrupt
(INT0 to 7)
000554
H
|
000568H
- - - - Reserved
00056CH -
CSVCR[R/W] B
-0--1--0
- - CSV
000570H
CRTR[R/W]
B,H,W 01111111 - - -
WDT1
calibration
(trimming)
000574
H
|
00057CH
- - - - Reserved
000580H
REGSEL[R/W]
B,H,W
01--110-
- - - Regulator
control
000584H
LVD5R[R/W]
B,H,W
-------1
LVD5F[R/W]
B,H,W
0-010--1
LVD[R/W]
B,H,W
01000--0
- Low-voltage
detection
/'\
S PA N 5 IO N
\
5 Address offset value/Register name
+ 0 + 1 +2 +3
000588
\
UOOSSCH
PMUSTR [R w] PMUCTLR[R’W] PWRTMCTL[R w]
BJ—LW B,H,w B,H,W
0" IX 0700"" ""7011
PMUlNTF1[R/W] PMUINTF2[RW]
B,H,w B,H,W
00000000 ,00 77777
000590H , , , ,
00059cH , , , ,
0005A0
\
0005FCH
000600
\
00060cH
000610
\
00063cH
000640
\
00064cH
000650
\
00067cH
000680
\
UOOéXCH
000690
\
000613CH
0006c0
\
0006CCH
0006D0
\
0006F0H
0006F4H , Reserved
0006Fx
\
0006FCH
000700H , Reserved
000704
\
00070cH
BPCCRA[R’W] B BPCCRB[R/W] B BPCCRC[R’W] B
00000000 00000000 00000000
BPCTRA[R/W] w
00000000 00000000 00000000 00000000
BPCTRB[R’W] w
00000000 00000000 00000000 00000000
BPCTRC[R/W] w
00000000 00000000 00000000 00000000
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 51
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
000588
H
|
00058CH
- - - - Reserved
000590H
PMUSTR [R/W]
B,H,W
0-----1X
PMUCTLR[R/W]
B,H,W
0-00----
PWRTMCTL[R/W]
B,H,W
-----011
-
PMU
000594H -
PMUINTF1[R/W]
B,H,W
00000000
PMUINTF2[R/W]
B,H,W
-00-----
-
000598H
-
-
-
-
00059CH
-
-
-
-
0005A0
H
|
0005FCH
- - - - Reserved
000600
H
|
00060CH
- - - - Reserved [S]
000610
H
|
00063CH
- - - - Reserved [S]
000640
H
|
00064CH
- - - - Reserved [S]
000650
H
|
00067CH
- - - - Reserved [S]
000680
H
|
00068CH
- - - - Reserved [S]
000690
H
|
0006BCH
- - - - Reserved [S]
0006C0
H
|
0006CCH
- - - - Reserved [S]
0006D0
H
|
0006F0H
- - - - Reserved
0006F4H
-
Reserved
0006F8
H
|
0006FCH
- - - - Reserved
000700H
-
Reserved
000704
H
|
00070CH
- - - - Reserved
000710H
BPCCRA[R/W] B
00000000
BPCCRB[R/W] B
00000000
BPCCRC[R/W] B
00000000
-
Bus performance
counter
000714H
BPCTRA[R/W] W
00000000 00000000 00000000 00000000
000718H
BPCTRB[R/W] W
00000000 00000000 00000000 00000000
00071CH
BPCTRC[R/W] W
00000000 00000000 00000000 00000000
/\
5 PA N 5 IO N
‘
5 Address offset value/Register name
+0 +1 +2 +3
000720
\
0007F8H
BMODR[R] B.H,W
xxxxxxxx
000800
\
00083cH
FCTLR[R’W] H FSTR[R/W] B Flash memory
70771000 00m ""7001 reg [Cr [S]
000844H , , , , Reserved [S]
000848
\
000854H
WREN[R’W] H
00000000 00000000
00085c
\
00087cH
WRAR()()[R/W] w
7777777777 xxxxxx xxxxxxxx xxxxxx"
WRDR()()[R/W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
WRAR()1[R/W] w
7777777777 xxxxxx xxxxxxxx xxxxxx"
WRDR()1[R/W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
WRAR()Z[R/W] w
rxxxxxx xxxxxxxx xxxxxx"
WRDR()Z[R/W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
WRAR()3[R/W] w
7777777777 xxxxxx xxxxxxxx xxxxxx"
WRDR()3[R/W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
WRAR()4[R/W] w
7777777777 xxxxxx xxxxxxxx xxxxxx"
WRDR()4[R/W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
WRAR()S[R/W] w
7777777777 xxxxxx xxxxxxxx xxxxxx"
WRDR()S[R/W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
WRAR()6[R/W] w
7777777777 xxxxxx xxxxxxxx xxxxxx"
WRDR()6[R/W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
WRAR()7[R/W] w
7777777777 xxxxxx xxxxxxxx xxxxxx"
WRDR()7[R/W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
WRAR()8[R/W] w
7777777777 xxxxxx xxxxxxxx xxxxxx"
WRDR()8[R/W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
DataSheet
52 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
000720
H
|
0007F8H
- - - - Reserved
0007FCH
BMODR[R] B,H,W
XXXXXXXX
- - - Operation mode
000800
H
|
00083CH
- - - - Reserved [S]
000840H
FCTLR[R/W] H
-0--1000 0--0----
-
FSTR[R/W] B
-----001
Flash memory
register [S]
000844H
-
-
-
-
Reserved [S]
000848
H
|
000854H
- - - - Reserved [S]
000858H - -
WREN[R/W] H
00000000 00000000
Wild register [S]
00085C
H
|
00087CH
- - - - Reserved [S]
000880H
WRAR00[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
Wild register [S]
000884H
WRDR00[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000888H
WRAR01[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
00088CH
WRDR01[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000890H
WRAR02[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
000894H
WRDR02[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000898H
WRAR03[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
00089CH
WRDR03[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008A0H
WRAR04[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008A4H
WRDR04[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008A8H
WRAR05[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008ACH
WRDR05[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008B0H
WRAR06[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008B4H
WRDR06[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008B8H
WRAR07[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008BCH
WRDR07[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008C0H
WRAR08[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008C4H
WRDR08[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
/'\
SPANSION
‘
Address offset value/Register name
\+1\+2\+3
WRAR09[R/W] w
7777777777 xxxxxx xxxxxxxx xxxxxx"
WRDR09[R/W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
WRAR10[R/W] w
7777777777 xxxxxx xxxxxxxx xxxxxx"
WRDR1()[R/W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
WRARI l [R w] w
7777777777 xxxxxx xxxxxxxx xxxxxx"
WRDRl l [R w] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
WRARlZ[R/W] w
7777777777 xxxxxx xxxxxxxx xxxxxx"
WRDRlZ[R/W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
WRAR13[R/W] w
7777777777 xxxxxx xxxxxxxx xxxxxx"
WRDR13[R/W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
WRAR14[R/W] w
7777777777 xxxxxx xxxxxxxx xxxxxx"
WRDR14[R/W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
WRARlS[R/W] w
7777777777 xxxxxx xxxxxxxx xxxxxx"
WRDRlS[R/W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
000900
\
00013FxH
UER[W] B.H,W
DCCRO[R/W] w
0777000 ~00~00 00000000 07000000
DCSRUUUW] H DTCRO[K w] H
0"" 000 00000000 00000000
DSARU[R’W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
DDARO[R/W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
DCCR1[R/W] w
0777000 ~00~00 00000000 07000000
DCSR1[R’W] H DTCRI [R w] H
0"" 000 00000000 00000000
DSAR1[R’W] w
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR] [R/W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
DCCR2[R/W] w
0777000 ~00~00 00000000 07000000
DCSR2[R’W] H DTCR2[K w] H
0" 000 00000000 00000000
DSAR2[R’W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 53
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
0008C8H
WRAR09[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
Wild register [S]
0008CCH
WRDR09[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008D0H
WRAR10[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008D4H
WRDR10[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008D8H
WRAR11[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008DCH
WRDR11[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008E0H
WRAR12[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008E4H
WRDR12[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008E8H
WRAR13[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008ECH
WRDR13[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008F0H
WRAR14[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008F4H
WRDR14[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008F8H
WRAR15[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008FCH
WRDR15[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000900
H
|
000BF8H
- - - - Reserved
000BFCH - -
UER[W] B,H,W
-------- -------X
OCDU
000C00H
DCCR0[R/W] W
0----000 --00--00 00000000 0-000000
DMA controller
[S]
000C04H
DCSR0[R/W] H
0------- -----000
DTCR0[R/W] H
00000000 00000000
000C08H
DSAR0[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C0CH
DDAR0[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C10H
DCCR1[R/W] W
0----000 --00--00 00000000 0-000000
000C14H
DCSR1[R/W] H
0------- -----000
DTCR1[R/W] H
00000000 00000000
000C18H
DSAR1[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C1CH
DDAR1[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C20H
DCCR2[R/W] W
0----000 --00--00 00000000 0-000000
000C24H
DCSR2[R/W] H
0------- -----000
DTCR2[R/W] H
00000000 00000000
000C28H
DSAR2[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
/\
5 PA N 5 IO N
‘
5 Address offset value/Register name
+ 0 ‘ + 1 ‘ +2 ‘ +3
DDAR2[R/W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
DCCR3[R/W] w
07777000 "0000 00000000 07000000
Dc rum/w] H DTCR3[K w] H
7000 00000000 00000000
DSAR3[R’W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
DDAR3[R/W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
DCCR4[R/w] w
07777000 "0000 00000000 07000000
DCSR4[R’W] H DTCR4[K w] H
0"" 000 00000000 00000000
DSAR4[R’W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
DDAR4[R/W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
DCCRS[R/W] w
07777000 "0000 00000000 07000000
Dc R5[R’W] H DTCR5[K w] H
7000 00000000 00000000
DSAR5[R’W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
DDAR5[R/W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
DCCR6[R/W] w
07777000 "0000 00000000 07000000
DCSRfiUUW] H DTCR6[K w] H
0"" 000 00000000 00000000
DSAR6[R’W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
DDAR6[R/W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
DCCR7[R/W] w
07777000 "0000 00000000 07000000
DCSR7[R’W] H DTCR7[K w] H
0"" 000 00000000 00000000
DSAR7[R’W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
DDAR7[R/W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
UOOCXO
\
000DF0H
DNMlR[R/W] B DILVR[K w] B
0 m] 1 1 1 l
()OODFCH , \ , , Reserved [S]
DataSheet
54 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
000C2CH
DDAR2[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DMA controller
[S]
000C30H
DCCR3[R/W] W
0----000 --00--00 00000000 0-000000
000C34H
DCSR3[R/W] H
0------- -----000
DTCR3[R/W] H
00000000 00000000
000C38H
DSAR3[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C3CH
DDAR3[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C40H
DCCR4[R/W] W
0----000 --00--00 00000000 0-000000
000C44H
DCSR4[R/W] H
0------- -----000
DTCR4[R/W] H
00000000 00000000
000C48H
DSAR4[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C4CH
DDAR4[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C50H
DCCR5[R/W] W
0----000 --00--00 00000000 0-000000
000C54H
DCSR5[R/W] H
0------- -----000
DTCR5[R/W] H
00000000 00000000
000C58H
DSAR5[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C5CH
DDAR5[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C60H
DCCR6[R/W] W
0----000 --00--00 00000000 0-000000
000C64H
DCSR6[R/W] H
0------- -----000
DTCR6[R/W] H
00000000 00000000
000C68H
DSAR6[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C6CH
DDAR6[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C70H
DCCR7[R/W] W
0----000 --00--00 00000000 0-000000
000C74H
DCSR7[R/W] H
0------- -----000
DTCR7[R/W] H
00000000 00000000
000C78H
DSAR7[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C7CH
DDAR7[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C80
H
|
000DF0H
- - - -
000DF4H - -
DNMIR[R/W] B
0------0
DILVR[R/W] B
---11111
000DF8H
DMACR[R/W] W
0------- -------- 0------- --------
000DFCH
-
-
-
-
Reserved [S]
/‘\
S PA N 5 IO N
‘
5 Address offset value/Register name
+0 +1 +2 +3
DDRDataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 55
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
000E00H
DDR00[R/W] B,H
00000000
DDR01[R/W] B,H
00000000
DDR02[R/W] B,H
00000000
DDR03[R/W] B,H
00000000
Data direction
register
000E04H
DDR04[R/W] B,H
-----000
-
DDR06[R/W] B,H
00000000
DDR07[R/W] B,H
00000000
000E08H
DDR08[R/W] B,H
00000000
DDR09[R/W] B,H
00000000
DDR10[R/W] B,H
00000000
DDR11[R/W] B,H
00000000
000E0CH
DDR12[R/W] B,H
00000000
DDR13[R/W] B,H
00-00000
- -
000E10
H
|
000E1CH
- - - - Reserved
000E20H
PFR00[R/W] B,H
00000000
PFR01[R/W] B,H
00000000
PFR02[R/W] B,H
00000000
PFR03[R/W] B,H
00000000
Port function
register
000E24H
PFR04[R/W] B,H
-----000
-
PFR06[R/W] B,H
00000000
PFR07[R/W] B,H
00000000
000E28H
PFR08[R/W] B,H
00000000
PFR09[R/W] B,H
00000000
PFR10[R/W] B,H
00000000
PFR11[R/W] B,H
00000000
000E2CH
PFR12[R/W] B,H
00000000
PFR13[R/W] B,H
00-00000
- -
000E30
H
|
000E3CH
- - - - Reserved
000E40H
PDDR00[R]
B,H,W
XXXXXXXX
PDDR01[R]
B,H,W
XXXXXXXX
PDDR02[R]
B,H,W
XXXXXXXX
PDDR03[R]
B,H,W
XXXXXXXX
Input data direct
read register
000E44H
PDDR04[R]
B,H,W
-----XXX
-
PDDR06[R]
B,H,W
XXXXXXXX
PDDR07[R]
B,H,W
XXXXXXXX
000E48H
PDDR08[R]
B,H,W
XXXXXXXX
PDDR09[R]
B,H,W
XXXXXXXX
PDDR10[R]
B,H,W
XXXXXXXX
PDDR11[R]
B,H,W
XXXXXXXX
000E4CH
PDDR12[R]
B,H,W
XXXXXXXX
PDDR13[R]
B,H,W
XX-XXXXX
- -
000E50
H
|
000E5CH
- - - - Reserved
000E60H
EPFR00[R/W] B,H
-----000
EPFR01[R/W] B,H
------00
EPFR02[R/W] B,H
--000000
EPFR03[R/W] B,H
00000000
Extended port
function register
000E64H
EPFR04[R/W] B,H
00000000
EPFR05[R/W] B,H
00000000
EPFR06[R/W] B,H
------00
EPFR07[R/W] B,H
----0000
000E68H
EPFR08[R/W] B,H
----0000
EPFR09[R/W] B,H
-------0
EPFR10[R/W] B,H
00000000
EPFR11[R/W] B,H
----0000
000E6CH
EPFR12[R/W] B,H
--000000
EPFR13[R/W] B,H
-------1
EPFR14[R/W] B,H
-0000000
EPFR15[R/W] B,H
-0000000
000E70H
EPFR16[R/W] B,H
--000000
EPFR17[R/W] B,H
00000000
EPFR18[R/W] B,H
00000000
EPFR19[R/W] B,H
00000000
000E74H
EPFR20[R/W] B,H
00000000
EPFR21[R/W] B,H
00000000
EPFR22[R/W] B,H
00000000
EPFR23[R/W] B,H
00000000
000E78H
EPFR24[R/W] B,H
00000000
EPFR25[R/W] B,H
00000000
EPFR26[R/W] B,H
00000000
EPFR27[R/W] B,H
00000000
000E7CH
EPFR28[R/W] B,H
00000000
EPFR29[R/W] B,H
00000000
EPFR30[R/W] B,H
00000000
EPFR31[R/W] B,H
00000000
000E80H
EPFR32[R/W] B,H
00000000
- - -
/\
5 PA N 5 IO N
‘
5 Address offset value/Register name
+0 +1 +2 +3
(J(JUE84
1
000E13cH
PPERUU[R/W] 13,1-1 PPER01[R/W]B,1-1 PPER02[R/W]B,H PPER03[R’W]B.H
00000000 00000000 00000000 00000000
PPERU4[R/W] 13,1-1 PPERDataSheet
56 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
000E84
H
|
000EBCH
- - - - Reserved
000EC0H
PPER00[R/W] B,H
00000000
PPER01[R/W] B,H
00000000
PPER02[R/W] B,H
00000000
PPER03[R/W] B,H
00000000
Port
pull-up/down
enable register
000EC4H
PPER04[R/W] B,H
-----000
-
PPER06[R/W] B,H
00000000
PPER07[R/W] B,H
00000000
000EC8H
PPER08[R/W] B,H
00000000
PPER09[R/W] B,H
00000000
PPER10[R/W] B,H
00000000
PPER11[R/W] B,H
00000000
000ECCH
PPER12[R/W] B,H
00000000
PPER13[R/W] B,H
00-00000
- -
000ED0
H
|
000EDCH
- - - - Reserved
000EE0H
PILR00[R/W] B,H
11111111
PILR01[R/W] B,H
11111111
PILR02[R/W] B,H
11111111
PILR03[R/W] B,H
11111111
Port input level
selection register
000EE4H
PILR04[R/W] B,H
-----111
-
PILR06[R/W] B,H
11111111
PILR07[R/W] B,H
11111111
000EE8H
PILR08[R/W] B,H
11111111
PILR09[R/W] B,H
11111111
PILR10[R/W] B,H
11111111
PILR11[R/W] B,H
11111111
000EECH
PILR12[R/W] B,H
11111111
PILR13[R/W] B,H
11-11111
- -
000EF0
H
|
000EFCH
- - - - Reserved
000F00
H
|
000F1CH
- - - - Reserved
000F20H
PODR00[R/W]
B,H
00000000
PODR01[R/W]
B,H
00000000
PODR02[R/W]
B,H
00000000
PODR03[R/W]
B,H
00000000
Port output drive
register
000F24H
PODR04[R/W]
B,H
-----000
-
PODR06[R/W]
B,H
00000000
PODR07[R/W]
B,H
00000000
000F28H
PODR08[R/W]
B,H
00000000
PODR09[R/W]
B,H
00000000
PODR10[R/W]
B,H
00000000
PODR11[R/W] B,H
00000000
000F2CH
PODR12[R/W]
B,H
00000000
PODR13[R/W]
B,H
00-00000
- -
000F30
H
|
000F3CH
- - - - Reserved
000F40H
PORTEN[R/W]
B,H,W
------00
- - -
Port input enable
register
000F44H
KEYCDR[R/W] H
00000000 00000000
- - Port key code
000F48H
ADERH[R/W] B,H
-------- 11111111
ADERL[R/W] B,H
11111111 11111111
Analog input
enable register
000F4CH
-
-
-
-
Reserved
000F50
H
|
000FFCH
- - - - Reserved
/'\
SPANSION
Address offset value/Register name
+0 +1
+2 +3
SACR[R/W] PlCD[R/W]
1-1,w 13,1-1,w
0 ""001 1
Synchronous/My
nchmnous
swimh control
00 l U04
1
001013CH
CRCCR[K w]
13.1-1,w
0000000
CRClNIT[R/W] 13,1-1.w
11111111111111111111111111111111
CRCIN [R’W] B,H,W
00000000 00000000 00000000 00000000
CRCR[R] 13,1-1,w
11111111111111111111111111111111
00 1 0D!)
1
0010FCH
TCGS[K w]
13 1-1,w
00
TCGSE[R/W]
13.1-1,w
"000000
Freerrun finlcr
simuhancou
activation
CPCLRBO/CPCLRO[R/W] H,W
llllllll llllllll
TCDTU[R’W] 1-1,w
00000000 00000000
TCCS()[R/W] 13,1-1,w
00000000 01000000 ""0000 ,,
CPCLRBl/CPCLR1[R/W] H,W
llllllllllllllll
TCDT1[R’W] 1-1,w
00000000 00000000
TCCSl[R/W] 13,1-1,w
00000000 01000000 ,
UUU
CPCLRBZ/CPCLRZ[R/W] H,W
llllllll llllllll
TCDTZUUW] 1-1,w
00000000 00000000
chszm/w] 13,1-1,w
00000000 01000000 ""0000 ,,
CPCLRBS/CPCLR3[R/W] H,W
llllllll llllllll
TCDT3[R’W] 1-1,w
00000000 00000000
TCCS3[R/W] 13,1-1,w
00000000 01000000 ""0000 ,,
CPCLRB4/CPCLR4[R/W] H,W
llllllll llllllll
TCDT4[R’W] 1-1,w
00000000 00000000
ch34[R/w] 13,1-1,w
00000000 01000000 ""0000 ,,
CPCLRBS/CPCLRS[R/W] H,W
llllllll llllllll
TCDTSUUW] 1-1,w
00000000 00000000
chssm/w] 13,1-1,w
00000000 01000000 ""0000 77777777
‘
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 57
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
001000H
SACR[R/W]
B,H,W
-------0
PICD[R/W]
B,H,W
----0011
- -
Synchronous/asy
nchronous
switch control
001004
H
|
0010BCH
- - - - Reserved
0010C0H - - -
CRCCR[R/W]
B,H,W
-0000000
CRC arithmetic
operation
0010C4H
CRCINIT[R/W] B,H,W
11111111 11111111 11111111 11111111
0010C8H
CRCIN[R/W] B,H,W
00000000 00000000 00000000 00000000
0010CCH
CRCR[R] B,H,W
11111111 11111111 11111111 11111111
0010D0
H
|
0010FCH
- - - - Reserved
001100H
TCGS[R/W]
B,H,W
------00
- -
TCGSE[R/W]
B,H,W
--000000
Free-run timer
simultaneous
activation
001104H
CPCLRB0/CPCLR0[R/W] H,W
11111111 11111111
TCDT0[R/W] H,W
00000000 00000000
Free-run timer 0
001108H
TCCS0[R/W] B,H,W
00000000 01000000 ----0000 --------
00110CH
CPCLRB1/CPCLR1[R/W] H,W
11111111 11111111
TCDT1[R/W] H,W
00000000 00000000
Free-run timer 1
001110H
TCCS1[R/W] B,H,W
00000000 01000000 ----0000 --------
001114H
CPCLRB2/CPCLR2[R/W] H,W
11111111 11111111
TCDT2[R/W] H,W
00000000 00000000
Free-run timer 2
001118H
TCCS2[R/W] B,H,W
00000000 01000000 ----0000 --------
00111CH
CPCLRB3/CPCLR3[R/W] H,W
11111111 11111111
TCDT3[R/W] H,W
00000000 00000000
Free-run timer 3
001120H
TCCS3[R/W] B,H,W
00000000 01000000 ----0000 --------
001124H
CPCLRB4/CPCLR4[R/W] H,W
11111111 11111111
TCDT4[R/W] H,W
00000000 00000000
Free-run timer 4
001128H
TCCS4[R/W] B,H,W
00000000 01000000 ----0000 --------
00112CH
CPCLRB5/CPCLR5[R/W] H,W
11111111 11111111
TCDT5[R/W] H,W
00000000 00000000
Free-run timer 5
001130H
TCCS5[R/W] B,H,W
00000000 01000000 ----0000 --------
/\
5 PA N 5 IO N
‘
5 Address offset value/Register name
+ 0 + 1 +2 +3
FRSU[R’W] BJ—LW
77777777 000000 000000 000000
FRSl [R’W] BJ—LW
rrrrrrrrrrrrrrrr 000000 000000
FRS2[R’W] BJ—LW
000000 000000 000000
FRS3[R/w] B.H,W
77777777 W 000000 000000
FRS4[R’W] BJ—LW
000000 000000 000000 000000
FRSS[R’W] BJ—LW
000000 000000 000000 000000
“(Sam/w] BJ—LW
000000 000000 000000 000000
001 150H W
()CCPBU/OCCPO[R/w] H,W OCCPBUOCCPHR w] H,w
00000000 00000000 00000000 00000000
OCMODU l [R w]
BJ—LW
W )0
()CCPBZ’OCCPZUUW] H,W OCCPB3/0CCP3[R w] H,w
00000000 00000000 00000000 00000000
OCM()D23[K w]
BJ—LW
W )0
()CCPB4’()CCP4[R/W] H,W OCCPBS/OCCP5[R w] H,w
00000000 00000000 00000000 00000000
OCM()D45[K w]
BJ—LW
W W00
()CCPB6’()CCP6[R/W] H,W OCCPB7/()CCP7[R w] H,w
00000000 00000000 00000000 00000000
OCM()D67[K w]
BJ—LW
W W00
()CCPBX’OCCPXUUW] H,W ()CCPB9/()CCP9[R w] H,w
00000000 00000000 00000000 00000000
OCM()D89[K w]
BJ—LW
W W00
()CCPB 1 U’()CCP1(J[R/W] H,W OCCPB l l/()CCP l 1 [WW] H,W
00000000 00000000 00000000 00000000
OCMOD 1 01 1
R w] EH,
)0
lPCP(J[R] H,w IPCP1[R] H,W
00000000 00000000 00000000 00000000
st smw]
BJ—LW
WW00000
lPCP2[R] H,w IPCP3[R] H,W
00000000 00000000 00000000 00000000
1C823[R w] B,H,w
WWWWWW 00 00000000
DataSheet
58 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
001134H
FRS0[R/W] B,H,W
-------- -000-000 -000-000 -000-000
Free-run timer
selection
001138H
FRS1[R/W] B,H,W
-------- -------- -000-000 -000-000
00113CH
FRS2[R/W] B,H,W
-------- -000-000 -000-000 -000-000
001140H
FRS3[R/W] B,H,W
-------- -------- -000-000 -000-000
001144H
FRS4[R/W] B,H,W
-000-000 -000-000 -000-000 -000-000
001148H
FRS5[R/W] B,H,W
-000-000 -000-000 -000-000 -000-000
00114CH
FRS6[R/W] B,H,W
-000-000 -000-000 -000-000 -000-000
001150H
-
001154H
OCCPB0/OCCP0[R/W] H,W
00000000 00000000
OCCPB1/OCCP1[R/W] H,W
00000000 00000000
Output compare
0/1
001158H
OCS01[R/W] B,H,W
-110--00 00001100 -
OCMOD01[R/W]
B,H,W
------00
00115CH
OCCPB2/OCCP2[R/W] H,W
00000000 00000000
OCCPB3/OCCP3[R/W] H,W
00000000 00000000
Output compare
2/3
001160H
OCS23[R/W] B,H,W
-110--00 00001100 -
OCMOD23[R/W]
B,H,W
------00
001164H
OCCPB4/OCCP4[R/W] H,W
00000000 00000000
OCCPB5/OCCP5[R/W] H,W
00000000 00000000
Output compare
4/5
001168H
OCS45[R/W] B,H,W
-110--00 00001100 -
OCMOD45[R/W]
B,H,W
------00
00116CH
OCCPB6/OCCP6[R/W] H,W
00000000 00000000
OCCPB7/OCCP7[R/W] H,W
00000000 00000000
Output compare
6/7
001170H
OCS67[R/W] B,H,W
-110--00 00001100 -
OCMOD67[R/W]
B,H,W
------00
001174H
OCCPB8/OCCP8[R/W] H,W
00000000 00000000
OCCPB9/OCCP9[R/W] H,W
00000000 00000000
Output compare
8/9
001178H
OCS89[R/W] B,H,W
-110--00 00001100 -
OCMOD89[R/W]
B,H,W
------00
00117CH
OCCPB10/OCCP10[R/W] H,W
00000000 00000000
OCCPB11/OCCP11[R/W] H,W
00000000 00000000
Output compare
10/11
001180H
OCS1011[R/W] B,H,W
-110--00 00001100 -
OCMOD1011
[R/W] B,H,W
------00
001184H
IPCP0[R] H,W
00000000 00000000
IPCP1[R] H,W
00000000 00000000
Input capture 0/1
001188H
ICS01[R/W] B,H,W
------00 00000000 -
LSYNS[R/W]
B,H,W
---00000
00118CH
IPCP2[R] H,W
00000000 00000000
IPCP3[R] H,W
00000000 00000000
Input capture 2/3
001190H
ICS23[R/W] B,H,W
------00 00000000
- -
/'\
S PA N 5 IO N
‘
5 Address offset value/Register name
+ 0 ] + 1 +2 ] +3
IPCP4[R] H,w IPCPS[R] H,W
00000000 00000000 00000000 00000000
1C545[R w] B,H,w
777777 00 00000000
lPCP6[R] H,w IPCP7[R] H,W
00000000 00000000 00000000 00000000
lCSé7[R w] B,H,w
777777 00 00000000
DT SR[K w]
B.H,w
, l0
TMRRO[R/W] H,w TMRRI[K w] H.w
00000000 00000001 00000000 00000001
TMRRZ[R/W] H,w
00000000 00000001
DTSCRO[R/W] DTSCR] [R/W] DTSCR2[R/W]
B,H,w B,H,w B,H,w
00000000 00000000 00000000
DT1R0[K w] DTMNSU[R’W]
B,H,w BJ—LW
000000" 00777000
SlGCRlUUUW] SIGCR20[K w]
B,H,w BJ—LW
00000000 00000071
PIcS0[R/w] BJ—Lw
000000 777777777 ,
TMRR3[R/w] H,w TMRR4[K w] H.w
00000000 00000001 00000000 00000001
TMRRS[R/W] H,w
00000000 00000001
DTSCR3[R/w] DTSCR4[R/W] DTSCRS[R/W]
B,H,w B,H,w B,H,w
00000000 00000000 00000000
DTlRl[K w] DTMNSI[R’W]
B,H,w BJ—LW
000000" 00777000
SI(;CR11[R/w] SI(}CR2|[K w]
B,H,w BJ—LW
00000000 00000071
PICSl[R/W] BJ—Lw
000000
001leH , , , ,
ADT s s [R w]
H,w
)
ADTSE[R/W] BJ—Lw
,,,,,,,, 00000000 0
0000000 00000000
ADCOMPO/ADCOMPBO[K W] H.W
00000000 00000000
ADCOMPI,ADCOMPB1[R’W] H,W
00000000 00000000
ADCOMPZ/ADCOMPB2[K W] H.W
00000000 00000000
ADCOMP}, ADCOMPB3 [R’W] H,W
00000000 00000000
ADCOMPMADCOMPB4[K W] H.W
00000000 00000000
ADCOMPS, ADCOMPBS [R’W] H,W
00000000 00000000
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 59
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
001194H
IPCP4[R] H,W
00000000 00000000
IPCP5[R] H,W
00000000 00000000
Input capture 4/5
001198H
ICS45[R/W] B,H,W
------00 00000000
- -
00119CH
IPCP6[R] H,W
00000000 00000000
IPCP7[R] H,W
00000000 00000000
Input capture 6/7
0011A0H
ICS67[R/W] B,H,W
------00 00000000
- -
0011A4H
DTSR[R/W]
B,H,W
------10
- - - DTTI selection
0011A8H
TMRR0[R/W] H,W
00000000 00000001
TMRR1[R/W] H,W
00000000 00000001
Waveform
generator 0/1/2
0011ACH
TMRR2[R/W] H,W
00000000 00000001
- -
0011B0H
DTSCR0[R/W]
B,H,W
00000000
DTSCR1[R/W]
B,H,W
00000000
DTSCR2[R/W]
B,H,W
00000000
-
0011B4H -
DTIR0[R/W]
B,H,W
000000--
-
DTMNS0[R/W]
B,H,W
00---000
0011B8H -
SIGCR10[R/W]
B,H,W
00000000
-
SIGCR20[R/W]
B,H,W
000000-1
0011BCH
PICS0[R/W] B,H,W
000000-- -------- -------- --------
0011C0H
TMRR3[R/W] H,W
00000000 00000001
TMRR4[R/W] H,W
00000000 00000001
Waveform
generator 3/4/5
0011C4H
TMRR5[R/W] H,W
00000000 00000001
- -
0011C8H
DTSCR3[R/W]
B,H,W
00000000
DTSCR4[R/W]
B,H,W
00000000
DTSCR5[R/W]
B,H,W
00000000
-
0011CCH -
DTIR1[R/W]
B,H,W
000000--
-
DTMNS1[R/W]
B,H,W
00---000
0011D0H -
SIGCR11[R/W]
B,H,W
00000000
-
SIGCR21[R/W]
B,H,W
000000-1
0011D4H
PICS1[R/W] B,H,W
000000-- -------- -------- --------
0011D8H
-
-
-
-
12-bit A/D
converter
0011DCH
ADTSS[R/W]
B,H,W
-------0
- - -
0011E0H
ADTSE[R/W] B,H,W
-------- 00000000 00000000 00000000
0011E4H
ADCOMP0/ADCOMPB0[R/W] H,W
00000000 00000000
ADCOMP1/ADCOMPB1[R/W] H,W
00000000 00000000
0011E8H
ADCOMP2/ADCOMPB2[R/W] H,W
00000000 00000000
ADCOMP3/ADCOMPB3[R/W] H,W
00000000 00000000
0011ECH
ADCOMP4/ADCOMPB4[R/W] H,W
00000000 00000000
ADCOMP5/ADCOMPB5[R/W] H,W
00000000 00000000
/\
SPANSION
‘
Address offset value/Register name
+0 1 +1
+2 ‘ +3
ADCOMP6/ADCOMPB6[K W] H.W
00000000 00000000
ADCOMP7/ ADCOMPB7[R’W] H,W
00000000 00000000
ADC()MP8/ADC()MPB8[K W] H.W
00000000 00000000
ADCOMP‘J/ ADCOMPB9[R’W] H,W
00000000 00000000
ADCOMP l0/ADCOMPB l U[R/W] H,W
00000000 00000000
ADCOMP] l/ADCOMPBIHR/W] H,W
00000000 00000000
ADCOMP l2/ADCOMPB12[R/W] H,W
00000000 00000000
ADCOMP l 31ADC0MPB l 3[R/W] H,W
00000000 00000000
ADCOMP l4/ADCOMPB14[R/W] H,W
00000000 00000000
ADCOMP151ADC0MPB l 5[R/W] H,W
00000000 00000000
ADCOMP l6/ADCOMPB16[R/W] H,W
00000000 00000000
ADCOMP171ADC0MPB l 7[R/W] H,W
00000000 00000000
ADCOMP l X/ADCOMPB l X[R/W] H,W
00000000 00000000
ADCOMP191ADC0MPB l 9[R/W] H,W
00000000 00000000
ADCOMP20/ADCOMPBZU[R/W] H,W
00000000 00000000
ADCOMPZ l/ADCOMPBZI [R/W] H,W
00000000 00000000
ADC()MP22/ADCOMPB22[R/W] H,W
00000000 00000000
ADCOMPZ}1ADC0MPBZ3[R/W] H,W
00000000 00000000
001214H , , , ,
00121 x“ , , , ,
00121cH , , , ,
001220H , , , ,
ADTcsomw] 13,1-1,w ADTCSIULW] BJ—LW
00000000 00107000 00000000 0010000
ADTcszmw] 13,1-1,w ADTCSSULW] BJ—LW
00000000 00107000 00000000 0010000
ADTcsamw] 13,1-1,w ADTcssmw] BJ—LW
00000000 00107000 00000000 0010000
ADTC36[KW] 13,1-1,w ADTCS7[R’W] BJ—LW
00000000 00107000 00000000 0010000
ADTCSxmw] 13,1-1,w ADTcsumw] BJ—LW
00000000 00107000 00000000 0010000
ADTCSI()[R/W] 13,1-1,w ADTCSll[R’W] 13.1-1,w
00000000 00107000 00000000 0010000
ADTCSI2[R/W] 13,1-1,w ADTcsumw] BJ—LW
00000000 00107000 00000000 0010000
ADTCSI4[R/W] 13,1-1,w ADTCSlsmw] BJ—LW
00000000 00107000 00000000 0010000
ADTCSI6[R/W] 13,1-1,w ADTcsnmw] BJ—LW
00000000 00100000 00000000 00100000
ADTCSI8[R/W] 13,1-1,w ADTcswmw] BJ—LW
00000000 00100000 00000000 00100000
ADTCSZ()[R/W] 13,1-1,w ADTcsz1[1Lw]B.1-1,w
00000000 00100000 00000000 00100000
ADTCSZZ[R/W] 13,1-1,w ADTcszzmw] BJ—LW
00000000 00100000 00000000 00100000
001254H , , , ,
001250H , , , ,
00125cH , , , ,
001250H , ,
ADTCDO[R] B,1—1,w
10770000 00000000
ADTCD1[R] BJ—Lw
10770000 00000000
ADTCD2[R] B,1—1,w
10770000 00000000
ADTCD3[R] BJ—Lw
10770000 00000000
DataSheet
60 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
0011F0H
ADCOMP6/ADCOMPB6[R/W] H,W
00000000 00000000
ADCOMP7/ADCOMPB7[R/W] H,W
00000000 00000000
12-bit A/D
converter
0011F4H
ADCOMP8/ADCOMPB8[R/W] H,W
00000000 00000000
ADCOMP9/ADCOMPB9[R/W] H,W
00000000 00000000
0011F8H
ADCOMP10/ADCOMPB10[R/W] H,W
00000000 00000000
ADCOMP11/ADCOMPB11[R/W] H,W
00000000 00000000
0011FCH
ADCOMP12/ADCOMPB12[R/W] H,W
00000000 00000000
ADCOMP13/ADCOMPB13[R/W] H,W
00000000 00000000
001200H
ADCOMP14/ADCOMPB14[R/W] H,W
00000000 00000000
ADCOMP15/ADCOMPB15[R/W] H,W
00000000 00000000
001204H
ADCOMP16/ADCOMPB16[R/W] H,W
00000000 00000000
ADCOMP17/ADCOMPB17[R/W] H,W
00000000 00000000
001208H
ADCOMP18/ADCOMPB18[R/W] H,W
00000000 00000000
ADCOMP19/ADCOMPB19[R/W] H,W
00000000 00000000
00120CH
ADCOMP20/ADCOMPB20[R/W] H,W
00000000 00000000
ADCOMP21/ADCOMPB21[R/W] H,W
00000000 00000000
001210H
ADCOMP22/ADCOMPB22[R/W] H,W
00000000 00000000
ADCOMP23/ADCOMPB23[R/W] H,W
00000000 00000000
001214H
-
-
-
-
001218H
-
-
-
-
00121CH
-
-
-
-
001220H
-
-
-
-
001224H
ADTCS0[R/W] B,H,W
00000000 0010-000
ADTCS1[R/W] B,H,W
00000000 0010-000
001228H
ADTCS2[R/W] B,H,W
00000000 0010-000
ADTCS3[R/W] B,H,W
00000000 0010-000
00122CH
ADTCS4[R/W] B,H,W
00000000 0010-000
ADTCS5[R/W] B,H,W
00000000 0010-000
001230H
ADTCS6[R/W] B,H,W
00000000 0010-000
ADTCS7[R/W] B,H,W
00000000 0010-000
001234H
ADTCS8[R/W] B,H,W
00000000 0010-000
ADTCS9[R/W] B,H,W
00000000 0010-000
001238H
ADTCS10[R/W] B,H,W
00000000 0010-000
ADTCS11[R/W] B,H,W
00000000 0010-000
00123CH
ADTCS12[R/W] B,H,W
00000000 0010-000
ADTCS13[R/W] B,H,W
00000000 0010-000
001240H
ADTCS14[R/W] B,H,W
00000000 0010-000
ADTCS15[R/W] B,H,W
00000000 0010-000
001244H
ADTCS16[R/W] B,H,W
00000000 00100000
ADTCS17[R/W] B,H,W
00000000 00100000
001248H
ADTCS18[R/W] B,H,W
00000000 00100000
ADTCS19[R/W] B,H,W
00000000 00100000
00124CH
ADTCS20[R/W] B,H,W
00000000 00100000
ADTCS21[R/W] B,H,W
00000000 00100000
001250H
ADTCS22[R/W] B,H,W
00000000 00100000
ADTCS23[R/W] B,H,W
00000000 00100000
001254H
-
-
-
-
001258H
-
-
-
-
00125CH
-
-
-
-
001260H
-
-
-
-
001264H
ADTCD0[R] B,H,W
10--0000 00000000
ADTCD1[R] B,H,W
10--0000 00000000
001268H
ADTCD2[R] B,H,W
10--0000 00000000
ADTCD3[R] B,H,W
10--0000 00000000
/'\
S PA N 5 IO N
‘
5 Address offset value/Register name
+0 ‘ +1 +2 ‘ +3
ADTCD4[R] B,H,w ADTCD5[R] BJ—Lw
10770000 00000000 100000 00000000
ADTCD6[R] B,H,w ADTCD7[R] BJ—Lw
10770000 00000000 100000 00000000
ADTCD8[R] B,H,w ADTCD9[R] BJ—Lw
10770000 00000000 100000 00000000
ADTCD l0[R] B,H,w ADTCDl 1 [R] B,H,w
10770000 00000000 100000 00000000
ADTCDIZ[R] B,H,w ADTCD13[R] BJ—Lw
10770000 00000000 100000 00000000
ADTCD14[R] B,H,w ADTCD15[R] BJ—Lw
10770000 00000000 100000 00000000
ADTCD16[R] B,H,w ADTCD17[R] BJ—Lw
10770000 00000000 100000 00000000
ADTCD18[R] B,H,w ADTCD19[R] BJ—Lw
10770000 00000000 100000 00000000
ADTCD20[R] B,H,w ADTCD21[R] BJ—Lw
10770000 00000000 100000 00000000
ADTCD22[R] B,H,w ADTCD23[R] BJ—Lw
10770000 00000000 100000 00000000
001294H , , , ,
001298H , , , ,
00129cH , , , ,
0012A0H , , , ,
ADMDO[R/w]
BJ—LW
""0000
ADMD1[R/W]
BJ—LW
""0000
ADMDZ[R/W]
BJ—LW
""0000
001280
\
0012FCH
RDCCTR(J[R/W] RDCCTR] [R/W] RDCINTR[R] RDClCER[R/W]
B,H,w B,H,w B,H,w BJ—LW
0~~000 70000000 70000000 W ~00
RDCCTR2[R/W]
B,H,w
"700000
RDC 12le w] H.w RDC ‘PR2[R’W] H,w
000 00000000 , 70000 00000000
RDCCPR3[K w] H.W RDCCPR4[R’W] H,w
777777 00 00000000 77777700 00000000
AGLDR[R] H,w
lmXXXX xxxxxxxx
A(}VLDR[R] H.W
xxxxxxxx xxxxxxxx
AGLDBR[R] H,w
lmXXXX xxxxxxxx
AGVLDBR[R] H,w
xxxxxxxx xxxxxxxx
sccan/w] H,w
1 "0000 00000000
SINDR[R] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 61
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
00126CH
ADTCD4[R] B,H,W
10--0000 00000000
ADTCD5[R] B,H,W
10--0000 00000000
12-bit A/D
converter
001270H
ADTCD6[R] B,H,W
10--0000 00000000
ADTCD7[R] B,H,W
10--0000 00000000
001274H
ADTCD8[R] B,H,W
10--0000 00000000
ADTCD9[R] B,H,W
10--0000 00000000
001278H
ADTCD10[R] B,H,W
10--0000 00000000
ADTCD11[R] B,H,W
10--0000 00000000
00127CH
ADTCD12[R] B,H,W
10--0000 00000000
ADTCD13[R] B,H,W
10--0000 00000000
001280H
ADTCD14[R] B,H,W
10--0000 00000000
ADTCD15[R] B,H,W
10--0000 00000000
001284H
ADTCD16[R] B,H,W
10--0000 00000000
ADTCD17[R] B,H,W
10--0000 00000000
001288H
ADTCD18[R] B,H,W
10--0000 00000000
ADTCD19[R] B,H,W
10--0000 00000000
00128CH
ADTCD20[R] B,H,W
10--0000 00000000
ADTCD21[R] B,H,W
10--0000 00000000
001290H
ADTCD22[R] B,H,W
10--0000 00000000
ADTCD23[R] B,H,W
10--0000 00000000
001294H
-
-
-
-
001298H
-
-
-
-
00129CH
-
-
-
-
0012A0H
-
-
-
-
0012A4H
ADCS0[R/W] B,H,W
0------- --------
ADCH0[R] B,H,W
-----000
ADMD0[R/W]
B,H,W
----0000
0012A8H
ADCS1[R/W] B,H,W
0------- --------
ADCH1[R] B,H,W
-----000
ADMD1[R/W]
B,H,W
----0000
0012ACH
ADCS2[R/W] B,H,W
0------- --------
ADCH2[R] B,H,W
-----000
ADMD2[R/W]
B,H,W
----0000
0012B0
H
|
0012FCH
- - - - Reserved
001300H
RDCCTR0[R/W]
B,H,W
0----000
RDCCTR1[R/W]
B,H,W
-0000000
RDCINTR[R]
B,H,W
-0000000
RDCICER[R/W]
B,H,W
------00
RDC
001304H -
RDCCTR2[R/W]
B,H,W
---00000
RDCIPR[R/W] H,W
----0000 00000000
001308H
RDCCPR1[R/W] H,W
----0000 00000000
RDCCPR2[R/W] H,W
----0000 00000000
00130CH
RDCCPR3[R/W] H,W
------00 00000000
RDCCPR4[R/W] H,W
------00 00000000
001310H
AGLDR[R] H,W
1---XXXX XXXXXXXX
AGVLDR[R] H,W
XXXXXXXX XXXXXXXX
001314H
AGLDBR[R] H,W
1---XXXX XXXXXXXX
AGVLDBR[R] H,W
XXXXXXXX XXXXXXXX
001318 H
SCCIR[R/W] H,W
1---0000 00000000
- -
00131CH
SINDR[R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
/\
5 PA N 5 IO N
‘
5 Address offset value/Register name
+0 ‘ +1 ‘ +2 ‘ +3
COSDR[R] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
001324H , \ ,
SINDR] [R] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
COSDR1[R] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
001330H , ,
001334
\
001chH
001400H , , , , Rcscrvcd
001404
\
0014FCH
SCRO/(IBCRO) SMRO[R/W] SSRU[R’W] ESCRO/(IBSRO)
R’W] B,H,w B,H,w B,H,w R w] BJ—LW
000000 00000070 00001 1 00000000
r/(RDRIU’(TDRI()))[R/W] H,w RDROO/(TDR00)[R/W] BJ—Lw
, 7777777777 , "0 00000000 ‘
SAL R0[K w] BJ—LW STMRU[R] BJ—Lw
0, 000 00000000 00000000 00000000
STMCR()[R/W] BJ—Lw 7,1 SFU R0) [R w] BJ—LW
00000000 00000000 "W
:( SFLRIO) [R’W] 2( SFLRUU) [R/W]
B,H.w BJ—LW
r,[lSMKO)[R’W] r’(lSBAO)[R/W]
B,H,w BJ—Lw
FCR10[R/W] FCR()0[R/W] FBYTE20[K w] FBYTE]0[R/W]
BJ‘LW BJ‘LW B,H.,W B.H,W
00700100 70000000 00000000 00000000
DataSheet
62 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
001320H
COSDR[R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RDC
001324H
-
-
001328H
SINDR1[R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00132CH
COSDR1[R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001330H
-
-
001334
H
|
0013FCH
- - - - Reserved
001400H
-
-
-
-
Reserved
001404
H
|
0014FCH
- - - - Reserved
001500H
SCR0/(IBCR0)
[R/W] B,H,W
0--00000
SMR0[R/W]
B,H,W
000000-0
SSR0[R/W]
B,H,W
0--00011
ESCR0/(IBSR0)
[R/W] B,H,W
00000000
Multi Function
Serial I/F 0
*1: Byte access
is possible only
for access to
lower 8 bits.
*2: Reserved
because I2C
mode is not set
immediately
after reset
*3: Reserved
because CSIO
mode is not set
immediately
after reset
*4: Reserved
because LIN2.1
mode is not set
immediately
after reset
001504H
-/(RDR10/(TDR10))[R/W] H,W
-------- --------
*3
RDR00/(TDR00)[R/W] B,H,W
-------0 00000000
*1
001508H
SACSR0[R/W] B,H,W
0----000 00000000
STMR0[R] B,H,W
00000000 00000000
00150CH
STMCR0[R/W] B,H,W
00000000 00000000
-/( SFUR0) [R/W] B,H,W
-------- --------
*4
001510H - -
-/( SFLR10) [R/W]
B,H,W
--------
*4
-/( SFLR00) [R/W]
B,H,W
--------
*4
001514H - - - -
001518H - - - -
00151CH
BGR0[R/W] H,W
00000000 00000000
-/(ISMK0)[R/W]
B,H,W
--------
*2
-/(ISBA0)[R/W]
B,H,W
--------
*2
001520H
FCR10[R/W]
B,H,W
00-00100
FCR00[R/W]
B,H,W
-0000000
FBYTE20[R/W]
B,H,W
00000000
FBYTE10[R/W]
B,H,W
00000000
/'\
S PA N 5 IO N
‘
5 Address offset value/Register name
+0 +1 +2 +3
SCRI/(IBCRI) SMR][R/W] SSR1[R’W] ESCRl/(IBSRI)
R’W] B,H,w B,H,w B,H,w K W] B.H,W
000000 00000070 00001 1 00000000
r/(RDRI l,[TDR11))[R’W] H.w RDR0l/(TDR01)[R/w] B,H.w
, 7777777777 , "0 00000000 ‘
SAL Rl[K w] BJ—LW
0~~000 00000000
STMRl [R] BJ—Lw
00000000 00000000
STMCR1[R/W] BJ—Lw
00000000 00000000
r/(SCSCRISFURI) [R/W] B,H,w
,, [SCSTR3 1) ,, [SCSTRZU r/(SCSTRI l/SFLRl STR01 ’SFLR
R’W]B,H,W R’W]B,H,W [R/W]B ,w [KW] H,
TBYTE01[R/W]
BJ—LW
00000000
r,[lSMK1)[R’W] J(lSBAl)[R/W]
B,H.w BJ—LW
FCR] [[K w] FCRO] [R/W] FBYTEZ l [R w] FBYTEI 1[R/W]
B,H,w B,H,w B,H,w BJ—LW
00700100 70000000 00000000 00000000
w SMR2[R/W] ssmnvw] Escmm/w]
B,H,w B,H,w BJ—LW
00000070 04001 1 00000000
r/(RDR12’(TDRIZ))[R/W] H,W RDROZ/(TDR(J2)[R/W] BJ—Lw
7777777777 , "7000000000 ‘
SALstm w] BJ—LW
0~~000 00000000
STMR2[R] BJ—Lw
00000000 00000000
STMCRZ[R/W] BJ—Lw
00000000 00000000
r/(SCSCRZSFURZ) [R/W] B,H,w
fitscsnuz) fitscsnuz) r/(SCSTRIZ/SFLR ,(s STROTSFLR
R’W]B,H,W R’W]B,H,W [R/W] H, [KW] H,
TBYTEOZ[R/W]
BJ—LW
00000000
BGRZ[R/W] H,w
00000000 00000000
FCR12[R/W] FCR()2[R/W] FBYTE22[KW] FBYTE]2[R/W]
B,H,w B,H,w B,H,w BJ—LW
00700100 70000000 00000000 00000000
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 63
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
001524H
SCR1/(IBCR1)
[R/W] B,H,W
0--00000
SMR1[R/W]
B,H,W
000000-0
SSR1[R/W]
B,H,W
0--00011
ESCR1/(IBSR1)
[R/W] B,H,W
00000000
Multi Function
Serial I/F 1
*1: Byte access
is possible only
for access to
lower 8 bits.
*2: Reserved
because I2C
mode is not set
immediately
after reset
*3: Reserved
because CSIO
mode is not set
immediately
after reset
*4: Reserved
because LIN2.1
mode is not set
immediately
after reset
001528H
-/(RDR11/(TDR11))[R/W] H,W
-------- --------
*3
RDR01/(TDR01)[R/W] B,H,W
-------0 00000000
*1
00152CH
SACSR1[R/W] B,H,W
0----000 00000000
STMR1[R] B,H,W
00000000 00000000
001530H
STMCR1[R/W] B,H,W
00000000 00000000
-/(SCSCR1/SFUR1) [R/W] B,H,W
-------- --------
*3,*4
001534H
-/(SCSTR31)
[R/W] B,H,W
--------
*3
-/(SCSTR21)
[R/W] B,H,W
--------
*3
-/(SCSTR11/SFLR1
1) [R/W] B,H,W
--------
*3,*4
-/(SCSTR01/SFLR
01) [R/W] B,H,W
--------
*3,*4
001538H - - - -
00153CH - - -
TBYTE01[R/W]
B,H,W
00000000
001540H
BGR1[R/W] H,W
00000000 00000000
-/(ISMK1)[R/W]
B,H,W
--------
*2
-/(ISBA1)[R/W]
B,H,W
--------
*2
001544H
FCR11[R/W]
B,H,W
00-00100
FCR01[R/W]
B,H,W
-0000000
FBYTE21[R/W]
B,H,W
00000000
FBYTE11[R/W]
B,H,W
00000000
001548H
SCR2[R/W] B,H,W
0--00000
SMR2[R/W]
B,H,W
000000-0
SSR2[R/W]
B,H,W
0--00011
ESCR2[R/W]
B,H,W
00000000
Multi Function
Serial I/F 2
*1: Byte access
is possible only
for access to
lower 8 bits.
*3: Reserved
because CSIO
mode is not set
immediately
after reset
*4: Reserved
because LIN2.1
mode is not set
immediately
after reset
00154CH
-/(RDR12/(TDR12))[R/W] H,W
-------- --------
*3
RDR02/(TDR02)[R/W] B,H,W
-------0 00000000
*1
001550H
SACSR2[R/W] B,H,W
0----000 00000000
STMR2[R] B,H,W
00000000 00000000
001554H
STMCR2[R/W] B,H,W
00000000 00000000
-/(SCSCR2/SFUR2) [R/W] B,H,W
-------- --------
*3,*4
001558H
-/(SCSTR32)
[R/W] B,H,W
--------
*3
-/(SCSTR22)
[R/W] B,H,W
--------
*3
-/(SCSTR12/SFLR
12) [R/W] B,H,W
--------
*3,*4
-/(SCSTR02/SFLR
02) [R/W] B,H,W
--------
*3,*4
00155CH - - - -
001560H - - -
TBYTE02[R/W]
B,H,W
00000000
001564H
BGR2[R/W] H,W
00000000 00000000
- -
001568H
FCR12[R/W]
B,H,W
00-00100
FCR02[R/W]
B,H,W
-0000000
FBYTE22[R/W]
B,H,W
00000000
FBYTE12[R/W]
B,H,W
00000000
/\
5 PA N 5 IO N
‘
5 Address offset value/Register name
+0 +1 +2 +3
SCR3/(IBCR3) SMR3[R/w] SSR3[R’W] ESCR3/(IBSR3)
R’W] B,H,w B,H,w B,H,w KW] B.H,W
000000 00000070 00001 1 00000000
r/(RDR13’(TDRI3))[R/W] H,w RDRO}/(TDR(J3)[R/W] B,H.w
, 7777777777 , "0 00000000 ‘
SAL R3[KW] B.H,W STMR3[R] BJ—Lw
0~~000 00000000 00000000 00000000
STMCR3[R/W] BJ—Lw r/(SCSCRZSFURBJ) [R/W] BJ-Lw
00000000 00000000
r,[SCSTR33) r,[SCSTR23) r/(SCSTRIZ/SFLR
R’W] B,H,w R’W] B,H,w [R/W] H,
TBYTEo3[R/w]
BJ—LW
00000000
r,[lSMK3)[R’W] J(lSBA3)[R/W]
B,H,w BJ—LW
FCR13[R/W] FCR()3[R/W] FBYTE23[K w] FBYTE]3[R/W]
B,H,w B,H,w B,H,w BJ—LW
00700100 70000000 00000000 00000000
SCRA/(IBCRA) SMR4[R/w] SSR4[R’W] ESCRA/(IBSRA)
R’W] B,H,w B,H,w B,H,w KW] B.H,W
000000 00000070 00001 1 00000000
r/(RDR14’(TDR14))[R/W] H,w RDR04/(TDR(J4)[R/W] B,H.w
, 7777777777 , "0 00000000 ‘
SAL R4[KW] B.H,W STMR4[R] BJ—Lw
0~~000 00000000 00000000 00000000
STMCR4[R/w] BJ—Lw r/(SCSCRASFURA) [R/W] BJ-Lw
00000000 00000000
r,[SCSTR34) r,[SCSTR24) r/(SCSTRM/SFLR ,(s STRDataSheet
64 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
00156CH
SCR3/(IBCR3)
[R/W] B,H,W
0--00000
SMR3[R/W]
B,H,W
000000-0
SSR3[R/W]
B,H,W
0--00011
ESCR3/(IBSR3)
[R/W] B,H,W
00000000
Multi Function
Serial I/F 3
*1: Byte access
is possible only
for access to
lower 8 bits.
*2: Reserved
because I2C
mode is not set
immediately
after reset
*3: Reserved
because CSIO
mode is not set
immediately
after reset
*4: Reserved
because LIN2.1
mode is not set
immediately
after reset
001570H
-/(RDR13/(TDR13))[R/W] H,W
-------- --------
*3
RDR03/(TDR03)[R/W] B,H,W
-------0 00000000
*1
001574H
SACSR3[R/W] B,H,W
0----000 00000000
STMR3[R] B,H,W
00000000 00000000
001578H
STMCR3[R/W] B,H,W
00000000 00000000
-/(SCSCR3/SFUR3) [R/W] B,H,W
-------- --------
*3,*4
00157CH
-/(SCSTR33)
[R/W] B,H,W
--------
*3
-/(SCSTR23)
[R/W] B,H,W
--------
*3
-/(SCSTR13/SFLR
13) [R/W] B,H,W
--------
*3,*4
-/(SCSTR03/SFLR
03) [R/W] B,H,W
--------
*3,*4
001580H - - - -
001584H - - -
TBYTE03[R/W]
B,H,W
00000000
001588H
BGR3[R/W] H,W
00000000 00000000
-/(ISMK3)[R/W]
B,H,W
--------
*2
-/(ISBA3)[R/W]
B,H,W
--------
*2
00158CH
FCR13[R/W]
B,H,W
00-00100
FCR03[R/W]
B,H,W
-0000000
FBYTE23[R/W]
B,H,W
00000000
FBYTE13[R/W]
B,H,W
00000000
001590H
SCR4/(IBCR4)
[R/W] B,H,W
0--00000
SMR4[R/W]
B,H,W
000000-0
SSR4[R/W]
B,H,W
0--00011
ESCR4/(IBSR4)
[R/W] B,H,W
00000000
Multi Function
Serial I/F 4
*1: Byte access
is possible only
for access to
lower 8 bits.
*2: Reserved
because I2C
mode is not set
immediately
after reset
*3: Reserved
because CSIO
mode is not set
immediately
after reset
*4: Reserved
because LIN2.1
mode is not set
immediately
after reset
001594H
-/(RDR14/(TDR14))[R/W] H,W
-------- --------
*3
RDR04/(TDR04)[R/W] B,H,W
-------0 00000000
*1
001598H
SACSR4[R/W] B,H,W
0----000 00000000
STMR4[R] B,H,W
00000000 00000000
00159CH
STMCR4[R/W] B,H,W
00000000 00000000
-/(SCSCR4/SFUR4) [R/W] B,H,W
-------- --------
*3,*4
0015A0H
-/(SCSTR34)
[R/W] B,H,W
--------
*3
-/(SCSTR24)
[R/W] B,H,W
--------
*3
-/(SCSTR14/SFLR
14) [R/W] B,H,W
--------
*3,*4
-/(SCSTR04/SFLR
04) [R/W] B,H,W
--------
*3,*4
0015A4H -
-/(SCSFR24)[R/W]
B,H,W
--------
*3
-/(SCSFR14)[R/W]
B,H,W
--------
*3
-/(SCSFR04)[R/W]
B,H,W
--------
*3
0015A8H
-/(TBYTE34)[R/W]
B,H,W
--------
*3
-/(TBYTE24)[R/W]
B,H,W
--------
*3
-/(TBYTE14)[R/W]
B,H,W
--------
*3
TBYTE04[R/W]
B,H,W
00000000
0015ACH
BGR4[R/W] H,W
00000000 00000000
-/(ISMK4)[R/W]
B,H,W
--------
*2
-/(ISBA4)[R/W]
B,H,W
--------
*2
0015B0H
FCR14[R/W]
B,H,W
00-00100
FCR04[R/W]
B,H,W
-0000000
FBYTE24[R/W]
B,H,W
00000000
FBYTE14[R/W]
B,H,W
00000000
0015B4
H
|
001FFCH
- - - - Reserved
/'\
S PA N 5 IO N
\
5 Address offset value/Register name
+0 1 +1 +2 1 +3
CTRLRU[R’W] B,1—1,w STATRO[K w] B,1—1,w
W W 000W0001 WW 00000000
ERRC T0 [R] B,1—1.w BTRO[K w] B,1—1,w
00000000 00000000 W010001 1 00000001
INTRO[R] B,1—1,w TESTRO[K w] BJ—LW
00000000 00000000 77777777 X00000W
BRPERO[R/W] 13,1-1,w
777777777777 0000
lFlCREQUUUW] BJ—LW lFlCMSKO[R/W] B,1—1.w
0 W 00000001 WW 00000000
lFlMSK20[K w] 13,1-1,w IF] MSKIU[R’W] BJ—LW
11W1111111111111 1111111111111111
lFlARB20[K w] B,1—1,w IF] ARBIU[R’W] BJ—LW
00000000 00000000 00000000 00000000
[Fl MCTRO[K w] B,1—1,w
00000000 0WW0000
IF] DTAl0[R w] 13,1-1,w [Fl DTA2U[R’W] BJ—LW
00000000 00000000 00000000 00000000
IFlDTB]0[R/W] B,1-1.w lFlDTBZ()[R/W] 13,1-1,w
00000000 00000000 00000000 00000000
002028H
00202cH
002030H
002034H
002038H
00203cH
1F2CREQU[R’W] BJ—LW lFZCMSKO[R/W] B,1—1.w
0WW W 00000001 WW 00000000
lFZMSK20[K w] 13,1-1,w 1F2MSK10[R/w]13.1-1,w
11W1111111111111 1111111111111111
lF2ARB20[K w] B,1—1,w IF2ARB10[R’W]B.H,W
00000000 00000000 00000000 00000000
IFZMCTRO[K w] B,1—1,w
00000000 0WW0000
IF2DTAl0[R w] 13,1-1,w IFZDTAZU[R’W] BJ—LW
00000000 00000000 00000000 00000000
IFZDTB]0[R/W] B,1-1.w lFZDTBZ()[R/W] 13,1-1,w
00000000 00000000 00000000 00000000
002058H
00205cH
002060H
002054H
002068
1
00207cH
TREQR20[R] 13,1-1,w TREQR10[R] BJ—LW
00000000 00000000 00000000 00000000
TREQR40[R] 13,1-1,w TREQR30[R] BJ—LW
00000000 00000000 00000000 00000000
002080H W W
00208cH W W
NEWDTZO[R] B,H,W
00000000 00000000
NEWDT lU[R] B,H.W
00000000 00000000
NEWDT40[R] B,1—1,w
00000000 00000000
NEWDT}U[R] B,H.W
00000000 00000000
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 65
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
002000H
CTRLR0[R/W] B,H,W
-------- 000-0001
STATR0[R/W] B,H,W
-------- 00000000
CAN 0
64msb
002004H
ERRCNT0 [R] B,H,W
00000000 00000000
BTR0[R/W] B,H,W
-0100011 00000001
002008H
INTR0[R] B,H,W
00000000 00000000
TESTR0[R/W] B,H,W
-------- X00000--
00200CH
BRPER0[R/W] B,H,W
-------- ----0000
-
002010H
IF1CREQ0[R/W] B,H,W
0------- 00000001
IF1CMSK0[R/W] B,H,W
-------- 00000000
002014H
IF1MSK20[R/W] B,H,W
11-11111 11111111
IF1MSK10[R/W] B,H,W
11111111 11111111
002018H
IF1ARB20[R/W] B,H,W
00000000 00000000
IF1ARB10[R/W] B,H,W
00000000 00000000
00201CH
IF1MCTR0[R/W] B,H,W
00000000 0---0000
-
002020H
IF1DTA10[R/W] B,H,W
00000000 00000000
IF1DTA20[R/W] B,H,W
00000000 00000000
002024H
IF1DTB10[R/W] B,H,W
00000000 00000000
IF1DTB20[R/W] B,H,W
00000000 00000000
002028
H,
00202CH
- -
002030
H,
002034H
Reserved (IF1 data mirror)
002038
H,
00203CH
- -
002040H
IF2CREQ0[R/W] B,H,W
0------- 00000001
IF2CMSK0[R/W] B,H,W
-------- 00000000
002044H
IF2MSK20[R/W] B,H,W
11-11111 11111111
IF2MSK10[R/W] B,H,W
11111111 11111111
002048H
IF2ARB20[R/W] B,H,W
00000000 00000000
IF2ARB10[R/W] B,H,W
00000000 00000000
00204CH
IF2MCTR0[R/W] B,H,W
00000000 0---0000
-
002050H
IF2DTA10[R/W] B,H,W
00000000 00000000
IF2DTA20[R/W] B,H,W
00000000 00000000
002054H
IF2DTB10[R/W] B,H,W
00000000 00000000
IF2DTB20[R/W] B,H,W
00000000 00000000
002058
H,
00205CH
- -
002060
H,
002064H
Reserved (IF2 data mirror)
002068
H
|
00207CH
- -
002080H
TREQR20[R] B,H,W
00000000 00000000
TREQR10[R] B,H,W
00000000 00000000
002084H
TREQR40[R] B,H,W
00000000 00000000
TREQR30[R] B,H,W
00000000 00000000
002088H
-
-
00208CH
-
-
002090H
NEWDT20[R] B,H,W
00000000 00000000
NEWDT10[R] B,H,W
00000000 00000000
002094H
NEWDT40[R] B,H,W
00000000 00000000
NEWDT30[R] B,H,W
00000000 00000000
/\
5 PA N 5 IO N
‘
5 Address offset value/Register name
+ 0 ‘ + 1 +2 ‘ +3
002098H W W
00209cH W W
INTPNDZU[R] B,H,w lNTPNDl(J[R] B.1—1,W
00000000 00000000 00000000 00000000
INTPND4U[R] B,H,w lNTPND3(J[R] B.1—1,W
00000000 00000000 00000000 00000000
()(JZOAXH W W
0020AcH W W
MSGVAL2(J[R] B,H,w MSGVAL1()[R] B.1—1,W
00000000 00000000 00000000 00000000
MSGVAL40[R] B,H,w MSGVAL3()[R] B.1—1,W
00000000 00000000 00000000 00000000
0020138H W W
002013CH W W
0020c0
1
0020FCH
CTRLR1[R’W] B,1—1,w STATRI [R w] B,H,w
W W 000W0001 W 00000000
ERRCNTI [R] B,1-1.w BTRI[K w] B,1—1,w
00000000 00000000 010001 1 00000001
INTRl [R] B,1—1,w TESTRI [K w]B.1—1,w
00000000 00000000 77777777 X00000W
BRPER1[R/W] B,H,w
777777777777 0000
1F1CREQ1[R/w] B.1—1,W lFlCMSKl[R/W] B,1-1.w
0WW W 00000001 W 00000000
lFlMSK2l[R w] B,H,w lFlMSKll[R/W] B,1-1,w
11W1111111111111 1111111111111111
lFlARBZ 1 [K w]B,1-1,W lFlARB 1 1 [WW] B,1-1,w
00000000 00000000 00000000 00000000
[Fl MCTRI [K w]B,1-1,W
00000000 0WW0000
lFlDTA] 1[R’W] B.1—1,w IFlDTA21[R’W] B.1—1,W
00000000 00000000 00000000 00000000
lFlDTBl1[R w] B,H,w lFl DTBZ 1 [WW] B,H,w
00000000 00000000 00000000 00000000
002128H
00212cH
002130H
002134H
002138H
00213cH
1F2CREQ1[R/w] B.1—1,W lFZCMSKl[R/W] B,1-1.w
0WW W 00000001 W 00000000
1F2MSK2 1 [R w] B,H,w lFZMSK1][R/W] B,1-1,w
11W1111111111111 1111111111111111
1F2ARB2 1 [K w]B,1-1,W lFZARB 1 1 [WW] B,1-1,w
00000000 00000000 00000000 00000000
IFZMCTRI [K w]B,1-1,W
00000000 0WW0000
lFZDTA] 1[R’W] B.1—1,w 1F2DTA21 [R’W] B.1—1,W
00000000 00000000 00000000 00000000
lF2DTBl1[R w] B,H,w lFZDTBZ 1 [WW] B,H,w
00000000 00000000 00000000 00000000
DataSheet
66 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
002098H
-
-
CAN 0
64msb
00209CH
-
-
0020A0H
INTPND20[R] B,H,W
00000000 00000000
INTPND10[R] B,H,W
00000000 00000000
0020A4H
INTPND40[R] B,H,W
00000000 00000000
INTPND30[R] B,H,W
00000000 00000000
0020A8H
-
-
0020ACH
-
-
0020B0H
MSGVAL20[R] B,H,W
00000000 00000000
MSGVAL10[R] B,H,W
00000000 00000000
0020B4H
MSGVAL40[R] B,H,W
00000000 00000000
MSGVAL30[R] B,H,W
00000000 00000000
0020B8H
-
-
0020BCH
-
-
0020C0
H
|
0020FCH
- -
002100H
CTRLR1[R/W] B,H,W
-------- 000-0001
STATR1[R/W] B,H,W
-------- 00000000
CAN 1
64msb
002104H
ERRCNT1 [R] B,H,W
00000000 00000000
BTR1[R/W] B,H,W
-0100011 00000001
002108H
INTR1[R] B,H,W
00000000 00000000
TESTR1[R/W] B,H,W
-------- X00000--
00210CH
BRPER1[R/W] B,H,W
-------- ----0000
-
002110H
IF1CREQ1[R/W] B,H,W
0------- 00000001
IF1CMSK1[R/W] B,H,W
-------- 00000000
002114H
IF1MSK21[R/W] B,H,W
11-11111 11111111
IF1MSK11[R/W] B,H,W
11111111 11111111
002118H
IF1ARB21[R/W] B,H,W
00000000 00000000
IF1ARB11[R/W] B,H,W
00000000 00000000
00211CH
IF1MCTR1[R/W] B,H,W
00000000 0---0000
-
002120H
IF1DTA11[R/W] B,H,W
00000000 00000000
IF1DTA21[R/W] B,H,W
00000000 00000000
002124H
IF1DTB11[R/W] B,H,W
00000000 00000000
IF1DTB21[R/W] B,H,W
00000000 00000000
002128
H,
00212CH
- -
002130
H,
002134H
Reserved (IF1 data mirror)
002138
H,
00213CH
- -
002140H
IF2CREQ1[R/W] B,H,W
0------- 00000001
IF2CMSK1[R/W] B,H,W
-------- 00000000
002144H
IF2MSK21[R/W] B,H,W
11-11111 11111111
IF2MSK11[R/W] B,H,W
11111111 11111111
002148H
IF2ARB21[R/W] B,H,W
00000000 00000000
IF2ARB11[R/W] B,H,W
00000000 00000000
00214CH
IF2MCTR1[R/W] B,H,W
00000000 0---0000
-
002150H
IF2DTA11[R/W] B,H,W
00000000 00000000
IF2DTA21[R/W] B,H,W
00000000 00000000
002154H
IF2DTB11[R/W] B,H,W
00000000 00000000
IF2DTB21[R/W] B,H,W
00000000 00000000
/'\
SPANSION
‘
5
Address offset value/Register name
+0 ] +1
+2 ] +3
002158H
00215cH
002100H
002154H
002168
]
00217cH
TREQR21[R] 13,1-1,w
00000000 00000000
TREQRI 1 [R] 13,1-1,w
00000000 00000000
TREQR41[R] 13,1-1,w
00000000 00000000
TREQR31[R] B.1-1,w
00000000 00000000
002188“
00218cH
NEWDTZ l [R] B,H,W
00000000 00000000
NEWDTI 1 [R] B.1-1,w
00000000 00000000
NEWDT4l[R] 13,1-1,w
00000000 00000000
NEWDT31 [R] B,H.W
00000000 00000000
002198“
00219cH
lNTPNDZl [R] B,H,W
00000000 00000000
lNTPNDl 1 [R] B,1—1.w
00000000 00000000
INTPND41 [R] B,H,W
00000000 00000000
lNTPND3 1 [R] 13.1-1,w
00000000 00000000
002 l AXH
0021AcH
MSGVALZ] [R] B,H,W
00000000 00000000
MSGVALll[R] 13,1-1,w
00000000 00000000
MSGVALAH [R] B,H,W
00000000 00000000
MSGVAL3 1 [R] 13.1-1,w
00000000 00000000
00211321H
0021BCH
002 [C0
]
0021 FCH
CTRLR2[R’W] B,H,W
, 0007000]
STATR2[R w] B,1-1,w
00000000
ERRCNTZ [R] BJ-LW
00000000 00000000
BTR2[R w]13,1-1,w
7010001 1 00000001
INTRZ[R] 13,1-1,w
00000000 00000000
TESTR2[R w] 13.1-1,w
,,,,,,,, X00000"
BRPERZ[R/W] 13,1-1,w
777777777777 0000
lFlCREQ2[R’W] 13.1-1,w lFlCMSK2[R/W] 13,1-1.w
0 410000001 ,, "700000000
lFlMSK22[RW] B,H,W
llrlllll llllllll
IF]MSK12[R’W] B.H,W
lllllll] llllllll
1F 1 ARB22[R W] B,H,W
00000000 00000000
IF]ARB12[R’W] B.H,W
00000000 00000000
[Fl MCTR2[R W] B,H,W
00000000 07770000
IF] DTAIZ[R W] B,H,W
00000000 00000000
[Fl DTA22[R’W] B.H,W
00000000 00000000
IFlDTB]2[R/W] B,1—1.w
00000000 00000000
IF I DTBZZ[R/W] B,H,W
00000000 00000000
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 67
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
002158
H,
00215CH
- -
CAN 1
64msb
002160
H,
002164H
Reserved (IF2 data mirror)
002168
H
|
00217CH
- -
002180H
TREQR21[R] B,H,W
00000000 00000000
TREQR11[R] B,H,W
00000000 00000000
002184H
TREQR41[R] B,H,W
00000000 00000000
TREQR31[R] B,H,W
00000000 00000000
002188H
-
-
00218CH
-
-
002190H
NEWDT21[R] B,H,W
00000000 00000000
NEWDT11[R] B,H,W
00000000 00000000
002194H
NEWDT41[R] B,H,W
00000000 00000000
NEWDT31[R] B,H,W
00000000 00000000
002198H
-
-
00219CH
-
-
0021A0H
INTPND21[R] B,H,W
00000000 00000000
INTPND11[R] B,H,W
00000000 00000000
0021A4H
INTPND41[R] B,H,W
00000000 00000000
INTPND31[R] B,H,W
00000000 00000000
0021A8H
-
-
0021ACH
-
-
0021B0H
MSGVAL21[R] B,H,W
00000000 00000000
MSGVAL11[R] B,H,W
00000000 00000000
0021B4H
MSGVAL41[R] B,H,W
00000000 00000000
MSGVAL31[R] B,H,W
00000000 00000000
0021B8H
-
-
0021BCH
-
-
0021C0
H
|
0021FCH
- -
002200H
CTRLR2[R/W] B,H,W
-------- 000-0001
STATR2[R/W] B,H,W
-------- 00000000
CAN 2
64msb
002204H
ERRCNT2 [R] B,H,W
00000000 00000000
BTR2[R/W] B,H,W
-0100011 00000001
002208H
INTR2[R] B,H,W
00000000 00000000
TESTR2[R/W] B,H,W
-------- X00000--
00220CH
BRPER2[R/W] B,H,W
-------- ----0000
-
002210H
IF1CREQ2[R/W] B,H,W
0------- 00000001
IF1CMSK2[R/W] B,H,W
-------- 00000000
002214H
IF1MSK22[R/W] B,H,W
11-11111 11111111
IF1MSK12[R/W] B,H,W
11111111 11111111
002218H
IF1ARB22[R/W] B,H,W
00000000 00000000
IF1ARB12[R/W] B,H,W
00000000 00000000
00221CH
IF1MCTR2[R/W] B,H,W
00000000 0---0000
-
002220H
IF1DTA12[R/W] B,H,W
00000000 00000000
IF1DTA22[R/W] B,H,W
00000000 00000000
002224H
IF1DTB12[R/W] B,H,W
00000000 00000000
IF1DTB22[R/W] B,H,W
00000000 00000000
/\
5 PA N 5 IO N
‘
5 Address offset value/Register name
+ 0 ‘ + 1 +2 ‘ +3
002228H
00222cH
002230H
002234H
002238H
00223cH
1F2CREQ2[R/w] BJ—LW lFZCMSK2[R/W] B,H.w
0 , 00000001 W 00000000
1F2MSK22[R w] B,H,w IF2MSK12[R’W] BJ—LW
1171111111111111 1111111111111111
1F2ARB22[K w] B,H,W IF2ARB12[R’W] BJ—LW
00000000 00000000 00000000 00000000
IFZMCTR2[K w] B,H,W
00000000 07770000
IF2DTAlZ[R w] B,H,w IFZDTA22[R’W] BJ—LW
00000000 00000000 00000000 00000000
IFZDTB]2[R/W] BJ—Lw 1F2DTBzz[R/w] B,H,w
00000000 00000000 00000000 00000000
002258H
00225cH
002260H
002254H
002268
\
00227cH
TREQR22[R] B,H,w TREQR12[R] B.H,W
00000000 00000000 00000000 00000000
TREQR42[R] B,H,w TREQR32[R] B.H,W
00000000 00000000 00000000 00000000
(JOZZXXH , ,
00228cH , ,
NEWDT22[R] B,H,w NEWDT12[R] B,H.w
00000000 00000000 00000000 00000000
NEWDT42[R] B,H,w NEWDT32[R] B,H.w
00000000 00000000 00000000 00000000
002290H , ,
00229cH , ,
INTPND22[R] B,H,w lNTPND]2[R] B.H,W
00000000 00000000 00000000 00000000
INTPND42[R] B,H,w lNTPND32[R] B.H,W
00000000 00000000 00000000 00000000
()(JZZAXH , ,
0022AcH , ,
MSGVAL22[R] B,H,w MSGVAL12[R] BJ—LW
00000000 00000000 00000000 00000000
MSGVAL42[R] B,H,w MSGVAL3Z[R] BJ—LW
00000000 00000000 00000000 00000000
002288H , ,
()OZZBCH , ,
0022c0
\
0022FCH
DataSheet
68 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
002228
H,
00222CH
- -
CAN 2
64msb
002230
H,
002234H
Reserved (IF1 data mirror)
002238
H,
00223CH
- -
002240H
IF2CREQ2[R/W] B,H,W
0------- 00000001
IF2CMSK2[R/W] B,H,W
-------- 00000000
002244H
IF2MSK22[R/W] B,H,W
11-11111 11111111
IF2MSK12[R/W] B,H,W
11111111 11111111
002248H
IF2ARB22[R/W] B,H,W
00000000 00000000
IF2ARB12[R/W] B,H,W
00000000 00000000
00224CH
IF2MCTR2[R/W] B,H,W
00000000 0---0000
-
002250H
IF2DTA12[R/W] B,H,W
00000000 00000000
IF2DTA22[R/W] B,H,W
00000000 00000000
002254H
IF2DTB12[R/W] B,H,W
00000000 00000000
IF2DTB22[R/W] B,H,W
00000000 00000000
002258
H,
00225CH
- -
002260
H,
002264H
Reserved (IF2 data mirror)
002268
H
|
00227CH
- -
002280H
TREQR22[R] B,H,W
00000000 00000000
TREQR12[R] B,H,W
00000000 00000000
002284H
TREQR42[R] B,H,W
00000000 00000000
TREQR32[R] B,H,W
00000000 00000000
002288H
-
-
00228CH
-
-
002290H
NEWDT22[R] B,H,W
00000000 00000000
NEWDT12[R] B,H,W
00000000 00000000
002294H
NEWDT42[R] B,H,W
00000000 00000000
NEWDT32[R] B,H,W
00000000 00000000
002298H
-
-
00229CH
-
-
0022A0H
INTPND22[R] B,H,W
00000000 00000000
INTPND12[R] B,H,W
00000000 00000000
0022A4H
INTPND42[R] B,H,W
00000000 00000000
INTPND32[R] B,H,W
00000000 00000000
0022A8H
-
-
0022ACH
-
-
0022B0H
MSGVAL22[R] B,H,W
00000000 00000000
MSGVAL12[R] B,H,W
00000000 00000000
0022B4H
MSGVAL42[R] B,H,W
00000000 00000000
MSGVAL32[R] B,H,W
00000000 00000000
0022B8H
-
-
0022BCH
-
-
0022C0
H
|
0022FCH
- - - -
/'\
S PA N 5 IO N
‘
5 Address offset value/Register name
+0 ‘ +1 +2 +3
DFCTLR[R’W] BJ—LW DFSTR[K w]
70 777777777 ,, BJ—LW ""7001
002304H , , , ,
FLIFCTLR[R/W] FLIFFER1[R’W] FLIFFERZUUW]
B,H,w B,H,w BJ—LW
m0~00
00230c
\
002FFCH
SEEARX[R] BJ—LW DEEARX[R] BJ—Lw
70000000 00000000 70000000 00000000
EECSRX[R’W]
B,H,w
""0070
EFECRX[R/W] B,H,w
7777777 0 00000000 00000000
TEAROX[R] BJ—Lw
000 77777777777777 0000000 00000000
TEAR]X[R] BJ—Lw
000 77777777777777 0000000 00000000
TEAR2X[R] BJ—Lw
70000000 00000000
TAEARX[R/W] BJ—Lw TASARX[R/W] BJ—Lw
7101 l 1 1 l l 1 1 1 l 1 1 1 70000000 00000000
TFECRX[R’W] TlCRX[R/W]
B,H,w B,H,w
""0000 ""0000
TSRCRX[R/W] TKCCRX[R/W]
B,H,w BJ—LW
07 00~~00
SEEARA[R] BJ—LW DEEARA[R] BJ-Lw
"000000 00000000 "000000 00000000
EECSRA[R’W]
B,H,w
""0070
EFECRA[R/W] B,H,w
7777777 0 00000000 00000000
TEAROA[R] BJ—Lw
000 rrrrrrrrrrrrrrrrrr 000 00000000
TEAR]A[R] BJ—Lw
000 rrrrrrrrrrrrrrrrrr 000 00000000
TEAR2A[R] BJ—Lw
000 rrrrrrrrrrrrrrrrrr 000 00000000
TAEARA[R/W] BJ—Lw TASARA[R/W] BJ—Lw
77777 lll 11111111 ""7000 00000000
TFECRA[R’W] TlCRA[R/W]
B,H,w B,H,w
""0000 ""0000
TSRCRA[R/W] TKCCRA[R/W]
B,H, BJ—LW
07 00~~00
003048
\
0030FCH
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 69
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
002300H
DFCTLR[R/W] B,H,W
-0------ --------
-
DFSTR[R/W]
B,H,W -----001
WorkFlash
002304H
-
-
-
-
002308H
FLIFCTLR[R/W]
B,H,W
---0--00
-
FLIFFER1[R/W]
B,H,W
--------
FLIFFER2[R/W]
B,H,W
--------
00230C
H
|
002FFCH
- - - - Reserved
003000H
SEEARX[R] B,H,W
-0000000 00000000
DEEARX[R] B,H,W
-0000000 00000000
XBS RAM
ECC control
register
003004H
EECSRX[R/W]
B,H,W
----00-0
- EFEARX[R/W] B,H,W
-0000000 00000000
003008H -
EFECRX[R/W] B,H,W
-------0 00000000 00000000
00300CH
TEAR0X[R] B,H,W
000----- -------- -0000000 00000000
XBS RAM
diagnosis
register
003010H
TEAR1X[R] B,H,W
000----- -------- -0000000 00000000
003014H
TEAR2X[R] B,H,W
000----- -------- -0000000 00000000
003018H
TAEARX[R/W] B,H,W
-1011111 11111111
TASARX[R/W] B,H,W
-0000000 00000000
00301CH
TFECRX[R/W]
B,H,W
----0000
TICRX[R/W]
B,H,W
----0000
TTCRX[R/W] B,H,W
------00 00001100
003020H
TSRCRX[R/W]
B,H,W
0-------
- -
TKCCRX[R/W]
B,H,W
00----00
003024H
SEEARA[R] B,H,W
--000000 00000000
DEEARA[R] B,H,W
--000000 00000000
Backup RAM
ECC control
register
003028H
EECSRA[R/W]
B,H,W
----00-0
- EFEARA[R/W] B,H,W
--000000 00000000
00302CH -
EFECRA[R/W] B,H,W
-------0 00000000 00000000
003030H
TEAR0A[R] B,H,W
000----- -------- -----000 00000000
Backup RAM
diagnosis
register
003034H
TEAR1A[R] B,H,W
000----- -------- -----000 00000000
003038H
TEAR2A[R] B,H,W
000----- -------- -----000 00000000
00303CH
TAEARA[R/W] B,H,W
-----111 11111111
TASARA[R/W] B,H,W
-----000 00000000
003040H
TFECRA[R/W]
B,H,W
----0000
TICRA[R/W]
B,H,W
----0000
TTCRA[R/W] B,H,W
------00 00001100
003044H
TSRCRA[R/W]
B,H,W
0-------
- -
TKCCRA[R/W]
B,H,W
00----00
003048
H
|
0030FCH
- - - - Reserved
/\
5 PA N 5 IO N
‘
5 Address offset value/Register name
+ 0 ‘ + 1 +2 ‘ +3
BUSDIGSRO[K w] 1-1,w BUSDI(}SR1[R’W] H.W
00000000 0 77777 00 00000000 07777700
BUSDIGSR2[K w] 1-1,w BUSTSTR(J[R/W] 1-1.,w
00000000 0 77777 00 000000 00000000
BUSADRO[R] w
00000000 00000000 00000000 00000000
BUSADRI [R] w
00000000 00000000 00000000 00000000
BUSADR2[R] w
00000000 00000000 00000000 00000000
BUSDI(}SR3[R’W] H.W
00000000 07777700
BUSDIGSR4[K w]1-1,w BUSTSTR] [R/W] 1-1.,w
00000000 0 77777 00 000000 00000000
0031 lCH ,
BUSADR3[R] w
00000000 00000000 00000000 00000000
BUSADR4[R] w
00000000 00000000 00000000 00000000
00:1 128
1
003FFCH
004000
1
005FFCH
006000
00CFFCH
C1F0[R] w
00000100111111110101101111111111
C1F1[R’W] w
00000000 7777777 0 70000000 77777777
00D008
1
00D00CH
00D010H ,
00D014H ,
00001 8H , , 1 , ,
LCK[K w] w
00000000
EIR[R/W] w
""7000 77777 000 ""0000 00000000
SlR[R’W] w
777777 00 "Woo 00000000 00000000
EILS[R/W] w
""7000 77777 000 ""0000 00000000
SILS[R’W] w
777777 11777777111111111111111111
EIES[R/W] w
""7000 77777 000 ""0000 00000000
EIER[R/W] w
""7000 77777 000 ""0000 00000000
SIES[R’W] w
777777 00 "Woo 00000000 00000000
DataSheet
70 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
003100H
BUSDIGSR0[R/W] H,W
00000000 0-----00
BUSDIGSR1[R/W] H,W
00000000 0-----00
Bus diagnosis
003104H
BUSDIGSR2[R/W] H,W
00000000 0-----00
BUSTSTR0[R/W] H,W
00--0000 00000000
003108H
BUSADR0[R] W
00000000 00000000 00000000 00000000
00310CH
BUSADR1[R] W
00000000 00000000 00000000 00000000
003110H
BUSADR2[R] W
00000000 00000000 00000000 00000000
003114H -
BUSDIGSR3[R/W] H,W
00000000 0-----00
003118H
BUSDIGSR4[R/W] H,W
00000000 0-----00
BUSTSTR1[R/W] H,W
00--0000 00000000
00311CH
-
003120H
BUSADR3[R] W
00000000 00000000 00000000 00000000
003124H
BUSADR4[R] W
00000000 00000000 00000000 00000000
003128
H
|
003FFCH
- - - - Reserved
004000
H
|
005FFCH
Backup RAM Backup RAM
area
006000
H
|
00CFFCH
- - - - Reserved
00D000H
CIF0[R] W
00000100 11111111 01011011 11111111
FlexRay
CIF
00D004H
CIF1[R/W] W
00000000 -------0 -0000000 --------
00D008
H
|
00D00CH
- - - - Reserved
00D010H
-
FlexRay
GIF
00D014H
-
00D018H
-
-
-
-
00D01CH
LCK[R/W] W
-------- -------- -------- 00000000
00D020H
EIR[R/W] W
-----000 -----000 ----0000 00000000
FlexRay
INT
00D024H
SIR[R/W] W
------00 ------00 00000000 00000000
00D028H
EILS[R/W] W
-----000 -----000 ----0000 00000000
00D02CH
SILS[R/W] W
------11 ------11 11111111 11111111
00D030H
EIES[R/W] W
-----000 -----000 ----0000 00000000
00D034H
EIER[R/W] W
-----000 -----000 ----0000 00000000
00D038H
SIES[R/W] W
------00 ------00 00000000 00000000
/'\
SPANSION
Address offset value/Register name
+0 ‘ +1 ‘ +2 ‘ +3
SIER[R’W] W
777777 00 77777700 00000000 00000000
ILE[R’W] w
TOC[R/W] w
"000000 00000000 0000000 777777 00
T 1 C[R/W] w
~000000 00000010 ,,,,,,,,,,,,,, 00
STPW1[R/W] w
"000000 00000000 "000000 70000000
STPW2[R] w
77777 000 00000000 ,,,,,(,(,(, 00000000
00D054
1
00007CH
succumw] w
""1100 01000000 0001000 17770000
succzmw] w
""0001 "700000 00000101 00000100
swam/w] w
000 1 000 1
NEMC[K W] W
rrrrrrrrrrrrrrrrrrrrrrrrrrrr 0000
Flchay
NEM
PRTCI[KW] w
0000100 0100110000007110 00110011
PRTC2[KW] w
"00111100101101~001010~001110
M HDC [ R/W] W
"00000 00000000 77777777 70000000
Flchay
MHD
00D09CH
Reserved
GTUC1[R’W] W
,,,,,,,,,,,, 0000 00000010 10000000
GTUC2[R’W] W
,,,,,,,,,,,, 0010 "000000 0000l010
mummw] w
70000010 70000010 00000000 00000000
GTUC4[R’W] w
"000000 00001000 "000000 000001 1 1
GTUC5[R’W] w
00001 1 10 "700000 00000000 00000000
GTUC6[R’W] w
77777 000 00000010 ,,,,,(,(,(, 00000000
GTUC7[R’W] w
777777 00 00000010 "W00 00000100
GTUCX[R’W] W
"00000 00000000 77 0000 [0
GTUC9[R’W] w
00 "700001 "000001
GTUC10[R’W] W
77777 000 00000010 "000000 00000101
(iTUCl1[R/W] w
77777 000 ""7000 ""7700 "W00
00DOCC
1
00D0FCH
‘
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 71
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
00D03CH
SIER[R/W] W
------00 ------00 00000000 00000000
FlexRay
INT
00D040H
ILE[R/W] W
-------- -------- -------- ------00
00D044H
T0C[R/W] W
--000000 00000000 -0000000 ------00
00D048H
T1C[R/W] W
--000000 00000010 -------- ------00
00D04CH
STPW1[R/W] W
--000000 00000000 --000000 -0000000
00D050H
STPW2[R] W
-----000 00000000 -----000 00000000
00D054
H
|
00D07CH
- - - - Reserved
00D080H
SUCC1[R/W] W
----1100 01000000 00010-00 1---0000
FlexRay
SUC
00D084H
SUCC2[R/W] W
----0001 ---00000 00000101 00000100
00D088H
SUCC3[R/W] W
-------- -------- -------- 00010001
00D08CH
NEMC[R/W] W
-------- -------- -------- ----0000
FlexRay
NEM
00D090H
PRTC1[R/W] W
000010-0 01001100 0000-110 00110011
FlexRay
PRT
00D094H
PRTC2[R/W] W
--001111 00101101 --001010 --001110
00D098H
MHDC[R/W] W
---00000 00000000 -------- -0000000
FlexRay
MHD
00D09CH
-
Reserved
00D0A0H
GTUC1[R/W] W
-------- ----0000 00000010 10000000
FlexRay
GTU
00D0A4H
GTUC2[R/W] W
-------- ----0010 --000000 00001010
00D0A8H
GTUC3[R/W] W
-0000010 -0000010 00000000 00000000
00D0ACH
GTUC4[R/W] W
--000000 00001000 --000000 00000111
00D0B0H
GTUC5[R/W] W
00001110 ---00000 00000000 00000000
00D0B4H
GTUC6[R/W] W
-----000 00000010 -----000 00000000
00D0B8H
GTUC7[R/W] W
------00 00000010 ------00 00000100
00D0BCH
GTUC8[R/W] W
---00000 00000000 -------- --000010
00D0C0H
GTUC9[R/W] W
-------- ------00 ---00001 --000001
00D0C4H
GTUC10[R/W] W
-----000 00000010 --000000 00000101
00D0C8H
GTUC11[R/W] W
-----000 -----000 ------00 ------00
00D0CC
H
|
00D0FCH
- Reserved
/\
SPANSION
‘
Address offset value/Register name
+0 ‘ +1 ‘ +2 ‘ +3
CCSV[R] w
W000000 00010000 W100W00 00000000
CCEV[R] w
WW00000 00W0000
00D [08H
UUD10CH
SCV[R] w
77777 000 00000000 WWW000 00000000
MTCCV[R] W
7777777777 000000 "000000 00000000
RCV[R] w
W0000 00000000
()CV[R] w
000 00000000 00000000
S F S [R] W
,,,,,,,,,,,, 0000 00000000 00000000
sw.\11T[R] w
W0000 00000000
ACS[R’W] W
rrrrrrrrrrrrrrrrrrr 00000 "700000
00[)12cH
ESIDl [R] w
W 00WW00 00000000
ESID2[R] w
W 00WW00 00000000
ESID3[R] w
W 00WW00 00000000
1381 D4 [R] w
W 00WW00 00000000
Es1Ds[R] w
W 00WW00 00000000
ESID6[R] w
W 00WW00 00000000
ESID7[R] w
W 00WW00 00000000
Es1Dx[R] w
W 00WW00 00000000
ESID9[R] w
W 00WW00 00000000
ESIDIU[R] w
W 00WW00 00000000
ESlDl 1 [R] w
W 00WW00 00000000
ESID12[R] w
W 00WW00 00000000
ESID13[R] w
W 00WW00 00000000
ESID14[R] w
0 00 00000000
ESID15[R] w
W 00WW00 00000000
UUD16CH
()SID 1 [R] w
WWWWWWWWWWWWWWWW 00WW00 00000000
DataSheet
72 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
00D100H
CCSV[R] W
--000000 00010000 -100--00 00000000
FlexRay
SUC
00D104H
CCEV[R] W
-------- -------- ---00000 00--0000
00D108
H
00D10CH
- Reserved
00D110H
SCV[R] W
-----000 00000000 -----000 00000000
FlexRay
GTU
00D114H
MTCCV[R] W
-------- --000000 --000000 00000000
00D118H
RCV[R] W
-------- -------- ----0000 00000000
00D11CH
OCV[R] W
-------- -----000 00000000 00000000
00D120H
SFS[R] W
-------- ----0000 00000000 00000000
00D124H
SWNIT[R] W
-------- -------- ----0000 00000000
00D128H
ACS[R/W] W
-------- -------- ---00000 ---00000
00D12CH
-
00D130H
ESID1[R] W
-------- -------- 00----00 00000000
00D134H
ESID2[R] W
-------- -------- 00----00 00000000
00D138H
ESID3[R] W
-------- -------- 00----00 00000000
00D13CH
ESID4[R] W
-------- -------- 00----00 00000000
00D140H
ESID5[R] W
-------- -------- 00----00 00000000
00D144H
ESID6[R] W
-------- -------- 00----00 00000000
00D148H
ESID7[R] W
-------- -------- 00----00 00000000
00D14CH
ESID8[R] W
-------- -------- 00----00 00000000
00D150H
ESID9[R] W
-------- -------- 00----00 00000000
00D154H
ESID10[R] W
-------- -------- 00----00 00000000
00D158H
ESID11[R] W
-------- -------- 00----00 00000000
00D15CH
ESID12[R] W
-------- -------- 00----00 00000000
00D160H
ESID13[R] W
-------- -------- 00----00 00000000
00D164H
ESID14[R] W
-------- -------- 00----00 00000000
00D168H
ESID15[R] W
-------- -------- 00----00 00000000
00D16CH
-
00D170H
OSID1[R] W
-------- -------- 00----00 00000000
/'\
SPANSION
‘
Address offset value/Register name
+0 ‘ +1 ‘ +2 ‘ +3
()SID2[R] w
W 00WW00 00000000
()SID3[R] w
W 00WW00 00000000
051mm] w
W 00WW00 00000000
()SID5[R] w
W 00WW00 00000000
()SID6[R] w
W 00WW00 00000000
()SID7[R] w
W 00WW00 00000000
051mm] w
W 00WW00 00000000
051mm] w
W 00WW00 00000000
osm 10[R] w
,,,,,,,,,,,,,,,, 00WW00 00000000
05101 1 [R] w
W 00WW00 00000000
osm 12[R] w
W 00WW00 00000000
osm l3[R] w
W 00WW00 00000000
osm l4[R] w
W 00WW00 00000000
osm l5[R] w
,,,,,,,,,,,,,,,, 00WW00 00000000
(JUDIACH
Reserved
NM v 1 [R] w
00000000 00000000 00000000 00000000
NM v2 [R] w
00000000 00000000 00000000 00000000
NM V; [R] w
00000000 00000000 00000000 00000000
00D] BC
1
00D2FCH
M RC [ R/w] w
001 10000000 00000000 00000000
FRF [ R/w] w
WWWWWWW 1 10000000 WW00000 00000000
FRFM[K w] w
WW00000 000000W
FCL[R/W] w
WWWWWWWWWWWWWWWWWWWWWWWW 10000000
MHDS[R w] w
0000000 0000000 0000000 00000000
LDTS[R] w
WWWWW 000 00000000 WWW000 00000000
FSR[R] w
00000000 WWWWW 000
MHDF[R w] w
U 00000000
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 73
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
00D174H
OSID2[R] W
-------- -------- 00----00 00000000
FlexRay
GTU
00D178H
OSID3[R] W
-------- -------- 00----00 00000000
00D17CH
OSID4[R] W
-------- -------- 00----00 00000000
00D180H
OSID5[R] W
-------- -------- 00----00 00000000
00D184H
OSID6[R] W
-------- -------- 00----00 00000000
00D188H
OSID7[R] W
-------- -------- 00----00 00000000
00D18CH
OSID8[R] W
-------- -------- 00----00 00000000
00D190H
OSID9[R] W
-------- -------- 00----00 00000000
00D194H
OSID10[R] W
-------- -------- 00----00 00000000
00D198H
OSID11[R] W
-------- -------- 00----00 00000000
00D19CH
OSID12[R] W
-------- -------- 00----00 00000000
00D1A0H
OSID13[R] W
-------- -------- 00----00 00000000
00D1A4H
OSID14[R] W
-------- -------- 00----00 00000000
00D1A8H
OSID15[R] W
-------- -------- 00----00 00000000
00D1ACH
-
Reserved
00D1B0H
NMV1[R] W
00000000 00000000 00000000 00000000
FlexRay
NEM
00D1B4H
NMV2[R] W
00000000 00000000 00000000 00000000
00D1B8H
NMV3[R] W
00000000 00000000 00000000 00000000
00D1BC
H
|
00D2FCH
- Reserved
00D300H
MRC[R/W] W
-----001 10000000 00000000 00000000
FlexRay
MHD
00D304H
FRF[R/W] W
-------1 10000000 ---00000 00000000
00D308H
FRFM[R/W] W
-------- -------- ---00000 000000--
00D30CH
FCL[R/W] W
-------- -------- -------- 10000000
00D310H
MHDS[R/W] W
-0000000 -0000000 -0000000 00000000
00D314H
LDTS[R] W
-----000 00000000 -----000 00000000
00D318H
FSR[R] W
-------- -------- 00000000 -----000
00D31CH
MHDF[R/W] W
-------- -------- -------0 00000000
/\
SPANSION
‘
Address offset value/Register name
1 +1 1 +2 1
TXRQl [R] w
00000000 00000000 00000000 00000000
TXRQ2[R] w
00000000 00000000 00000000 00000000
TXRQ3 [R] w
00000000 00000000 00000000 00000000
TXRQ4[R] w
00000000 00000000 00000000 00000000
N DAT 1 [R] w
00000000 00000000 00000000 00000000
N DATZ [R] w
00000000 00000000 00000000 00000000
N DAT3 [R] w
00000000 00000000 00000000 00000000
N DAT4[R] w
00000000 00000000 00000000 00000000
M 13 sc 1 [R] w
00000000 00000000 00000000 00000000
M 13 scz [R] w
00000000 00000000 00000000 00000000
M 13 sc3 [R] w
00000000 00000000 00000000 00000000
M 13 SC4[R] w
00000000 00000000 00000000 00000000
()(JD350
(JODZECH
CRE L[R] w
00010000 001 1 1001 00000010 000001 10
ENDN[R] w
10000111 01100101 01000011 00100001
UOD3FX
1
00D3FCH
()(JD400
1
00D4FCH
WRHSl [R/W] w
"000000 0000000 ""7000 00000000
WRHSZ[R/W] w
77777777 0000000 ""7000 00000000
WRHS3[R/W] w
"000 00000000
UUDSOCH
IBCM[R1W] w
~00 , ""7000
lBCR[R1W] w
0 7777777 70000000 0me 70000000
()(JDS l8
1
00D5FCH
DataSheet
74 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
00D320H
TXRQ1[R] W
00000000 00000000 00000000 00000000
FlexRay
MHD
00D324H
TXRQ2[R] W
00000000 00000000 00000000 00000000
00D328H
TXRQ3[R] W
00000000 00000000 00000000 00000000
00D32CH
TXRQ4[R] W
00000000 00000000 00000000 00000000
00D330H
NDAT1[R] W
00000000 00000000 00000000 00000000
00D334H
NDAT2[R] W
00000000 00000000 00000000 00000000
00D338H
NDAT3[R] W
00000000 00000000 00000000 00000000
00D33CH
NDAT4[R] W
00000000 00000000 00000000 00000000
00D340H
MBSC1[R] W
00000000 00000000 00000000 00000000
00D344H
MBSC2[R] W
00000000 00000000 00000000 00000000
00D348H
MBSC3[R] W
00000000 00000000 00000000 00000000
00D34CH
MBSC4[R] W
00000000 00000000 00000000 00000000
00D350
H
|
00D3ECH
- Reserved
00D3F0H
CREL[R] W
00010000 00111001 00000010 00000110
FlexRay
GIF
00D3F4H
ENDN[R] W
10000111 01100101 01000011 00100001
00D3F8
H
|
00D3FCH
- Reserved
00D400
H
|
00D4FCH
WRDSn[1-64][R/W] W
00000000 00000000 00000000 00000000
FlexRay
IBF
00D500H
WRHS1[R/W] W
--000000 -0000000 -----000 00000000
00D504H
WRHS2[R/W] W
-------- -0000000 -----000 00000000
00D508H
WRHS3[R/W] W
-------- -------- -----000 00000000
00D50CH
-
00D510H
IBCM[R/W] W
-------- ------00 -------- -----000
00D514H
IBCR[R/W] W
0------- -0000000 0------- -0000000
00D518
H
|
00D5FCH
- Reserved
/'\
S PA N 5 IO N
‘
5 Address offset value/Register name
+0 ‘ +1 ‘ +2 ‘ +3
()(JDéOO
\
()ODfiFCH
RDHS l [R] w
"000000 70000000 ""7000 00000000
RDHSZ[R] w
70000000 70000000 ""7000 00000000
RDH53[R] w
"000000 "000000 ""7000 00000000
MBS[R] w
"000000 "000000 00700000 00000000
()BCM[R’W] w
W00
()BCR[R/W] w
70000000 0~~00 70000000
()(JD718
\
00D7FCH
00on0
\
00EFFCH
00F000
\
00FEFCH
DSUCR[R/W] B,H,w
77777777 , 0
00FF04
\
00FF0CH
PCSR[R/W] BJ—Lw
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
PSSR[R/W] B,H.w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
00Fle
\
00FFF4H
EDIR1[R] B,H,w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
EDIRU[R] B,H,w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 75
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
00D600
H
|
00D6FCH
RDDSn[1-64][R] W
00000000 00000000 00000000 00000000
FlexRay
OBF
00D700H
RDHS1[R] W
--000000 -0000000 -----000 00000000
00D704H
RDHS2[R] W
-0000000 -0000000 -----000 00000000
00D708H
RDHS3[R] W
--000000 --000000 -----000 00000000
00D70CH
MBS[R] W
--000000 --000000 00-00000 00000000
00D710H
OBCM[R/W] W
-------- ------00 -------- ------00
00D714H
OBCR[R/W] W
-------- -0000000 0-----00 -0000000
00D718
H
|
00D7FCH
- Reserved
00D800
H
|
00EFFCH
- Reserved
00F000
H
|
00FEFCH
- Reserved [S]
00FF00H
DSUCR[R/W] B,H,W
-------- -------0
- - OCDU [S]
00FF04
H
|
00FF0CH
- - - - Reserved [S]
00FF10H
PCSR[R/W] B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
OCDU [S]
00FF14H
PSSR[R/W] B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00FF18
H
|
00FFF4H
- - - - Reserved [S]
00FFF8H
EDIR1[R] B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
OCDU [S]
00FFFCH
EDIR0[R] B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
[S]: It is a system register. The illegal instruction exception (data access error) is generated when reading and
writing to these registers in the user mode.
/\
SPANSION
‘
- M391F585LB/F586LB/F587LB/F585LD/F586LD/F587LD
3 Address offset value/Register name
+0 +1 +2 +3
PDR()()[R/W] PDR01 [R w] PDRUZ[R’W] PDR03[R/w]
B.H,w B,H,w B,H,w B,H,w
XXXXXXXX XXXXXXXX xxxxxxxx xxxxxxxx
PDR04[R/w] PDR05[K w] PDR06[R/w] PDR07[R/w]
B.H,w B,H,w B,H,w B,H,w
XXXXXXXX XXXXXXXX xxxxxxxx xxxxxxxx
PDR()8[R/W] PDR09[K w] PDRlU[R’W] PDRl1[R/W]
B.H,w B,H,w B,H,w B,H,w
XXXXXXXX XXXXXXXX xxxxxxxx xxxxxxxx
PDRlZ[R/W] PDRl3[K w]
B.H,w B,H,w
XXXXXXXX xxrxxxxx
000010
1
000038H
WDTCRO[K w] WDTCPRO[W] WDTCR] [R] WDTCPR] [w]
B.H,w B,H,w B,H,w B,H,w
70770000 00000000 ""0010 00000000
H _
D1CR[R/W] B
7777777 0
000048
1
00005cH
TMRLRA(J[R/W] H TMR(J[R] H
xxxxxxxx XXXXXXXX XXXXXXXX xxxxxxxx
TMRLRBO[R w] H TMCSR()[R/W] B,H,w
xxxxxxxx XXXXXXXX 00000000 07000000
000068
1
00007cH
BT(JTMR[R] H BTOTMCR[R/w] H
00000000 00000000 70000000 00000000
BTOTMCRZ BTUSTC
[R/W] B [R/W] B
7777777 0 70707070
BTUPCSR/BTUPRLL BTOPDUT’BTUPRLH/BTUDTBF
[ww] H [R/W] H
00000000 00000000 00000000 00000000
000(chH , 1 , , 1 ,
BT1TMR[R] H BTlTMCR[R/W] H
00000000 00000000 70000000 00000000
BTITMCR2 BTlSTC
[R/W] B [R/W] B
7777777 0 70707070
BTlPCSR/BTIPRLL BTlPDUT’BTlPRLH/BTIDTBF
[ww] H [R/W] H
00000000 00000000 00000000 00000000
BTSEL()][R/W] B BTSSSR[W] EH
""0000 77777777777777 1 1
0000A0
1
0000FcH
DataSheet
76 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
• MB91F585LB/F586LB/F587LB/F585LD/F586LD/F587LD
Address
Address offset value/Register name
Block
+0
+1
+2
+3
000000H
PDR00[R/W]
B,H,W
XXXXXXXX
PDR01[R/W]
B,H,W
XXXXXXXX
PDR02[R/W]
B,H,W
XXXXXXXX
PDR03[R/W]
B,H,W
XXXXXXXX
Port data register
000004H
PDR04[R/W]
B,H,W
XXXXXXXX
PDR05[R/W]
B,H,W
XXXXXXXX
PDR06[R/W]
B,H,W
XXXXXXXX
PDR07[R/W]
B,H,W
XXXXXXXX
000008H
PDR08[R/W]
B,H,W
XXXXXXXX
PDR09[R/W]
B,H,W
XXXXXXXX
PDR10[R/W]
B,H,W
XXXXXXXX
PDR11[R/W]
B,H,W
XXXXXXXX
00000CH
PDR12[R/W]
B,H,W
XXXXXXXX
PDR13[R/W]
B,H,W
XX-XXXXX
- -
000010
H
|
000038H
- - - - Reserved
00003CH
WDTCR0[R/W]
B,H,W
-0--0000
WDTCPR0[W]
B,H,W
00000000
WDTCR1[R]
B,H,W
----0010
WDTCPR1[W]
B,H,W
00000000
Watchdog timer
[S]
000040H
-
-
-
-
Reserved
000044H
DICR[R/W] B
-------0
- - - Delay interrupt
000048
H
|
00005CH
- - Reserved
000060H
TMRLRA0[R/W] H
XXXXXXXX XXXXXXXX
TMR0[R] H
XXXXXXXX XXXXXXXX
Reload timer 0
000064H
TMRLRB0[R/W] H
XXXXXXXX XXXXXXXX
TMCSR0[R/W] B,H,W
00000000 0-000000
000068
H
|
00007CH
- - - - Reserved
000080H
BT0TMR[R] H
00000000 00000000
BT0TMCR[R/W] H
-0000000 00000000
Base timer 0
000084H
BT0TMCR2
[R/W] B
-------0
BT0STC
[R/W] B
-0-0-0-0
- -
000088H
BT0PCSR/BT0PRLL
[R/W] H
00000000 00000000
BT0PDUT/BT0PRLH/BT0DTBF
[R/W] H
00000000 00000000
00008CH
-
-
-
-
000090H
BT1TMR[R] H
00000000 00000000
BT1TMCR[R/W] H
-0000000 00000000
Base timer 1
000094H
BT1TMCR2
[R/W] B
-------0
BT1STC
[R/W] B
-0-0-0-0
- -
000098H
BT1PCSR/BT1PRLL
[R/W] H
00000000 00000000
BT1PDUT/BT1PRLH/BT1DTBF
[R/W] H
00000000 00000000
00009CH
BTSEL01[R/W] B
----0000
-
BTSSSR[W] B,H
-------- ------11
Base timer 0, 1
0000A0
H
|
0000FCH
- - - - Reserved
/'\
S PIX N S I()r!
‘
3 Address offset value/Register name
+0 ‘ +1 +2 ‘ +3
TMRLRA][R/W] H TMR][R] H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
TMRLRBI[K w] H TMCSR1[R/W] B,H,W
XXXXXXXX XXXXXXXX 00000000 07000000
TMRLRA2[R/W] H TMR2[R] H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
TMRLRB2[K w] H TMCSRZ[R/W] B,H,W
XXXXXXXX XXXXXXXX 00000000 07000000
TMRLRA3[R/w] H TMR3[R] H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
TMRLRB3[K w] H TMCSR3[R/W] B,H,W
XXXXXXXX XXXXXXXX 00000000 07000000
000118
\
00011cH
IRPROH[R]B,H,W IRPROL[R]B,H,W IRPR1H[R]B,H,W IRPR1L[R]B,H,W
00 777777 00m 00 77777777777777
IRPR2H[R]B,H,W IRPR2L[R]B,H,W IRPR3H[R]B,H,W IRPR3L[R]B,H,W
77777777 0000"" 00mm 00mm
IRPR4H[R]B,H,W IRPR4L[R]B,H,W IRPR5H[R]B,H,W IRPR5L[R]B,H,W
00 777777 000000" 00 777777 00 777777
IRPR6H[R]B,H,W IRPR6L[R]B,H,W IRPR7H[R]B,H,W IRPR7L[R]B,H,W
000000" 000000" 000000" 000000"
IRPR8H[R]B,H,W IRPR8L[R]B,H,W IRPR9H[R]B,H,W IRPR9L[R]B,H,W
000000" 00m 00 777777 00 777777
IRPRIOH[R] IRPR10L[R] IRPR11H[R] IRPR11L[R]
B.H,W B,H,w B,H,W st
00 777777 00 ,, 0000000
IRPRIZH[R] IRPR12L[R] 1RPR13H[R] lRPR]3L[R]
B.H,W B,H,w B,H,W B,H,W
0000000 00000000 00000000 00000000
IRPR14H[R] IRPRI4L[R] lRPR15H[R] 1RPR15L[R]
B.H,W B,H,w B,H,W B,H,W
00 777777 00 00000000 000007"
IRPRI6H[R] IRPR16L[R] lRPR17H[R] lRPR17L[R]
B.H,W B,H,w B,H w B,H w
00 777777 00 007 ,, 007 ,,
IRPR18H[R] IRPR18L[R]
B.H,W B,H,w
00 777777 000000"
000148
\
000 chH
PCN()[R/W] B,H,w
00000000 0000000
PCSR()[W] H,w
xxxxxxxx xxxxxxxx
PDUTU[W] H,w
xxxxxxxx xxxxxxxx
PTMRO[R] H,w
1111111111111111
PCN1[R/W] B,H,w
00000000 0000000
PCSR1[W] H,w
xxxxxxxx xxxxxxxx
PDUT1[W] H,w
xxxxxxxx xxxxxxxx
PTMRI[R] H,w
1111111111111111
PCNZ[R/W] B,H,w
00000000 0000000
PCSRZ[W] H,w
xxxxxxxx xxxxxxxx
PDUT2[W] H,w
xxxxxxxx xxxxxxxx
PTMR2[R] H,w
1111111111111111
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 77
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
000100H
TMRLRA1[R/W] H
XXXXXXXX XXXXXXXX
TMR1[R] H
XXXXXXXX XXXXXXXX
Reload timer 1
000104H
TMRLRB1[R/W] H
XXXXXXXX XXXXXXXX
TMCSR1[R/W] B,H,W
00000000 0-000000
000108H
TMRLRA2[R/W] H
XXXXXXXX XXXXXXXX
TMR2[R] H
XXXXXXXX XXXXXXXX
Reload timer 2
00010CH
TMRLRB2[R/W] H
XXXXXXXX XXXXXXXX
TMCSR2[R/W] B,H,W
00000000 0-000000
000110H
TMRLRA3[R/W] H
XXXXXXXX XXXXXXXX
TMR3[R] H
XXXXXXXX XXXXXXXX
Reload timer 3
000114H
TMRLRB3[R/W] H
XXXXXXXX XXXXXXXX
TMCSR3[R/W] B,H,W
00000000 0-000000
000118
H
|
00011CH
- - - - Reserved
000120H
IRPR0H[R] B,H,W
00------
IRPR0L[R] B,H,W
00------
IRPR1H[R] B,H,W
00------
IRPR1L[R] B,H,W
--------
Interrupt request
batch read
register
000124H
IRPR2H[R] B,H,W
--------
IRPR2L[R] B,H,W
0000----
IRPR3H[R] B,H,W
00------
IRPR3L[R] B,H,W
00------
000128H
IRPR4H[R] B,H,W
00------
IRPR4L[R] B,H,W
000000--
IRPR5H[R] B,H,W
00------
IRPR5L[R] B,H,W
00------
00012CH
IRPR6H[R] B,H,W
000000--
IRPR6L[R] B,H,W
000000--
IRPR7H[R] B,H,W
000000--
IRPR7L[R] B,H,W
000000--
000130H
IRPR8H[R] B,H,W
000000--
IRPR8L[R] B,H,W
00------
IRPR9H[R] B,H,W
00------
IRPR9L[R] B,H,W
00------
000134H
IRPR10H[R]
B,H,W
00------
IRPR10L[R]
B,H,W
00------
IRPR11H[R]
B,H,W
00------
IRPR11L[R]
B,H,W
0000000-
000138H
IRPR12H[R]
B,H,W
0000000-
IRPR12L[R]
B,H,W
00000000
IRPR13H[R]
B,H,W
00000000
IRPR13L[R]
B,H,W
00000000
00013CH
IRPR14H[R]
B,H,W
00------
IRPR14L[R]
B,H,W
00------
IRPR15H[R]
B,H,W
00000000
IRPR15L[R]
B,H,W
00000---
000140 H
IRPR16H[R]
B,H,W
00------
IRPR16L[R]
B,H,W
00------
IRPR17H[R]
B,H,W
00------
IRPR17L[R]
B,H,W
00------
000144 H
IRPR18H[R]
B,H,W
00------
IRPR18L[R]
B,H,W
000000--
- -
000148
H
|
0001FCH
- - - - Reserved
000200H
PCN0[R/W] B,H,W
00000000 000000-0
PCSR0[W] H,W
XXXXXXXX XXXXXXXX
PPG0
000204H
PDUT0[W] H,W
XXXXXXXX XXXXXXXX
PTMR0[R] H,W
11111111 11111111
000208H
PCN1[R/W] B,H,W
00000000 000000-0
PCSR1[W] H,W
XXXXXXXX XXXXXXXX
PPG1
00020CH
PDUT1[W] H,W
XXXXXXXX XXXXXXXX
PTMR1[R] H,W
11111111 11111111
000210H
PCN2[R/W] B,H,W
00000000 000000-0
PCSR2[W] H,W
XXXXXXXX XXXXXXXX
PPG2
000214H
PDUT2[W] H,W
XXXXXXXX XXXXXXXX
PTMR2[R] H,W
11111111 11111111
/\
SPANSION
‘
Address offset value/Register name
+0 ‘ +1
+2 ‘ +3
PCN3[R/W] B,H,w
00000000 0000000
PCSR3[W] H,w
xxxxxxxx xxxxxxxx
PDUT3[W] H,w
xxxxxxxx xxxxxxxx
PTMR3[R] H,w
1111111111111111
PCN4[R/W] B,H,w
00000000 0000000
PCSR4[W] H,w
xxxxxxxx xxxxxxxx
PDUT4[W] H,w
xxxxxxxx xxxxxxxx
PTMR4[R] H,w
1111111111111111
PCNS[R/W] B,H,w
00000000 0000000
PCSRS[W] H,w
xxxxxxxx xxxxxxxx
PDUT5[W] H,w
xxxxxxxx xxxxxxxx
PTMR5[R] H,w
1111111111111111
PCN6[R/W] B,H,w
00000000 0000000
PCSR6[W] H,w
xxxxxxxx xxxxxxxx
PDUT6[W] H,w
xxxxxxxx xxxxxxxx
PTMR6[R] H,w
1111111111111111
PCN7[R/W] B,H,w
00000000 0000000
PCSR7[W] H,w
xxxxxxxx xxxxxxxx
PDUT7[W] H,w
xxxxxxxx xxxxxxxx
PTMR7[R] H,w
1111111111111111
PCN8[R/W] B,H,w
00000000 0000000
PCSR8[W] H,w
xxxxxxxx xxxxxxxx
PDUTX[W] H,w
xxxxxxxx xxxxxxxx
PTMR8[R] H,w
1111111111111111
PCN9[R/W] B,H,w
00000000 0000000
PCSR9[W] H,w
xxxxxxxx xxxxxxxx
PDUT9[W] H,w
xxxxxxxx xxxxxxxx
PTMR9[R] H,w
1111111111111111
PCN](J[R/W] B,H,w
00000000 0000000
PCSR10[W] H,w
xxxxxxxx xxxxxxxx
PDUTIU[W] H.W
xxxxxxxx xxxxxxxx
PTMRIO[R] H,w
1111111111111111
PCN 1 l [R w] B,H,W
00000000 0000000
PCSRll[W] H,w
xxxxxxxx xxxxxxxx
PDUTll[W] H,w
xxxxxxxx xxxxxxxx
PTMR]1[R] H,w
1111111111111111
PCN]2[R/W] B,H,w
00000000 0000000
PCSR12[W] H,w
xxxxxxxx xxxxxxxx
PDUT12[W] H.W
xxxxxxxx xxxxxxxx
PTMRIZ[R] H,w
1111111111111111
PCN]3[R/W] B,H,w
00000000 0000000
PCSR13[W] H,w
xxxxxxxx xxxxxxxx
PDUT13[W] H.W
xxxxxxxx xxxxxxxx
PTMR13[R] H,w
1111111111111111
PCN]4[R/W] B,H,w
00000000 0000000
PCSR14[W] H,w
xxxxxxxx xxxxxxxx
PDUT14[W] H.W
xxxxxxxx xxxxxxxx
PTMR14[R] H,w
1111111111111111
PCN]5[R/W] B,H,w
00000000 0000000
PCSR15[W] H,w
xxxxxxxx xxxxxxxx
PDUT15[W] H.W
xxxxxxxx xxxxxxxx
PTMRIS[R] H,w
1111111111111111
DataSheet
78 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
000218H
PCN3[R/W] B,H,W
00000000 000000-0
PCSR3[W] H,W
XXXXXXXX XXXXXXXX
PPG3
00021CH
PDUT3[W] H,W
XXXXXXXX XXXXXXXX
PTMR3[R] H,W
11111111 11111111
000220H
PCN4[R/W] B,H,W
00000000 000000-0
PCSR4[W] H,W
XXXXXXXX XXXXXXXX
PPG4
000224H
PDUT4[W] H,W
XXXXXXXX XXXXXXXX
PTMR4[R] H,W
11111111 11111111
000228H
PCN5[R/W] B,H,W
00000000 000000-0
PCSR5[W] H,W
XXXXXXXX XXXXXXXX
PPG5
00022CH
PDUT5[W] H,W
XXXXXXXX XXXXXXXX
PTMR5[R] H,W
11111111 11111111
000230H
PCN6[R/W] B,H,W
00000000 000000-0
PCSR6[W] H,W
XXXXXXXX XXXXXXXX
PPG6
000234H
PDUT6[W] H,W
XXXXXXXX XXXXXXXX
PTMR6[R] H,W
11111111 11111111
000238H
PCN7[R/W] B,H,W
00000000 000000-0
PCSR7[W] H,W
XXXXXXXX XXXXXXXX
PPG7
00023CH
PDUT7[W] H,W
XXXXXXXX XXXXXXXX
PTMR7[R] H,W
11111111 11111111
000240H
PCN8[R/W] B,H,W
00000000 000000-0
PCSR8[W] H,W
XXXXXXXX XXXXXXXX
PPG8
000244H
PDUT8[W] H,W
XXXXXXXX XXXXXXXX
PTMR8[R] H,W
11111111 11111111
000248H
PCN9[R/W] B,H,W
00000000 000000-0
PCSR9[W] H,W
XXXXXXXX XXXXXXXX
PPG9
00024CH
PDUT9[W] H,W
XXXXXXXX XXXXXXXX
PTMR9[R] H,W
11111111 11111111
000250H
PCN10[R/W] B,H,W
00000000 000000-0
PCSR10[W] H,W
XXXXXXXX XXXXXXXX
PPG10
000254H
PDUT10[W] H,W
XXXXXXXX XXXXXXXX
PTMR10[R] H,W
11111111 11111111
000258H
PCN11[R/W] B,H,W
00000000 000000-0
PCSR11[W] H,W
XXXXXXXX XXXXXXXX
PPG11
00025CH
PDUT11[W] H,W
XXXXXXXX XXXXXXXX
PTMR11[R] H,W
11111111 11111111
000260H
PCN12[R/W] B,H,W
00000000 000000-0
PCSR12[W] H,W
XXXXXXXX XXXXXXXX
PPG12
000264H
PDUT12[W] H,W
XXXXXXXX XXXXXXXX
PTMR12[R] H,W
11111111 11111111
000268H
PCN13[R/W] B,H,W
00000000 000000-0
PCSR13[W] H,W
XXXXXXXX XXXXXXXX
PPG13
00026CH
PDUT13[W] H,W
XXXXXXXX XXXXXXXX
PTMR13[R] H,W
11111111 11111111
000270H
PCN14[R/W] B,H,W
00000000 000000-0
PCSR14[W] H,W
XXXXXXXX XXXXXXXX
PPG14
000274H
PDUT14[W] H,W
XXXXXXXX XXXXXXXX
PTMR14[R] H,W
11111111 11111111
000278H
PCN15[R/W] B,H,W
00000000 000000-0
PCSR15[W] H,W
XXXXXXXX XXXXXXXX
PPG15
00027CH
PDUT15[W] H,W
XXXXXXXX XXXXXXXX
PTMR15[R] H,W
11111111 11111111
/'\
S PA N 5 IO N
‘
3 Address offset value/Register name
+0 ‘ +1 +2 ‘ +3
PCN]6[R/W] B,H,w PCSR16[W] H,w
00000000 0000000 XXXXXXXX XXXXXXXX
PDUT16[W] H.w PTMR16[R] H,w
XXXXXXXXXXXXXXXX 1111111111111111
PCN]7[R/W] B,H,w PCSR17[W] H,w
00000000 0000000 XXXXXXXX XXXXXXXX
PDUT17[W] H.w PTMRI7[R] H,w
XXXXXXXXXXXXXXXX 1111111111111111
PCle[R/w] B,H,w PCSR18[W] H,w
00000000 0000000 XXXXXXXX XXXXXXXX
PDUTIXDV] H.w PTMR18[R] H,w
XXXXXXXXXXXXXXXX 1111111111111111
PCN]9[R/W] B,H,w PCSR19[W] H,w
00000000 0000000 XXXXXXXX XXXXXXXX
PDUT19[W] H.w PTMR19[R] H,w
XXXXXXXXXXXXXXXX 1111111111111111
PCN2(J[R/W] B,H,w PCSRZ()[W] H,w
00000000 0000000 XXXXXXXX XXXXXXXX
PDUT20[w] H.w PTMR20[R] H,w
XXXXXXXXXXXXXXXX 1111111111111111
PCN21[R/W] B,H,w PCSR21[W] H,w
00000000 0000000 XXXXXXXX XXXXXXXX
PDUT21[w] H.w PTMR21[R] H,w
XXXXXXXXXXXXXXXX 1111111111111111
PCN22[R/W] B,H,w PCSRZZ[W] H,w
00000000 0000000 XXXXXXXX XXXXXXXX
PDUT22[w] H.w PTMR22[R] H,w
XXXXXXXXXXXXXXXX 1111111111111111
PCN23[R/W] B,H,w PCSRZ3[W] H,w
00000000 0000000 XXXXXXXX XXXXXXXX
PDUT23[W] H.w PTMR23[R] H,w
XXXXXXXXXXXXXXXX 1111111111111111
GTRS(J[R/W] B,H.w GTRS l [R w] B,H,w
70000000 70000000 70000000 70000000
GTRSZ[R/W] B,H.w GTRS}[K w] B,H,w
70000000 70000000 70000000 70000000
GTRSAUVW] B,H.w GTRSS[K w] B,H,w
70000000 70000000 70000000 70000000
(iTRSfi[R/W] B,H.w GTRS7[K w] B,H,w
70000000 70000000 70000000 70000000
GTRsx[R/w] B,H.w GTRS‘)[K w] B,H,w
70000000 70000000 70000000 70000000
GTRSIO[R/w] B,H,w (iTRSll[R’W] B,H,w
70000000 70000000 70000000 70000000
GTREN(J[R/W] H,w GTREN l [R w] H,w
00000000 00000000 77777777 00000000
0002DCH , , Reserved
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 79
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
000280H
PCN16[R/W] B,H,W
00000000 000000-0
PCSR16[W] H,W
XXXXXXXX XXXXXXXX
PPG16
000284H
PDUT16[W] H,W
XXXXXXXX XXXXXXXX
PTMR16[R] H,W
11111111 11111111
000288H
PCN17[R/W] B,H,W
00000000 000000-0
PCSR17[W] H,W
XXXXXXXX XXXXXXXX
PPG17
00028CH
PDUT17[W] H,W
XXXXXXXX XXXXXXXX
PTMR17[R] H,W
11111111 11111111
000290H
PCN18[R/W] B,H,W
00000000 000000-0
PCSR18[W] H,W
XXXXXXXX XXXXXXXX
PPG18
000294H
PDUT18[W] H,W
XXXXXXXX XXXXXXXX
PTMR18[R] H,W
11111111 11111111
000298H
PCN19[R/W] B,H,W
00000000 000000-0
PCSR19[W] H,W
XXXXXXXX XXXXXXXX
PPG19
00029CH
PDUT19[W] H,W
XXXXXXXX XXXXXXXX
PTMR19[R] H,W
11111111 11111111
0002A0H
PCN20[R/W] B,H,W
00000000 000000-0
PCSR20[W] H,W
XXXXXXXX XXXXXXXX
PPG20
0002A4H
PDUT20[W] H,W
XXXXXXXX XXXXXXXX
PTMR20[R] H,W
11111111 11111111
0002A8H
PCN21[R/W] B,H,W
00000000 000000-0
PCSR21[W] H,W
XXXXXXXX XXXXXXXX
PPG21
0002ACH
PDUT21[W] H,W
XXXXXXXX XXXXXXXX
PTMR21[R] H,W
11111111 11111111
0002B0H
PCN22[R/W] B,H,W
00000000 000000-0
PCSR22[W] H,W
XXXXXXXX XXXXXXXX
PPG22
0002B4H
PDUT22[W] H,W
XXXXXXXX XXXXXXXX
PTMR22[R] H,W
11111111 11111111
0002B8H
PCN23[R/W] B,H,W
00000000 000000-0
PCSR23[W] H,W
XXXXXXXX XXXXXXXX
PPG23
0002BCH
PDUT23[W] H,W
XXXXXXXX XXXXXXXX
PTMR23[R] H,W
11111111 11111111
0002C0H
GTRS0[R/W] B,H,W
-0000000 -0000000
GTRS1[R/W] B,H,W
-0000000 -0000000
PPG Control
0002C4H
GTRS2[R/W] B,H,W
-0000000 -0000000
GTRS3[R/W] B,H,W
-0000000 -0000000
0002C8H
GTRS4[R/W] B,H,W
-0000000 -0000000
GTRS5[R/W] B,H,W
-0000000 -0000000
0002CCH
GTRS6[R/W] B,H,W
-0000000 -0000000
GTRS7[R/W] B,H,W
-0000000 -0000000
0002D0H
GTRS8[R/W] B,H,W
-0000000 -0000000
GTRS9[R/W] B,H,W
-0000000 -0000000
0002D4H
GTRS10[R/W] B,H,W
-0000000 -0000000
GTRS11[R/W] B,H,W
-0000000 -0000000
0002D8H
GTREN0[R/W] H,W
00000000 00000000
GTREN1[R/W] H,W
-------- 00000000
0002DCH
-
-
Reserved
/\
5 PA N 5 IO N
‘
3 Address offset value/Register name
+0 +1 +2 +3
GATECU[R’W] GATECZ[R/W]
B H,w B,H,w
, 00 ,, JU
GATEC4[R’W] GATEC8[R/W]
B H,w B,H,w
, 00 ,, JU
GATECIU[R’W] GATEClZ[R/W]
B H,w B,H w
, 00 J0
0002ECH , , , , Reserved
RCRH()[W] RCRL0[w] UDCRH()[R] UDCRLO[R]
H,w B,H,w PLW B,H,w
00000000 00000000 00000000 00000000
CCRU[R’W] 3.1-1 CSR0[R] B
00000000 70001000 00000000
RCRH1[W] RCRLI[W] UDCRH1[R] UDCRLI[R]
H,w B,H,w PLW B,H,w
00000000 00000000 00000000 00000000
CCR1[R’W] 3.1-1 CSRl[R] B
00000000 70001000 00000000
000300H , Reserved
000304H , \ , , \ , Reserved
000308H ,
00030cH , , , \ ,
MPUCR[R/w] H
0000000 ""0100
000314H , , , \ ,
000318H ,
00031cH , , \ ,
DPVAR[R] w
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DPVSR[R/W] H
,,,,,,,, 00000~0
DEAR[R] w
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DESR[R w] H
,,,,,,,, 00000~0
PABRU[R’W] w
XXXXXXXX XXXXXXXX XXXXXXXX XXXXOOOU
PAC R(J[R/W] H
00000070 000000
PABRI [R’W] w
XXXXXXXX XXXXXXXX XXXXXXXX XXXXOOOU
PAC R 1 [WW] H
00000070 000000
PABR2[R’W] w
XXXXXXXX XXXXXXXX XXXXXXXX XXXXOOOU
PAC R2[R/w] H
00000070 000000
PABR3[R’W] w
XXXXXXXX XXXXXXXX XXXXXXXX XXXXOOOU
PAC R3 [R/W] H
00000070 000000
PABR4[R’W] w
XXXXXXXX XXXXXXXX XXXXXXXX XXXXOOOU
DataSheet
80 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
0002E0H -
GATEC0[R/W]
B,H,W
------00
-
GATEC2[R/W]
B,H,W
------00
PPG GATE
Control
0002E4H -
GATEC4[R/W]
B,H,W
------00
-
GATEC8[R/W]
B,H,W
------00
0002E8H -
GATEC10[R/W]
B,H,W
------00
-
GATEC12[R/W]
B,H,W
------00
0002ECH
-
-
-
-
Reserved
0002F0H
RCRH0[W]
H,W
00000000
RCRL0[W]
B,H,W
00000000
UDCRH0[R]
H,W
00000000
UDCRL0[R]
B,H,W
00000000
U/D counter 0
0002F4H
CCR0[R/W] B,H
00000000 -0001000
-
CSR0[R] B
00000000
0002F8H
RCRH1[W]
H,W
00000000
RCRL1[W]
B,H,W
00000000
UDCRH1[R]
H,W
00000000
UDCRL1[R]
B,H,W
00000000
U/D counter 1
0002FCH
CCR1[R/W] B,H
00000000 -0001000
-
CSR1[R] B
00000000
000300H
-
Reserved
000304H
-
-
-
-
Reserved
000308H
-
Reserved
00030CH
-
-
-
-
000310H - -
MPUCR[R/W] H
000000-0 ----0100
MPU [S]
(Only the CPU
can access this
area)
000314H
-
-
-
-
000318H
-
00031CH
-
-
-
000320H
DPVAR[R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000324H - -
DPVSR[R/W] H
-------- 00000--0
000328H
DEAR[R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00032CH - -
DESR[R/W] H
-------- 00000--0
000330H
PABR0[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
000334H - -
PACR0[R/W] H
000000-0 00000--0
000338H
PABR1[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
00033CH - -
PACR1[R/W] H
000000-0 00000--0
000340H
PABR2[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
000344H - -
PACR2[R/W] H
000000-0 00000--0
000348H
PABR3[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
00034CH - -
PACR3[R/W] H
000000-0 00000--0
000350H
PABR4[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
/'\
5 PA N 5 IO N
‘
s Address offset value/Register name
+0 +1 +2 ‘ +3
PACR4[R/W] H
0000000 000000
PABR5[R’W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000
PACR5[R/W] H
0000000 000000
PABR6[R’W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000
PACR6[R/W] H
0000000 000000
PABR7[R’W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000
PACR7[R/W] H
0000000 000000
000370H W
000374H W \ W \ W
000378H W
00037cH W \ W \ W
000380H W
000384H W \ W \ W
000388H W
()0038CH W \ W \ W
000390H W
000394H W \ W \ W
000398H W
00039cH W \ W \ W
0003A0H W
0003MH W \ W \ W
UUUZAXH W
0003AcH W W W
0003130
\
000chH
lCSELDataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 81
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
000354H - -
PACR4[R/W] H
000000-0 00000--0
MPU [S]
(Only the CPU
can access this
area)
000358H
PABR5[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
00035CH - -
PACR5[R/W] H
000000-0 00000--0
000360H
PABR6[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
000364H - -
PACR6[R/W] H
000000-0 00000--0
000368H
PABR7[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
00036CH - -
PACR7[R/W] H
000000-0 00000--0
000370H
-
Reserved [S]
000374H
-
-
-
000378H
-
00037CH
-
-
-
000380H
-
000384H
-
-
-
000388H
-
00038CH
-
-
-
000390H
-
000394H
-
-
-
Reserved [S]
000398H
-
00039CH
-
-
-
0003A0H
-
0003A4H
-
-
-
0003A8H
-
0003ACH
-
-
-
0003B0
H
|
0003FCH
- - - - Reserved [S]
000400H
ICSEL0[R/W]
B,H,W
-----000
ICSEL1[R/W]
B,H,W
-------0
ICSEL2[R/W]
B,H,W
-------0
ICSEL3[R/W]
B,H,W
-------0
Generation and
clearing of DMA
transfer requests
000404H
ICSEL4[R/W]
B,H,W
-------0
ICSEL5[R/W]
B,H,W
-------0
ICSEL6[R/W]
B,H,W
-------0
ICSEL7[R/W]
B,H,W
-----000
000408H
ICSEL8[R/W]
B,H,W
-------0
ICSEL9[R/W]
B,H,W
-------0
ICSEL10[R/W]
B,H,W
-----000
ICSEL11[R/W]
B,H,W
-----000
00040CH
ICSEL12[R/W]
B,H,W
-----000
ICSEL13[R/W]
B,H,W
-----000
ICSEL14[R/W]
B,H,W
-----000
ICSEL15[R/W]
B,H,W
-------0
000410H
ICSEL16[R/W]
B,H,W
-------0
ICSEL17[R/W]
B,H,W
-------0
ICSEL18[R/W]
B,H,W
-------0
ICSEL19[R/W]
B,H,W
-------0
/\
5 PA N 5 IO N
‘
3 Address offset value/Register name
+0 +1 +2 +3
lCSEL2(J[R/W] ICSELZ 1 [WW] ICSEL22[K w] ICSEL23[K w]
B.1-1,W B,1—1,w B,H,w B,H,w
, 70 W 7000 7000 000
ICSEL24[R/w] ICSEL25[R/W] ICSEL26[K w] ICSEL27[K w] "“1
B.1-1,W B,1—1,w B,H v B,H v A
77777 000 ""7000
00041cH , , , ,
000420H , , , ,
000424
1
00043cH
lCR()()[R/W] 1CR01 [R w] ICRUZ[K w] ICRDataSheet
82 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
000414H
ICSEL20[R/W]
B,H,W
-------0
ICSEL21[R/W]
B,H,W
-----000
ICSEL22[R/W]
B,H,W
-----000
ICSEL23[R/W]
B,H,W
-----000
Generation and
clearing of DMA
transfer requests
000418H
ICSEL24[R/W]
B,H,W
-----000
ICSEL25[R/W]
B,H,W
-----000
ICSEL26[R/W]
B,H,W
-------0
ICSEL27[R/W]
B,H,W
-------0
00041CH
-
-
-
-
000420H
-
-
-
-
000424
H
|
00043CH
- - - - Reserved
000440H
ICR00[R/W]
B,H,W
---11111
ICR01[R/W]
B,H,W
---11111
ICR02[R/W]
B,H,W
---11111
ICR03[R/W]
B,H,W
---11111
Interrupt
controller [S]
000444H
ICR04[R/W]
B,H,W
---11111
ICR05[R/W]
B,H,W
---11111
ICR06[R/W]
B,H,W
---11111
ICR07[R/W]
B,H,W
---11111
000448H
ICR08[R/W]
B,H,W
---11111
ICR09[R/W]
B,H,W
---11111
ICR10[R/W]
B,H,W
---11111
ICR11[R/W]
B,H,W
---11111
00044CH
ICR12[R/W]
B,H,W
---11111
ICR13[R/W]
B,H,W
---11111
ICR14[R/W]
B,H,W
---11111
ICR15[R/W]
B,H,W
---11111
000450H
ICR16[R/W]
B,H,W
---11111
ICR17[R/W]
B,H,W
---11111
ICR18[R/W]
B,H,W
---11111
ICR19[R/W]
B,H,W
---11111
000454H
ICR20[R/W]
B,H,W
---11111
ICR21[R/W]
B,H,W
---11111
ICR22[R/W]
B,H,W
---11111
ICR23[R/W]
B,H,W
---11111
000458H
ICR24[R/W]
B,H,W
---11111
ICR25[R/W]
B,H,W
---11111
ICR26[R/W]
B,H,W
---11111
ICR27[R/W]
B,H,W
---11111
00045CH
ICR28[R/W]
B,H,W
---11111
ICR29[R/W]
B,H,W
---11111
ICR30[R/W]
B,H,W
---11111
ICR31[R/W]
B,H,W
---11111
000460H
ICR32[R/W]
B,H,W
---11111
ICR33[R/W]
B,H,W
---11111
ICR34[R/W]
B,H,W
---11111
ICR35[R/W]
B,H,W
---11111
000464H
ICR36[R/W]
B,H,W
---11111
ICR37[R/W]
B,H,W
---11111
ICR38[R/W]
B,H,W
---11111
ICR39[R/W]
B,H,W
---11111
000468H
ICR40[R/W]
B,H,W
---11111
ICR41[R/W]
B,H,W
---11111
ICR42[R/W]
B,H,W
---11111
ICR43[R/W]
B,H,W
---11111
00046CH
ICR44[R/W]
B,H,W
---11111
ICR45[R/W]
B,H,W
---11111
ICR46[R/W]
B,H,W
---11111
ICR47[R/W]
B,H,W
---11111
000470
H
|
00047CH
- - - - Reserved [S]
/'\
S PA N 5 IO N
‘
s Address offset value/Register name
+0 +1 +2 +3
Rcscl eomrol [S]
Power
eonsumpxion
comm] [S]
* Writing to
STBCR by
DMA is
disabled.
000484H , , , , Reserved [S]
D1VRO[R/w] D1VR1 [R w] DIVR2[R/W]
BJ—LW B,1—1,w B,H,w
000 77777 0001"" 001 1
00048cH , , , , Reserved [S]
10RRO[R/W] 10RR1[R/w] 10RR2[R w] 1()RR3[R’W]
BJ—LW B,1—1,w B,H,w B,H,w
0000000 70000000 70000000 70000000
10RR4[R/W] IURRS[R/W] I()RR6[K w] 1()RR7[R’W]
BJ—LW B,1—1,w B,H,w B,H,w
0000000 70000000 70000000 70000000
000498H , , , ,
000chH , , , ,
0004A0H , , , , Reserved
CANPRE[R w]
BJ—LW
""0000
UUUAAX
1
0004ACH
0004130H , , , , Reserved
000434
1
0004C0H
CUCRI [R w] B.H,W CUTD1[R’W] B,1—1,w
77777777 "0700 11000011 01010000
CUTR][R] B,H,w
00000000 00000000 00000000
(J(J(J4CC
1
0004DCH
CSCF(}[K w] CMCFG[K w]
B,H,w B,H,w
W0 00000000
0004134H , , , ,
PLL2D1VM[R/w] PLL2D1VN[R/w] PLL2D1VG[R w] PLLZMULG[R/W]
BJ—LW B,1—1,w B,H,w B,H,w
""0000 70000000 ""0000 00000000
PLL2CTRL[R w] PLL2D1VK[R/w] CLKR2[R’W]
BJ—LW B 1-1,w B,H,w
""0000 000000
0004F0
1
0004KH
000500H , Reserved
000504H , Reserved
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 83
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
000480H
RSTRR[R]
B,H,W
XXXX--XX
RSTCR[R/W]
B,H,W
111----0
STBCR[R/W]
B,H,W*
000---11
-
Reset control [S]
Power
consumption
control [S]
* Writing to
STBCR by
DMA is
disabled.
000484H
-
-
-
-
Reserved [S]
000488H
DIVR0[R/W]
B,H,W
000-----
DIVR1[R/W]
B,H,W
0001----
DIVR2[R/W]
B,H,W
0011----
- Clock control
[S]
00048CH
-
-
-
-
Reserved [S]
000490H
IORR0[R/W]
B,H,W
-0000000
IORR1[R/W]
B,H,W
-0000000
IORR2[R/W]
B,H,W
-0000000
IORR3[R/W]
B,H,W
-0000000
DMA transfer
request from a
peripheral [S]
000494H
IORR4[R/W]
B,H,W
-0000000
IORR5[R/W]
B,H,W
-0000000
IORR6[R/W]
B,H,W
-0000000
IORR7[R/W]
B,H,W
-0000000
000498H
-
-
-
-
00049CH
-
-
-
-
0004A0H
-
-
-
-
Reserved
0004A4H
CANPRE[R/W]
B,H,W
----0000
- - - CAN prescaler
0004A8
H
|
0004ACH
- - - - Reserved
0004B0H
-
-
-
-
Reserved
0004B4
H
|
0004C0H
- - - - Reserved
0004C4H
CUCR1[R/W] B,H,W
-------- ---0--00
CUTD1[R/W] B,H,W
11000011 01010000
WDT1
calibration
0004C8H
CUTR1[R] B,H,W
-------- 00000000 00000000 00000000
0004CC
H
|
0004DCH
- - - - Reserved
0004E0H - -
CSCFG[R/W]
B,H,W
---0----
CMCFG[R/W]
B,H,W
00000000
Clock monitor
0004E4H
-
-
-
-
0004E8H
PLL2DIVM[R/W]
B,H,W
----0000
PLL2DIVN[R/W]
B,H,W
-0000000
PLL2DIVG[R/W]
B,H,W
----0000
PLL2MULG[R/W]
B,H,W
00000000
FlexRay clock
control
0004ECH
PLL2CTRL[R/W]
B,H,W
----0000
PLL2DIVK[R/W]
B,H,W
-------0
CLKR2[R/W]
B,H,W
000--000
-
0004F0
H
|
0004FCH
- - - - Reserved
000500H
-
Reserved
000504H
-
Reserved
/\
5 PA N 5 IO N
‘
s Address offset value/Register name
+0 +1 +2 +3
000508
\
00050cH
CSELR[K w] CM()NR[R] MTMCR[R/W]
BJ—LW B,H,w B,H,w
r0~~00 r01m00 00001 1 1 1
CSTBR[K w] PTMCR[R’W]
B,H,w B,H w
""0000
CPUAR[R/W]
B,H,w
Umxxxx
cH -
CCPSSELR[R’W] CCPSDIVR[K w]
BJ—LW B,H,w
, ,0 70007000
CCPLLFBR[R/W] CCSSFBR()[R/W] CCSSFBR1[R/W]
B,H,w B,H,w B,H,w
70000000 "000000 "700000
CCSSCCRO[K w]
B,H,w
""0000
CCCGRCRU[R’W] CCCGRCR1[R/W] CCCGRCRZUUW]
B,H,w B,H,w B,H,w
00~~00 00000000 00000000
CCPMUCRDataSheet
84 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
000508
H
|
00050CH
- - - - Reserved
000510H
CSELR[R/W]
B,H,W
-0----00
CMONR[R]
B,H,W
-01---00
MTMCR[R/W]
B,H,W
00001111
-
Clock control
[S]
000514H
PLLCR[R/W] B,H,W
00-00000 11110000
CSTBR[R/W]
B,H,W
----0000
PTMCR[R/W]
B,H,W
00------
000518H - -
CPUAR[R/W]
B,H,W
0---XXXX
- Reset [S]
00051CH
-
-
-
-
Reserved [S]
000520H
CCPSSELR[R/W]
B,H,W
-------0
- -
CCPSDIVR[R/W]
B,H,W
-000-000
Clock control 2
000524H -
CCPLLFBR[R/W]
B,H,W
-0000000
CCSSFBR0[R/W]
B,H,W
--000000
CCSSFBR1[R/W]
B,H,W
---00000
000528H -
CCSSCCR0[R/W]
B,H,W
----0000
CCSSCCR1[R/W] H,W
000----- --------
00052CH -
CCCGRCR0[R/W]
B,H,W
00----00
CCCGRCR1[R/W]
B,H,W
00000000
CCCGRCR2[R/W]
B,H,W
00000000
000530H - -
CCPMUCR0[R/W]
B,H,W
0-----00
CCPMUCR1[R/W]
B,H,W
0--00000
000534H
-
-
-
-
000538H
-
-
-
-
00053CH
-
-
-
-
000540
H
|
00054CH
- - - - Reserved
000550H
EIRR0[R/W]
B,H,W
XXXXXXXX
ENIR0[R/W]
B,H,W
00000000
ELVR0[R/W] B,H,W
00000000 00000000
External
interrupt
(INT0 to 7)
000554
H
|
000568H
- - - - Reserved
00056CH -
CSVCR[R/W] B
-0--1--0
- - CSV
000570H
CRTR[R/W]
B,H,W 01111111 - - -
WDT1
calibration
(trimming)
000574
H
|
00057CH
- - - - Reserved
000580H
REGSEL[R/W]
B,H,W
01--110-
- - - Regulator
control
000584H
LV D 5 R[ R /W]
B,H,W
-------1
LVD5F[R/W]
B,H,W
0-010--1
LVD[R/W]
B,H,W
01000--0
- Low-voltage
detection
/'\
S PA N 5 IO N
‘
s Address offset value/Register name
+0 +1 +2 +3
000588
1
()OOSXCH
PMUSTR[R/W] PMUCTLR[R’W] PWRTMCTL[R/W]
B.1-1,W B,1—1,W B,H,W
0 "IX 0700"" W 7011
PMUlNTFl[R/W] PMUINTFZ[R/W]
B,1—1,W B,H,W
00000000 7007""
000598H , , , ,
00059cH , , , ,
0005A0
1
UUUSFCH
ASRO[K w] W
00000000 00000000 77777777 1 111001
ASRl [R w] W
xxxxxxxx xxxxxxxx 77777777 XXXXVXXO
ASR2[K w] W
xxxxxxxx xxxxxxxx 77777777 XXXXVXXO
ASR3[K w] W
xxxxxxxx xxxxxxxx , XXXXVXXO
000610
1
00063cH
ACRO[R/W] W
000650
1
00067cH
AWRO[K w] W
1 1 1 00000000 1 1 1 10000 000000
AWRl [R w] W
rmxxxx xxxxxxxx xxxxxxxx XXXXXVXV
AWR2[K w] W
rmxxxx xxxxxxxx xxxxxxxx XXXXXVXV
AWR3[K w] W
rmxxxx xxxxxxxx xxxxxxxx XXXXXVXV
000690
1
000613cH
DMARO[R/W] w
""0000
DMAR] [R/W] w
""0000
DMAR2[R/W] w
""0000
DMAR3[R/W] w
""0000
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 85
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
000588
H
|
00058CH
- - - - Reserved
000590H
PMUSTR [R/W]
B,H,W
0-----1X
PMUCTLR[R/W]
B,H,W
0-00----
PWRTMCTL[R/W]
B,H,W
-----011
-
PMU
000594H -
PMUINTF1[R/W]
B,H,W
00000000
PMUINTF2[R/W]
B,H,W
-00-----
-
000598H
-
-
-
-
00059CH
-
-
-
-
0005A0
H
|
0005FCH
- - - - Reserved
000600H
ASR0[R/W] W
00000000 00000000 -------- 1111-001
External bus
interface [S]
000604H
ASR1[R/W] W
XXXXXXXX XXXXXXXX -------- XXXX-XX0
000608H
ASR2[R/W] W
XXXXXXXX XXXXXXXX -------- XXXX-XX0
00060CH
ASR3[R/W] W
XXXXXXXX XXXXXXXX -------- XXXX-XX0
000610
H
|
00063CH
- - - - Reserved[S]
000640H
ACR0[R/W] W
-------- -------- -------- 00--00--
External bus
interface [S]
000644H
ACR1[R/W] W
-------- -------- -------- XX--XX--
000648H
ACR2[R/W] W
-------- -------- -------- XX--XX--
00064CH
ACR3[R/W] W
-------- -------- -------- XX--XX--
000650
H
|
00067CH
- - - - Reserved[S]
000680H
AWR0[R/W] W
----1111 00000000 11110000 00000-0-
External bus
interface [S]
000684H
AWR1[R/W] W
----XXXX XXXXXXXX XXXXXXXX XXXXX-X-
000688H
AWR2[R/W] W
----XXXX XXXXXXXX XXXXXXXX XXXXX-X-
00068CH
AWR3[R/W] W
----XXXX XXXXXXXX XXXXXXXX XXXXX-X-
000690
H
|
0006BCH
- - - - Reserved[S]
0006C0H
DMAR0[R/W] W
-------- -------- -------- ----0000
External bus
interface [S]
0006C4H
DMAR1[R/W] W
-------- -------- -------- ----0000
0006C8H
DMAR2[R/W] W
-------- -------- -------- ----0000
0006CCH
DMAR3[R/W] W
-------- -------- -------- ----0000
/\
SPANSION
‘
S
Address offset value/Register name
+0 +1 +2 +3
0006DDataSheet
86 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
0006D0
H
|
0006F0H
- - - - Reserved
0006F4H
-
Reserved
0006F8
H
|
0006FCH
- - - - Reserved
000700H
-
Reserved
000704
H
|
00070CH
- - - - Reserved
000710H
BPCCRA[R/W] B
00000000
BPCCRB[R/W] B
00000000
BPCCRC[R/W] B
00000000
-
Bus performance
counter
000714H
BPCTRA[R/W] W
00000000 00000000 00000000 00000000
000718H
BPCTRB[R/W] W
00000000 00000000 00000000 00000000
00071CH
BPCTRC[R/W] W
00000000 00000000 00000000 00000000
000720
H
|
0007F8H
- - - - Reserved
0007FCH
BMODR[R] B,H,W
XXXXXXXX
- - - Operation mode
000800
H
|
00083CH
- - - - Reserved [S]
000840H
FCTLR[R/W] H
-0--1000 0--0----
-
FSTR[R/W] B
-----001
Flash memory
register [S]
000844H
-
-
-
-
Reserved [S]
000848
H
|
000854H
- - - - Reserved [S]
000858H - -
WREN[R/W] H
00000000 00000000
Wild register [S]
00085C
H
|
00087CH
- - - - Reserved [S]
000880H
WRAR00[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
Wild register [S]
000884H
WRDR00[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000888H
WRAR01[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
00088CH
WRDR01[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000890H
WRAR02[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
000894H
WRDR02[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000898H
WRAR03[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
00089CH
WRDR03[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
/'\
SPANSION
‘
Address offset value/Register name
+0 ‘ +1 ‘ +2 ‘ +3
WRARDataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 87
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
0008A0H
WRAR04[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
Wild register [S]
0008A4H
WRDR04[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008A8H
WRAR05[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008ACH
WRDR05[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008B0H
WRAR06[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008B4H
WRDR06[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008B8H
WRAR07[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008BCH
WRDR07[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008C0H
WRAR08[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008C4H
WRDR08[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008C8H
WRAR09[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008CCH
WRDR09[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008D0H
WRAR10[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008D4H
WRDR10[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008D8H
WRAR11[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008DCH
WRDR11[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008E0H
WRAR12[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008E4H
WRDR12[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008E8H
WRAR13[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008ECH
WRDR13[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008F0H
WRAR14[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008F4H
WRDR14[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008F8H
WRAR15[R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008FCH
WRDR15[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000900
H
|
000BF8H
- - - - Reserved
000BFCH - -
UER[W] B,H,W
-------- -------X
OCDU
/\
SPANSION
‘
Address offset value/Register name
\ +1 \ +2 \ +3
DCCRU[R’W] w
0~~000 ~00~00 00000000 07000000
DCSRO[R w] H DTCRO[R w] H
00000000 00000000
DSAR()[R/W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
DDARU[R’W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
DCCR1[R’W] w
0~~000 ~00~00 00000000 07000000
DCSRI [R w] H DTCRI [R w] H
00000000 00000000
DSAR1[R/W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
DDAR1[R’W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
DCCRZUUW] w
0~~000 ~00~00 00000000 07000000
DCSR2[R w] H DTCR2[R w] H
00000000 00000000
DSAR2[R/W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
DDAR2[R’W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
DCCRSUUW] w
0~~000 ~00~00 00000000 07000000
DCSR3[R w] H DTCR3[R w] H
00000000 00000000
DSAR3[R/W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
DDAR3[R’W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
DCCR4[R’W] w
0~~000 ~00~00 00000000 07000000
DCSR4[R w] H DTCR4[R w] H
00000000 00000000
DSAR4[R/W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
DDAR4[R’W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
DCCR5[R’W] w
0~~000 ~00~00 00000000 07000000
DCSR5[R w] H DTCR5[R w] H
0" ""7000 0000000000000000
DSARS[R/W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
DDAR5[R’W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
DCCR6[R’W] w
0~~000 ~00~00 00000000 07000000
DCSR6[R w] H DTCR6[R w] H
00000000 00000000
DSAR6[R/W] w
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
DataSheet
88 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
000C00H
DCCR0[R/W] W
0----000 --00--00 00000000 0-000000
DMA
controller [S]
000C04H
DCSR0[R/W] H
0------- -----000
DTCR0[R/W] H
00000000 00000000
000C08H
DSAR0[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C0CH
DDAR0[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C10H
DCCR1[R/W] W
0----000 --00--00 00000000 0-000000
000C14H
DCSR1[R/W] H
0------- -----000
DTCR1[R/W] H
00000000 00000000
000C18H
DSAR1[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C1CH
DDAR1[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C20H
DCCR2[R/W] W
0----000 --00--00 00000000 0-000000
000C24H
DCSR2[R/W] H
0------- -----000
DTCR2[R/W] H
00000000 00000000
000C28H
DSAR2[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C2CH
DDAR2[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C30H
DCCR3[R/W] W
0----000 --00--00 00000000 0-000000
000C34H
DCSR3[R/W] H
0------- -----000
DTCR3[R/W] H
00000000 00000000
000C38H
DSAR3[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C3CH
DDAR3[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C40H
DCCR4[R/W] W
0----000 --00--00 00000000 0-000000
000C44H
DCSR4[R/W] H
0------- -----000
DTCR4[R/W] H
00000000 00000000
000C48H
DSAR4[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C4CH
DDAR4[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C50H
DCCR5[R/W] W
0----000 --00--00 00000000 0-000000
000C54H
DCSR5[R/W] H
0------- -----000
DTCR5[R/W] H
00000000 00000000
000C58H
DSAR5[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C5CH
DDAR5[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C60H
DCCR6[R/W] W
0----000 --00--00 00000000 0-000000
000C64H
DCSR6[R/W] H
0------- -----000
DTCR6[R/W] H
00000000 00000000
000C68H
DSAR6[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
/'\
SPANSION
Address offset value/Register name
+0 ‘ +1 ‘ +2 ‘ +3
DDAR6[R’W] w
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DCCR7[R’W] w
07777000 77007700 00000000 07000000
DCSR7[R w] H DTCR7[R w] H
U 777777777777 000 00000000 00000000
DSAR7[R/W] w
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDAR7[R’W] w
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000CXU
\
000DF0H
DNMIR[R/W] B DILVR[R/W] B
7771 1 l l 1
ooqucH , , , , Reserved [S]
DDRuo[R w] B,H DDRUl [R’W] B.H DDR()Z[R/W] BJ—I DDR()3[R/W] BJ—I
00000000 00000000 00000000 00000000
DDR04[R w] B,H DDRUS[R’W] B.H DDR()6[R/W] BJ—I DDR()7[R/W] BJ—I
00000000 00000000 00000000 00000000
DDR08[K w] B,H DDRU9[R’W] B.H DDR1()[R/W] BJ—I DDR11[R’W]B.H
00000000 00000000 00000000 00000000
DDR12[R w] B,H DDR13[R’W] B.H
00000000 00700000
0001310
\
000E1CH
PFRUU[R’W] B.H PFRDataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 89
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
000C6CH
DDAR6[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DMA
controller [S]
000C70H
DCCR7[R/W] W
0----000 --00--00 00000000 0-000000
000C74H
DCSR7[R/W] H
0------- -----000
DTCR7[R/W] H
00000000 00000000
000C78H
DSAR7[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C7CH
DDAR7[R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C80
H
|
000DF0H
- - - -
000DF4H - -
DNMIR[R/W] B
0------0
DILVR[R/W] B
---11111
000DF8H
DMACR[R/W] W
0------- -------- 0------- --------
000DFCH
-
-
-
-
Reserved [S]
000E00H
DDR00[R/W] B,H
00000000
DDR01[R/W] B,H
00000000
DDR02[R/W] B,H
00000000
DDR03[R/W] B,H
00000000
Data direction
register
000E04H
DDR04[R/W] B,H
00000000
DDR05[R/W] B,H
00000000
DDR06[R/W] B,H
00000000
DDR07[R/W] B,H
00000000
000E08H
DDR08[R/W] B,H
00000000
DDR09[R/W] B,H
00000000
DDR10[R/W] B,H
00000000
DDR11[R/W] B,H
00000000
000E0CH
DDR12[R/W] B,H
00000000
DDR13[R/W] B,H
00-00000
- -
000E10
H
|
000E1CH
- - - - Reserved
000E20H
PFR00[R/W] B,H
00000000
PFR01[R/W] B,H
00000000
PFR02[R/W] B,H
00000000
PFR03[R/W] B,H
00000000
Port function
register
000E24H
PFR04[R/W] B,H
00000000
PFR05[R/W] B,H
00000000
PFR06[R/W] B,H
00000000
PFR07[R/W] B,H
00000000
000E28H
PFR08[R/W] B,H
00000000
PFR09[R/W] B,H
00000000
PFR10[R/W] B,H
00000000
PFR11[R/W] B,H
00000000
000E2CH
PFR12[R/W] B,H
00000000
PFR13[R/W] B,H
00-00000
- -
000E30
H
|
000E3CH
- - - - Reserved
000E40H
PDDR00[R]
B,H,W
XXXXXXXX
PDDR01[R]
B,H,W
XXXXXXXX
PDDR02[R]
B,H,W
XXXXXXXX
PDDR03[R]
B,H,W
XXXXXXXX
Input data direct
read register
000E44H
PDDR04[R]
B,H,W
XXXXXXXX
PDDR05[R]
B,H,W
XXXXXXXX
PDDR06[R]
B,H,W
XXXXXXXX
PDDR07[R]
B,H,W
XXXXXXXX
000E48H
PDDR08[R]
B,H,W
XXXXXXXX
PDDR09[R]
B,H,W
XXXXXXXX
PDDR10[R]
B,H,W
XXXXXXXX
PDDR11[R]
B,H,W
XXXXXXXX
000E4CH
PDDR12[R]
B,H,W
XXXXXXXX
PDDR13[R]
B,H,W
XX-XXXXX
- -
000E50
H
|
000E5CH
- - - - Reserved
/\
5 PA N 5 IO N
‘
3 Address offset value/Register name
+0 +1 +2 +3
EPFRUU[R’W]B.H EPFR01[R/w] 13,1-1 EPFR02[R/W]B,H EPFR03[KW]B,H
77777 000 ""7700 "000000 00000000
EPFRU4[R’W]B.H EPFR05[R/w] 13,1-1 EPFR06[R/W]B,H EPFRO7[KW]B,H
00000000 00000000 WW00 ""0000
EPFRUX[R’W]B.H EPFR09[R/w] 13,1-1 EPFR10[R/W]B,H EPFR]1[R’W]B.H
0000 , 0 00000000 000
EPFR]3[R/ ]B,1—1 EPFR14[R/W]B,H EPFRIS[KW]B,H
W1 70000000 70000000
EPFR16[R’W]B.H EPFR17[R/W]B,1-1 EPFR18[R/W]B,H EPFRI9[KW]B,H
”000000 00000000 00000000 00000000
EPFRZU[R’W]B.H EPFR21[R/W] 13,1-1 EPFR22[R/W]B,H EPFR23[KW]B,H
00000000 00000000 00000000 00000000
EPFR24[R’W]B.H EPFR25[R/W] 13,1-1 EPFR26[R/W]B,H EPFR27[KW]B,H
00000000 00000000 00000000 00000000
EPFRZX[R’W]B.H EPFR29[R/w] 13,1-1 EPFR30[R/W]B,H EPFR3l[KW]B,H
00000000 00000000 00000000 00000000
EPFR32[R’W] 13.1-1
00000000
0001384
1
000E13CH
PPEROO[R’W]B.H PPER01[R/W]B,1-1 PPER02[R/W]B,H PPER03[KW]B,H
00000000 00000000 00000000 00000000
PPERO4[R’W]B.H PPER05[R/w] 13,1-1 PPER05[R/W]B,H PPER()7[KW]B,H
00000000 00000000 00000000 00000000
PPEROX[R’W]B.H PPERU9[R/W] 13,1-1 PPER10[R/W]B,H PPER11[R’W]B.H
00000000 00000000 00000000 00000000
PPERIZUUW] 13.1-1 PPER13[R/W] 13,1-1
00000000 00700000
000EDO
1
000EDCH
PILRDataSheet
90 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
000E60H
EPFR00[R/W] B,H
-----000
EPFR01[R/W] B,H
------00
EPFR02[R/W] B,H
--000000
EPFR03[R/W] B,H
00000000
Extended port
function register
000E64H
EPFR04[R/W] B,H
00000000
EPFR05[R/W] B,H
00000000
EPFR06[R/W] B,H
------00
EPFR07[R/W] B,H
----0000
000E68H
EPFR08[R/W] B,H
----0000
EPFR09[R/W] B,H
-------0
EPFR10[R/W] B,H
00000000
EPFR11[R/W] B,H
----0000
000E6CH -
EPFR13[R/W] B,H
-------1
EPFR14[R/W] B,H
-0000000
EPFR15[R/W] B,H
-0000000
000E70H
EPFR16[R/W] B,H
--000000
EPFR17[R/W] B,H
00000000
EPFR18[R/W] B,H
00000000
EPFR19[R/W] B,H
00000000
000E74H
EPFR20[R/W] B,H
00000000
EPFR21[R/W] B,H
00000000
EPFR22[R/W] B,H
00000000
EPFR23[R/W] B,H
00000000
000E78H
EPFR24[R/W] B,H
00000000
EPFR25[R/W] B,H
00000000
EPFR26[R/W] B,H
00000000
EPFR27[R/W] B,H
00000000
000E7CH
EPFR28[R/W] B,H
00000000
EPFR29[R/W] B,H
00000000
EPFR30[R/W] B,H
00000000
EPFR31[R/W] B,H
00000000
000E80H
EPFR32[R/W] B,H
00000000
- - -
000E84
H
|
000EBCH
- - - - Reserved
000EC0H
PPER00[R/W] B,H
00000000
PPER01[R/W] B,H
00000000
PPER02[R/W] B,H
00000000
PPER03[R/W] B,H
00000000
Port
pull-up/down
enable register
000EC4H
PPER04[R/W] B,H
00000000
PPER05[R/W] B,H
00000000
PPER06[R/W] B,H
00000000
PPER07[R/W] B,H
00000000
000EC8H
PPER08[R/W] B,H
00000000
PPER09[R/W] B,H
00000000
PPER10[R/W] B,H
00000000
PPER11[R/W] B,H
00000000
000ECCH
PPER12[R/W] B,H
00000000
PPER13[R/W] B,H
00-00000
- -
000ED0
H
|
000EDCH
- - - - Reserved
000EE0H
PILR00[R/W] B,H
11111111
PILR01[R/W] B,H
11111111
PILR02[R/W] B,H
11111111
PILR03[R/W] B,H
11111111
Port input level
selection register
000EE4H
PILR04[R/W] B,H
11111111
PILR05[R/W] B,H
11111111
PILR06[R/W] B,H
11111111
PILR07[R/W] B,H
11111111
000EE8H
PILR08[R/W] B,H
11111111
PILR09[R/W] B,H
11111111
PILR10[R/W] B,H
11111111
PILR11[R/W] B,H
11111111
000EECH
PILR12[R/W] B,H
11111111
PILR13[R/W] B,H
11-11111
- -
000EF0
H
|
000EFCH
- - - - Reserved
000F00
H
|
000F1CH
- - - - Reserved
/'\
S PA N 5 IO N
‘
3 Address offset value/Register name
+0 +1 +2 +3
P()DR()(J[R/W] P()DR01[R/w] PODRUZ[K w] PODR03[R/w]
13,11 13,11 B,H B,H
00000000 00000000 00000000 00000000
P<)dr04[r ]="" p()dr05[r/w]="" podr06[k="" w]="" podru7[r1w]="" 13,11="" 13,11="" b,h="" b,h="" 00000000="" 00000000="" 00000000="" 00000000=""><)drox[r ]="" p()dr09[r/w]="" podr10[k="" w]="" 1-1="" 13,11="" 13,11="" b,h="" 00000000="" 00000000="" 00000000="" p()dr12[r/w]="" p()dr13[r/w]="" 13,11="" 13,11="" 00000000="" 00700000="" ()(j(jf3u="" 1="" 000cmh="" porten[r="" w]="" b.1-1,w="" ,="" ~00="" keycdr[k="" w]="" 1-1="" 00000000="" 00000000="" aderh[r/w]="" b,h="" aderl[r/w]="" b,h="" analog="" inpm="" 77777777="" 11111111="" 1111111111111111="" cnablcrcgismr="" daer[r="" w]13.1-1="" analog="" ompul="" 7777777="" 0="" enable="" rcgismr="" 000f511="" 1="" 000ffch="" sacr[k="" w]="" plcd[r/w]="" synchronous/my="" b.1-1,w="" b,1—1,w="" nchronous="" ,="" ,0="" ""0011="" swimh="" control="" 001004="" 1="" 001013ch="" crccr[r/w]="" b,h,w="" 70000000="" crcinit[r1w]="" b.1-1,w="" 11111111111111111111111111111111="" crc1n[k="" w]="" b,h,w="" 00000000="" 00000000="" 00000000="" 00000000="" crcr[r]="" b.h,w="" 11111111111111111111111111111111="" 0010d0="" 1="" 0010fch="" tcgs[r/w]="" tcgseuuw]="" freermn="" 1imcr="" b.1-1,w="" b,h,w="" simunancou="" ,="" 00="" "000000="" activation="" cpclrbu’cpc="" llllllll="" lr(j[r’w]="" 1-1,w="" 11111111="" tcdtu[r1w]="" 1-1.w="" 00000000="" 00000000="" tccs(j[r/w]="" 13,1-1,w="" uuuuuuuu="" u="" [000000="" ""0000="" "7="">DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 91
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
000F20H
PODR00[R/W]
B,H
00000000
PODR01[R/W]
B,H
00000000
PODR02[R/W]
B,H
00000000
PODR03[R/W]
B,H
00000000
Port output drive
register
000F24H
PODR04[R/W]
B,H
00000000
PODR05[R/W]
B,H
00000000
PODR06[R/W]
B,H
00000000
PODR07[R/W]
B,H
00000000
000F28H
PODR08[R/W]
B,H
00000000
PODR09[R/W]
B,H
00000000
PODR10[R/W]
B,H
00000000
PODR11[R/W] B,H
00000000
000F2CH
PODR12[R/W]
B,H
00000000
PODR13[R/W]
B,H
00-00000
- -
000F30
H
|
000F3CH
- - - - Reserved
000F40H
PORTEN[R/W]
B,H,W
------00
- - -
Port input enable
register
000F44H
KEYCDR[R/W] H
00000000 00000000
- - Port key code
000F48H
ADERH[R/W] B,H
-------- 11111111
ADERL[R/W] B,H
11111111 11111111
Analog input
enable register
000F4CH
DAER[R/W] B,H
-------0
- - -
Analog output
enable register
000F50
H
|
000FFCH
- - - - Reserved
001000H
SACR[R/W]
B,H,W
-------0
PICD[R/W]
B,H,W
----0011
- -
Synchronous/asy
nchronous
switch control
001004
H
|
0010BCH
- - - - Reserved
0010C0H - - -
CRCCR[R/W]
B,H,W
-0000000
CRC arithmetic
operation
0010C4H
CRCINIT[R/W] B,H,W
11111111 11111111 11111111 11111111
0010C8H
CRCIN[R/W] B,H,W
00000000 00000000 00000000 00000000
0010CCH
CRCR[R] B,H,W
11111111 11111111 11111111 11111111
0010D0
H
|
0010FCH
- - - - Reserved
001100H
TCGS[R/W]
B,H,W
------00
- -
TCGSE[R/W]
B,H,W
--000000
Free-run timer
simultaneous
activation
001104H
CPCLRB0/CPCLR0[R/W] H,W
11111111 11111111
TCDT0[R/W] H,W
00000000 00000000
Free-run timer 0
001108H
TCCS0[R/W] B,H,W
00000000 01000000 ----0000 --------
/\
SPANSION
‘
Address offset value/Register name
+0 ‘ +1
+2 ‘ +3
CPCLRBI ’CPCLR] [R’W] H,W
llllllll llllllll
TCDT1[R’W] H.W
00000000 00000000
TCCS] [R/W
]B,H,w
UUUUUUUU U lUUOUUO ""0000 "r w
CPCLRBZ’CPCLR2[R’W] H,W
llllllll llllllll
TCDTZUUW] H.W
00000000 00000000
chsz[R/w
]B,H,w
UUUUUUUU U lUUOUUO ""0000 "r w
CPCLRBB’CPCLR3[R’W] H,W
llllllll llllllll
TCDT3[R’W] H.W
00000000 00000000
chssmw
]B,H,w
UUUUUUUU U lUUOUUO ""0000 "r w
CPCLRB4’CPCLR4[R’W] H,W
llllllll llllllll
TCDT4[R’W] H.W
00000000 00000000
chs4[R/w
]B,H,w
UUUUUUUU U lUUOUUO ""0000 "r w
CPCLRBS’CPCLR5[R’W] H,W
llllllll llllllll
TCDT5[R’W] H.W
00000000 00000000
TCCSS[R/W] B,H,w
UUUUUUUU U lUUOUUO ,
0000 "7
FRSO[K w] B,H,w
rUUOr00U 70007000 rUUUr000
FRS l [R w] B,H,w
*7 rUUUr000 70007000
FRSZ[K w] B,H,w
*7 rUUOr00U 70007000 rUUUr000
FRS}[K w] B,H,w
*7 rUUUr000 70007000
FR54[K w] B,H,w
70007000 70007000 70007000 70007000
FRSS[K w] B,H,w
70007000 70007000 70007000 70007000
FRSé[K w] B,H,w
70007000 70007000 70007000 70007000
00115UH
0CCPB0,0CCPU[R’W] H,W
UUUOUUOU UOUUOUUO
()CCPBl/()CCP1[R/W] H,W
00000000 00000000
()CMOD01[R/W]
B,H,w
00
0CCPB2,0CCP2[R’W] H,W
UUUOUUOU UOUUOUUO
()CCPBS/()CCP3[R/W] H,W
00000000 00000000
()CMOD23[R/W]
B,H,w
00
0CCPB4,0CCP4[R’W] H,W
UUUOUUOU UOUUOUUO
()CCPBS/()CCPS[R/W] H,W
00000000 00000000
()CMOD45[R/W]
B,H,w
JU
0CCPB6,0CCP6[R’W] H,W
UUUOUUOU UOUUOUUO
()CCPB7/()CCP7[R/W] H,W
00000000 00000000
()CMOD67[R/W]
B,H,w
00
DataSheet
92 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
00110CH
CPCLRB1/CPCLR1[R/W] H,W
11111111 11111111
TCDT1[R/W] H,W
00000000 00000000
Free-run timer 1
001110H
TCCS1[R/W] B,H,W
00000000 01000000 ----0000 --------
001114H
CPCLRB2/CPCLR2[R/W] H,W
11111111 11111111
TCDT2[R/W] H,W
00000000 00000000
Free-run timer 2
001118H
TCCS2[R/W] B,H,W
00000000 01000000 ----0000 --------
00111CH
CPCLRB3/CPCLR3[R/W] H,W
11111111 11111111
TCDT3[R/W] H,W
00000000 00000000
Free-run timer 3
001120H
TCCS3[R/W] B,H,W
00000000 01000000 ----0000 --------
001124H
CPCLRB4/CPCLR4[R/W] H,W
11111111 11111111
TCDT4[R/W] H,W
00000000 00000000
Free-run timer 4
001128H
TCCS4[R/W] B,H,W
00000000 01000000 ----0000 --------
00112CH
CPCLRB5/CPCLR5[R/W] H,W
11111111 11111111
TCDT5[R/W] H,W
00000000 00000000
Free-run timer 5
001130H
TCCS5[R/W] B,H,W
00000000 01000000 ----0000 --------
001134H
FRS0[R/W] B,H,W
-------- -000-000 -000-000 -000-000
Free-run timer
selection
001138H
FRS1[R/W] B,H,W
-------- -------- -000-000 -000-000
00113CH
FRS2[R/W] B,H,W
-------- -000-000 -000-000 -000-000
001140H
FRS3[R/W] B,H,W
-------- -------- -000-000 -000-000
001144H
FRS4[R/W] B,H,W
-000-000 -000-000 -000-000 -000-000
001148H
FRS5[R/W] B,H,W
-000-000 -000-000 -000-000 -000-000
00114CH
FRS6[R/W] B,H,W
-000-000 -000-000 -000-000 -000-000
001150H
-
001154H
OCCPB0/OCCP0[R/W] H,W
00000000 00000000
OCCPB1/OCCP1[R/W] H,W
00000000 00000000
Output compare
0/1
001158H
OCS01[R/W] B,H,W
-110--00 00001100 -
OCMOD01[R/W]
B,H,W
------00
00115CH
OCCPB2/OCCP2[R/W] H,W
00000000 00000000
OCCPB3/OCCP3[R/W] H,W
00000000 00000000
Output compare
2/3
001160H
OCS23[R/W] B,H,W
-110--00 00001100 -
OCMOD23[R/W]
B,H,W
------00
001164H
OCCPB4/OCCP4[R/W] H,W
00000000 00000000
OCCPB5/OCCP5[R/W] H,W
00000000 00000000
Output compare
4/5
001168H
OCS45[R/W] B,H,W
-110--00 00001100 -
OCMOD45[R/W]
B,H,W
------00
00116CH
OCCPB6/OCCP6[R/W] H,W
00000000 00000000
OCCPB7/OCCP7[R/W] H,W
00000000 00000000
Output compare
6/7
001170H
OCS67[R/W] B,H,W
-110--00 00001100 -
OCMOD67[R/W]
B,H,W
------00
/'\
SPANSION
‘
Address offset value/Register name
+0 +1
+2 ‘ +3
0CCPB8,0CCPX[R’W] H,W
00000000 00000000
()CCPB9/()CCP9[R/W] H,W
00000000 00000000
()CMOD89[R/W]
B,1—1,w
r00
()CCPB l0,0CCPlU[R’W] H.W
00000000 00000000
OCCPBll/()CCP1][R/W] H,W
00000000 00000000
0cs101 1[R’W]
13,1-1,w
7110770000001100
OCMOD 1 01 1
R/W] 13,1-1.
lPCPU[R] 1-1,w
00000000 00000000
IPCP1[R] 1-1.,w
00000000 00000000
1cso1 [R/W]
13,1-1,w
777777 00 00000000
LSYNS[R’W]
B,1—1,w
"700000
lPCP2[R] 1-1,w
00000000 00000000
IPCP3[R] 1-1.,w
00000000 00000000
ICSZ3[R/W] BJ-LW
777777 00 00000000
lPCP4[R] 1-1,w
00000000 00000000
IPCPS[R] 1-1.,w
00000000 00000000
1c345[R/W] BJ-LW
777777 00 00000000
lPCP6[R] 1-1,w
00000000 00000000
IPCP7[R] 1-1.,w
00000000 00000000
ICS67[R/W] BJ-LW
777777 00 00000000
DTSR[R/W]
13.1-1,w
~10
TMRRO[R/W] 1-1,w
00000000 00000001
TMRRI [K w]1-1,w
00000000 00000001
TMRR2[R/W] 1-1,w
00000000 00000001
DTSCRO[K w] DTSCR1[R’W] DTSCR2[R/W]
B.1—1,w 13,1-1,w B,1—1,w
00000000 00000000 00000000
DT1R0[K w] DTMNSO[K w]
13,1-1,w B,1—1,w
000000" 00777000
SlGCRlU[R’W] SIGCR20[R/W]
13,1-1,w B,1—1,w
00000000 0000004
PICSU[R’W]
00000
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 93
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
001174H
OCCPB8/OCCP8[R/W] H,W
00000000 00000000
OCCPB9/OCCP9[R/W] H,W
00000000 00000000
Output compare
8/9
001178H
OCS89[R/W] B,H,W
-110--00 00001100 -
OCMOD89[R/W]
B,H,W
------00
00117CH
OCCPB10/OCCP10[R/W] H,W
00000000 00000000
OCCPB11/OCCP11[R/W] H,W
00000000 00000000
Output compare
10/11
001180H
OCS1011[R/W]
B,H,W
-110--00 00001100
-
OCMOD1011
[R/W] B,H,W
------00
001184H
IPCP0[R] H,W
00000000 00000000
IPCP1[R] H,W
00000000 00000000
Input capture 0/1
001188H
ICS01[R/W]
B,H,W
------00 00000000
-
LSYNS[R/W]
B,H,W
---00000
00118CH
IPCP2[R] H,W
00000000 00000000
IPCP3[R] H,W
00000000 00000000
Input capture 2/3
001190H
ICS23[R/W] B,H,W
------00 00000000
- -
001194H
IPCP4[R] H,W
00000000 00000000
IPCP5[R] H,W
00000000 00000000
Input capture 4/5
001198H
ICS45[R/W] B,H,W
------00 00000000
- -
00119CH
IPCP6[R] H,W
00000000 00000000
IPCP7[R] H,W
00000000 00000000
Input capture 6/7
0011A0H
ICS67[R/W] B,H,W
------00 00000000
- -
0011A4H
DTSR[R/W]
B,H,W
------10
- - - DTTI selection
0011A8H
TMRR0[R/W] H,W
00000000 00000001
TMRR1[R/W] H,W
00000000 00000001
Waveform
generator
0/1/2
0011ACH
TMRR2[R/W] H,W
00000000 00000001
- -
0011B0H
DTSCR0[R/W]
B,H,W
00000000
DTSCR1[R/W]
B,H,W
00000000
DTSCR2[R/W]
B,H,W
00000000
-
0011B4H -
DTIR0[R/W]
B,H,W
000000--
-
DTMNS0[R/W]
B,H,W
00---000
0011B8H -
SIGCR10[R/W]
B,H,W
00000000
-
SIGCR20[R/W]
B,H,W
000000-1
0011BCH
PICS0[R/W] B,H,W
000000-- -------- -------- --------
/\
5 PA N 5 IO N
‘
3 Address offset value/Register name
+0 ‘ +1 +2 ‘ +3
TMRR3[R/w] H,w TMRR4[K w] H,w
00000000 00000001 00000000 00000001
TMRR5[R/W] H,w
00000000 00000001
DTSCRzm w] DTSCR4[R’W] DTSCR5[R/W]
BJ—LW B,H,w B,H,w
00000000 00000000 00000000
DTlRl [K w] DTMNS l [K w]
B,H,w B,H,w
000000" 00777000
SI(}CR1][R/W] SIGCR21[R/W]
B,H,w B,H,w
00000000 0000004
PICS] [R’W] H,w
000000”
001 1 Dim , , , ,
ADTSS[R/W]
BJ—LW
, ,0
ADTSE[R’W] B,H,w
"7 00000000 0
0000000 00000000
ADC()MPO/ADC()MPBO[R/W] H,W
00000000 00000000
ADCOMP l/ ADCOMPB1[R’W] H.W
00000000 00000000
ADC()MP2/ADC()MPBZ[R/W] H,W
00000000 00000000
ADCOMPZ/ ADCOMPB3 [R’W] H,W
00000000 00000000
ADC()MP4/ADC()MPB4[R/W] H,W
00000000 00000000
ADCOMPS/ ADCOMPBS [R’W] H.W
00000000 00000000
ADC()MP6/ADC()MPB6[R/W] H,W
00000000 00000000
ADCOMP7/ ADCOMPB7[R’W] H.W
00000000 00000000
ADC()MPX/ADC()MPBX[R/W] H,W
00000000 00000000
ADCOMP‘J/ ADCOMPB9[R’W] H.W
00000000 00000000
ADCOMP l (J/ADCOMPB [MR/W] H.W
00000000 00000000
ADCOMPI l/ADCOMPBI [[R’W] H,W
00000000 00000000
ADCOMP l 2/ADCOMPB [2[R’W] H.W
00000000 00000000
ADCOMP IZ/ADCOMPB l 3 [WW] H,W
00000000 00000000
ADCOMP l 4/ADCOMPB l4[R’W] H.W
00000000 00000000
ADCOMP IS/ADCOMPB l 5 [WW] H,W
00000000 00000000
ADCOMP]6/ADC()MPB16[R’W] H.W
00000000 00000000
ADCOMP l7/ADCOMPB l 7[R/W] H,W
00000000 00000000
ADCOMP] X/ADCOMPB [8[R’W] H.W
00000000 00000000
ADCOMP lg/ADCOMPB l 9[R/W] H,W
00000000 00000000
ADC()MP20/ADC()MPBZO[R’W] H.W
00000000 00000000
ADCOMPZ l/ADCOMPBZI [R/W] H,W
00000000 00000000
ADC()MPZZ/ADCOMPBZZUUW] H.W
00000000 00000000
ADCOMPZLADCOMPBZTfi [R/W] H,W
00000000 00000000
001214H
001212;H
00121cH
001220H
ADTCSO[R/W] BJ—Lw
00000000 00107000
ADTCS l [K w] BJ-Lw
00000000 00107000
ADTCSZ[R/W] BJ—Lw
00000000 00107000
ADTcszm w] BJ-Lw
00000000 00107000
ADTCSAUVW] BJ—Lw
00000000 00107000
ADTcssm w] BJ-Lw
00000000 00107000
DataSheet
94 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
0011C0H
TMRR3[R/W] H,W
00000000 00000001
TMRR4[R/W] H,W
00000000 00000001
Waveform
generator
3/4/5
0011C4H
TMRR5[R/W] H,W
00000000 00000001
- -
0011C8H
DTSCR3[R/W]
B,H,W
00000000
DTSCR4[R/W]
B,H,W
00000000
DTSCR5[R/W]
B,H,W
00000000
-
0011CCH -
DTIR1[R/W]
B,H,W
000000--
-
DTMNS1[R/W]
B,H,W
00---000
0011D0H -
SIGCR11[R/W]
B,H,W
00000000
-
SIGCR21[R/W]
B,H,W
000000-1
0011D4H
PICS1[R/W] B,H,W
000000-- -------- -------- --------
0011D8H
-
-
-
-
12-bit A/D
converter
0011DCH
ADTSS[R/W]
B,H,W
-------0
- - -
0011E0H
ADTSE[R/W] B,H,W
-------- 00000000 00000000 00000000
0011E4H
ADCOMP0/ADCOMPB0[R/W] H,W
00000000 00000000
ADCOMP1/ADCOMPB1[R/W] H,W
00000000 00000000
0011E8H
ADCOMP2/ADCOMPB2[R/W] H,W
00000000 00000000
ADCOMP3/ADCOMPB3[R/W] H,W
00000000 00000000
0011ECH
ADCOMP4/ADCOMPB4[R/W] H,W
00000000 00000000
ADCOMP5/ADCOMPB5[R/W] H,W
00000000 00000000
0011F0H
ADCOMP6/ADCOMPB6[R/W] H,W
00000000 00000000
ADCOMP7/ADCOMPB7[R/W] H,W
00000000 00000000
0011F4H
ADCOMP8/ADCOMPB8[R/W] H,W
00000000 00000000
ADCOMP9/ADCOMPB9[R/W] H,W
00000000 00000000
0011F8H
ADCOMP10/ADCOMPB10[R/W] H,W
00000000 00000000
ADCOMP11/ADCOMPB11[R/W] H,W
00000000 00000000
0011FCH
ADCOMP12/ADCOMPB12[R/W] H,W
00000000 00000000
ADCOMP13/ADCOMPB13[R/W] H,W
00000000 00000000
001200H
ADCOMP14/ADCOMPB14[R/W] H,W
00000000 00000000
ADCOMP15/ADCOMPB15[R/W] H,W
00000000 00000000
001204H
ADCOMP16/ADCOMPB16[R/W] H,W
00000000 00000000
ADCOMP17/ADCOMPB17[R/W] H,W
00000000 00000000
001208H
ADCOMP18/ADCOMPB18[R/W] H,W
00000000 00000000
ADCOMP19/ADCOMPB19[R/W] H,W
00000000 00000000
00120CH
ADCOMP20/ADCOMPB20[R/W] H,W
00000000 00000000
ADCOMP21/ADCOMPB21[R/W] H,W
00000000 00000000
001210H
ADCOMP22/ADCOMPB22[R/W] H,W
00000000 00000000
ADCOMP23/ADCOMPB23[R/W] H,W
00000000 00000000
001214H
-
-
-
-
001218H
-
-
-
-
00121CH
-
-
-
-
001220H
-
-
-
-
001224H
ADTCS0[R/W] B,H,W
00000000 0010-000
ADTCS1[R/W] B,H,W
00000000 0010-000
001228H
ADTCS2[R/W] B,H,W
00000000 0010-000
ADTCS3[R/W] B,H,W
00000000 0010-000
00122CH
ADTCS4[R/W] B,H,W
00000000 0010-000
ADTCS5[R/W] B,H,W
00000000 0010-000
/'\
S PA N 5 IO N
‘
3 Address offset value/Register name
+0 ‘ + 1 +2 ‘ +3
ADTCSfi[R/W] B,1—1.w ADTCS7[K w] B,H,W
00000000 00107000 00000000 00107000
ADTCSX[R/W] B,1—1.w ADTCSum w] B,H,W
00000000 00107000 00000000 00107000
ADTCS](J[R/W] B,1—1.w ADTCS]1[R’W] B.1—1,W
00000000 00107000 00000000 00107000
ADTCS]2[R/W] B,1—1.w ADTCS 13m w]B,1—1,w
00000000 00107000 00000000 00107000
ADTCS]4[R/W] B,1—1.w ADTCS 15m w]B,1—1,w
00000000 00107000 00000000 00107000
ADTCS] 6[R/W] B,1—1.w ADTCS 17m w]B,1—1,w
00000000 00100000 00000000 00100000
ADTCS] x[R/w] B,1—1.w ADTCS 19m w]B,1—1,w
00000000 00100000 00000000 00100000
ADTCSZ(J[R/W] B,1—1.w ADTCSZI[K w] B,H,w
00000000 00100000 00000000 00100000
ADTC822[R/W] B,1—1.w ADTCSZ}[K w] B,H,w
00000000 00100000 00000000 00100000
001254H , , , ,
001258H , , , ,
00125cH , , , ,
00 1 260H , , , ,
ADTCD()[R] B.1—1,W ADTCDl [R] B,1—1.w
100000 00000000 100000 00000000
ADTCDZ[R] B.1—1,W ADTCD3[R] B,1—1.w
100000 00000000 100000 00000000
ADTCD4[R]B.1-1,w ADTCD5[R] B,1—1.w
100000 00000000 100000 00000000
ADTCD6[R] B.1—1,W ADTCD7[R] B,1—1.w
100000 00000000 100000 00000000
ADTCD8[R] B.1—1,W ADTCD9[R] B,1—1.w
100000 00000000 100000 00000000
ADTCD1(J[R] B.H,W ADTCD11[R] B,H,w
100000 00000000 100000 00000000
ADTCD12[R] B.H,W ADTCD13[R] B,1—1.w
100000 00000000 100000 00000000
ADTCD14[R] B.H,W ADTCD15[R] B,1—1.w
100000 00000000 100000 00000000
ADTCD16[R] B.H,W ADTCD17[R] B,1—1.w
100000 00000000 100000 00000000
ADTCD18[R] B.H,W ADTCD19[R] B,1—1.w
100000 00000000 100000 00000000
ADTCDZ(J[R] B.H,W ADTCD21[R] B,1—1.w
100000 00000000 100000 00000000
ADTCD22[R] B.H,W ADTCD23[R] B,1—1.w
100000 00000000 100000 00000000
001294H , , , ,
001298H , , , ,
00129cH , , , ,
0012A0H , , , ,
ADCS()[R/W] ADc1-10[R] ADMD(J[R/W]
B,H,w B,H,w
,, ,000 ""0000
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 95
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
001230H
ADTCS6[R/W] B,H,W
00000000 0010-000
ADTCS7[R/W] B,H,W
00000000 0010-000
12-bit A/D
converter
001234H
ADTCS8[R/W] B,H,W
00000000 0010-000
ADTCS9[R/W] B,H,W
00000000 0010-000
001238H
ADTCS10[R/W] B,H,W
00000000 0010-000
ADTCS11[R/W] B,H,W
00000000 0010-000
00123CH
ADTCS12[R/W] B,H,W
00000000 0010-000
ADTCS13[R/W] B,H,W
00000000 0010-000
001240H
ADTCS14[R/W] B,H,W
00000000 0010-000
ADTCS15[R/W] B,H,W
00000000 0010-000
001244H
ADTCS16[R/W] B,H,W
00000000 00100000
ADTCS17[R/W] B,H,W
00000000 00100000
001248H
ADTCS18[R/W] B,H,W
00000000 00100000
ADTCS19[R/W] B,H,W
00000000 00100000
00124CH
ADTCS20[R/W] B,H,W
00000000 00100000
ADTCS21[R/W] B,H,W
00000000 00100000
001250H
ADTCS22[R/W] B,H,W
00000000 00100000
ADTCS23[R/W] B,H,W
00000000 00100000
001254H
-
-
-
-
001258H
-
-
-
-
00125CH
-
-
-
-
001260H
-
-
-
-
001264H
ADTCD0[R] B,H,W
10--0000 00000000
ADTCD1[R] B,H,W
10--0000 00000000
001268H
ADTCD2[R] B,H,W
10--0000 00000000
ADTCD3[R] B,H,W
10--0000 00000000
00126CH
ADTCD4[R] B,H,W
10--0000 00000000
ADTCD5[R] B,H,W
10--0000 00000000
001270H
ADTCD6[R] B,H,W
10--0000 00000000
ADTCD7[R] B,H,W
10--0000 00000000
001274H
ADTCD8[R] B,H,W
10--0000 00000000
ADTCD9[R] B,H,W
10--0000 00000000
001278H
ADTCD10[R] B,H,W
10--0000 00000000
ADTCD11[R] B,H,W
10--0000 00000000
00127CH
ADTCD12[R] B,H,W
10--0000 00000000
ADTCD13[R] B,H,W
10--0000 00000000
001280H
ADTCD14[R] B,H,W
10--0000 00000000
ADTCD15[R] B,H,W
10--0000 00000000
001284H
ADTCD16[R] B,H,W
10--0000 00000000
ADTCD17[R] B,H,W
10--0000 00000000
001288H
ADTCD18[R] B,H,W
10--0000 00000000
ADTCD19[R] B,H,W
10--0000 00000000
00128CH
ADTCD20[R] B,H,W
10--0000 00000000
ADTCD21[R] B,H,W
10--0000 00000000
001290H
ADTCD22[R] B,H,W
10--0000 00000000
ADTCD23[R] B,H,W
10--0000 00000000
001294H
-
-
-
-
001298H
-
-
-
-
00129CH
-
-
-
-
0012A0H
-
-
-
-
0012A4H
ADCS0[R/W]
B,H,W
0------- --------
ADCH0[R]
B,H,W
-----000
ADMD0[R/W]
B,H,W
----0000
/\
SPANSION
‘
Address offset value/Register name
+1
+2
+3
ADCS 1 [WW]
B H,w
U,
ADCH][R] ADMD][R/W]
B,H,w
B,H,w
*7 ,()()() ""0000
ADcsz[R/w]
ADCH2[R] ADMD2[R/W]
B,H,w
B,H,w
*7 ,()()() ""0000
001230
1
UUlZFCH
U0 1 300“
001304“
001308“
00 1 30CH
001310“
001314“
0013le
00131CH
001320“
001324“
001328“
00132CH
001330“
001334
1
UUIZFCH
DACR[R/W]
BJ—Lw
, ,0
DADR[R/W]
H,w
xx xxxxxxxx
U0 1 404
1
UUl4FCH
DataSheet
96 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
0012A8H
ADCS1[R/W]
B,H,W
0------- --------
ADCH1[R]
B,H,W
-----000
ADMD1[R/W]
B,H,W
----0000
12-bit A/D
converter
0012ACH
ADCS2[R/W]
B,H,W
0------- --------
ADCH2[R]
B,H,W
-----000
ADMD2[R/W]
B,H,W
----0000
0012B0
H
|
0012FCH
- - - - Reserved
001300H
-
-
-
-
Reserved
001304H
-
-
-
-
001308H
-
-
-
-
00130CH
-
-
-
-
001310H
-
-
-
-
001314H
-
-
-
-
001318 H
-
-
-
-
00131CH
-
-
-
-
001320H
-
-
-
-
001324H
-
-
001328H
-
-
-
-
00132CH
-
-
-
-
001330H
-
-
001334
H
|
0013FCH
- - - - Reserved
001400H
DACR[R/W]
B,H,W
-------0
-
DADR[R/W]
H,W
------XX XXXXXXXX
DAC
001404
H
|
0014FCH
- - - - Reserved
/'\
S PA N 5 IO N
\
Address offset value/Register name
+0 +1 +2 +3
SCRO/(IBCRO) SMRO SSRO ESCRU’UBSRO)
R w] B,1-1,w R’W] B.1—1,w R/W] B,1-1.w R/W] B,1-1.w
07700000 0000000 00001 1 00000000
J(RDRI0,[TDR1(J))[R’W] 1-1.w RDR00/(TDR00)[R/w] B,1-1.w
, ,, 77777 0 00000000 '
SAC R()[R/W] B,1—1,w
0777000 00000000
STMRO[R] 13,1-1.w
00000000 00000000
STMCRU[R/W] 13,1-1,w
00000000 00000000
7,1 SFURO) [R w] 13,1-1,w
1 SFLROO) [ww]
13,1-1 v
7,1 SFLRIO) [ww]
13,1-1 w
,, [ISMKO)[K w] ,, [lSBAU)[R/W]
13,1-1,w 13,1-1,w
FCRIU[R’W] FCRUO FBYTEZU FBYTEIO
B.1-1,w va]13.1-1,w R/W] B,1—1.w R/W] B,1—1.w
00700100 70000000 00000000 00000000
SCRl/(IBCRI) SMR1[R’W] 153cm «1133111)
R w] B,1-1,w 13,1-1,w R/W] B,1—1.w
07700000 0000000 00000000
r/(RDRI 1/(TDR1 l))[R/W] 1-1,w RDR01/(TDR01 )[R/W] 13,1-1.w
,, 77777 0 00000000 '
SAC R1[R/W] B,1—1,w
0777000 00000000
STMRI[R] 13,1-1.w
00000000 00000000
STMCR1[R’W]B,H,W
00000000 00000000
r/(SCSCRISFURI) [R/W] B,1—1.w
r/(SCSTRZI) r/(SCSTRZI) r/(SCSTRII/SFLRI r/(SCSTROISFLR
Kw]B,1-1,w va]13.1-1,w [R/W]B ,w [R/W] 1-1,
TBYTEDataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 97
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
001500H
SCR0/(IBCR0)
[R/W] B,H,W
0--00000
SMR0
[R/W] B,H,W
000000-0
SSR0
[R/W] B,H,W
0--00011
ESCR0/(IBSR0)
[R/W] B,H,W
00000000
Multi Function
Serial I/F 0
*1: Byte access
is possible only
for access to
lower 8 bits.
*2: Reserved
because I2C
mode is not set
immediately
after reset
*3: Reserved
because CSIO
mode is not set
immediately
after reset
*4: Reserved
because LIN2.1
mode is not set
immediately
after reset
001504H
-/(RDR10/(TDR10))[R/W] H,W
-------- --------
*3
RDR00/(TDR00)[R/W] B,H,W
-------0 00000000
*1
001508H
SACSR0[R/W] B,H,W
0----000 00000000
STMR0[R] B,H,W
00000000 00000000
00150CH
STMCR0[R/W] B,H,W
00000000 00000000
-/( SFUR0) [R/W] B,H,W
-------- --------
*4
001510H - -
-/( SFLR10) [R/W]
B,H,W
--------
*4
-/( SFLR00) [R/W]
B,H,W
--------
*4
001514H - - - -
001518H - - - -
00151CH
BGR0[R/W] H,W
00000000 00000000
-/(ISMK0)[R/W]
B,H,W
--------
*2
-/(ISBA0)[R/W]
B,H,W
--------
*2
001520H
FCR10[R/W]
B,H,W
00-00100
FCR00
[R/W] B,H,W
-0000000
FBYTE20
[R/W] B,H,W
00000000
FBYTE10
[R/W] B,H,W
00000000
001524H
SCR1/(IBCR1)
[R/W] B,H,W
0--00000
SMR1[R/W]
B,H,W
000000-0
SSR1[R/W] B,H,W
0--00011
ESCR1/(IBSR1)
[R/W] B,H,W
00000000
Multi Function
Serial I/F 1
*1: Byte access
is possible only
for access to
lower 8 bits.
*2: Reserved
because I2C
mode is not set
immediately
after reset
*3: Reserved
because CSIO
mode is not set
immediately
after reset
*4: Reserved
because LIN2.1
mode is not set
immediately
after reset
001528H
-/(RDR11/(TDR11))[R/W] H,W
-------- --------
*3
RDR01/(TDR01)[R/W] B,H,W
-------0 00000000
*1
00152CH
SACSR1[R/W] B,H,W
0----000 00000000
STMR1[R] B,H,W
00000000 00000000
001530H
STMCR1[R/W] B,H,W
00000000 00000000
-/(SCSCR1/SFUR1) [R/W] B,H,W
-------- --------
*3,*4
001534H
-/(SCSTR31)
[R/W] B,H,W
--------
*3
-/(SCSTR21)
[R/W] B,H,W
--------
*3
-/(SCSTR11/SFLR1
1) [R/W] B,H,W
--------
*3,*4
-/(SCSTR01/SFLR
01) [R/W] B,H,W
--------
*3,*4
001538H - - - -
00153CH - - -
TBYTE01[R/W]
B,H,W
00000000
001540H
BGR1[R/W] H,W
00000000 00000000
-/(ISMK1)[R/W]
B,H,W
--------
*2
-/(ISBA1)[R/W]
B,H,W
--------
*2
001544H
FCR11[R/W]
B,H,W
00-00100
FCR01[R/W]
B,H,W
-0000000
FBYTE21[R/W]
B,H,W
00000000
FBYTE11[R/W]
B,H,W
00000000
/\
5 PA N 5 IO N
‘
3 Address offset value/Register name
+0 +1 +2 +3
W SMR2[R’W] SSR2[R’W] ESCR2[K w]
B,H,w B,H,w B,H,w
00000070 00001 1 00000000
J(RDRIZ,[TDR12))[K W] H.W
RDROZ/(TDR(J2)[R/W] BJ—Lw
77777 0 00000000 '
SAC RZ[R/W] B,H,w
0777000 00000000
STMR2[R] BJ—Lw
00000000 00000000
STMCRZUUW] B,H,W
00000000 00000000
r/(scscm, spun) [R/W] BJ—Lw
r/(scsnuz) r/(scsnm) J(SCSTRlZ/SFLR r/(SCSTROZSFLR
Kw]B,H,w R’W]B.H,W [R/W] H, [R/W] H,
TBYTEDataSheet
98 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
001548H
SCR2[R/W] B,H,W
0--00000
SMR2[R/W]
B,H,W
000000-0
SSR2[R/W]
B,H,W
0--00011
ESCR2[R/W]
B,H,W
00000000
Multi Function
Serial I/F 2
*1: Byte access
is possible only
for access to
lower 8 bits.
*3: Reserved
because CSIO
mode is not set
immediately
after reset
*4: Reserved
because LIN2.1
mode is not set
immediately
after reset
00154CH
-/(RDR12/(TDR12))[R/W] H,W
-------- --------
*3
RDR02/(TDR02)[R/W] B,H,W
-------0 00000000
*1
001550H
SACSR2[R/W] B,H,W
0----000 00000000
STMR2[R] B,H,W
00000000 00000000
001554H
STMCR2[R/W] B,H,W
00000000 00000000
-/(SCSCR2/SFUR2) [R/W] B,H,W
-------- --------
*3,*4
001558H
-/(SCSTR32)
[R/W] B,H,W
--------
*3
-/(SCSTR22)
[R/W] B,H,W
--------
*3
-/(SCSTR12/SFLR
12) [R/W] B,H,W
--------
*3,*4
-/(SCSTR02/SFLR
02) [R/W] B,H,W
--------
*3,*4
00155CH - - - -
001560H - - -
TBYTE02[R/W]
B,H,W
00000000
001564H
BGR2[R/W] H,W
00000000 00000000 - -
001568H
FCR12[R/W]
B,H,W
00-00100
FCR02[R/W]
B,H,W
-0000000
FBYTE22[R/W]
B,H,W
00000000
FBYTE12[R/W]
B,H,W
00000000
00156CH
SCR3/(IBCR3)
[R/W] B,H,W
0--00000
SMR3
[R/W] B,H,W
000000-0
SSR3
[R/W] B,H,W
0--00011
ESCR3/(IBSR3)
[R/W] B,H,W
00000000
Multi Function
Serial I/F 3
*1: Byte access
is possible only
for access to
lower 8 bits.
*2: Reserved
because I2C
mode is not set
immediately
after reset
*3: Reserved
because CSIO
mode is not set
immediately
after reset
*4: Reserved
because LIN2.1
mode is not set
immediately
after reset
001570H
-/(RDR13/(TDR13))[R/W] H,W
-------- --------
*3
RDR03/(TDR03)[R/W] B,H,W
-------0 00000000
*1
001574H
SACSR3[R/W] B,H,W
0----000 00000000
STMR3[R] B,H,W
00000000 00000000
001578H
STMCR3[R/W] B,H,W
00000000 00000000
-/(SCSCR3/SFUR3) [R/W] B,H,W
-------- --------
*3,*4
00157CH
-/(SCSTR33)
[R/W] B,H,W
--------
*3
-/(SCSTR23)
[R/W] B,H,W
--------
*3
-/(SCSTR13/SFLR
13) [R/W] B,H,W
--------
*3,*4
-/(SCSTR03/SFLR
03) [R/W] B,H,W
--------
*3,*4
001580H - - - -
001584H - - -
TBYTE03[R/W]
B,H,W
00000000
001588H
BGR3[R/W] H,W
00000000 00000000
-/(ISMK3)[R/W]
B,H,W
--------
*2
-/(ISBA3)[R/W]
B,H,W
--------
*2
00158CH
FCR13[R/W]
B,H,W
00-00100
FCR03[R/W]
B,H,W
-0000000
FBYTE23[R/W]
B,H,W
00000000
FBYTE13[R/W]
B,H,W
00000000
/'\
S PA N 5 IO N
\
3 Address offset value/Register name
+0 +1 +2 +3
SCRA/(IBCRA) SMR4 $3124 ESCR4’(IBSR4)
R w] B,1-1,w R’W] B.1—1,w R/W] B,1-1.w R/W] B,1-1.w
07700000 0000000 00001 1 00000000
J(RDRI4,[TDR14))[R’W] 1-1.w RDR04/(TDR04)[R/w] B,1-1.w
, ,, 77777 0 00000000 '
SAC R4[R/w] B,1-1.,w STMR4[R] B,1—1.w
07777000 00000000 00000000 00000000
STMCR4[R’W] B,1—1,w r/(SCSCRASFURA) [R/W] B,1-1.w
00000000 00000000
r/(SCSTRZA) r/(SCSTR24) J(SCSTRl4/SFLR r/(SCSTROA, SFLR
R w] B,1-1,w R’W] B.1—1,w [R/W] 1-1, [R/W] 1-1,
r/(SCSFR24)[R/W] ,, [SC FR14)[K w] J(SCSFR04)[R’W]
B 1-1,w 13,1-1 v 13,1-1 v
r/(TBYTE34)[K w] r,[TBYTE24)[R’W] r/(TBYTE14)[R/W] TBYTEDataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 99
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
001590H
SCR4/(IBCR4)
[R/W] B,H,W
0--00000
SMR4
[R/W] B,H,W
000000-0
SSR4
[R/W] B,H,W
0--00011
ESCR4/(IBSR4)
[R/W] B,H,W
00000000
Multi Function
Serial I/F 4
*1: Byte access
is possible only
for access to
lower 8 bits.
*2: Reserved
because I2C
mode is not set
immediately
after reset
*3: Reserved
because CSIO
mode is not set
immediately
after reset
*4: Reserved
because LIN2.1
mode is not set
immediately
after reset
001594H
-/(RDR14/(TDR14))[R/W] H,W
-------- --------
*3
RDR04/(TDR04)[R/W] B,H,W
-------0 00000000
*1
001598H
SACSR4[R/W] B,H,W
0----000 00000000
STMR4[R] B,H,W
00000000 00000000
00159CH
STMCR4[R/W] B,H,W
00000000 00000000
-/(SCSCR4/SFUR4) [R/W] B,H,W
-------- --------
*3,*4
0015A0H
-/(SCSTR34)
[R/W] B,H,W
--------
*3
-/(SCSTR24)
[R/W] B,H,W
--------
*3
-/(SCSTR14/SFLR
14) [R/W] B,H,W
--------
*3,*4
-/(SCSTR04/SFLR
04) [R/W] B,H,W
--------
*3,*4
0015A4H -
-/(SCSFR24)[R/W]
B,H,W
--------
*3
-/(SCSFR14)[R/W]
B,H,W
--------
*3
-/(SCSFR04)[R/W]
B,H,W
--------
*3
0015A8H
-/(TBYTE34)[R/W]
B,H,W
--------
*3
-/(TBYTE24)[R/W]
B,H,W
--------
*3
-/(TBYTE14)[R/W]
B,H,W
--------
*3
TBYTE04[R/W]
B,H,W
00000000
0015ACH
BGR4[R/W] H,W
00000000 00000000
-/(ISMK4)[R/W]
B,H,W
--------
*2
-/(ISBA4)[R/W]
B,H,W
--------
*2
0015B0H
FCR14[R/W]
B,H,W
00-00100
FCR04[R/W]
B,H,W
-0000000
FBYTE24[R/W]
B,H,W
00000000
FBYTE14[R/W]
B,H,W
00000000
0015B4
H
|
001FFCH
- - - - Reserved
002000H
CTRLR0[R/W] B,H,W
-------- 000-0001
STATR0[R/W] B,H,W
-------- 00000000
CAN 0
64msb
002004H
ERRCNT0 [R] B,H,W
00000000 00000000
BTR0[R/W] B,H,W
-0100011 00000001
002008H
INTR0[R] B,H,W
00000000 00000000
TESTR0[R/W] B,H,W
-------- X00000--
00200CH
BRPER0[R/W] B,H,W
-------- ----0000
-
002010H
IF1CREQ0[R/W] B,H,W
0------- 00000001
IF1CMSK0[R/W] B,H,W
-------- 00000000
002014H
IF1MSK20[R/W] B,H,W
11-11111 11111111
IF1MSK10[R/W] B,H,W
11111111 11111111
002018H
IF1ARB20[R/W] B,H,W
00000000 00000000
IF1ARB10[R/W] B,H,W
00000000 00000000
00201CH
IF1MCTR0[R/W] B,H,W
00000000 0---0000
-
002020H
IF1DTA10[R/W] B,H,W
00000000 00000000
IF1DTA20[R/W] B,H,W
00000000 00000000
002024H
IF1DTB10[R/W] B,H,W
00000000 00000000
IF1DTB20[R/W] B,H,W
00000000 00000000
002028
H,
00202CH
- -
002030
H,
002034H
Reserved (IF1 data mirror)
002038
H,
00203CH
- -
002040H
IF2CREQ0[R/W] B,H,W
0------- 00000001
IF2CMSK0[R/W] B,H,W
-------- 00000000
/\
5 PA N 5 IO N
‘
3 Address offset value/Register name
+0 ‘ +1 +2 ‘ +3
lFZMSKZ()[R/W] BJ—Lw IFZMSKIU[R’W] B.1—1,W
1171111111111111 1111111111111111
IFZARBZ(J[R/W] B,H.w 1F2ARB10[K w] B.H,w
00000000 00000000 00000000 00000000
IF2MCTR()[R/W] B,H.w
00000000 07770000
1F2DTA10[R/W] B,1—1.w IF2DTA20[K w] B.H,W
00000000 00000000 00000000 00000000
1F2DTB10[K w]B,1-1,w IFZDTBZ(J[R/W] B,H,w
00000000 00000000 00000000 00000000
002058H
00205cH
002060H
002064H
002068
1
00207cH
TREQR20[R] B,1—1.w TREQR](J[R] B,H,w
00000000 00000000 00000000 00000000
TREQR40[R] B,1—1.w TREQR3(J[R] B,H,w
00000000 00000000 00000000 00000000
002088H , ,
002(chH , ,
NEWDT2()[R] B.1—1,w NEWDT lU[R] B,H.w
00000000 00000000 00000000 00000000
NEWDT40[R] B.1—1,w NEWDT}U[R] B,H.w
00000000 00000000 00000000 00000000
002098H , ,
00209cH , ,
1NTPND20[R] BJ—Lw lNTPNDl(J[R] B.1—1,W
00000000 00000000 00000000 00000000
1NTPND40[R] BJ—Lw 1NTPND30[R] B.1—1,W
00000000 00000000 00000000 00000000
UU20A8H , ,
0020ACH , ,
MSGVAL20[R] B,1—1.w MSGVAL1(J[R] B.H,W
00000000 00000000 00000000 00000000
MSGVAL4U[R] B,1—1.w MSGVAL3(J[R] B.H,W
00000000 00000000 00000000 00000000
()OZOBXH , ,
002013cH , ,
0020C0
1
0020FCH
CTRLRI [R w] B,H,w STATRI [R w] B,H,w
,, , 0000001 77777777 00000000
ERRCNTI [R] B.1—1,w BTRI[K w] B.1—1,W
00000000 00000000 70100011 00000001
INTR] [R] B.1—1,W TESTRI [K w]B,1—1,W
00000000 00000000 ,, X00000"
BRPER][R/W] B,1—1.w
777777777777 0000
lFlCREQl[R w] B,H,w lFlCMSKl[R/W] B,1—1,w
(J,,,,,,, 00000001 77777777 00000000
DataSheet
100 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
002044H
IF2MSK20[R/W] B,H,W
11-11111 11111111
IF2MSK10[R/W] B,H,W
11111111 11111111
CAN 0
64msb
002048H
IF2ARB20[R/W] B,H,W
00000000 00000000
IF2ARB10[R/W] B,H,W
00000000 00000000
00204CH
IF2MCTR0[R/W] B,H,W
00000000 0---0000
-
002050H
IF2DTA10[R/W] B,H,W
00000000 00000000
IF2DTA20[R/W] B,H,W
00000000 00000000
002054H
IF2DTB10[R/W] B,H,W
00000000 00000000
IF2DTB20[R/W] B,H,W
00000000 00000000
002058
H,
00205CH
- -
002060
H,
002064H
Reserved (IF2 data mirror)
002068
H
|
00207CH
- -
002080H
TREQR20[R] B,H,W
00000000 00000000
TREQR10[R] B,H,W
00000000 00000000
002084H
TREQR40[R] B,H,W
00000000 00000000
TREQR30[R] B,H,W
00000000 00000000
002088H
-
-
00208CH
-
-
002090H
NEWDT20[R] B,H,W
00000000 00000000
NEWDT10[R] B,H,W
00000000 00000000
002094H
NEWDT40[R] B,H,W
00000000 00000000
NEWDT30[R] B,H,W
00000000 00000000
002098H
-
-
00209CH
-
-
0020A0H
INTPND20[R] B,H,W
00000000 00000000
INTPND10[R] B,H,W
00000000 00000000
0020A4H
INTPND40[R] B,H,W
00000000 00000000
INTPND30[R] B,H,W
00000000 00000000
0020A8H
-
-
0020ACH
-
-
0020B0H
MSGVAL20[R] B,H,W
00000000 00000000
MSGVAL10[R] B,H,W
00000000 00000000
0020B4H
MSGVAL40[R] B,H,W
00000000 00000000
MSGVAL30[R] B,H,W
00000000 00000000
0020B8H
-
-
0020BCH
-
-
0020C0
H
|
0020FCH
- -
002100H
CTRLR1[R/W] B,H,W
-------- 000-0001
STATR1[R/W] B,H,W
-------- 00000000
CAN 1
64msb
002104H
ERRCNT1 [R] B,H,W
00000000 00000000
BTR1[R/W] B,H,W
-0100011 00000001
002108H
INTR1[R] B,H,W
00000000 00000000
TESTR1[R/W] B,H,W
-------- X00000--
00210CH
BRPER1[R/W] B,H,W
-------- ----0000
-
002110H
IF1CREQ1[R/W] B,H,W
0------- 00000001
IF1CMSK1[R/W] B,H,W
-------- 00000000
/'\
SPANSION
‘
Address offset value/Register name
+0 ‘ +1
+2 ‘ +3
lFlMSK21[R/W] B,1—1.w
1171111111111111
lFlMSKll[R/W]B,H,W
llllllllllllllll
IFlARBZ 1 [WW] B,H.W
00000000 00000000
IFlARBl 1[R’W] B,H,W
00000000 00000000
IF]MCTR1[R/W] B,H.W
00000000 07770000
IF]DTA11[R/W] 13,1-1,w
00000000 00000000
IF] DTA2 l [K W] B.H,W
00000000 00000000
IFlDTBll[R/W] 13,1-1.w
00000000 00000000
[Fl DTBZ 1 [WW] B,H,W
00000000 00000000
002128”
00212CH
002 1 30H
002134H
002138”
00213CH
lFZCREQl [R w] 13,1-1,w
(,,,,,,,, 00000001
lFZCMSKl[R/W] 13,1-1,w
00000000
lFZMSK21[R/W] B,1—1.w
1171111111111111
lF2MSK1][R/W]B,H,W
llllllllllllllll
IF2ARBZ 1 [WW] B,H.W
00000000 00000000
IF2ARBl 1[R’W] B,H,W
00000000 00000000
IF2MCTR1[R/W] B,H.W
00000000 07770000
IF2DTA11[R/W] 13,1-1,w
00000000 00000000
IF2DTA2 l [K W] B.H,W
00000000 00000000
IFZDTB 1 1[R/w] 13,1-1.w
00000000 00000000
IF2DTBZ 1 [WW] B,H,W
00000000 00000000
002158”
00215CH
002 1 60”
002104H
002 I68
1
002 1 7cH
TREQR2l[R] 13,1-1.w
00000000 00000000
TREQRI 1 [R] 13.1-1,w
00000000 00000000
TREQR4l[R] 13,1-1.w
00000000 00000000
TREQR31[R] B,1-1,w
00000000 00000000
002188H
00218CH
NEWDTZI [R] 13.1-1,w
00000000 00000000
NEWDTI 1 [R] B.1-1,w
00000000 00000000
NEWDT41 [R] 13.1-1,w
00000000 00000000
NEWDT31 [R] B,H.W
00000000 00000000
002198H
002 l 9CH
INTPND2l[R] B,1—1.w
00000000 00000000
l.\lTP.\lDl 1 [R] B,1—1.w
00000000 00000000
INTPND4l[R] B,1—1.w
00000000 00000000
lNTPND3 1 [R] 13.1-1,w
00000000 00000000
UUZIAXH
002 1AcH
MSGVAL21[R] 13,1-1.w
00000000 00000000
MSGVALl 1 [R] 13,1-1,w
00000000 00000000
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 101
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
002114H
IF1MSK21[R/W] B,H,W
11-11111 11111111
IF1MSK11[R/W] B,H,W
11111111 11111111
CAN 1
64msb
002118H
IF1ARB21[R/W] B,H,W
00000000 00000000
IF1ARB11[R/W] B,H,W
00000000 00000000
00211CH
IF1MCTR1[R/W] B,H,W
00000000 0---0000
-
002120H
IF1DTA11[R/W] B,H,W
00000000 00000000
IF1DTA21[R/W] B,H,W
00000000 00000000
002124H
IF1DTB11[R/W] B,H,W
00000000 00000000
IF1DTB21[R/W] B,H,W
00000000 00000000
002128
H,
00212CH
- -
002130
H,
002134H
Reserved (IF1 data mirror)
002138
H,
00213CH
- -
002140H
IF2CREQ1[R/W] B,H,W
0------- 00000001
IF2CMSK1[R/W] B,H,W
-------- 00000000
002144H
IF2MSK21[R/W] B,H,W
11-11111 11111111
IF2MSK11[R/W] B,H,W
11111111 11111111
002148H
IF2ARB21[R/W] B,H,W
00000000 00000000
IF2ARB11[R/W] B,H,W
00000000 00000000
00214CH
IF2MCTR1[R/W] B,H,W
00000000 0---0000
-
002150H
IF2DTA11[R/W] B,H,W
00000000 00000000
IF2DTA21[R/W] B,H,W
00000000 00000000
002154H
IF2DTB11[R/W] B,H,W
00000000 00000000
IF2DTB21[R/W] B,H,W
00000000 00000000
002158
H,
00215CH
- -
002160
H,
002164H
Reserved (IF2 data mirror)
002168
H
|
00217CH
- -
002180H
TREQR21[R] B,H,W
00000000 00000000
TREQR11[R] B,H,W
00000000 00000000
002184H
TREQR41[R] B,H,W
00000000 00000000
TREQR31[R] B,H,W
00000000 00000000
002188H
-
-
00218CH
-
-
002190H
NEWDT21[R] B,H,W
00000000 00000000
NEWDT11[R] B,H,W
00000000 00000000
002194H
NEWDT41[R] B,H,W
00000000 00000000
NEWDT31[R] B,H,W
00000000 00000000
002198H
-
-
00219CH
-
-
0021A0H
INTPND21[R] B,H,W
00000000 00000000
INTPND11[R] B,H,W
00000000 00000000
0021A4H
INTPND41[R] B,H,W
00000000 00000000
INTPND31[R] B,H,W
00000000 00000000
0021A8H
-
-
0021ACH
-
-
0021B0H
MSGVAL21[R] B,H,W
00000000 00000000
MSGVAL11[R] B,H,W
00000000 00000000
/\
5 PA N 5 IO N
‘
3 Address offset value/Register name
+0 ‘ +1 +2 ‘ +3
MSGVAL41[R] B,1—1.w MSGVAL3][R] B.H,W
00000000 00000000 00000000 00000000
002 1 BXH , ,
002113cH , ,
002 ICU
1
002 [FCH
CTRLR2[K w] B,H,w STATR2[R w] B,H,w
,, , 0000001 77777777 00000000
ERRCNTZ [R] B.1—1,w BTR2[K w] B.1—1,W
00000000 00000000 70100011 00000001
INTR2[R] B.1—1,W TESTR2[K w] B,H,W
00000000 00000000 ,, X00000"
BRPER2[R/w] B,1—1.w
1000
lFlCREQ2[R w]B,1—1,w lFlCMSK2[R/W] B,1—1,w
(J,,,,,,, 00000001 00000000
lFlMSKZZ[R/W] BJ—Lw IF]MSK12[R’W] B.1—1,W
1171111111111111 1111111111111111
1F1AR1322[R/W]B,1-1.w lFlARB12[K w]B.1-1,w
00000000 00000000 00000000 00000000
IF]MCTRZ[R/W] B,H.w
00000000 07770000
1F lDTA12[R/W] B,1—1.w IF] DTA22[K w]B.1—1,W
00000000 00000000 00000000 00000000
lFlDTB12[K w]B,1-1,w [Fl DT1322[R/w] B,H,w
00000000 00000000 00000000 00000000
002228H
00222cH
002230H
002234H
002238H
00223cH
lFZCREQ2[R w] B,H,w lFZCMSK2[R/W] B,1—1,w
(J,,,,,,, 00000001 00000000
lFZMSKZZ[R/W] BJ—Lw IF2MSK12[R’W] B.1—1,W
1171111111111111 1111111111111111
1F2AR1322[R/w] B,H.w 1F2ARB12[K w]B.1-1,w
00000000 00000000 00000000 00000000
IF2MCTRZ[R/W] B,H.w
00000000 07770000
1F2DTA12[R/W] B,1—1.w IF2DTA22[K w] B,H,W
00000000 00000000 00000000 00000000
1F2DTB12[K w]B,1-1,w 1F2DT1322[R/W]B,1-1,w
00000000 00000000 00000000 00000000
002258H
00225cH
002260H
002264H
002268
1
00227cH
TREQR22[R] B,1—1.w TREQR]2[R] B,H,w
00000000 00000000 00000000 00000000
DataSheet
102 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
0021B4H
MSGVAL41[R] B,H,W
00000000 00000000
MSGVAL31[R] B,H,W
00000000 00000000
CAN 1
64msb
0021B8H
-
-
0021BCH
-
-
0021C0
H
|
0021FCH
- -
002200H
CTRLR2[R/W] B,H,W
-------- 000-0001
STATR2[R/W] B,H,W
-------- 00000000
CAN 2
64msb
002204H
ERRCNT2 [R] B,H,W
00000000 00000000
BTR2[R/W] B,H,W
-0100011 00000001
002208H
INTR2[R] B,H,W
00000000 00000000
TESTR2[R/W] B,H,W
-------- X00000--
00220CH
BRPER2[R/W] B,H,W
-------- ----0000
-
002210H
IF1CREQ2[R/W] B,H,W
0------- 00000001
IF1CMSK2[R/W] B,H,W
-------- 00000000
002214H
IF1MSK22[R/W] B,H,W
11-11111 11111111
IF1MSK12[R/W] B,H,W
11111111 11111111
002218H
IF1ARB22[R/W] B,H,W
00000000 00000000
IF1ARB12[R/W] B,H,W
00000000 00000000
00221CH
IF1MCTR2[R/W] B,H,W
00000000 0---0000
-
002220H
IF1DTA12[R/W] B,H,W
00000000 00000000
IF1DTA22[R/W] B,H,W
00000000 00000000
002224H
IF1DTB12[R/W] B,H,W
00000000 00000000
IF1DTB22[R/W] B,H,W
00000000 00000000
002228
H,
00222CH
- -
002230
H,
002234H
Reserved (IF1 data mirror)
002238
H,
00223CH
- -
002240H
IF2CREQ2[R/W] B,H,W
0------- 00000001
IF2CMSK2[R/W] B,H,W
-------- 00000000
002244H
IF2MSK22[R/W] B,H,W
11-11111 11111111
IF2MSK12[R/W] B,H,W
11111111 11111111
002248H
IF2ARB22[R/W] B,H,W
00000000 00000000
IF2ARB12[R/W] B,H,W
00000000 00000000
00224CH
IF2MCTR2[R/W] B,H,W
00000000 0---0000
-
002250H
IF2DTA12[R/W] B,H,W
00000000 00000000
IF2DTA22[R/W] B,H,W
00000000 00000000
002254H
IF2DTB12[R/W] B,H,W
00000000 00000000
IF2DTB22[R/W] B,H,W
00000000 00000000
002258
H,
00225CH
- -
002260
H,
002264H
Reserved (IF2 data mirror)
002268
H
|
00227CH
- -
002280H
TREQR22[R] B,H,W
00000000 00000000
TREQR12[R] B,H,W
00000000 00000000
/'\
S PA N 5 IO N
‘
3 Address offset value/Register name
+0 ‘ +1 +2 ‘ +3
TREQR42[R] B,H.w TREQR32[R] B,H,w
00000000 00000000 00000000 00000000
002288H , ,
00228CH , ,
NEWDT22[R] BJ—LW NEWDT12[R] B,H.w
00000000 00000000 00000000 00000000
NEWDT42[R] BJ—LW NEWDT32[R] B,H.w
00000000 00000000 00000000 00000000
002298H , ,
00229cH , ,
INTPND22[R] BJ—Lw lNTPND]2[R] BJ—LW
00000000 00000000 00000000 00000000
INTPND42[R] BJ—Lw 1NTPND32[R] BJ—LW
00000000 00000000 00000000 00000000
UU22A8H , ,
0022ACH , ,
MSGVAL22[R] BJ—Lw MSGVAL12[R] B.H,W
00000000 00000000 00000000 00000000
MSGVAL42[R] BJ—Lw MSGVAL32[R] B.H,W
00000000 00000000 00000000 00000000
0022BXH , ,
002chH , ,
0022CU
\
0022FcH
DFSTR[R/W]
B,H,w
,, 001
002304H , , , ,
FLIFCTLR[R’W] FLIFFERI[K w] FLIFFER2[K w]
BJ—LW B,H w B,H v
"70700 , ,
00230c
\
002FFCH
SEEARX[R] B,H,w
70000000 00000000
DEEARX[R] BJ—Lw
70000000 00000000
EECSRX[R w]
BJ—Lw
""0070
EFEARX[K w]
B,H,w
70000000 00000000
EFECRX[R’W] B,H,W
70 00000000 00000000
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 103
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
002284H
TREQR42[R] B,H,W
00000000 00000000
TREQR32[R] B,H,W
00000000 00000000
CAN 2
64msb
002288H
-
-
00228CH
-
-
002290H
NEWDT22[R] B,H,W
00000000 00000000
NEWDT12[R] B,H,W
00000000 00000000
002294H
NEWDT42[R] B,H,W
00000000 00000000
NEWDT32[R] B,H,W
00000000 00000000
002298H
-
-
00229CH
-
-
0022A0H
INTPND22[R] B,H,W
00000000 00000000
INTPND12[R] B,H,W
00000000 00000000
0022A4H
INTPND42[R] B,H,W
00000000 00000000
INTPND32[R] B,H,W
00000000 00000000
0022A8H
-
-
0022ACH
-
-
0022B0H
MSGVAL22[R] B,H,W
00000000 00000000
MSGVAL12[R] B,H,W
00000000 00000000
0022B4H
MSGVAL42[R] B,H,W
00000000 00000000
MSGVAL32[R] B,H,W
00000000 00000000
0022B8H
-
-
0022BCH
-
-
0022C0
H
|
0022FCH
- - - -
002300H
DFCTLR[R/W]
B,H,W
-0------ --------
-
DFSTR[R/W]
B,H,W
-----001
WorkFlash
002304H
-
-
-
-
002308H
FLIFCTLR[R/W]
B,H,W
---0--00
-
FLIFFER1[R/W]
B,H,W
--------
FLIFFER2[R/W]
B,H,W
--------
00230C
H
|
002FFCH
- - - - Reserved
003000H
SEEARX[R] B,H,W
-0000000 00000000
DEEARX[R] B,H,W
-0000000 00000000
XBS RAM
ECC control
register
003004H
EECSRX[R/W]
B,H,W
----00-0
-
EFEARX[R/W]
B,H,W
-0000000 00000000
003008H -
EFECRX[R/W] B,H,W
-------0 00000000 00000000
/\
SPANSION
‘
Address offset value/Register name
+0 ‘ +1 ‘ +2 ‘ +3
TEARUX[R] 13,1-1,w
,, 70000000 00000000
TEAR1X[R] 13,1-1,w
,, 70000000 00000000
TEAR2X[R] 13,1-1,w
,, 70000000 00000000
TAEARX[R/W] 13,1-1,w TASARX[R/W] 13,1-1.w
71011111 11111111 70000000 00000000
TFECRX[R/W] TlCRX[R/W] TTCRx[R w]
BJ-LW 13,1-1,w 13,1-1,w
""0000 ""0000 777777 00 00001100
TSRCRX[R/W] TKCCRX[R/W]
B.1-1,w 13,1-1,w
0" 00~~00
SEEARA[R] 13,1-1,w DEEARA[R] 13,1-1.w
"000000 00000000 "000000 00000000
EEcSRA[R w] EFEARA[R w]
BJ-LW 13,1-1,w
""000 "000000 00000000
EFECRAUUW] BJ—LW
7777777 0 00000000 00000000
TEARUA[R] 13,1-1,w
000 00000000
TEAR1A[R] 13,1-1,w
000 00000000
TEAR2A[R] 13,1-1,w
000 , 000 00000000
TAEARA[R/W] 13,1-1,w TASARA[R/W] 13,1-1.w
111 11111111 ""7000 00000000
TFECRA[R w] TlCRA[R/W] TTCRA[R w]
BJ-LW 13,1-1,w 13,1-1,w
""0000 ""0000 777777 00 00001100
TSRCRA[R/W] TKCCRA[R/W]
BJ-LW 13,1-1,w
0 77777 00~~00
003048
1
0030ch
BUSDlGSR()[R/W] 1-1,w BUSDIGSRMR’W] 1-1.w
00000000 0 77777 00 00000000 07777700
BUSD1(;SR2[R/w] 1-1,w BUSTSTR(J[R/W] 1-1.,w
00000000 0 77777 00 000000 00000000
BUSADR()[R] w
00000000 00000000 00000000 00000000
BU SADR 1 [R] w
00000000 00000000 00000000 00000000
BU SADRZ [R] w
00000000 00000000 00000000 00000000
BUSDI(}SR3[R’W] H.W
00000000 07777700
BUSD1(;SR4[R/w] 1-1,w BUSTSTR] [R/W] 1-1.,w
00000000 0 77777 00 000000 00000000
00311cH
BU SADR3 [R] w
00000000 00000000 00000000 00000000
DataSheet
104 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
00300CH
TEAR0X[R] B,H,W
000----- -------- -0000000 00000000
XBS RAM
diagnosis
register
003010H
TEAR1X[R] B,H,W
000----- -------- -0000000 00000000
003014H
TEAR2X[R] B,H,W
000----- -------- -0000000 00000000
003018H
TAEARX[R/W] B,H,W
-1011111 11111111
TASARX[R/W] B,H,W
-0000000 00000000
00301CH
TFECRX[R/W]
B,H,W
----0000
TICRX[R/W]
B,H,W
----0000
TTCRX[R/W]
B,H,W
------00 00001100
003020H
TSRCRX[R/W]
B,H,W
0-------
- -
TKCCRX[R/W]
B,H,W
00----00
003024H
SEEARA[R] B,H,W
--000000 00000000
DEEARA[R] B,H,W
--000000 00000000
Backup RAM
ECC control
register
003028H
EECSRA[R/W]
B,H,W
----00-0
-
EFEARA[R/W]
B,H,W
--000000 00000000
00302CH -
EFECRA[R/W] B,H,W
-------0 00000000 00000000
003030H
TEAR0A[R] B,H,W
000----- -------- -----000 00000000
Backup RAM
diagnosis
register
003034H
TEAR1A[R] B,H,W
000----- -------- -----000 00000000
003038H
TEAR2A[R] B,H,W
000----- -------- -----000 00000000
00303CH
TAEARA[R/W] B,H,W
-----111 11111111
TASARA[R/W] B,H,W
-----000 00000000
003040H
TFECRA[R/W]
B,H,W
----0000
TICRA[R/W]
B,H,W
----0000
TTCRA[R/W]
B,H,W
------00 00001100
003044H
TSRCRA[R/W]
B,H,W
0-------
- -
TKCCRA[R/W]
B,H,W
00----00
003048
H
|
0030FCH
- - - - Reserved
003100H
BUSDIGSR0[R/W] H,W
00000000 0-----00
BUSDIGSR1[R/W] H,W
00000000 0-----00
Bus diagnosis
003104H
BUSDIGSR2[R/W] H,W
00000000 0-----00
BUSTSTR0[R/W] H,W
00--0000 00000000
003108H
BUSADR0[R] W
00000000 00000000 00000000 00000000
00310CH
BUSADR1[R] W
00000000 00000000 00000000 00000000
003110H
BUSADR2[R] W
00000000 00000000 00000000 00000000
003114H -
BUSDIGSR3[R/W] H,W
00000000 0-----00
003118H
BUSDIGSR4[R/W] H,W
00000000 0-----00
BUSTSTR1[R/W] H,W
00--0000 00000000
00311CH
-
003120H
BUSADR3[R] W
00000000 00000000 00000000 00000000
/'\
S PA N 5 IO N
\
s Address offset value/Register name
+0 ‘ + 1 ‘ +2 ‘ +3
BUSADR4[R] w
00000000 00000000 00000000 00000000
003128
1
003FFCH
004000
1
005FFCH
006000
1
00CFFCH
CIF()[R] w
00000100111111110101101111111111
ClF 1 [R w] w
00000000 "0 70000000 77777777
00D00x
1
00D00CH
00D010H ,
00D014H ,
000011;H , , 1 , ,
LCK[R/W] w
,, W ,, 00000000
E1R[R’W] w
77777 000 ""7000 ""0000 00000000
SlR[K w] w
777777 00 77777700 00000000 00000000
ElLS[R/W] w
77777 000 ""7000 ""0000 00000000
SlLS[R w] w
111111111111111111
‘[R’W] w
77777 000 ""7000 ""0000 00000000
EIER[R’W] w
77777 000 ""7000 ""0000 00000000
8113301 w] w
777777 00 77777700 00000000 00000000
SlER[K w] w
777777 00 77777700 00000000 00000000
11.1301 w] w
TDataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 105
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
003124H
BUSADR4[R] W
00000000 00000000 00000000 00000000
Bus diagnosis
003128
H
|
003FFCH
- - - - Reserved
004000
H
|
005FFCH
Backup RAM Backup RAM
area
006000
H
|
00CFFCH
- - - - Reserved
00D000H
CIF0[R] W
00000100 11111111 01011011 11111111
FlexRay
CIF
00D004H
CIF1[R/W] W
00000000 -------0 -0000000 --------
00D008
H
|
00D00CH
- - - - Reserved
00D010H
-
FlexRay
GIF
00D014H
-
00D018H
-
-
-
-
00D01CH
LCK[R/W] W
-------- -------- -------- 00000000
00D020H
EIR[R/W] W
-----000 -----000 ----0000 00000000
FlexRay
INT
00D024H
SIR[R/W] W
------00 ------00 00000000 00000000
00D028H
EILS[R/W] W
-----000 -----000 ----0000 00000000
00D02CH
SILS[R/W] W
------11 ------11 11111111 11111111
00D030H
EIES[R/W] W
-----000 -----000 ----0000 00000000
00D034H
EIER[R/W] W
-----000 -----000 ----0000 00000000
00D038H
SIES[R/W] W
------00 ------00 00000000 00000000
00D03CH
SIER[R/W] W
------00 ------00 00000000 00000000
00D040H
ILE[R/W] W
-------- -------- -------- ------00
00D044H
T0C[R/W] W
--000000 00000000 -0000000 ------00
00D048H
T1C[R/W] W
--000000 00000010 -------- ------00
00D04CH
STPW1[R/W] W
--000000 00000000 --000000 -0000000
00D050H
STPW2[R] W
-----000 00000000 -----000 00000000
00D054
H
|
00D07CH
- - - - Reserved
/\
SPANSION
‘
Address offset value/Register name
+0 ‘ +1 ‘ +2 ‘ +3
SUCC1[R’W] w
""1 100 01000000 00010700 17770000
succzm'w] w
""0001 "700000 00000101 00000100
sucmm'w] w
00010001
NEMC[R/W] w
""0000
Flchay
NEM
PRTC1[R/W] w
00001070 01001 100 000071 10 001 1001 1
PRTCZ[R/W] w
"00111100101101~001010~001110
00DDataSheet
106 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
00D080H
SUCC1[R/W] W
----1100 01000000 00010-00 1---0000
FlexRay
SUC
00D084H
SUCC2[R/W] W
----0001 ---00000 00000101 00000100
00D088H
SUCC3[R/W] W
-------- -------- -------- 00010001
00D08CH
NEMC[R/W] W
-------- -------- -------- ----0000
FlexRay
NEM
00D090H
PRTC1[R/W] W
000010-0 01001100 0000-110 00110011
FlexRay
PRT
00D094H
PRTC2[R/W] W
--001111 00101101 --001010 --001110
00D098H
MHDC[R/W] W
---00000 00000000 -------- -0000000
FlexRay
MHD
00D09CH
-
Reserved
00D0A0H
GTUC1[R/W] W
-------- ----0000 00000010 10000000
FlexRay
GTU
00D0A4H
GTUC2[R/W] W
-------- ----0010 --000000 00001010
00D0A8H
GTUC3[R/W] W
-0000010 -0000010 00000000 00000000
00D0ACH
GTUC4[R/W] W
--000000 00001000 --000000 00000111
00D0B0H
GTUC5[R/W] W
00001110 ---00000 00000000 00000000
00D0B4H
GTUC6[R/W] W
-----000 00000010 -----000 00000000
00D0B8H
GTUC7[R/W] W
------00 00000010 ------00 00000100
00D0BCH
GTUC8[R/W] W
---00000 00000000 -------- --000010
00D0C0H
GTUC9[R/W] W
-------- ------00 ---00001 --000001
00D0C4H
GTUC10[R/W] W
-----000 00000010 --000000 00000101
00D0C8H
GTUC11[R/W] W
-----000 -----000 ------00 ------00
00D0CC
H
|
00D0FCH
- Reserved
00D100H
CCSV[R] W
--000000 00010000 -100--00 00000000
FlexRay
SUC
00D104H
CCEV[R] W
-------- -------- ---00000 00--0000
00D108
H
00D10CH
- Reserved
00D110H
SCV[R] W
-----000 00000000 -----000 00000000
FlexRay
GTU
00D114H
MTCCV[R] W
-------- --000000 --000000 00000000
00D118H
RCV[R] W
-------- -------- ----0000 00000000
00D11CH
OCV[R] W
-------- -----000 00000000 00000000
/'\
SPANSION
‘
Address offset value/Register name
+0 ‘ +1 ‘ +2 ‘ +3
SFS[R] W
rrrrrrrrrrrr ()000 00000000 00000000
SWN [T [R] w
0000 00000000
ACS[R/W] w
"700000 "700000
00012cH
E s 10 1 [R] w
,, 007mm) 00000000
E s 102 [R] w
,, 007mm) 00000000
E s 103 [R] w
,, 007mm) 00000000
E s 104[R] w
0( 00 00000000
E s 105 [R] w
,, 007mm) 00000000
E s 100 [R] w
,, 007mm) 00000000
E s 107 [R] w
,, 007mm) 00000000
E s 108 [R] w
,, 007mm) 00000000
E s 109 [R] w
,, 007mm) 00000000
10 10[R] w
,, 007mm) 00000000
ESID]1[R] w
,, 007mm) 00000000
10 1 2 [ R] w
,, 007mm) 00000000
10 1 3 [ R] w
007mm) 00000000
‘ 10 1 4[ R] w
007mm) 00000000
ES 10 1 5 [ R] w
,, 007mm) 00000000
0001 at“ ,
0510 1 [R] w
,, 007mm) 00000000
OSlDZ[R] w
,, 007mm) 00000000
OSlD3[R] w
,, 007mm) 00000000
OSlD4[R] w
*7 ()()~~00 00000000
OSlDS[R] w
,, 007mm) 00000000
05 1D6[ R] w
,, 007mm) 00000000
05 107[ R] w
,, 007mm) 00000000
OSlD8[R] w
,, 007mm) 00000000
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 107
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
00D120H
SFS[R] W
-------- ----0000 00000000 00000000
FlexRay
GTU
00D124H
SWNIT[R] W
-------- -------- ----0000 00000000
00D128H
ACS[R/W] W
-------- -------- ---00000 ---00000
00D12CH
-
00D130H
ESID1[R] W
-------- -------- 00----00 00000000
00D134H
ESID2[R] W
-------- -------- 00----00 00000000
00D138H
ESID3[R] W
-------- -------- 00----00 00000000
00D13CH
ESID4[R] W
-------- -------- 00----00 00000000
00D140H
ESID5[R] W
-------- -------- 00----00 00000000
00D144H
ESID6[R] W
-------- -------- 00----00 00000000
00D148H
ESID7[R] W
-------- -------- 00----00 00000000
00D14CH
ESID8[R] W
-------- -------- 00----00 00000000
00D150H
ESID9[R] W
-------- -------- 00----00 00000000
00D154H
ESID10[R] W
-------- -------- 00----00 00000000
00D158H
ESID11[R] W
-------- -------- 00----00 00000000
00D15CH
ESID12[R] W
-------- -------- 00----00 00000000
00D160H
ESID13[R] W
-------- -------- 00----00 00000000
00D164H
ESID14[R] W
-------- -------- 00----00 00000000
00D168H
ESID15[R] W
-------- -------- 00----00 00000000
00D16CH
-
00D170H
OSID1[R] W
-------- -------- 00----00 00000000
00D174H
OSID2[R] W
-------- -------- 00----00 00000000
00D178H
OSID3[R] W
-------- -------- 00----00 00000000
00D17CH
OSID4[R] W
-------- -------- 00----00 00000000
00D180H
OSID5[R] W
-------- -------- 00----00 00000000
00D184H
OSID6[R] W
-------- -------- 00----00 00000000
00D188H
OSID7[R] W
-------- -------- 00----00 00000000
00D18CH
OSID8[R] W
-------- -------- 00----00 00000000
/\
SPANSION
‘
Address offset value/Register name
+0 ‘ +1 ‘ +2 ‘ +3
05 109[ R] w
,, 00777700 00000000
OSlD1()[R] w
,, 00777700 00000000
031m 1 [R] w
,, 00777700 00000000
0511) 1 2 [R] w
,, 00777700 00000000
0511) 1 3 [R] w
,, 00777700 00000000
0511) 1 4[R] w
,, 00777700 00000000
0511) 1 5 [R] w
,, 00777700 00000000
00D1AcH
Reserved
NMv 1 [R] w
00000000 00000000 00000000 00000000
NMVZ [ R] w
00000000 00000000 00000000 00000000
NMV3 [ R] w
00000000 00000000 00000000 00000000
()(JDIBC
\
0002 FcH
M RC [R’W] w
77777 001 10000000 00000000 00000000
FRF[R/W] w
7777777 1 10000000 "00000 00000000
FRFM [ R/w] w
00000 000000"
FCL [R’W] w
10000000
M HDS[ R/W] w
70000000 70000000 70000000 00000000
LDTS[R] w
77777 000 00000000 ""7000 00000000
FSR[R] w
,,,,,,,,,,,,,,,, 00000000 ""7000
M HDF[ R/W] w
,0 00000000
TXRQI [R] w
00000000 00000000 00000000 00000000
TXRQZ [ R] w
00000000 00000000 00000000 00000000
TXRQ3 [ R] w
00000000 00000000 00000000 00000000
TXRQ4[R] w
00000000 00000000 00000000 00000000
N DAT 1 [R] w
00000000 00000000 00000000 00000000
N DATZ [R] w
00000000 00000000 00000000 00000000
N DAT} [R] w
00000000 00000000 00000000 00000000
DataSheet
108 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
00D190H
OSID9[R] W
-------- -------- 00----00 00000000
FlexRay
GTU
00D194H
OSID10[R] W
-------- -------- 00----00 00000000
00D198H
OSID11[R] W
-------- -------- 00----00 00000000
00D19CH
OSID12[R] W
-------- -------- 00----00 00000000
00D1A0H
OSID13[R] W
-------- -------- 00----00 00000000
00D1A4H
OSID14[R] W
-------- -------- 00----00 00000000
00D1A8H
OSID15[R] W
-------- -------- 00----00 00000000
00D1ACH
-
Reserved
00D1B0H
NMV1[R] W
00000000 00000000 00000000 00000000
FlexRay
NEM
00D1B4H
NMV2[R] W
00000000 00000000 00000000 00000000
00D1B8H
NMV3[R] W
00000000 00000000 00000000 00000000
00D1BC
H
|
00D2FCH
- Reserved
00D300H
MRC[R/W] W
-----001 10000000 00000000 00000000
FlexRay
MHD
00D304H
FRF[R/W] W
-------1 10000000 ---00000 00000000
00D308H
FRFM[R/W] W
-------- -------- ---00000 000000--
00D30CH
FCL[R/W] W
-------- -------- -------- 10000000
00D310H
MHDS[R/W] W
-0000000 -0000000 -0000000 00000000
00D314H
LDTS[R] W
-----000 00000000 -----000 00000000
00D318H
FSR[R] W
-------- -------- 00000000 -----000
00D31CH
MHDF[R/W] W
-------- -------- -------0 00000000
00D320H
TXRQ1[R] W
00000000 00000000 00000000 00000000
00D324H
TXRQ2[R] W
00000000 00000000 00000000 00000000
00D328H
TXRQ3[R] W
00000000 00000000 00000000 00000000
00D32CH
TXRQ4[R] W
00000000 00000000 00000000 00000000
00D330H
NDAT1[R] W
00000000 00000000 00000000 00000000
00D334H
NDAT2[R] W
00000000 00000000 00000000 00000000
00D338H
NDAT3[R] W
00000000 00000000 00000000 00000000
/'\
SPANSION
‘
Address offset value/Register name
1
0007 FcH
8 +0 1 +1 1 +2 1 +3
NDAT4[R] w
00000000 00000000 00000000 00000000
MBSC] [R] w
00000000 00000000 00000000 00000000
MBSC2[R] w
00000000 00000000 00000000 00000000
MBSC3[R] w
00000000 00000000 00000000 00000000
MBSC4[R] w
00000000 00000000 00000000 00000000
000350
1
0003EcH
CREL[R] w
00010000 001 1 1001 00000010 000001 10
ENDN[R] w
10000111011001010100001100100001
00030;
1
000chH
000400
1
0004FcH
WRHS] [R/W] w
"000000 70000000 ""7000 00000000
WRHsz[R/w] w
,, 70000000 77777 000 00000000
WRHS3[R/W] w
"000 00000000
00050cH ,
lBCM[R/W] w
77777777777777 00 ,,,,,000
IBCR[K w] w
70000000 (,,,,,,,, 0000000
0005 1 x
1
0005FcH
UUD60DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 109
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
00D33CH
NDAT4[R] W
00000000 00000000 00000000 00000000
FlexRay
MHD
00D340H
MBSC1[R] W
00000000 00000000 00000000 00000000
00D344H
MBSC2[R] W
00000000 00000000 00000000 00000000
00D348H
MBSC3[R] W
00000000 00000000 00000000 00000000
00D34CH
MBSC4[R] W
00000000 00000000 00000000 00000000
00D350
H
|
00D3ECH
- Reserved
00D3F0H
CREL[R] W
00010000 00111001 00000010 00000110
FlexRay
GIF
00D3F4H
ENDN[R] W
10000111 01100101 01000011 00100001
00D3F8
H
|
00D3FCH
- Reserved
00D400
H
|
00D4FCH
WRDSn[1-64][R/W] W
00000000 00000000 00000000 00000000
FlexRay
IBF
00D500H
WRHS1[R/W] W
--000000 -0000000 -----000 00000000
00D504H
WRHS2[R/W] W
-------- -0000000 -----000 00000000
00D508H
WRHS3[R/W] W
-------- -------- -----000 00000000
00D50CH
-
00D510H
IBCM[R/W] W
-------- ------00 -------- -----000
00D514H
IBCR[R/W] W
0------- -0000000 0------- -0000000
00D518
H
|
00D5FCH
- Reserved
00D600
H
|
00D6FCH
RDDSn[1-64][R] W
00000000 00000000 00000000 00000000
FlexRay
OBF
00D700H
RDHS1[R] W
--000000 -0000000 -----000 00000000
00D704H
RDHS2[R] W
-0000000 -0000000 -----000 00000000
00D708H
RDHS3[R] W
--000000 --000000 -----000 00000000
00D70CH
MBS[R] W
--000000 --000000 00-00000 00000000
00D710H
OBCM[R/W] W
-------- ------00 -------- ------00
00D714H
OBCR[R/W] W
-------- -0000000 0-----00 -0000000
00D718
H
|
00D7FCH
- Reserved
/\
5 PA N 5 IO N
‘
s Address offset value/Register name
+0 ‘ +1 ‘ +2 ‘ +3
UUono
\
OOEFFCH
()(JF(J(JU
\
OOFEFCH
DSUCR[R’W] BJ—LW
mo
UOFF04
\
()OFFOCH
PCSR[R’\ 1] BJ—LW
xxxxxxxx xxxxxxxx XXXXXXXX xxxxxxxx
PSSR[R’\ 1] BJ—LW
xxxxxxxx xxxxxxxx XXXXXXXX xxxxxxxx
UOFF l x
\
()OFFFAH
EDlRl[R] B,H,w
xxxxxxxx xxxxxxxx XXXXXXXX xxxxxxxx
ED1R0[R] B,H,w
xxxxxxxx xxxxxxxx XXXXXXXX xxxxxxxx
DataSheet
110 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Address
Address offset value/Register name
Block
+0
+1
+2
+3
00D800
H
|
00EFFCH
- Reserved
00F000
H
|
00FEFCH
- Reserved [S]
00FF00H
DSUCR[R/W] B,H,W
-------- -------0
- - OCDU [S]
00FF04
H
|
00FF0CH
- - - - Reserved [S]
00FF10H
PCSR[R/W] B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
OCDU [S]
00FF14H
PSSR[R/W] B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00FF18
H
|
00FFF4H
- - - - Reserved [S]
00FFF8H
EDIR1[R] B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
OCDU [S]
00FFFCH
EDIR0[R] B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
[S]: It is a system register. The illegal instruction exception (data access error) is generated when reading and
writing to these registers in the user mode.
/'\
S PA N 5 IO N
‘
Interrupt Interrupt
number eq uest
Hexa batch
deci read
mal target
Reset (J ()0 , 3FCH <><>DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 111
CONFIDENTIAL
INTERRUPT VECTOR TABLE
Interrupt factor
Interrupt
number
Interrupt
level Offset
TBR
default
address
RN*1
Interrupt
request
batch
read
target
Deci
mal
Hexa
deci
mal
Reset
0
00
-
3FCH
000FFFFCH
-
-
System reserved
1
01
-
3F8H
000FFFF8H
-
-
System reserved
2
02
-
3F4H
000FFFF4H
-
-
System reserved
3
03
-
3F0H
000FFFF0H
-
-
System reserved
4
04
-
3ECH
000FFFECH
-
-
FPU exception
5
05
-
3E8H
000FFFE8H
-
-
Instruction access protection violation
exception
6 06 - 3E4H 000FFFE4H - -
Data access protection violation
exception
7 07 - 3E0H 000FFFE0H - -
Data access error interrupts
8
08
-
3DCH
000FFFDCH
-
-
INTE instruction
9
09
-
3D8H
000FFFD8H
-
-
Instruction break
10
0A
-
3D4H
000FFFD4H
-
-
System reserved
11
0B
-
3D0H
000FFFD0H
-
-
System reserved
12
0C
-
3CCH
000FFFCCH
-
-
System reserved
13
0D
-
3C8H
000FFFC8H
-
-
Exception of invalid instruction
14
0E
-
3C4H
000FFFC4H
-
-
NMI request
Error generation at internal bus
diagnosis
RAM double-bit error
Backup RAM double-bit error
RDC abnormality
*5
15 0F 15(FH)
Fixed 3C0H 000FFFC0H -
External interrupt 0-7
16
10
ICR00
3BCH
000FFFBCH
0
-
Reload timer 0 / 1
17
11
ICR01
3B8H
000FFFB8H
1
Reload timer 2 / 3
18
12
ICR02
3B4H
000FFFB4H
2
Multifunction serial interface ch0
(reception completed) /
Multifunction serial interface ch0
(status)
19 13 ICR03 3B0H 000FFFB0H 3*2
Multifunction serial interface ch0
(transmission completed)
20 14 ICR04 3ACH 000FFFACH 4 -
Multifunction serial interface ch1
(reception completed) /
Multifunction serial interface ch1
(status)
21 15 ICR05 3A8H 000FFFA8H 5*2
Multifunction serial interface ch1
(transmission completed)
22 16 ICR06 3A4H 000FFFA4H 6 -
Multifunction serial interface ch2
(reception completed) /
Multifunction serial interface ch2
(status)
23 17 ICR07 3A0H 000FFFA0H 7*2
Multifunction serial interface ch2
(transmission completed)
24 18 ICR08 39CH 000FFF9CH 8 -
Multifunction serial interface ch 3
(reception completed) /
Multifunction serial interface ch3
(status)
25 19 ICR09 398H 000FFF98H 9*2
/\
5 PA N 5 IO N
‘
Interrupt Interrupt
number eq uest
Hexa batch
deci read
mal target
Multifunction erial interface c113
(transln n completed)
Multifunction serial interface ch 4
tion comp
n serial i
(status)
Multifunction serial interface c114
(transmission completed)
CAN 0 29 1D 1CR13 388..) (JUUFFFXXH , ,
CAN 1 30 IE 1CR14 3x4H (JUUFFF84H , ,
CAN 2 , Flchay 0 31 1F lCRl 5 3qu (JUUFFFXUH ,
FlexRay 1 32 20 lCRl n 37cH UUUFFF7CH , ,
Flchay timer 0 33 21 1CR17 37xH (JUUFFF78H , ,
Flchay timer 1 34 22 lCRl x 374H (JUUFFF74H , ,
RAM diagnosis completed
initialization com
iteration at RAM
AM diagno s
RAM iniua
completed
ation at Ba
diagnosis
Main Iimer/PLL timer, PLL gear for
Flchay/PLL alarm for Flchay
Clock calibration unit
(CR oscillation)
U/D counter 0/ 1 3x 26 1CR22 36.4H (JUUFFFMH 22
Freerrun timer 0 (U detcction)’
(compare clear)
Freerrun timer 1 (U detcction)’
(compare clear)
Freerrun timer 2 (U detcction)’
(compare clear)
PPG()/l,2/3
Freerrun timer 3 (U detcction)’
(compare clear)
Freerrun timer 4 (U detcction)’
(compare clear)
Freerrun timer 5 (U detcction)’
(compare clear)
PPG 4 / 5 , 6 / 7
ICU u (fetching) 101 1 (fetching)
PPGX’9/IU, 11
ICU 2 (fetching) 101 3 (fetching)
PPG 12/ 13 1 14/ 15
1w 4 (fetching), ICU 5 (fetching)
PPG 16/17’18/19
ICU 6 (fetching) 101 7 (fetching)
PPG 20/21 122/23
OCU U (match), CCU 1 (match) 49 31 lCR33 338..) (JUUFFFZXH 33
OCU 2 (match), CCU 3 (match) 50 32 lCR34 334“ (JUUFFF34H 34
OCU 4 (match), CCU 5 (match) 5] 33 lCR35 330“ (JUUFFFZOH 35
DataSheet
112 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Interrupt factor
Interrupt
number
Interrupt
level Offset
TBR
default
address
RN*1
Interrupt
request
batch
read
target
Deci
mal
Hexa
deci
mal
Multifunction serial interface ch3
(transmission completed)
26 1A ICR10 394H 000FFF94H 10 -
Multifunction serial interface ch 4
(reception completed) /
Multifunction serial interface ch4
(status)
27 1B ICR11 390H 000FFF90H 11*2
Multifunction serial interface ch4
(transmission completed)
28 1C ICR12 38CH 000FFF8CH 12 -
CAN 0
29
1D
ICR13
388H
000FFF88H
-
-
CAN 1
30
1E
ICR14
384H
000FFF84H
-
-
CAN 2 / FlexRay 0
31
1F
ICR15
380H
000FFF80H
-
FlexRay 1
32
20
ICR16
37CH
000FFF7CH
-
-
FlexRay timer 0
33
21
ICR17
378H
000FFF78H
-
-
FlexRay timer 1
34
22
ICR18
374H
000FFF74H
-
-
RAM diagnosis completed
RAM initialization completed
Error generation at RAM diagnosis
Backup RAM diagnosis completed
Backup RAM initialization
completed
Error generation at Backup RAM
diagnosis
35 23 ICR19 370H 000FFF70H -
Main timer/PLL timer/PLL gear for
FlexRay/PLL alarm for FlexRay
36 24 ICR20 36CH 000FFF6CH 20*3
Clock calibration unit
(CR oscillation)
37 25 ICR21 368H 000FFF68H - -
U/D counter 0 / 1
38
26
ICR22
364H
000FFF64H
22
Free-run timer 0 (0 detection)/
(compare clear)
39 27 ICR23 360H 000FFF60H 23
Free-run timer 1 (0 detection)/
(compare clear)
40 28 ICR24 35CH 000FFF5CH 24
Free-run timer 2 (0 detection)/
(compare clear)
PPG 0 / 1 / 2 / 3
41 29 ICR25 358H 000FFF58H 25
Free-run timer 3 (0 detection)/
(compare clear)
42 2A ICR26 354H 000FFF54H 26
Free-run timer 4 (0 detection)/
(compare clear)
43 2B ICR27 350H 000FFF50H 27
Free-run timer 5 (0 detection)/
(compare clear)
PPG 4 / 5 / 6 / 7
44 2C ICR28 34CH 000FFF4CH 28
ICU 0 (fetching) / ICU 1 (fetching)
PPG 8 / 9 / 10 / 11
45 2D ICR29 348H 000FFF48H 29
ICU 2 (fetching) / ICU 3 (fetching)
PPG 12 / 13 / 14 / 15
46 2E ICR30 344H 000FFF44H 30
ICU 4 (fetching)) / ICU 5 (fetching)
PPG 16 / 17 / 18 / 19
47 2F ICR31 340H 000FFF40H 31
ICU 6 (fetching) / ICU 7 (fetching)
PPG 20 / 21 / 22 / 23
48 30 ICR32 33CH 000FFF3CH 32
OCU 0 (match) / OCU 1 (match)
49
31
ICR33
338H
000FFF38H
33
OCU 2 (match) / OCU 3 (match)
50
32
ICR34
334H
000FFF34H
34
OCU 4 (match) / OCU 5 (match)
51
33
ICR35
330H
000FFF30H
35
/'\
S PA N 5 IO N
\
Interrupt Interrupt
number equest
Hexa batch
deei read
mal target
001 5 (match), 001 7 (match) 52 34 10135 32cH OOOFFFZCH 35
001 8 (match), 001 9 (match) 53 35 10137 32xH (JUUFFFZXH 37
OCU 10(mateh), OCU 11 (match) 54 35 1CR3X 324H (JUUFFF24H 38
W6 dead timer Imderflow 0 / 1, 2
d timer reload
WU DTTI 0
WG dead timer underflow 3 ’4 / 5
d timer reload
WU DTTI 1
ADconVerterO/ 1 , 2 '3/4 '5/5, 7 57 39 10141 3le (JUUFFFIXH 41
ADeonverterx, 9 ' 10/11/12 ' 13/
14, 15
ADconVerterl6/17,18/19,2U’
21 /22 '23
Base timer 0 1110 0’
base timer 0 1110 1
Base timer 1 1110 0’
base timer 1 1110 1
DMAC(J/ 1 /2, 3/4, 5 '5/7 52 3E 10145 3114H (JUUFFFMH ,
Delay interrupt 53 3F 10147 31111H (JUUFFFOOH , ,
System reserved
(Used for REALOS ‘4.)
System reserved
(Used for REALOS ‘4.)
55 42 2F4 (J(J(JFFEF4
i i i i
255 FF uuuH (J(J(JFFC00H
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 113
CONFIDENTIAL
Interrupt factor
Interrupt
number
Interrupt
level Offset
TBR
default
address
RN*1
Interrupt
request
batch
read
target
Deci
mal
Hexa
deci
mal
OCU 6 (match) / OCU 7 (match)
52
34
ICR36
32CH
000FFF2CH
36
OCU 8 (match) / OCU 9 (match)
53
35
ICR37
328H
000FFF28H
37
OCU 10 (match) / OCU 11 (match)
54
36
ICR38
324H
000FFF24H
38
WG dead timer underflow 0 / 1/ 2
WG dead timer reload 0 / 1/ 2
WG DTTI 0
55 37 ICR39 320H 000FFF20H 39
WG dead timer underflow 3 / 4 / 5
WG dead timer reload 3 / 4 / 5
WG DTTI 1
56 38 ICR40 31CH 000FFF1CH 40
AD converter 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7
57
39
ICR41
318H
000FFF18H
41
AD converter 8 / 9 / 10 / 11 / 12 / 13 /
14 / 15
58 3A ICR42 314H 000FFF14H 42
AD converter 16 / 17 / 18 / 19 / 20 /
21 / 22 / 23
59 3B ICR43 310H 000FFF10H 43
Base timer 0 IRQ 0/
base timer 0 IRQ 1
60 3C ICR44 30CH 000FFF0CH 44
Base timer 1 IRQ 0/
base timer 1 IRQ 1
61 3D ICR45 308H 000FFF08H 45
DMAC 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7
62
3E
ICR46
304H
000FFF04H
-
Delay interrupt
63
3F
ICR47
300H
000FFF00H
-
-
System reserved
(Used for REALOS
*4
.)
64 40 - 2FCH 000FFEFCH - -
System reserved
(Used for REALOS
*4
.)
65 41 - 2F8H 000FFEF8H - -
Used with the INT instruction.
66
|
255
42
|
FF
-
2F4
H
|
000H
000FFEF4
H
|
000FFC00H
- -
*1 : Does not support a DMA transfer request caused by an interrupt generated from a peripheral to which no
RN (resource number) is assigned.
*2 : The multi-function serial interface status does not support DMA transfer caused by I2C reception.
*3 : "PLL gear for FlexRay" and "PLL alarm for FlexRay" do not support DMA transfer.
*4 : REALOS is a trademark of Spansion LLC.
*5 : For RDC, the MB91F585LA/F586LA/F587LA/F585LC/F586LC/F587LC have corresponding functions.
/\
SPANSION
‘
1. Absolute Maximum Ratings
Rating
Min Max
Power supply vollege" ‘2 V“ VSSVUJ vssmx) v
Analog neuver supply
vollagc
Analog reference vollage‘I AVRH VSSVUJ Vss+6.() v AVRH s AVn
lnpul vellage‘I v, VSSVUJ vn+o.3 v
Analog pin inplll vollage“ VM vssrulz Vaduz v
()ulpul vollege" V0 VSSVUJ vn+o.3 v
Maximum clamp eurrenl lL MW , 4 mA *9
Telel maximum clamp eurrenl Ellrmw l , 20 mA *9
1m, , 7 mA when selling le 2nrA"’
l0L2 , 14 mA when selling le 4mA "
1m , 175 mA when selling le SmA "‘
1mm , 2 mA when selling le 2mA ‘“
10W: , 4 mA when selling le 4mA "
10mm , 5 mA when selling le SmA "‘
"L" lcvcl lelel ompul eurrenl“ 21m , 50 mA *6
log, , ,7 mA when selling le 2mA ‘“
l0H2 , 714 mA when selling le 4mA "
10H; , 7175 mA when selling le SmA "‘
1mm, , 72 mA when selling le 2mA ‘“
1mm , ,4 mA when selling le 4mA "
1mm; , 75 mA when selling le SmA "‘
"H" lcvcl lolal oulpul eurrenl‘S :10H , 750 mA *6
Power eensuinplion PD , 690 mW
()pcrming lemperalure TA ,40 +125 "c *lo.*11
Sloruge lemperalure Tslg 755 +150 "C
DataSheet
114 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Symbol
Rating
Unit Remarks
Min
Max
Power supply voltage*1 ,*2
VCC
VSS-0.3
VSS+6.0
V
Analog power supply
voltage
*1, *2
AV CC VSS-0.3 VSS+6.0 V Avcc ≤ Vcc
Analog reference voltage*1
AV R H
VSS-0.3
VSS+6.0
V
AV R H ≤ AV CC
Input voltage*1
VI
VSS-0.3
VCC+0.3
V
Analog pin input voltage*1
VIA
VSS-0.3
VCC+0.3
V
Output voltage*1
VO
VSS-0.3
VCC+0.3
V
Maximum clamp current
ICLAMP
-
4
mA
*9
Total maximum clamp current
Σ|ICLAMP |
-
20
mA
*9
"L" level maximum output
current*3
IOL1
-
7
mA
When setting to 2mA*6
IOL2
-
14
mA
When setting to 4mA *7
IOL3
-
17.5
mA
When setting to 5mA *8
"L" level average output
current*4
IOLAV1
-
2
mA
When setting to 2mA *6
IOLAV2
-
4
mA
When setting to 4mA *7
IOLAV3
-
5
mA
When setting to 5mA *8
"L" level total output current*5
ΣIOL
-
50
mA
*6
"H" level maximum output
current*3
IOH1
-
-7
mA
When setting to 2mA *6
IOH2
-
-14
mA
When setting to 4mA *7
IOH3
-
-17.5
mA
When setting to 5mA *8
"H" level average output
current*4
IOHAV1
-
-2
mA
When setting to 2mA *6
IOHAV2
-
-4
mA
When setting to 4mA *7
IOHAV3
-
-5
mA
When setting to 5mA *8
"H" level total output current*5
ΣIOH
-
-50
mA
*6
Power consumption
PD
-
690
mW
Operating temperature
TA
-40
+125
°C
*10,*11
Storage temperature
Tstg
-55
+150
°C
*1: These parameters are based on the condition that VSS= AV SS =0.0V.
*2: Caution must be taken that AVCC does not exceed VCC.
*3: The maximum output current is defined as the value of the peak current flowing through any one of the
corresponding pins.
*4: The average output current is defined as the value of the average current flowing through any one of the
corresponding pins for a 10 ms period. The average value is the operation current × the operation ratio.
*5: The total output current is defined as the maximum current value flowing through all of corresponding pins.
*6: Corresponding pins: General-purpose ports
*7: Corresponding pins: General-purpose ports of P003 to P007, P010
*8: Corresponding pins: General-purpose ports other than those of P003 to P007, P010
/'\
SPANSION
‘
Sample recommended circuit
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 115
CONFIDENTIAL
*9: • Corresponding pins: General-purpose ports
• Use the devices within recommended operating conditions.
• Use the devices with direct voltage (current).
• The + B signal should always be applied by connecting a limiting resistor between the + B signal and the
microcontroller.
• The value of the limiting resistor should be set so that the current input to the microcontroller pin does not
exceed rated values at any time regardless of instantaneously or constantly when the + B signal is input.
• Note that when the microcontroller drive current is low, such as in the low-power consumption modes, the
+ B input potential can increase the potential at the VCC pin via a protective diode, possibly affecting other
devices.
• Note that if the + B signal is input when the microcontroller is off (not fixed at 0 V), since the power is
supplied through the pin, the microcontroller may operate incompletely.
• Note that if the +B signal is input at power-on, since the power is supplied through the pin, the power-on
reset may not function in the power supply voltage.
• Do not leave + B input pins open.
Sample recommended circuit
MB91580L series
+B input (12 to 16V)
Protective diode Limiting resistor current
*10: To use this product at TA=125°C, equip this on a multilayer board with four or more layers.
To equip this on a single-layer board, change the operating conditions (operating frequency, power supply
voltage, etc) to use this at the power consumption PD=500mW or lower, or use this at TA=110°C or lower.
*11: When it is used exceeding TA=125°C, contact your sales representative.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage,
current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these
ratings.
/\
5 PA N 5 IO N
‘
(Vs; AV;(0.DataSheet
116 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
2. Recommended operating conditions
(VSS= AV SS=0.0V)
Parameter Symbol
Value
Unit Remarks
Min
Max
Power supply
voltage
VCC
4.5
5.5
V
Recommended operation guarantee range
AV CC
4.5
5.5
V
VCC
3.7
5.5
V
Operation guarantee range
AV CC
3.7
5.5
V
Smoothing
capacitor*1 CS 4.7
(tolerance within ±50%) µF
Use a ceramic capacitor or a capacitor that
has the similar frequency characteristics.
Use a capacitor with a capacitance greater
than CS as the smoothing capacitor on the
VCC pin.
Operating
temperature
TA -40 +125 °C *2
*1: For connection of smoothing capacitor CS, see the figure below.
*2: When it is used exceeding TA=125°C, contact your sales representative.
• C Pin Connection Diagram
C
S
C
V
SS
AV
SS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
/'\
SPANSION
‘
(TA: Recommended operating conditions, VarstVilou/a, v5; AV55*0.0V)
Value
Min
Typ
Max
P000 10 P002,
P011 [0 P017,
P020 10 P027,
P030 10 P037,
P040 10 P042,
P043 10 P047 .
P050 10 P057 .
P060 10 P067,
P070 10 P077,
P080 10 P087,
P090 10 P097,
P100 10 P107,
P110 [0 P117.
P120 10 P 127,
P 130 10 P134,
P136 10 P137
P000 10 P007,
P010 10 P017,
P020 10 P027,
P030 10 P037,
P040 10 P042,
P043 10 P047 .
P050 10 P057 .
P060 10 P067,
P070 10 P077,
P080 10 P087,
P090 10 P097,
P100 10 P107,
P110 [0 P117.
P120 10 P127,
P 130 10 P134,
P136 10 P 137
When
xRay inp
level is
sclcclcd
RSTX, NMlX
0.7 x v“
v(r+o.3
< mdo,="" md]="" 0.7="" x="" v“="" v(r+o.3="">< debugif="" 2.0="" v(r+o.3=""><>DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 117
CONFIDENTIAL
3. DC characteristics
(TA: Recommended operating conditions, Vcc=5.0V±10%, VSS= AV SS=0.0V)
Parameter Symbol Pin name Conditions
Value
Unit Remarks
Min
Typ
Max
"H" level
input voltage
VIH1
P000 to P002,
P011 to P017,
P020 to P027,
P030 to P037,
P040 to P042,
P043 to P047*,
P050 to P057*,
P060 to P067,
P070 to P077,
P080 to P087,
P090 to P097,
P100 to P107,
P110 to P117,
P120 to P127,
P130 to P134,
P136 to P137
When CMOS
schmitt input
level is
selected
0.7 × VCC - VCC+0.3 V
VIH2
P000 to P007,
P010 to P017,
P020 to P027,
P030 to P037,
P040 to P042,
P043 to P047*,
P050 to P057*,
P060 to P067,
P070 to P077,
P080 to P087,
P090 to P097,
P100 to P107,
P110 to P117,
P120 to P127,
P130 to P134,
P136 to P137
When
Automotive
input level is
selected
0.8 × VCC - VCC+0.3 V
VIH3 P003 to P007,
P010
When
FlexRay input
level is
selected
0.7 × VCC - VCC+0.3 V
VIH4
RSTX, NMIX
-
0.7 × VCC
-
VCC+0.3
V
VIH5
MD0, MD1
-
0.7 × VCC
-
VCC+0.3
V
VIH6
DEBUGIF
-
2.0
-
VCC+0.3
V
*: Only available with MB91F585LB/F586LB/F587LB, MB91F585LD/F586LD/F587LD
/\
SPANSION
‘
(TA: Recommended operaling conditions, Vcc’5.(JVi10“/a, Vs; AV55*0.0V)
Value
Min Typ Max
P000 10 P002,
P011 [0 P017,
P02010 P027,
P030 10 P037,
P040 Io P042,
P043 Io P047 ,
P05010 P057 ,
P062010 P067,
P07010 P077,
P080 10 P087,
P090 Io P097,
P100 Io P107,
P11010P117,
P120 Io P127,
P130 Io P134,
P 136 10 P137
P000 10 P007,
P01010 P017,
P02010 P027,
P030 10 P037,
P040 Io P042,
P043 Io P047 ,
P05010 P057 ,
P062010 P067,
P07010 P077,
P080 10 P087,
P090 Io P097,
P100 Io P107,
P11010P117,
P 120 Io P127,
P 130 Io P134,
P 136 m P137
When
xRay 111p
level is
sclccmd
VIM RSTX,.\IM1X , Vssr(J.3 , 0.3 x V“ V
VI” MD1), MD1 , Vssr(J.3 , 0.3 x V“ V
VI“, DEBUGIF , Vssr(J.3 , 018 V
DataSheet
118 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
(TA: Recommended operating conditions, Vcc=5.0V±10%, VSS= AV SS=0.0V)
Parameter Symbol Pin name Conditions
Value
Unit Remarks
Min
Typ
Max
"L" level
input voltage
VIL1
P000 to P002,
P011 to P017,
P020 to P027,
P030 to P037,
P040 to P042,
P043 to P047*,
P050 to P057*,
P060 to P067,
P070 to P077,
P080 to P087,
P090 to P097,
P100 to P107,
P110 to P117,
P120 to P127,
P130 to P134,
P136 to P137
When CMOS
schmitt input
level is
selected
Vss-0.3 - 0.3 × VCC V
VIL2
P000 to P007,
P010 to P017,
P020 to P027,
P030 to P037,
P040 to P042,
P043 to P047*,
P050 to P057*,
P060 to P067,
P070 to P077,
P080 to P087,
P090 to P097,
P100 to P107,
P110 to P117,
P120 to P127,
P130 to P134,
P136 to P137
When
Automotive
input level is
selected
Vss-0.3 - 0.5 × VCC V
VIL3 P003 to P007,
P010
When
FlexRay input
level is
selected
Vss-0.3 - 0.3 × VCC V
VIL4
RSTX, NMIX
-
Vss-0.3
-
0.3 × VCC
V
VIL5
MD0, MD1
-
Vss-0.3
-
0.3 × VCC
V
VIL6
DEBUGIF
-
Vss-0.3
-
0.8
V
*: Only available with MB91F585LB/F586LB/F587LB, MB91F585LD/F586LD/F587LD
/'\
SPANSION
A: ccommcn c opcrmmgcon mons, or. i a, s; 55*.
T R d d ' d" V 50V 10“/ V AV 00V
Value
Min
Typ
Max
P000 m P007,
P010 m P017,
P020 m P027,
P030 m P037,
P040 Io P042,
P043 Io P047 ,
P050 m P057 ,
P062010 P067,
P070 m P077,
P080 m P087,
P090 Io P097,
P100 Io P107,
P110!OP117,
P120 Io P127,
P130 Io P134,
P136 m P137
When
Flchay
selected
P000 m P002,
P011 [0 P017,
P020 m P027,
P030 m P037,
P040 Io P042,
P043 Io P047 ,
P050 m P057 ,
P062010 P067,
P070 m P077,
P080 m P087,
P090 Io P097,
P100 Io P107,
P110!OP117,
P120 Io P127,
P130 Io P134,
P 136 m P137
‘
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 119
CONFIDENTIAL
(TA: Recommended operating conditions, Vcc=5.0V±10%,VSS= AV SS=0.0V)
Parameter Symbol Pin name Conditions
Value
Unit Remarks
Min
Typ
Max
"H" level
output
voltage
VOH1
P000 to P007,
P010 to P017,
P020 to P027,
P030 to P037,
P040 to P042,
P043 to P047*,
P050 to P057*,
P060 to P067,
P070 to P077,
P080 to P087,
P090 to P097,
P100 to P107,
P110 to P117,
P120 to P127,
P130 to P134,
P136 to P137
Vcc=4.5V
IOH=-2.0mA Vcc-0.5 - Vcc V
VOH2 P003 to P007,
P010
Vcc=4.5V
IOH=-4.0mA Vcc-0.5 - Vcc V
When
FlexRay is
selected
VOH3
P000 to P002,
P011 to P017,
P020 to P027,
P030 to P037,
P040 to P042,
P043 to P047*,
P050 to P057*,
P060 to P067,
P070 to P077,
P080 to P087,
P090 to P097,
P100 to P107,
P110 to P117,
P120 to P127,
P130 to P134,
P136 to P137
Vcc=4.5V
IOH=-5.0mA Vcc-0.5 - Vcc V
*: Only available with MB91F585LB/F586LB/F587LB, MB91F585LD/F586LD/F587LD
/\
SPANSION
‘
(TA: Recommended operaling conditions, VarstVilou/a, Vs; AV5570.0V)
Value
Min Typ Max
P000 10 P007,
P010 10 P017,
P020 10 P027,
P030 10 P037,
P04010 P042,
P043 Io P047 ,
P050 10 P057 ,
P062010 P067,
P070 10 P077,
P080 10 P087,
P09010 P097,
P100 Io P107,
Pll()1oPl17,
P 120 Io P127,
P1301o P134,
P 130 10 P137
P003 10 P007, Vcc’4.5V When Flchay
P010 10174011114 is selected
P000 10 P002,
P011 [0 P017,
P020 10 P027,
P030 10 P037,
P04010 P042,
P043 Io P047 ,
P050 10 P057 ,
P062010 P067,
P070 10 P077,
P080 10 P087,
P09010 P097,
P100 Io P107,
Pll()1oPl17,
P 120 Io P127,
P1301o P134,
P 130 10 P137
P001 ,P002,
P021,P022,
P()25,P()26,
P073,P074,
P()76,P()77,
P 127,P13DataSheet
120 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
(TA: Recommended operating conditions, Vcc=5.0V±10%, VSS= AV SS=0.0V)
Parameter Symbol Pin name Conditions
Value
Unit Remarks
Min
Typ
Max
"L" level
output
voltage
VOL1
P000 to P007,
P010 to P017,
P020 to P027,
P030 to P037,
P040 to P042,
P043 to P047*,
P050 to P057*,
P060 to P067,
P070 to P077,
P080 to P087,
P090 to P097,
P100 to P107,
P110 to P117,
P120 to P127,
P130 to P134,
P136 to P137
Vcc=4.5V
IOL=2.0mA 0 - 0.4 V
VOL2
P003 to P007,
P010
Vcc=4.5V
IOL=4.0mA
0 - 0.4 V
When FlexRay
is selected
VOL3
P000 to P002,
P011 to P017,
P020 to P027,
P030 to P037,
P040 to P042,
P043 to P047*,
P050 to P057*,
P060 to P067,
P070 to P077,
P080 to P087,
P090 to P097,
P100 to P107,
P110 to P117,
P120 to P127,
P130 to P134,
P136 to P137
Vcc=4.5V
IOL=5.0mA 0 - 0.4 V
VOL4
P001,P002,
P021,P022,
P025,P026,
P073,P074,
P076,P077,
P127,P130
Vcc=4.5V
IOL=3.0mA 0 - 0.4 V
I2C shared pin
(when I2C is
selected)
VOL5 DEBUGIF
Vcc=2.7V
IOL=25.0mA
0 - 0.25 V
*: Only available with MB91F585LB/F586LB/F587LB, MB91F585LD/F586LD/F587LD
/'\
SPANSION
‘
(TA: Recommended operatin‘ conditions, VarstVilou/a, Vs; AV55*0.0V)
Value
Min
Typ
Max
Input Leak
Current
Var AV((’S.5V
vSS < v,="">< v“="" rum="" rstx,="" nmix="" 25="" 100="" ks!="" p000="" [0="" p007,="" p010="" [0="" p017,="" p020="" [0="" p027,="" p030="" [0="" p037,="" p040="" [0="" p042,="" p043="" [0="" p047="" ,="" p050="" [0="" p057="" ,="" p060="" [0="" p067,="" p070="" [0="" p077,="" p080="" [0="" p087,="" p090="" [0="" p097,="" p100="" [0="" p107,="" p110="" [0="" p117,="" p120="" [0="" p127,="" p130="" [0="" p134,="" p136="" [0="" p137="" other="" than="" vcc,="" v="" ss="" av="" c="">DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 121
CONFIDENTIAL
(TA: Recommended operating conditions, Vcc=5.0V±10%, VSS= AV SS=0.0V)
Parameter Symbol Pin name Conditions
Value
Unit Remarks
Min
Typ
Max
Input Leak
Current
IIL All input pins
Vcc= AV
CC
=5.5V
VSS < VI < VCC
-5 - +5 µA
Pull-up
resistance
RUP1
RSTX, NMIX
-
25
-
100
kΩ
RUP2
P000 to P007,
P010 to P017,
P020 to P027,
P030 to P037,
P040 to P042,
P043 to P047*,
P050 to P057*,
P060 to P067,
P070 to P077,
P080 to P087,
P090 to P097,
P100 to P107,
P110 to P117,
P120 to P127,
P130 to P134,
P136 to P137
When pull-up
resistance is
selected
25 - 100 kΩ
Input
Capacitor CIN
Other than VCC,
VSS, AV C C ,
AVSS,
C
- - 5 15 pF
*: Only available with MB91F585LB/F586LB/F587LB, MB91F585LD/F586LD/F587LD
/\
SPANSION
‘
(TA: Recommended opcrming conditions, VarstVilo‘Va, Vs; AV55*0.0V)
Pin Value
name Min Typ Max
*l.*3
RDC’OFF, Flchay *ON
*l.*3
RDC’ON, Flchay *OFF
*2.*4
Flchay *UN
*2.*4
Flchay *UFF
*l.*3
RDC’OFF, Flchay *ON
*l.*3
RDC’ON, Flchay *OFF
*2.*4
Flchay *UN
*2.*4
Flchay *UFF
, mu 125 mA *1.*3.*5
(
F(-y,.:32MI[z
, IOU 125 mA *l.*3.*5
- :IZMIIZ
DataSheet
122 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
(TA: Recommended operating conditions, Vcc=5.0V±10%, VSS= AV SS=0.0V)
Parameter Symbol
Pin
name
Conditions
Value
Unit Remarks
Min
Typ
Max
Power supply
current ICC VCC5
Normal
operations
FCP=128MHz,
FCPP=32MHz
- 85 110 mA
*1, *3
RDC=OFF, FlexRay =ON
- 82 105 mA
*1, *3
RDC=ON, FlexRay =OFF
- 85 110 mA
*2, *4
FlexRay =ON
- 79 104 mA
*2, *4
FlexRay =OFF
Normal
operations
FCP=80MHz,
FCPP=40MHz
- 69 91 mA
*1, *3
RDC=OFF, FlexRay =ON
- 67 89 mA
*1, *3
RDC=ON, FlexRay =OFF
- 69 91 mA
*2, *4
FlexRay =ON
- 64 87 mA
*2, *4
FlexRay =OFF
Flash write
FCP=128MHz,
FCPP=32MHz
-
100
125
mA
*1, *3, *5
- 100 125 mA *2, *4, *5
Flash erase
FCP=128MHz,
FCPP=32MHz
-
100
125
mA
*1, *3, *5
- 100 125 mA *2, *4, *5
*1: MB91F585LA/F586LA/F587LA
*2: MB91F585LB/F586LB/F587LB
*3: MB91F585LC/F586LC/F587LC
*4: MB91F585LD/F586LD/F587LD
*5: This series has 2 types of flash; main flash and WorkFlash; however, this is the specification when only one
of those is written/erased.
/'\
SPANSION
(3: Recommended operming conditions, VarstViiou/a, Vs; AV55*0.()V)
Pin
name
Value
Min
Typ
Max
,.
F(.r,,:32M|Iz
,.
F..ry:32Miiz
When using external cleave
315°C, *1, *2, *3, *4
When using crysiai
315°C, *1, *2, *3, *4
When using external chasm
315°C, *3, *4
When using crysiai
315°C, *3, *4
When using external chasm
315°C, *1, *2
When using crysiai
315°C, *1, *2
1.0
[.6
mA
315°C, *3, *4
0.6
[.1
mA
315°C, *1, *2
0.5
0.6
mA
315°C, *3, *4
0.]
0.2
mA
315°C, *1, *2
‘
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 123
CONFIDENTIAL
(TA: Recommended operating conditions, Vcc=5.0V±10%, VSS= AV SS=0.0V)
Parameter Symbol
Pin
name
Conditions
Value
Unit Remarks
Min
Typ
Max
Power supply
current
ICCS
VCC5
CPU sleep
FCP=128MHz,
FCPP=32MHz
- 46 68 mA *1, *2, *3, *4
ICCBS
Bus sleep
FCP=128MHz,
FCPP=32MHz
- 31 54 mA *1, *2, *3, *4
ICCT
Clock mode
4MHz source
oscillation
- 1.2 1.8 mA
When using external clock*6
TA=25°C, *1, *2, *3, *4
- 2.7 3.3 mA
When using crystal
TA=25°C, *1, *2, *3, *4
ICCTS
Clock mode
shutdown
4MHz source
oscillation
- 0.7 0.8 mA
When using external clock*6
TA=25°C, *3, *4
- 2.2 2.3 mA
When using crystal
TA=25°C, *3, *4
- 0.3 0.4 mA
When using external clock*6
TA=25°C, *1, *2
- 1.8 1.9 mA
When using crystal
TA=25°C, *1, *2
ICCH STOP mode
-
1.0
1.6
mA
TA=25°C, *3, *4
-
0.6
1.1
mA
TA=25°C, *1, *2
ICCHS STOP mode
shutdown
-
0.5
0.6
mA
TA=25°C, *3, *4
-
0.1
0.2
mA
TA=25°C, *1, *2
*1: MB91F585LA/F586LA/F587LA
*2: MB91F585LB/F586LB/F587LB
*3: MB91F585LC/F586LC/F587LC
*4: MB91F585LD/F586LD/F587LD
*6: The power supply current is the current value when the external clock is supplied from the X1 pin. Note that
the power supply current value when using the external clock is different from that using the oscillator.
/\
SPANSION
‘
(TA: Recommended operating condmons. v“ ’5.(JVil()"/a, V5;’AV;(0.DataSheet
124 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
4. AC characteristics
(1) Main Clock Timing
(TA: Recommended operating conditions, VCC =5.0V±10%, VSS= AV SS=0.0V)
Parameter Symbol
Pin
name
Conditions
Value
Unit Remarks
Min
Typ
Max
Source oscillation
clock frequency
FC X0, X1 - 4 - 20 MHz
Source oscillation
clock cycle time
tCYL X0, X1 - 50 - 250 ns
Internal operating
clock frequency*
FCP
-
-
-
-
128
MHz
CPU clock
FCPP
-
-
-
-
40
MHz
Peripheral bus clock
FCPT
-
-
-
-
40
MHz
External bus clocks
Internal operating
clock cycle time*
tCP
-
-
7.82
-
-
ns
CPU clock
tCPP
-
-
25
-
-
ns
Peripheral bus clock
tCPT
-
-
25
-
-
ns
External bus clocks
CAN PLL jitter
(during lock)
tPJ - - -10 - +10 ns
Built-in CR
oscillation frequency
FCCR - - 50 100 150 kHz
*: The maximum/minimum value is defined when using the main clock and PLL clock.
• X0,X1 clock timing
X0
t
CYL
• CAN PLL jitter
t1 t2 t3
t1 t2 t3
tn-1 tn
tn-1
tn
Deviation time from the ideal clock is assured per cycle out of 20, 000 cycles.
Ideal clock
PLL output
Slow
Fast
/'\
5 PA N S IO N
\
I' 'I
|_ _I
I
i..__ I- _ _ ____________________
1
Internal operation clock frequency
.n PLL clock
'k Mullipli Mullipli Mullipli Mullipli Multiplied Multiplied
edby1edby2 edby3edby4 " by20 by32
()scillulion clock
frequency
X
S‘IEJW/é
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 125
CONFIDENTIAL
• Guaranteed operation range
Internal operation clock frequency vs. Power supply voltage
Internal operation clock frequency F
CP
(MHz)
1284
2
3.7
5.5
Power supply voltage V
CC
(V)
MB91F58x guaranteed
operation range
PLL guaranteed
operation range
4.5
MB91F58x recommended
guaranteed operation range
Note: The CPU will be reset at the power supply voltage of the low-voltage detection setting
voltage or less.
Oscillation clock frequency vs. Internal operation clock frequency
Internal operation clock frequency
Main
clock
PLL clock
Multipli
ed by 1
Multipli
ed by 2
Multipli
ed by 3
Multipli
ed by 4
...
Multiplied
by 20
...
Multiplied
by 32
Oscillation clock
frequency
4MHz
2MHz
4MHz 8MHz 12MHz 16MHz ...
80MHz ... 128MHz
• Example of oscillation circuit
X1X0
R=330Ω
C2=12pF
C1=12pF
4MHz
Note: If it is impossible to start the oscillation within or equal to 20ms when starting from the
oscillation stop state, the clock supervisor performs a detection of oscillation stop and moves
to the fail safe operation.
Design your print circuit board so that the oscillator can start oscillation within 20ms.
In addition, when configuring the oscillator circuit, it is recommended to ask matching
evaluation of the circuit to oscillator manufacturers for the design.
/\
SPANSION
‘
DataSheet
126 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
AC characteristics are specified by the following measurement reference voltage values.
• Input Signal Waveform
• Output Signal Waveform
Hysteresis Input Pin (Automotive)
0.5Vcc
0.8Vcc
Output Pin
0.8V
2.4V
Hysteresis Input Pin (CMOS schmitt)
0.3Vcc
0.7Vcc
Hysteresis Input Pin (FlexRay)
0.35Vcc
0.65Vcc
/'\
SPANSION
(TA: Recommended opcmmg commons, Vcc *S.(JViIO%, VsrAVsroow
Pm Value
name Min Max
During normal
opcrauon
Oscillation time of
scillmo
+0.1
[00 , us At Clock mode
Width for rcscl
input removal
—\
(—7’
‘
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 127
CONFIDENTIAL
(2) Reset input
(TA: Recommended operating conditions, Vcc =5.0V±10%, Vss=AVss=0.0V)
Parameter Symbol
Pin
name
Conditions
Value
Unit Remarks
Min
Max
Reset input time
tRSTL RSTX -
10 - µs
During normal
operation
Oscillation time of
oscillator *
+0.1
- ms At Stop mode
100
-
µs
At Clock mode
Width for reset
input removal
1 - µs
*: The oscillation time of the oscillator is the time it takes for the amplitude of the oscillations to reach 90%.
For crystal oscillators, this time is between several ms and several tens of ms, for ceramic oscillators the time
is between several hundred µs and several ms, and for an external clock, the time is 0 ms.
RSTX
0.2Vcc 0.2Vcc
t
RSTL
• In Stop mode
0.2 V
CC
0.2 V
CC
100 µs
RSTX
X0
90% of
amplitude
Internal operation
clock
Oscillation time
of oscillator
Oscillation stabilization
waiting time
Instruction
execution
Internal reset
tRSTL
/\
SPANSION
‘
(TA: Recommended operating conditions. Vssronw
Pin Value
name Min Typ Max
Level detection when luming
voltage on power
Level detection During voltage
hysteresis widlh drop
Level detection
ume
Slope dclcclion
Ilndclccm
slandurd
Power offlimc [OFF VCCS , 50 , , ms *3
DataSheet
128 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
(3) Power-on Conditions
(TA: Recommended operating conditions, VSS=0.0V)
Parameter Symbol Pin
name
Conditions
Value
Unit Remarks
Min
Typ
Max
Level detection
voltage
- VCC5 - 2.1 2.3 2.5 V
When turning
on power
Level detection
hysteresis width
- VCC5 - - - 125 mV
During voltage
drop
Level detection
time
- - - - - 30 μs *1
Slope detection
undetected
standard
- VCC5 VCC= at level detection
release level - - 4 mV/μs *2
Power off time
tOFF
VCC5
-
50
-
-
ms
*3
*1: If the fluctuation of the power supply is faster than the low-voltage detection time, there is the possibility to
generate or release after the power supply voltage has exceeded the detection voltage range.
*2: When setting the power supply fluctuation to this standard or less, it is possible to suppress the slope
detection. This is the standard when the power supply fluctuation is stable.
*3: This time is to start the slope detection at next power on after power down and internal charge loss.
/'\
SPANSION
‘
(TA: Recommended operating conditions. vn ’5.(JVil()"/a, V5;’AV;(().(JV)
Value
Mln Max
Serial clock eyele
time
SCKO to SCK4,
SCK371 .SCKU
SCKO to SCK4,
SCK371 'CKL
SOTO [0 S014,
SOTLl .SOTU
Valid SIN :, SCK ’l
setup time
SCK ’l 2 Valid SIN
hold lime
Serial clock
"H" pulse width
Serial clock
"L" pulse width
SCKO to SCK4,
SCK371.SCK47
SOTO [0 S014,
SOTLl .SOTU
Valid SIN :, SCK ’l
setup time
SCK ’l 2 Valid SIN
hold lime
SCKO to SCK4,
SCKLL SCKU
SCKO to SCK4,
SCKLL SCKU
Notes' - ThiS is the AC characteristic in CLK synchronized mode.
- CL |S the load capacitance applied to pins during testing
a The maximum baud rate is limited by the internal operation clock used and other parameters
Sec Hardware Manual for details.
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 129
CONFIDENTIAL
(4) Multi-function Serial
(4-1) CSIO timing (SMR:MD2-0="010"b)
(4-1-1) Normal synchronous transfer (SCR:SPI=0) and serial clock output signal detect level "H"
(SMR:SCINV=0)
(TA: Recommended operating conditions, VCC =5.0V±10%, VSS= AV SS=0.0V)
Parameter Symbol Pin name Conditions
Value
Unit Remarks
Min
Max
Serial clock cycle
time
tSCYC
SCK0 to SCK4,
SCK3_1,SCK4_1
Master mode
CL=50pF
4tCPP - ns
SCK ↓ ⇒ SOT delay
time tSLOVI
SCK0 to SCK4,
SCK3_1,SCK4_1,
SOT0 to SOT4,
SOT3_1,SOT4_1
-30 +30 ns
Valid SIN ⇒ SCK ↑
setup time
tIVSHI SCK0 to SCK4,
SCK3_1, SCK4_1,
SIN0 to SIN4,
SIN3_1, SIN4_1
30 - ns
SCK ↑ ⇒ Valid SIN
hold time
tSHIXI 0 - ns
Serial clock
"H" pulse width
tSHSL SCK0 to SCK4,
SCK3_1, SCK4_1
Slave mode
CL=50pF
tCPP+10 - ns
Serial clock
"L" pulse width
tSLSH 2tCPP-10 - ns
SCK ↓ ⇒ SOT
delay time tSLOVE
SCK0 to SCK4,
SCK3_1,SCK4_1,
SOT0 to SOT4,
SOT3_1,SOT4_1
- 30 ns
Valid SIN ⇒ SCK ↑
setup time
tIVSHE SCK0 to SCK4,
SCK3_1, SCK4_1,
SIN0 to SIN4,
SIN3_1, SIN4_1
10 - ns
SCK ↑ ⇒ Valid SIN
hold time
tSHIXE 20 - ns
SCK fall time tF
SCK0 to SCK4,
SCK3_1, SCK4_1
- 5 ns
SCK rise time tR
SCK0 to SCK4,
SCK3_1, SCK4_1
- 5 ns
Notes:
• This is the AC characteristic in CLK synchronized mode.
• CL is the load capacitance applied to pins during testing.
• The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
SSSSSSSS
Slave
DataSheet
130 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
t
SCYC
V
OL
t
SLOVI
t
IVSHI
t
SHIXI
V
IH
V
IL
V
OH
V
OL
SCK
SOT
SIN V
IH
V
IL
V
OH
Master Mode
t
SLSH
V
IL
t
SLOVE
t
IVSHE
t
SHIXE
V
IH
V
IL
V
OH
V
OL
SCK
SOT
SIN V
IH
V
IL
t
F
V
IH
V
IL
V
IH
t
SHSL
t
R
V
IH
Slave Mode
/'\
SPANSION
‘
(TA: Recommended operating conditions. vn ’5.(JVil()"/a, V5;’AV;(().(JV)
Value
Mln Max
Serial eloek eyele
time
SCKO to SCK4,
semi] .SCKU
SCKO to SCK4,
semi] .SCKL
SOTO [0 S014,
SOTLl .SOTU
Valid SIN :, SCK l
setup time
SCK l 2 Valid SIN
hold lime
Serial clock
"H" pulse width
Serial clock
"L" pulse width
SCKO to SCK4,
semi] .SCKL
SOTO [0 S014,
SOTLl .SOTU
Valid SIN :, SCK l
setup time
SCK l 2 Valid SIN
hold lime
SCKO to SCK4,
SCKLL SCKU
SCKO to SCK4,
SCKLL SCKU
Notes: - This is the AC characteristic in CLK synchronized mode.
- CL is the load capacitance applied to pins during testing
a The maximum baud rate is limited by the internal operation clock used and other parameters
Sec Hardware Manual for details.
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 131
CONFIDENTIAL
(4-1-2) Normal synchronous transfer (SCR:SPI=0) and serial clock output signal detect level
"L"(SMR:SCINV=1)
(TA: Recommended operating conditions, VCC =5.0V±10%, VSS= AV SS=0.0V)
Parameter Symbol Pin name Conditions
Value
Unit Remarks
Min
Max
Serial clock cycle
time
tSCYC
SCK0 to SCK4,
SCK3_1,SCK4_1
Master mode
CL=50pF
4tCPP - ns
SCK ↑ ⇒ SOT
delay time tSHOVI
SCK0 to SCK4,
SCK3_1,SCK4_1,
SOT0 to SOT4,
SOT3_1,SOT4_1
-30 +30 ns
Valid SIN ⇒ SCK ↓
setup time
tIVSLI SCK0 to SCK4,
SCK3_1, SCK4_1,
SIN0 to SIN4,
SIN3_1, SIN4_1
30 - ns
SCK ↓ ⇒ Valid SIN
hold time
tSLIXI 0 - ns
Serial clock
"H" pulse width
tSHSL SCK0 to SCK4,
SCK3_1, SCK4_1
Slave mode
CL=50pF
tCPP+10 - ns
Serial clock
"L" pulse width
tSLSH 2tCPP-10 - ns
SCK ↑ ⇒ SOT
delay time tSHOVE
SCK0 to SCK4,
SCK3_1,SCK4_1,
SOT0 to SOT4,
SOT3_1,SOT4_1
- 30 ns
Valid SIN ⇒ SCK ↓
setup time
tIVSLE SCK0 to SCK4,
SCK3_1, SCK4_1,
SIN0 to SIN4,
SIN3_1, SIN4_1
10 - ns
SCK ↓ ⇒ Valid SIN
hold time
tSLIXE 20 - ns
SCK fall time tF
SCK0 to SCK4,
SCK3_1, SCK4_1
- 5 ns
SCK rise time tR
SCK0 to SCK4,
SCK3_1, SCK4_1
- 5 ns
Notes:
• This is the AC characteristic in CLK synchronized mode.
• CL is the load capacitance applied to pins during testing.
• The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
SSSSSSSS
DataSheet
132 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
tSCYC
VOH
tSHOVI
tIVSLI tSLIXI
VIH
VIL
VOH
VOL
SCK
SOT
SIN VIH
VIL
VOL
Master Mode
tSHSL
VIL
tSHOVE
tIVSLE tSLIXE
VIH
VIL
VOH
VOL
SCK
SOT
SIN VIH
VIL
tR
VIH
VIL
VIH
tSLSH
tF
VIL
Slave Mode
/'\
SPANSION
‘
(TA: Recommended operating conditions. vn ’5.(JVil()"/a , V5;’AV;(().(JV)
Value
Min Max
Serial clock cycle
time
SCKO re 5cm,
SCK371.SCK471
SCKO to 5cm,
SCK371.SCK47
SOTO to S014,
SOT371.SOT471
Valid SIN :, SCK l
setup time
SCK l 2 Valid SIN
hold lime
SCKO to 5cm,
SCK371.SCK47
SOTO to S014,
SOT371.SOT471
Serial clock
"H" pulse width
Serial clock
"L" pulse width
SCKO to 5cm,
SCK371.SCK47
SOTO to S014,
SOT371.SOT471
Valid SIN :, SCK l
setup time
SCK l 2 Valid SIN
hold lime
SCKO re 5cm,
SCKLl. SCKU
SCKO re 5cm,
SCK371.SCK471
Notes' . ThiS is the AC characteristic in CLK synchronized mode.
. CL |S the load capacitance applied to pins during testing
a The maximum baud rate is limited by the internal operation clock used and other parameters
Sec Hardware Manual for details.
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 133
CONFIDENTIAL
(4-1-3) SPI compatible (SCR:SPI=1) and serial clock output signal detect level "H"(SMR:SCINV=0)
(TA: Recommended operating conditions, VCC =5.0V±10% , VSS= AV SS=0.0V)
Parameter Symbol
Pin name Conditions
Value
Unit Remarks
Min
Max
Serial clock cycle
time
tSCYC
SCK0 to SCK4,
SCK3_1,SCK4_1
Master mode
CL=50pF
4tCPP - ns
SCK ↑ ⇒ SOT
delay time tSHOVI
SCK0 to SCK4,
SCK3_1,SCK4_1,
SOT0 to SOT4,
SOT3_1,SOT4_1
-30 +30 ns
Valid SIN ⇒ SCK ↓
setup time
tIVSLI SCK0 to SCK4,
SCK3_1, SCK4_1,
SIN0 to SIN4,
SIN3_1, SIN4_1
30 - ns
SCK ↓ ⇒ Valid SIN
hold time
tSLIXI 0 - ns
SOT ⇒ SCK ↓
delay time tSOVLI
SCK0 to SCK4,
SCK3_1,SCK4_1,
SOT0 to SOT4,
SOT3_1,SOT4_1
2tCPP-30 - ns
Serial clock
"H" pulse width
tSHSL SCK0 to SCK4,
SCK3_1,SCK4_1
Slave mode
CL=50pF
tCPP+10 - ns
Serial clock
"L" pulse width
tSLSH 2tCPP-10 - ns
SCK ↑ ⇒ SOT
delay time tSHOVE
SCK0 to SCK4,
SCK3_1,SCK4_1,
SOT0 to SOT4,
SOT3_1,SOT4_1
- 30 ns
Valid SIN ⇒ SCK ↓
setup time
tIVSLE SCK0 to SCK4,
SCK3_1, SCK4_1,
SIN0 to SIN4,
SIN3_1, SIN4_1
10 - ns
SCK ↓ ⇒ Valid SIN
hold time
tSLIXE 20 - ns
SCK fall time tF
SCK0 to SCK4,
SCK3_1, SCK4_1
- 5 ns
SCK rise time tR
SCK0 to SCK4,
SCK3_1,SCK4_1
- 5 ns
Notes:
• This is the AC characteristic in CLK synchronized mode.
• CL is the load capacitance applied to pins during testing.
• The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
/\
SPANSION
‘
V1
er
DataSheet
134 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
t
SCYC
V
OL
t
SOVLI
t
SLIXI
V
IH
V
IL
V
OH
V
OL
SCK
SOT
SIN V
IH
V
IL
V
OH
V
OH
V
OL
t
IVSLI
t
SHOVI
V
OL
Master Mode
t
SLSH
V
IL
t
F
t
SLIXE
V
IH
V
IL
V
OH
V
OL
SCK
SOT
SIN V
IH
V
IL
V
IH
V
OH
V
OL
t
IVSLE
t
SHOVE
V
IL
V
IH
V
IH
V
IL
t
SHSL
t
R
*
*: Changes when writing to TDR register
Slave Mode
/'\
SPANSION
‘
(TA: Recommended operating conditions. vn ’5.(JVil()"/a, V5;’AV;(().(JV)
Value
Min Max
Serial clock eyele sum re Sum,
rmie SCK3,1.SCK4,1
sum re Sum,
SCK3,1.SCK4,
SOTO re S014,
SOT3,1.SOT4,1
Valid SIN :, SCK ’l
setup time
SCK ’l 2 Valid SIN
hold rime
sum re Sum,
SCK3,1.SCK4,
SOTO re S014,
SOT3,1.SOT4,1
Serial clock
"H" pulse width
Serial clock
"L" pulse width
sum re Sum,
SCK3,1.SCK4,
SOTO re S014,
SOT3,1.SOT4,1
Valid SIN :, SCK ’l
setup time
SCK ’l 2 Valid SIN
hold rime
SCK fall rime rF sum re Sum, , 5 ns
SCK3,1. sum,
sum re Sum,
SCK3,1.SCK4,1
Notes: - This is the AC characteristic in CLK synchronized mode.
- CL is the load capacitance applied to pins during testing
a The maximum baud rate is limited by the internal operation clock used and other parameters
Sec Hardware Manual for details.
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 135
CONFIDENTIAL
(4-1-4) SPI compatible (SCR:SPI=1) and serial clock output signal detect level "L"(SMR:SCINV=1)
(TA: Recommended operating conditions, VCC =5.0V±10%, VSS= AV SS=0.0V)
Parameter Symbol
Pin name Conditions
Value
Unit Remarks
Min
Max
Serial clock cycle
time
tSCYC
SCK0 to SCK4,
SCK3_1,SCK4_1
Master mode
CL=50pF
4tCPP - ns
SCK ↓ ⇒ SOT
delay time tSLOVI
SCK0 to SCK4,
SCK3_1,SCK4_1,
SOT0 to SOT4,
SOT3_1,SOT4_1
-30 +30 ns
Valid SIN ⇒ SCK ↑
setup time
tIVSHI SCK0 to SCK4,
SCK3_1, SCK4_1,
SIN0 to SIN4,
SIN3_1, SIN4_1
30 - ns
SCK ↑ ⇒ Valid SIN
hold time
tSHIXI 0 - ns
SOT ⇒ SCK ↑
delay time tSOVHI
SCK0 to SCK4,
SCK3_1,SCK4_1,
SOT0 to SOT4,
SOT3_1,SOT4_1
2tCPP-30 - ns
Serial clock
"H" pulse width
tSHSL SCK0 to SCK4,
SCK3_1,SCK4_1,
SOT0 to SOT4,
SOT3_1,SOT4_1
Slave mode
CL=50pF
tCPP+10 - ns
Serial clock
"L" pulse width
tSLSH 2tCPP-10 - ns
SCK ↓ ⇒ SOT
delay time tSLOVE
SCK0 to SCK4,
SCK3_1,SCK4_1,
SOT0 to SOT4,
SOT3_1,SOT4_1
- 30 ns
Valid SIN ⇒ SCK ↑
setup time
tIVSHE SCK0 to SCK4,
SCK3_1, SCK4_1,
SIN0 to SIN4,
SIN3_1, SIN4_1
10 - ns
SCK ↑ ⇒ Valid SIN
hold time
tSHIXE 20 - ns
SCK fall time
tF
SCK0 to SCK4,
SCK3_1, SCK4_1
SCK0 to SCK4,
SCK3_1,SCK4_1
-
5
ns
SCK rise time tR - 5 ns
Notes:
• This is the AC characteristic in CLK synchronized mode.
• CL is the load capacitance applied to pins during testing.
• The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
{W
%fl_xfi
DataSheet
136 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
t
SCYC
V
OH
t
SOVHI
t
SHIXI
V
IH
V
IL
V
OH
V
OL
SCK
SOT
SIN V
IH
V
IL
V
OL
V
OH
V
OL
t
IVSHI
t
SLOVI
V
OH
Master Mode
t
SHSL
V
IL
t
R
t
SHIXE
V
IH
V
IL
V
OH
V
OL
SCK
SOT
SIN V
IH
V
IL
V
IH
V
OH
V
OL
t
IVSHE
t
SLOVE
V
IL
V
IH
V
IH
V
IL
t
SLSH
t
F
*
*: Changes when writing to TDR register
Slave Mode
/'\
SPANSION
(TA: Recommended operating conditions. v“ ’5.(JVil()“/a, V5;’AV;(0.(JV)
Value
Min
Max
5
scs L : SCK L
setup time
scs407| to scs4371
scs407| to scs4371
scs L : SCK L
setup time
scs407| to scs4371
scs407| to scs4371
scs L : SOT
delay time
SOT37|,SOT471
scs407| to scs4371
Notes: - This is the AC characteristic in CLK synchronized mode.
. CL is the load capacitance applied to pins during testing
a The maximum baud rate i limited by the internal operation clock used and other parameters
Sec Hardware Manual for details.
‘
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 137
CONFIDENTIAL
(4-1-5) When the serial chip select is used (SCSCR:CSEN=1)
• Serial clock output signal detect level "H"(SMR,SCSFR:SCINV=0)
• Serial chip select inactive level "H"(SCSCR,SCSFR:CSLVL=1)
(TA: Recommended operating conditions, VCC =5.0V±10%, VSS= AV SS=0.0V)
Parameter Symbol
Pin name Conditions
Value
Unit
Remarks
Min
Max
SCS ↓ ⇒ SCK ↓
setup time
tCSSI SCK1 to SCK4,
SCK3_1,SCK4_1,
SCS1 to SCS3,
SCS3_1,
SCS40 to SCS43
SCS40_1 to SCS43_1
Master mode
CL=50pF
tCSSU
*1+0 tCSSU
*1+50 ns
SCK ↑ ⇒ SCS ↑
hold time tCSHI tCSHD
*2-50 tCSHD
*2+0 ns
SCS
deselect time tCSDI
SCS1 to SCS3,
SCS3_1,
SCS40 to SCS43
SCS40_1 to SCS43_1
-50+5tCPP
+tCSDS
*3
+50+5tCPP
+tCSDS
*3 ns
SCS ↓ ⇒ SCK ↓
setup time
tCSSE SCK1 to SCK4,
SCK3_1,SCK4_1,
SCS1 to SCS3,
SCS3_1,
SCS40 to SCS43
SCS40_1 to SCS43_1
Slave mode
CL=50pF
3tCPP+30 - ns
SCK ↑ ⇒ SCS ↑
hold time tCSHE 0 - ns
SCS
deselect time tCSDE
SCS1 to SCS3,
SCS3_1,
SCS40 to SCS43
SCS40_1 to SCS43_1
3tCPP+30 - ns
SCS ↓ ⇒ SOT
delay time
tDSE SCS1 to SCS3,
SCS3_1,
SCS40 to SCS43
SCS40_1 to SCS43_1,
SOT0 to SOT4,
SOT3_1,SOT4_1
- 40 ns
SCS ↑ ⇒ SOT
delay time tDEE 0 - ns
SCK ↓ ⇒ SCS ↓
clock switch time tSCC
SCK1 to SCK4,
SCK3_1,SCK4_1,
SCS1 to SCS3,
SCS3_1,
SCS40 to SCS43
SCS40_1 to SCS43_1
Master mode
round
operation
CL=50pF
3tCPP+0 3tCPP+50 ns
*1: tCSSU =SCSTR:CSSU7-0 × Serial chip select timing operation clock
*2: tCSHD=SCSTR:CSHD7-0 × Serial chip select timing operation clock
*3: tCSDS=SCSTR:CSDS15-0 × Serial chip select timing operation clock
For details of *1, *2 and *3 above, see Hardware Manual.
Notes:
• This is the AC characteristic in CLK synchronized mode.
• CL is the load capacitance applied to pins during testing.
• The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
SSSSSSSS
SSSSS
DataSheet
138 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
SCK output
SOT
(Normal Sync transfer)
SOT
(SPI compatible)
t
CSSI
SCS output
t
CSHI
t
CSDI
Master Mode
SCK input
SOT
(Normal Sync
transfer)
SOT
(SPI compatible)
tCSSE
SCS input
tCSHE
tCSDE
tDSE
tDEE
Slave Mode
SCSy output
SCK output
SCSx output
t
SCC
Clock switching example by master mode round operation (x,y=0,1,2,3)
/'\
SPANSION
(TA: Recommended operating conditions. v“ ’5.(JVil()“/a, V5;’AV;(0.(JV)
Value
Min
Max
5
scs L : SCK T
setup time
SCSAOJ m scs4371
SCSAOJ m scs4371
scs L : SCK T
setup time
SCSAOJ m scs4371
SCSAOJ m scs4371
scs L : SOT
delay time
501371501371
SCSAOJ m scs4371
Notes: - This is the AC characteristic in CLK synchronized mode.
. CL is the load capacitance applied to pins during testing
a The maximum baud rate i limited by the internal operation clock used and other parameters
Sec Hardware Manual for details.
‘
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 139
CONFIDENTIAL
(4-1-6) When the serial chip select is used (SCSCR:CSEN=1)
• Serial clock output signal detect level "L"(SMR,SCSFR:SCINV=1)
• Serial chip select inactive level "H"(SCSCR,SCSFR:CSLVL=1)
(TA: Recommended operating conditions, VCC =5.0V±10%, VSS= AV SS=0.0V)
Parameter Symbol Pin name Conditions
Value
Unit
Remarks
Min
Max
SCS ↓ ⇒ SCK ↑
setup time
tCSSI SCK1 to SCK4,
SCK3_1,SCK4_1,
SCS1 to SCS3,
SCS3_1,
SCS40 to SCS43
SCS40_1 to SCS43_1
Master mode
CL=50pF
tCSSU
*1+0 tCSSU
*1+50 ns
SCK ↓ ⇒ SCS ↑
hold time tCSHI tCSHD
*2-50 tCSHD
*2+0 ns
SCS
deselect time tCSDI
SCS1 to SCS3,
SCS3_1,
SCS40 to SCS43
SCS40_1 to SCS43_1
-50+5tCPP
+tCSDS
*3
+50+5tCPP
+tCSDS
*3 ns
SCS ↓ ⇒ SCK ↑
setup time
tCSSE SCK1 to SCK4,
SCK3_1,SCK4_1,
SCS1 to SCS3,
SCS3_1,
SCS40 to SCS43
SCS40_1 to SCS43_1
Slave mode
CL=50pF
3tCPP+30 - ns
SCK ↓ ⇒ SCS ↑
hold time tCSHE 0 - ns
SCS
deselect time tCSDE
SCS1 to SCS3,
SCS3_1,
SCS40 to SCS43
SCS40_1 to SCS43_1
3tCPP+30 - ns
SCS ↓ ⇒ SOT
delay time
tDSE SCS1 to SCS3,
SCS3_1,
SCS40 to SCS43
SCS40_1 to SCS43_1,
SOT0 to SOT4,
SOT3_1,SOT4_1
- 40 ns
SCS ↑ ⇒ SOT
delay time tDEE 0 - ns
SCK ↑ ⇒ SCS ↓
clock switch time tSCC
SCK1 to SCK4,
SCK3_1,SCK4_1,
SCS1 to SCS3,
SCS3_1,
SCS40 to SCS43
SCS40_1 to SCS43_1
Master mode
round
operation
CL=50pF
3tCPP+0 3tCPP+50 ns
*1: tCSSU =SCSTR:CSSU7-0 × Serial chip select timing operation clock
*2: tCSHD=SCSTR:CSHD7-0 × Serial chip select timing operation clock
*3: tCSDS=SCSTR:CSDS15-0 × Serial chip select timing operation clock
For details of *1, *2 and *3 above, see Hardware Manual.
Notes:
• This is the AC characteristic in CLK synchronized mode.
• CL is the load capacitance applied to pins during testing.
• The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
SSSSSSSS
SSSSS
DataSheet
140 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
SCK output
SOT
(Normal Sync transfer)
SOT
(SPI compatible)
tCSSI
SCS output
tCSHI
tCSDI
Master Mode
SCK input
SOT
(Normal Sync
transfer)
SOT
(SPI compatible)
t
CSSE
SCS input
t
CSHE
t
CSDE
t
DSE
t
DEE
Slave Mode
SCSy output
SCK output
SCSx output tSCC
Clock switching example by master mode round operation (x,y=0,1,2,3)
/'\
SPANSION
(TA: Recommended operating conditions. v“ ’5.(JVil()“/a, V5;’AV;(0.(JV)
Value
Min
Max
5
scs T : SCK l
setup time
SCSAOJ m SCSASJ
SCSAOJ m SCSASJ
scs T : SCK l
setup time
SCSAOJ m scsa3f|
SCSAOJ m scsa3f|
scs T : SOT
delay time
SOTLLSO‘MJ
SCSAOJ m scsa3f|
Notes: - This is the AC characteristic in CLK synchronized mode.
. CL is the load capacitance applied to pins during testing
a The maximum baud rate i limited by the internal operation clock used and other parameters
Sec Hardware Manual for details.
‘
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 141
CONFIDENTIAL
(4-1-7) When the serial chip select is used (SCSCR:CSEN=1)
• Serial clock output signal detect level "H"(SMR,SCSFR:SCINV=0)
• Serial chip select inactive level "L"(SCSCR,SCSFR:CSLVL=0)
(TA: Recommended operating conditions, VCC =5.0V±10%, VSS= AV SS=0.0V)
Parameter Symbol Pin name Conditions
Value
Unit
Remarks
Min
Max
SCS ↑ ⇒ SCK ↓
setup time
tCSSI SCK1 to SCK4,
SCK3_1,SCK4_1,
SCS0 to SCS3,
SCS3_1,
SCS40 to SCS43
SCS40_1 to SCS43_1
Master mode
CL=50pF
tCSSU
*1+0 tCSSU
*1+50 ns
SCK ↑ ⇒ SCS ↓
hold time tCSHI tCSHD
*2-50 tCSHD
*2+0 ns
SCS
deselect time tCSDI
SCS0 to SCS3,
SCS3_1,
SCS40 to SCS43
SCS40_1 to SCS43_1
-50+5tCPP
+tCSDS
*3
+50+5tCPP
+tCSDS
*3 ns
SCS ↑ ⇒ SCK ↓
setup time
tCSSE SCK1 to SCK4,
SCK3_1,SCK4_1,
SCS0 to SCS3,
SCS3_1,
SCS40 to SCS43
SCS40_1 to SCS43_1
Slave mode
CL=50pF
3tCPP+30 - ns
SCK ↑ ⇒ SCS ↓
hold time tCSHE 0 - ns
SCS
deselect time tCSDE
SCS0 to SCS3,
SCS3_1,
SCS40 to SCS43,
SCS40_1 to SCS43_1
3tCPP+30 - ns
SCS ↑ ⇒ SOT
delay time
tDSE SCS0 to SCS3,
SCS3_1,
SCS40 to SCS43
SCS40_1 to SCS43_1,
SOT0 to SOT4,
SOT3_1,SOT4_1
- 40 ns
SCS ↓ ⇒ SOT
delay time tDEE 0 - ns
SCK ↓ ⇒ SCS ↑
clock switch time tSCC
SCK1 to SCK4,
SCK3_1,SCK4_1,
SCS0 to SCS3,
SCS3_1,
SCS40 to SCS43
SCS40_1 to SCS43_1
Master mode
round
operation
CL=50pF
3tCPP+0 3tCPP+50 ns
*1: tCSSU =SCSTR:CSSU7-0 × Serial chip select timing operation clock
*2: tCSHD=SCSTR:CSHD7-0 × Serial chip select timing operation clock
*3: tCSDS=SCSTR:CSDS15-0 × Serial chip select timing operation clock
For details of *1, *2 and *3 above, see Hardware Manual.
Notes:
• This is the AC characteristic in CLK synchronized mode.
• CL is the load capacitance applied to pins during testing.
• The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
SSSSSSSS
SSSSS
DataSheet
142 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
SCK output
SOT
(Normal Sync transfer)
SOT
(SPI compatible)
tCSSI
SCS output
tCSHI
tCSDI
Master Mode
SCK input
SOT
(Normal Sync
transfer)
SOT
(SPI compatible)
tCSSE
SCS input
tCSHE
tCSDE
tDSE
tDEE
Slave Mode
SCSy output
SCK output
SCSx output tSCC
Clock switching example by master mode round operation (x,y=0,1,2,3)
/'\
SPANSION
(TA: Recommended operating conditions. v“ ’5.(JVil()“/a, V5;’AV;(0.(JV)
Value
Min
Max
5
scs T : SCK T
setup time
SCSAOJ m scsa3f|
SCSAOJ m scsa3f|
scs T : SCK T
setup time
SCSAOJ m SCSAYLI
SCSAOJ m SCSAYLI
scs T : SOT
delay time
song ,SOT‘LI
SCSAOJ m SCSAYLI
Notes: - This is the AC characteristic in CLK synchronized mode.
. CL is the load capacitance applied to pins during testing
a The maximum baud rate i limited by the internal operation clock used and other parameters
Sec Hardware Manual for details.
‘
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 143
CONFIDENTIAL
(4-1-8) When the serial chip select is used (SCSCR:CSEN=1)
• Serial clock output signal detect level "L"(SMR,SCSFR:SCINV=1)
• Serial chip select inactive level "L"(SCSCR,SCSFR:CSLVL=0)
(TA: Recommended operating conditions, VCC =5.0V±10%, VSS= AV SS=0.0V)
Parameter Symbol Pin name Conditions
Value
Unit
Remarks
Min
Max
SCS ↑ ⇒ SCK ↑
setup time
tCSSI SCK1 to SCK4,
SCK3_1,SCK4_1,
SCS1 to SCS3,
SCS3_1,
SCS40 to SCS43
SCS40_1 to SCS43_1
Master
mode
CL=50pF
tCSSU
*1+0 tCSSU
*1+50 ns
SCK ↓ ⇒ SCS ↓
hold time tCSHI tCSHD
*2-50 tCSHD
*2+0 ns
SCS
deselect time tCSDI
SCS1 to SCS3,
SCS3_1,
SCS40 to SCS43
SCS40_1 to SCS43_1
-50+5tCPP
+tCSDS
*3
+50+5tCPP
+tCSDS
*3 ns
SCS ↑ ⇒ SCK ↑
setup time
tCSSE SCK1 to SCK4,
SCK3_1,SCK4_1,
SCS1 to SCS3,
SCS3_1,
SCS40 to SCS43
SCS40_1 to SCS43_1
Slave mode
CL=50pF
3tCPP+30 - ns
SCK ↓ ⇒ SCS ↓
hold time tCSHE 0 - ns
SCS
deselect time tCSDE
SCS1 to SCS3,
SCS3_1,
SCS40 to SCS43
SCS40_1 to SCS43_1
3tCPP+30 - ns
SCS ↑ ⇒ SOT
delay time
tDSE SCS1 to SCS3,
SCS3_1,
SCS40 to SCS43
SCS40_1 to SCS43_1,
SOT0 to SOT4,
SOT3_1,SOT4_1
- 40 ns
SCS ↓ ⇒ SOT
delay time tDEE 0 - ns
SCK ↑ ⇒ SCS ↑
clock switch time
tSCC
SCK1 to SCK4,
SCK3_1,SCK4_1,
SCS1 to SCS3,
SCS3_1,
SCS40 to SCS43
SCS40_1 to SCS43_1
Master
mode
round
operation
CL=50pF
3tCPP+0 3tCPP+50 ns
*1: tCSSU =SCSTR:CSSU7-0 × Serial chip select timing operation clock
*2: tCSHD=SCSTR:CSHD7-0 × Serial chip select timing operation clock
*3: tCSDS=SCSTR:CSDS15-0 × Serial chip select timing operation clock
For details of *1, *2 and *3 above, see Hardware Manual.
Notes:
• This is the AC characteristic in CLK synchronized mode.
• CL is the load capacitance applied to pins during testing.
• The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
SSSSSSSS
SSSSS
DataSheet
144 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
SCK output
SOT
(Normal Sync transfer)
SOT
(SPI compatible)
t
CSSI
SCS output
t
CSHI
t
CSDI
Master Mode
SCK input
SOT
(Normal Sync
transfer)
SOT
(SPI compatible)
t
CSSE
SCS input
t
CSHE
t
CSDE
t
DSE
t
DEE
Slave Mode
SCSy output
SCK output
SCSx output tSCC
Clock switching example by master mode round operation (x,y=0,1,2,3)
/'\
SPANSION
(TA: Recommended operalmg eondluous. v“ ’5.(JVil()"/a, V5;’AV;(0.DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 145
CONFIDENTIAL
(4-2) UART (Async Serial Interface) timing (SMR:MD2-0="000"b, "001"b)
(4-2-1) When the external clock is selected (BGR:EXT=1)
(TA: Recommended operating conditions, VCC =5.0V±10%, VSS= AV SS=0.0V)
Parameter Symbol Pin name Conditions
Value
Unit Remarks
Min
Max
Serial clock
"L" pulse width
tSLSH
SCK0 to SCK4,
SCK3_1,SCK4_1 CL=50pF
tCPP+10 - ns
Serial clock
"H" pulse width
tSHSL tCPP+10 - ns
SCK fall time
tF
-
5
ns
SCK rise time
tR
-
5
ns
SCK
t
SHSL
V
IL
V
IH
V
IH
t
R
t
SLSH
t
F
V
IL
V
IH
V
IL
When the external clock is selected
(4-3) LIN interface (v2.1) (LIN Communication Control Interface (v2.1)) timing (SMR:MD2-0="011"b)
(4-3-1) When the external clock is selected (BGR:EXT=1)
(TA: Recommended operating conditions, VCC =5.0V±10%, VSS= AV SS=0.0V)
Parameter Symbol Pin name Conditions
Value
Unit Remarks
Min
Max
Serial clock
"L" pulse width
tSLSH
SCK0 to SCK4,
SCK3_1,SCK4_1 CL=50pF
tCPP+10 - ns
Serial clock
"H" pulse width
tSHSL tCPP+10 - ns
SCK fall time
tF
-
5
ns
SCK rise time
tR
-
5
ns
SCK
t
SHSL
V
IL
V
IH
V
IH
t
R
t
SLSH
t
F
V
IL
V
IH
V
IL
When the external clock is selected
/\
SPANSION
‘
(TA: Recommended operating condmons, v“ ’5.(JVil()“/a, V5;’AV;(0.DataSheet
146 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
(4-4) I2C timing (SMR:MD2-0="100"b)
(TA: Recommended operating conditions, VCC=5.0V±10%, VSS=AVSS=0.0V)
Parameter Symbol
Pin name Conditions
Standard
mode
High-speed
mode
*3
Unit Remarks
Min Max Min Max
SCL clock
frequency fSCL
SCK0,SCK1,
SCK3,SCK4,
SCK3_1,SCK4_1
(SCL)
CL=50pF
R=(VP/IOL)
*1
0 100 0 400 kHz
"Repeat START
condition"
hold time
SDA ↓ → SCL ↓
tHDSTA
SCK0,SCK1,
SCK3,SCK4,
SCK3_1,SCK4_1
(SCL)
SOT0,SOT1,
SOT3,SOT4,
SOT3_1,SOT4_1
(SDA)
4.0 - 0.6 - µs
"L" width
for SCL clock tLOW SCK0,SCK1,
SCK3,SCK4,
SCK3_1,SCK4_1
(SCL)
4.7 - 1.3 - µs
"H" width
for SCL clock tHIGH 4.0 - 0.6 - µs
"Repeat START
condition"
setup time
SCL ↑ → SDA ↓
tSUSTA
SCK0,SCK1,
SCK3,SCK4,
SCK3_1,SCK4_1
(SCL)
SOT0,SOT1,
SOT3,SOT4,
SOT3_1,SOT4_1
(SDA)
4.7 - 0.6 - µs
Data hold time
SCL ↓ → SDA ↓ ↑ tHDDAT 0 3.45
*2 0 0.90
*3 µs
Data setup time
SDA ↓ ↑ → SCL ↑ tSUDAT 250 - 100 - ns
"STOP condition"
setup time
SCL ↑ → SDA ↑
tSUSTO 4.0 - 0.6 - µs
Bus free time
between "STOP
condition" and
"START condition"
tBUF - 4.7 - 1.3 - µs
Noise filter tSP - 2tCPP
*4 - 2tCPP
*4 - ns
*1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA output lines, respectively.
VP shows that the power supply voltage of the pull-up resistor and IOL shows the VOL guarantee current.
*2: The maximum tHDDAT only has to be met if the device does not extend the "L" width (tLOW) of the SCL signal.
*3: A high-speed mode I2C bus device can be used on a standard mode I2C bus system as long as the device
satisfies the requirement of "tSUDAT ≥ 250 ns".
*4: tCPP is the peripheral clock cycle time. Adjust the clock of the peripheral bus to 8MHz or more when use I2C.
SSSSSSSS
Eh
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 147
CONFIDENTIAL
SDA
SCL
t
HDSTA
t
LOW
t
HDDAT
t
SUDAT
t
HIGH
t
SUSTA
t
HDSTA
t
SP
t
BUF
t
SUSTO
/\
SPANSION
‘
(TA: Recommended operalmg condinons. v“ T5.(JVil()“/a, VSSTAVSSTOAJV)
Value
Min Max
T1.\IDataSheet
148 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
(5) Timer input timing
(TA: Recommended operating conditions, VCC =5.0V±10%, VSS= AV SS=0.0V)
Parameter Symbol Pin name Conditions
Value
Unit Remarks
Min
Max
Input pulse
width
tTIWH,
tTIWL
TIN0 to TIN3,
IN0 to IN7,
FRCK0 to FRCK5,
TIOA0, TIOA1,
TIOB0, TIOB1
- 4tCPP - ns
AIN0,AIN1,
BIN0,BIN1,
ZIN0,ZIN1
- 2tCPP - ns
• Timer input timing
V
IH
V
IL
TINx
INx t
TIWL
t
TIWH
V
IH
V
IL
FRCKx
TIOAx,TIOBx
AINx,BINx,ZINx
(6) Trigger input timing
(TA: Recommended operating conditions, VCC =5.0V±10% VSS= AV SS=0.0V)
Parameter Symbol Pin name Conditions
Value
Unit Remarks
Min
Max
Input pulse
width
tTRGH,
tTRGL
INT0 to INT7,
ADTG0 to ADTG2,
RX0 to RX2,
TRG0 to TRG5,
DTTI0,DTTI1
-
5tCPP - ns
1 - µs At Stop mode
• Trigger input timing
V
IH
V
IL
ADTGx
t
TRGL
t
TRGH
V
IH
V
IL
INTx
RXx
TRGx
DTTIx
/'\
SPANSION
‘
(TA: Recommended operating conditions. v“ ’5.(JVil()“/a, V5;’AV;(0.(JV)
Value
Min
Max
Input pulse width
‘NMIL
NMIX
41‘ W
ns
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 149
CONFIDENTIAL
(7) NMI input timing
(TA: Recommended operating conditions, VCC =5.0V±10%, VSS= AV SS=0.0V)
Parameter Symbol
Pin name Conditions
Value
Unit Remarks
Min
Max
Input pulse width
tNMIL
NMIX
-
4tCPP
-
ns
• NMIX input timing
V
IH
NMIX
t
NMIL
V
IH
V
IL
V
IL
/\
SPANSION
‘
(TA: Recommended operarin 1 condition VssiAVssimJV)
Value
Min
Typ
Max
Power supply
voltage range
when power supply
yolruge falls
detection lcv
scl initially
when power supply
voltage rises
Lowwollagc
demotion time
Power supply
voltage
fluctuation rate
(TA: Recommended operating conditions, VssiAVssimJV)
Pin
name
Value
Min
Typ
Max
Power supply
voltage range
When power
supply yolragc falls
when power
suppl
rlscs
Lowwollagc
demotion time
DataSheet
150 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
(8) Low-voltage detection (External low-voltage detection)
(TA: Recommended operating conditions, VSS= AV SS=0.0V)
Parameter Symbol
Pin
name
Conditions
Value
Unit Remarks
Min
Typ
Max
Power supply
voltage range
VDP5 VCC5 - - - 5.5 V
Detection voltage VDL VCC5 *1 3.7 3.9 4.1 V
When power supply
voltage falls and
detection level is
set initially
Hysteresis width VHYS VCC5 - - - 125 mV
When power supply
voltage rises
Low-voltage
detection time
Td - - - - 30 μs
Power supply
voltage
fluctuation rate
- VCC5 - -2 - 2 V/ms *2
*1: If the fluctuation of the power supply has exceeded the detection voltage range within the time less than the
low-voltage detection time (Td), there is the possibility to generate or release after the power supply voltage
has exceeded the detection voltage range.
*2: In order to perform the low-voltage detection at the detection voltage (VDL), be sure to suppress fluctuation
of the power supply within the limits of the power supply voltage fluctuation rate.
(9) Low-voltage detection (Internal low-voltage detection)
(TA: Recommended operating conditions, VSS= AV SS=0.0V)
Parameter Symbol
Pin
name
Conditions
Value
Unit Remarks
Min
Typ
Max
Power supply
voltage range
VRDP5 - - - - 1.3 V
Detection voltage VRDL - * 0.8 0.9 1.0 V
When power
supply voltage falls
Hysteresis width VRHYS - - - - 50 mV
When power
supply voltage
rises
Low-voltage
detection time
- - - - - 30 μs
*: If the fluctuation of the power supply is faster than the low-voltage detection time (Td), there is a possibility to
generate or release after the power supply voltage has exceeded the detection voltage range.
/'\
SPANSION
‘
(TA: Recommended operating! commons, v“ *AVU ’5.(JVil()"/a, V55*A\75(().DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 151
CONFIDENTIAL
(10) Clock output timing
(TA: Recommended operating conditions, VCC=AV CC=5.0V±10%, VSS= AV SS=0.0V)
Parameter Symbol Pin
name
Conditions
Value
Unit Remarks
Min
Max
Cycle time
tCYC
SYSCLK
-
tCPT
-
ns
SYSCLK ↑
→ SYSCLK ↓
tCHCL SYSCLK (1/2 tCYC)- 7 (1/2 tCYC)+ 7 ns
SYSCLK ↓
→ SYSCLK ↑
tCLCH SYSCLK (1/2 tCYC)- 7 (1/2 tCYC)+ 7 ns
SYSCLK V
OL
=V
CC
/2
t
CYC
t
CLCH
t
CHCL
V
OH
=V
CC
/2
V
OH
/\
SPANSION
‘
AV“*5.DataSheet
152 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
(11) External bus I/F (synchronous mode) timing
(TA: Recommended operating conditions, VCC =AV CC=5.0V±10%, VSS= AV SS=0.0V)
(External load capacitance 50pF)
Parameter Symbol Pin name
Value
Unit Remarks
Min
Max
Cycle time
tCYC
SYSCLK
25
-
ns
ASX delay time
t
CHASL
,
tCHASH
SYSCLK,
ASX
0.5 18.0 ns
CS0X to CS3X
delay time
t
CHCSL
,
tCHCSH
SYSCLK,
CS0X to CS3X
0.5 18.0 ns
A00 to A21
delay time
t
C H AV
,
tCHAX
SYSCLK,
A00 to A21
0.5 18.0 ns
RDX delay time
t
CHRL
,
tCHRH
SYSCLK,
RDX
0.5 18.0 ns
RDX minimum pulse tRLRH RDX
t
CYC
×
2 - 20
- ns
RWT=1, set RWT to 1 or
more.
*
Data setup → RDX ↑
time
tDSRH RDX,
D16 to D31
18 + tCYC
- ns
RWT=1, set RWT to 1 or
more.
*
RDX ↑ → data hold
tRHDH
0
-
ns
WRnX delay time
t
CHWL
,
tCHWH
SYSCLK,
WR0X, WR1X
0.5 18.0 ns
WRnX
minimum pulse width
tWLWH WR0X, WR1X tCYC - 10 - ns WWT=0*
SYSCLK ↑ →
data output time
tCHDV SYSCLK,
D16 to D31
0.5 18.0 ns
SYSCLK ↑ →
data hold time
tCHDX - 18 ns Set WRCS to 1 or more.
SYSCLK ↑ →
address output time
tCHMAV
SYSCLK,
D16 to D31
0.5 18.0 ns
SYSCLK ↑ →
address hold time tCHMAX - 18 ns
In multiplex mode, set as
follows:
• Set CSWR and CSRD to 2
or more.
• Set to ADCY>ASCY.
To prevent protocol
violation, satisfy the
following conditions:
ADCY + 1 ≤ ACS + CSRD
ADCY + 1 ≤ ACS + CSWR
ASCY + 1 ≤ ACS + CSRD
ASCY + 1 ≤ ACS + CSWR
For details, see Hardware
Manual.
*: If the bus is expanded by automatic wait insertion or RDY input, add time (tCYC × the number of expanded
cycles) to the rated value.
/'\
SPANSION
‘
It '1
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 153
CONFIDENTIAL
External bus I/F (synchronous mode, read operation, and multiplex mode) timing
ACS=0
t
CHCSL
t
CHASL
t
CYC
t1 t2 t3 t4
RDCS=0
t
CHRH
t
CHCSH
t
RHDH
t
DSRH
t
CHMAX
ADCY=1
t
CHMAV
CSRD=2
ASCY=0
t
CHASH
t
CHRL
RWT=1 t
RLRH
Valid Address Read Data
SYSCLK
ASX
CS0X to CS3X
RDX
D16 to D31
External bus I/F (synchronous mode, read operation, and split mode) timing
ACS=0
t
CHCSL
t
CHASL
t
CYC
t1 t2 t3 t4
t
CHCSH
t
CHAX
RDCS=0
t
CHRH
t
RHDH
t
DSRH
CSRD=0
ASCY=0
t
CHASH
t
CHRL
t
CHAV
RWT=1 t
RLRH
Valid Address
Read Data
SYSCLK
ASX
CS0X to CS3X
RDX
D16 to D31
A00 to A21
DataSheet
154 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
External bus I/F (synchronous mode, write operation, and multiplex mode) timing
ACS=0
t
CHCSL
t
CHASL
t
CYC
t1 t2 t3 t4
t
CHDX
t
CHCSH
t
CHDV
ADCY=1
t
CHMAV
CSWR=2
WWT=0
ASCY=0
t
CHASH
t
CHWL
t
WLWH
t
CHWH
WRCS=1
Valid Address Write Data
SYSCLK
ASX
CS0X to CS3X
WR0X,WR1X
D16 to D31
External bus I/F (synchronous mode, write operation, and split mode) timing
ACS=0
t
CHCSL
t
CHASL
t
CYC
t1 t2 t3 t4
t
CHCSH
t
CHAX
WRCS=1
t
CHDX
t
CHDV
CSWR=0
WWT=0
ASCY=0
t
CHASH
t
CHWL
t
CHAV
t
WLWH
t
CHWH
Valid Address
Write Data
SYSCLK
ASX
CS0X to CS3X
WR0X,WR1X
D16 to D31
A00 to A21
/'\
SPANSION
AVL(*5.(JVil()”/a, V55*A\75(().(JV)
(External load capacitance sum
Pin Value
name Min Max
Cycle time lrw SYSCLK 25 , nS
Address setup 4 RWT’l, set RWT to l or
RDX T time more.
RDX T ~>
Address hold
Data setup RWT’l, set RWT to l or
RDX T time more.
RDX T ~>
Data hold
Address setup 4 wwro.‘
WRnX T time
WRnX T a Set WRCS to 1 or more.
Address hold
Data setup WWT*0.'
WRnX T time
WRnX T a Set WRCS to 1 or more.
Data hold
Address setup »
ASX T time
ASCY’Ul
In mulliplcx mode, set as
follows:
. Set CSW
or more.
. Set to ADC
To preveri
violation
followin
ADCY +
ADCY +
ASCY +
ASCY +
For dctai
Manual.
‘
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 155
CONFIDENTIAL
(12) External bus I/F (Asynchronous mode) timing
(TA: Recommended operating conditions, VCC = AV CC=5.0V±10%, VSS= AV SS=0.0V)
(External load capacitance 50pF)
Parameter Symbol Pin
name
Value
Unit Remarks
Min
Max
Cycle time
tCYC
SYSCLK
25
-
ns
Address setup →
RDX ↑ time
tASRH RDX,
A00 to
A21
2 × tCYC – 12 2 × tCYC + 12 ns
RWT=1, set RWT to 1 or
more.
*
RDX ↑ →
Address hold
tRHAH tCYC – 12 tCYC + 12 ns Set RDCS to 1 or more.
Data setup
→ RDX ↑ time
tDSRH RDX,
D16 to
D31
18 +tCYC - ns
RWT=1, set RWT to 1 or
more.
RDX ↑ →
Data hold
tRHDH 0 - ns
Address setup →
WRnX ↑ time
tASWH WR0X to
WR1X,
A00 to
A21
tCYC – 12 tCYC + 12 ns
WWT=0.*
WRnX ↑ →
Address hold
tWHAH tCYC – 12 tCYC + 12 ns
Set WRCS to 1 or more.
Data setup
→ WRnX ↑ time
tDSWH WR0X to
WR1X,
D16 to
D31
tCYC – 16 tCYC + 16 ns
WWT=0.*
WRnX ↑ →
Data hold
tWHDH tCYC – 16 tCYC + 16 ns
Set WRCS to 1 or more.
Address setup →
ASX ↑ time
tMASASH
ASX,
D16 to
D31
tCYC – 16 tCYC + 16 ns
ASCY=0.
ASX ↑ →
Address hold tMASHAH tCYC – 16 tCYC + 16 ns
In multiplex mode, set as
follows:
• Set CSWR and CSRD to 2
or more.
• Set to ADCY>ASCY.
To prevent protocol
violation, satisfy the
following conditions:
ADCY + 1 ≤ ACS + CSRD
ADCY + 1 ≤ ACS + CSWR
ASCY + 1 ≤ ACS + CSRD
ASCY + 1 ≤ ACS + CSWR
For details, see Hardware
Manual.
*: If the bus is expanded by automatic wait insertion or RDY input, add time (tCYC × the number of expanded
cycles) to the rated value.
/\
SPANSION
‘
M
(2
l3
l4
l5
CSRD=2
ADCY=1
DataSheet
156 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
External bus I/F (asynchronous mode, read operation, and multiplex mode) timing
ACS=0
t
CYC
t1 t2 t3 t4 t5
RDCS=1
t
RHDH
t
DSRH
ADCY=1
t
MASASH
CSRD=2
ASCY=0
t
MASHAH
RWT=1
Read Data
SYSCLK
ASX
CS0X to CS3X
RDX
D16 to D31 Valid Address
External bus I/F (asynchronous mode, read operation, and split mode) timing
ACS=0
tCYC
t1 t2 t3 t4
RDCS=1
tRHAH
tASRH
tRHDH
tDSRH
CSRD=0
ASCY=0
RWT=1
Valid Address
Read Data
SYSCLK
ASX
CS0Xto CS3X
RDX
D16 to D31
A00 to A21
t5
/'\
SPANSION
M (2 (3 (4
WR1X CSWR=2 \
ADCY=I
WR1X
‘
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 157
CONFIDENTIAL
External bus I/F (asynchronous mode, write operation, and multiplex mode) timing
ACS=0
t
CYC
t1 t2 t3 t4
WRCS=1
t
DSWH
t
WHDH
ADCY=1
t
MASASH
CSWR=2
WWT=0
ASCY=0
t
MASHAH
SYSCLK
ASX
CS0X to CS3X
WR0X, WR1X
D16 to D31 ValidAddress Write Data
External bus I/F (asynchronous mode, write operation, and split mode) timing
ACS=0
t
CYC
t1 t2 t3 t4
t
ASWH
t
WHDH
t
WHAH
t
DSWH
WWT=0
CSWR=0
ASCY=0
Write Data
SYSCLK
ASX
CS0X to CS3X
WR0X, WR1X
D16 to D31
A00 to A21
WRCS=1
Valid Address
/\
SPANSION
‘
AV“ ’5.(JVil()"/a, V55*A\75(().DataSheet
158 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
(13) External bus I/F (ready) timing
(TA: Recommended operating conditions, VCC=AV CC=5.0V±10%, VSS= AV SS=0.0V)
(External load capacitance 50pF)
Parameter Symbol Pin name
Value
Unit Remarks
Min
Max
Cycle time
tCYC
SYSCLK
50
-
ns
If using RDY, set SYSCLK
to 20 MHz or less.
RDY setup time →
SYSCLK ↑
tRDYS
SYSCLK,
RDY
28
-
ns
SYSCLK ↑ →
RDY hold time
tRDYH
SYSCLK,
RDY
0
-
ns
External bus I/F (ready) timing
t
CYC
t1 t2 t3 t4
t
RDYS
t
RDYH
CSRD=2
ASCY=0
ACS=0
RWT=2
RDCS=0
SYSCLK
ASX
CS0X to CS3X
RDX
RDY
t5 t6
Auto wait cycle
Added cycle by RDY
/'\
SPANSION
(TA: Recommended operating conditions, v.1 ’5.DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 159
CONFIDENTIAL
5. A/D Converter
(1) Electrical Characteristics
(TA: Recommended operating conditions, VCC =5.0V±10%, AVCC=5.0V±10%, VSS= AV SS=0.0V)
Parameter Symbol
Pin name
Value
Unit Remarks
Min
Typ
Max
Resolution
-
-
-
-
12
bit
Non linearity error
-
-
-4.0
-
+4.0
LSB
Differential linearity
error
- - -1.9 - +1.9 LSB
Zero transition
voltage
VOT AN0 to AN23
AV R L +
0.5LSB-20
-
AV R L +
0.5LSB+20
mV 1LSB=
(VFST-VOT)/
4094
Full-scale transition
voltage
VFST AN0 to AN23
AV R H -
1.5LSB-20
-
AV R H -
1.5LSB+20
mV
Sampling time
tSMP
-
0.3
-
12
µs
*1
Compare time
tCMP
-
0.7
-
28
µs
*1
A/D conversion time
tCNV
-
1.0
-
40
µs
*1
Analog port input
current
IAIN AN0 to AN23 -1.0 - 1.0 µA
V
AV S S
≤
VAIN ≤ VAVCC
Analog input voltage
VAIN
AN0 to AN23
AV SS
-
AV R H
V
Reference voltage
AV R H
AVRH1,
AVRH2,
AVRH3
4.5 - 5.5 V Avcc ≥AV R H
AV R L
AV R L 1 ,
AV R L 2 ,
AV R L 3
- 0.0 - V
Power supply current
IA
AV C C 3
- 1.5 2.1
mA
3 units
operating
IAH - - 25
µA
3 units
operating
*2
IR AVRH1,
AVRH2,
AVRH3
- 3 6 mA
3 units
operating
IRH - - 4.8 µA
3 units
operating
*2
Variation between
channels
- AN0 to AN23 - - 4 LSB
*1: Time for each channel.
*2: The power supply current (Vcc=AVcc=5.0V) is specified if the A/D converter is not operating and CPU is
stopped.
/\
SPANSION
‘
niuerenual Imeamy error
Actua‘ converswon L
charactensucs 4— 7
(1 LSE (N 71p v.77)
vm - {1LSBX(N-1) + voT)
1LSB
vm , m - vm
WLSB
VFsT - VoT
4094
0/0 .
HA
HA
DataSheet
160 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
(2) Definition of Terms
• Resolution: Analog variation that is recognized by an A/D converter.
• Linearity error : Deviation of the actual conversion characteristics from a straight line that connects the
zero transition point ("0000 0000 0000"←→"0000 0000 0001") to the full-scale
transition point ("1111 1111 1110"←→"1111 1111 1111").
• Differential linearity error: Deviation of the input voltage from the ideal value that is required to
change the output code by 1LSB.
Linearity error Differential linearity error
Linearity error of digital output N = V
NT
- {1LSB×(N-1) + V
OT
}[LSB]
1LSB
Differential linearity error of digital output N = V
(N + 1)T
- V
NT
-1 LSB [LSB]
1LSB
1LSB = V
FST
- V
OT
[V]
4094
V
OT
: Voltage at which the digital output changes from "000
H
" to "001
H
".
V
FST
: Voltage at which the digital output changes from "FFE
H
" to "FFF
H
".
AVSS
(AVRL)
AVRH AVRH
Actual conversion
characteristics
{1 LSB (N - 1) + VOT}
AVSS
(AVRL)
VFST
VNT
VOT (Actually-measured value)
V(N+1)T
VNT
Ideal characteristics
Actual conversion
characteristics
Actual conversion
characteristics
Actual conversion
characteristics
Ideal characteristics
Digital output
(Actually-measured value)
(Actually-
measured
value)
(Actually-measured value)
Analog input Analog input
(Actually-measured
value)
Digital output
N - 1
N - 2
N
N + 1
FFF
FFE
FFD
004
003
002
001
(3) Notes on Using A/D Converter
<About the output impedance of the analog input of external circuit>
When the external impedance is too high, the sampling time for analog voltages may not be sufficient.
In this case, it is recommended to connect the capacitor (approx. 0.1 µF) to the analog input pin.
• Analog input circuit model
R C
12bit A/D 1.9kΩ (max) 8.30pF (max) (4.5V Avcc 5.5V)
Note: Listed values must be considered as reference values.
R
C
Sampling ON
Comparator
Analog input
/'\
SPANSION
(TA: Recommended operating conditions, vavmstVium, vssiAvssionw
Value
Min
Typ
Max
Resolution
[0
bil
Differential linearity
error
Voltage Is 0 5V [0 45V
|
‘
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 161
CONFIDENTIAL
6. D/A Converter
(TA: Recommended operating conditions, VCC=AV CC=5.0V±10%, VSS= AV SS=0.0V)
Parameter Symbol Pin name
Value
Unit Remarks
Min
Typ
Max
Resolution
-
-
-
-
10
bit
Differential linearity
error
- - -4.0 - +4.0 LSB When the analog output
voltage is 0.5V to 4.5V
/\
SPANSION
‘
Value
Min
Max
x Kbytc sector"
CXClu
time
x Kbytc sector"
lncllld
time
a4 Kbytc sector "
exclu
time
a4 Kbytc sector "
lnellld
time
Excluding overhead time at system
level
Excluding overhead time at system
level
Excluding overhead time at system
level
1.000 cycles 20 years,
10000 cycles 10 years
100.000 cycles 5 years
Average temperature T,r+xs°c '3
DataSheet
162 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
7. Flash memory
(1) Electrical Characteristics
Parameter
Value
Unit Remarks
Min
Typ
Max
Sector erase time
- 200 800 ms
8 Kbyte sector*1
excluding internal preprogramming
time
- 300 1100 ms
8 Kbyte sector*1
including internal preprogramming
time
- 400 2000 ms
64 Kbyte sector *1
excluding internal preprogramming
time
- 700 3700 ms
64 Kbyte sector *1
including internal preprogramming
time
8-bit writing time - 9 288 µs
Excluding overhead time at system
level
*1
16-bit writing time - 12 384 µs
Excluding overhead time at system
level
*1
ECC writing time - 9 288 µs
Excluding overhead time at system
level
*1
Erase cycle*2/
Data retention time
1,000 cycles/20 years,
10,000 cycles/10 years,
100,000 cycles/5 years
- - -
Average temperature T
A
=+85°C *3
*1: The guaranteed value for erase up to 100,000 cycles
*2: Number of erase cycles for each sector
*3: This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at + 85°C).
/‘\
SPANSION
‘
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 163
CONFIDENTIAL
(2) Notes
While the Flash memory is written or erased, shutdown of the external power supply (Vcc) is prohibited.
In the application system where Vcc might disappear while writing, be sure to turn the power off by using
an external low-voltage detector.
To put it concretely, after the external power supply voltage falls below the detection voltage (VDL
*), hold
Vcc at 2.7V or more within the duration calculated by the following expression:
Td*[µs] + (period of PCLK [µs] × 257) + 50[µs]
*: See "4. AC characteristics (8) Low-voltage detection (External low-voltage detection)."
/\
S PA N 5 IO N
‘
(TA: Recommended operating eondhions, V“ ’ AV“ ’5.UViS“/a, Vss’AVss’OXJV)
Val u e
Min Typ Max
()ulpm volrage
(amplitude)
()ulpm volrage
(displacemem)
()ulpm eurrem , , 1 mA
Sening wirh the
register
Resolver Amplhude AREFZVZXJ , AREF2+2lU V
response Maximum inpur
signnl frequency
Amplhude (J , AVCCO V More ‘han 2VW
Phase difference
from resolver
dereetion signal
Angle accurncy Vununen when
(eonversio
accuracy)
Resolution , 12 , bir
()ulpm delny 1.1 , 21 us
When bandwidrh
lleHz mode
When bandwidrh
GUOkHZ mode
Resolution , 0.261 , rps/LSB
Reference
ompul
voltage
Tracking loop When bandwidrh
characterist luXkHz mode
(OdB eross When bandwidrh
frequency) suOHz mode
Tracking loop When bandwidrh
characteristi luXkHz mode
(r3dB cross When bandwidrh
frequency) suOHz mode
When bandwidrh
lleHz mode
When bandwidrh
fiUOHz mode
When bandwidrh
lleHz mode
When bandwidrh
fiUOHz mode
When bandwidrh
lleHz mode
When bandwidrh
fiUOHz mode
DataSheet
164 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
8. R/D Converter
(TA: Recommended operating conditions, VCC = AVCC =5.0V±5%, VSS= AV SS=0.0V)
Parameter
Value
Unit Remarks
Min
Typ
Max
Excitation
signal
output
Output voltage
(amplitude)
0.4VCC-1% 0.4VCC 0.4VCC+1% V
Output voltage
(displacement)
-0.4VCC+(VCC/2) - 0.4VCC+(VCC/2) V
Output current
-
-
1
mA
Frequency - 10 or 20 - kHz
Setting with the
register
Resolver
response
signal
*1
Amplitude
AREF2-2.0
-
AREF2+2.0
V
Maximum input
frequency
- - 24 kHz
Excitation
input
signal*2
Amplitude
0
-
AV C C 0
V
More than 2Vp-p
Phase difference
from resolver
detection signal
-45 - 45 °
Angle
output
Angle accuracy
(conversion
accuracy)
-4 - 4 LSB
Variation when
pausing: ±1LSB
Resolution
-
12
-
bit
Output delay
1.1
-
2.1
μs
Angular
velocity
output
Maximum
angular velocity
- - 4000 rps
When bandwidth
1.8kHz mode
- - 3000 rps
When bandwidth
600kHz mode
Resolution
-
0.261
-
rps/LSB
Reference
output
voltage
AREF2 output
voltage AV C C 0 / 2 -3% - AVCC0/2+3% V
Operating
characteris
tics
Tracking loop
characteristics
(0dB cross
frequency)
- - 1.2 kHz
When bandwidth
1.8kHz mode
*3
- - 400 Hz
When bandwidth
600Hz mode
*3
Tracking loop
characteristics
(-3dB cross
frequency)
- - 1.8 kHz
When bandwidth
1.8kHz mode
*3
- - 600 Hz
When bandwidth
600Hz mode
*3
Maximum
tracking rate
- - 4000 rps
When bandwidth
1.8kHz mode
- - 3000 rps
When bandwidth
600Hz mode
Settling time
(179° step).
- - 4 ms
When bandwidth
1.8kHz mode
- - 12 ms
When bandwidth
600Hz mode
Maximum
angular velocity
- - 1,000,000 rad/s2
When bandwidth
1.8kHz mode
- - 150,000 rad/s2
When bandwidth
600Hz mode
*1: Corresponding pin: COS_PLUS,COS_MINUS,SIN_PLUS,SIN_MINUS
*2: Corresponding pin: MAG_PLUS,MAG_MINUS
*3: When signal amplitude is nominal
/‘\
SPANSION
‘
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 165
CONFIDENTIAL
EXAMPLE CHARACTERISTICS
This characteristic is an actual value of the arbitrary sample. It is not the guaranteed value.
• MB91F585LA/F586LA/F587LA/F585LC/F586LC/F587LC
• MB91F585LB/F586LB/F587LB/F585LD/F586LD/F587LD
10.00
100.00
-50 050 100 150
I
CC
5[mA]
T
A
[ºC]
normal operation
(1)Fcp=128MHz, Fcpp=32MHz, FlexRay=ON, RDC=OFF
(2)Fcp=128MHz, Fcpp=32MHz, FlexRay=OFF, RDC=ON
(3)Fcp=80MHz, Fcpp=40MHz, FlexRay=ON, RDC=OFF
(V
CC
= 5.5V)
(1)
(2)
(3)
(4)
(4)Fcp=80MHz, Fcpp=40MHz, FlexRay=OFF, RDC=ON
10.00
100.00
-50 050 100 150
ICC5[mA]
TA[ºC]
normal operation
(VCC = 5.5V)
(1)
(2)
(3)
(4)
(1)Fcp=128MHz, Fcpp=32MHz, FlexRay=ON, RDC=Not provided
(2)Fcp=128MHz, Fcpp=32MHz, FlexRay=OFF, RDC=Not provided
(3)Fcp=80MHz, Fcpp=40MHz, FlexRay=ON, RDC=Not provided
(4)Fcp=80MHz, Fcpp=40MHz, FlexRay=OFF, RDC=Not provided
/\
SPANSION’
‘
DataSheet
166 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
• MB91F585LA/F586LA/F587LA/F585LB/F586LB/F587LB/
F585LC/F586LC/F587LC/F585LD/F586LD/F587LD
10.000
100.000
-50 050 100 150
I
CC
S5/I
CC
BS5 [mA]
T
A
[ºC]
sleep mode
CPU Sleep(128MHz)
BUS Sleep (128MHz)
(V
CC
= 5.5V)
/‘\
SPANSION
‘
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 167
CONFIDENTIAL
• MB91F585LA/F586LA/F587LA/F585LB/F586LB/F587LB/
F585LC/F586LC/F587LC/F585LD/F586LD/F587LD
0.001
0.010
0.100
1.000
10.000
-50 050 100 150
ICCT5 [mA]
TA[ºC]
Watch mode
Main osc (4MHz)
External clock (4MHz)
(VCC = 5.5V)(VCC = 5.5V)
0.001
0.010
0.100
1.000
10.000
-50 050 100 150
I
CC
H5 [mA]
T
A
[ºC]
Stop mode
(V
CC
= 5.5V)
/\
SPANSION’
‘
DataSheet
168 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
• MB91F585LA/F586LA/F587LA/F585LB/F586LB/F587LB/
F585LC/F586LC/F587LC/F585LD/F586LD/F587LD
0.01
0.10
1.00
10.00
100.00
1000.00
-50 050 100 150
I
CC
T52 [µA]
T
A
[ºC]
Watch mode(power off)
Main osc (4MHz)
External clock (4MHz)
(V
CC
= 5.5V)(V
CC
= 5.5V)
0.01
0.10
1.00
10.00
100.00
1000.00
-50 050 100 150
ICCH52 [µA]
TA[ºC]
Stop mode(power off)
(VCC = 5.5V)
ORDERING INFORMATION
/'\
SPANSION
‘
Part number
Package‘
MB‘) lFSXSLAPMCrGTE]
MB‘) lFSXéLAPMCrGTEl
MB‘) lFSX7LAPMCrGTE]
MB91F585LBPMCVGTE1
MB91F586LBPMCrGTEl
MB91F587LBPMCVGTE1
MB91F585LCPMCVGTE1
MB91F586LCPMCVGTE1
MB91F587LCPMCVGTE1
MB‘) lFSXSLDPMCrGTE]
MB‘) lFSXéLDPMCrGTEl
MB‘) lFSX7LDPMCrGTE]
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 169
CONFIDENTIAL
ORDERING INFORMATION
Part number
Package*
MB91F585LAPMC-GTE1
MB91F586LAPMC-GTE1
MB91F587LAPMC-GTE1
144-pin plastic LQFP
(FPT-144P-M08)
MB91F585LBPMC-GTE1
MB91F586LBPMC-GTE1
MB91F587LBPMC-GTE1
144-pin plastic LQFP
(FPT-144P-M08)
MB91F585LCPMC-GTE1
MB91F586LCPMC-GTE1
MB91F587LCPMC-GTE1
144-pin plastic LQFP
(FPT-144P-M08)
MB91F585LDPMC-GTE1
MB91F586LDPMC-GTE1
MB91F587LDPMC-GTE1
144-pin plastic LQFP
(FPT-144P-M08)
*: For details of the package, see " PACKAGE DIMENSIONS ".
/\
SPANSION
‘
‘~ H 145m [:55
H (0061002)
WEEHmEHHHHHHHHHHHHHHHHHHHHHHHHHHH’
NHWHWHNHHNHHN
,H‘HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
\ )1 .v A“ 0501020
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH \ (nznzonar
" \ K19 ‘ 060:015
xl/ , / “ Wi‘
DataSheet
170 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
PACKAGE DIMENSIONS
144-pin plastic LQFP Lead pitch 0.50 mm
Package width
×
package length 20.0
×
20.0 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height
1.70 mm MAX
Weight 1.20 g
Code
(Reference)P-LFQFP144-20
×
20-0.50
144-pin plastic LQFP
(FPT-144P-M08)
(FPT-144P-M08)
C
2003-2010 FUJITSU SEMICONDUCTOR LIMITED F144019S-c-4-8
Details of "A" part
0.25(.010)
(Stand off)
(.004±.004)
0.10±0.10
(.024±.006)
0.60±0.15
(.020±.008)
0.50±0.20
1.50
+0.20
–0.10
+.008
–.004
.059
0°~8°
0.50(.020)
"A"
0.08(.003)
0.145±0.055
(.006±.002)
LEAD No.
136
INDEX
37
72
73108
109
144
0.22±0.05
(.009±.002)
M
0.08(.003)
22.00±0.20(.866±.008)SQ
(Mounting height)
*20.00±0.10(.787±.004)SQ
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Note 1) *:Values do not include resin protrusion.
Resin protrusion is +0.25(.010)Max(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
/'\
SPANSION
‘
Major Changes
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STMCRDO >STMCRO
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 171
CONFIDENTIAL
Major Changes
Page Section Change Results
Revision 1.0
-
-
Initial release.
Revision 1.1
-
-
Company name and layout design change
Revision 2.0
2 ■FEATURES
The feature of CR oscillation is corrected.
Oscillation frequency: 100kHz, with frequency accuracy ± 10%
↓
Oscillation frequency: 100kHz, with frequency accuracy ± 50%
(pre-trimming)
6, 7 ■FEATURES
The configuration of Waveform generator is corrected.
1 unit (6 channels) + 1 channel
↓
2 unit (7channels)
28 ■I/O CIRCUIT TYPE
The figure of type "L" is corrected.
↓
28, 29 ■I/O CIRCUIT TYPE
The specification of "H" level input voltage and "L" level input voltage of
FlexRay is corrected.
FlexRay input (0.65Vcc/0.35Vcc)
↓
FlexRay input (0.7Vcc/0.3Vcc)
39, 40 ■MEMORY MAP
The memory map is corrected.
The address of "Reset vector table" and "Interrupt vector table" are added.
62, 63, 64,
97, 98, 99
■I/O MAP
Address: 001504H,001528H, 00154CH, 001570H,
001594H,
The attribution of register is changed.
B,H,W
↓
H,W
62, 97 ■I/O MAP
Address:00150CH
The register name is corrected.
STMCR00 → STMCR0
TTL schmitt input
TTL schmitt input
Digital output
/\
SPANSION
‘
.I 0 MAP
00150Eh,
001513"
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SCSCRO. SCSTR30r ScsTRzor ScsTRlor SCSTRDO
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0 ,0
1
70000000 70000000 70000000 00000000
Th: remark rrr"0p:r..urrg mmpenflure" .: correcwd
* I0
*i0, *Il
Th: cxnl' mury um: “11 r» added
“I1 When n 25°C mnmu your m1:s represenmuvt
”Smumhmg can -
S
Th: remark ur'Tlprrnflmg \enrh:r..mr:" is added
*2
Th: :xhlunrdrrry mu: .: corrcfled
Th: speclfiuuuun or"H" level Inplfl Vuhuge urr'oru , P007, POIO lb
65
l
Mm 0 7 x Vt:
Th: speclfiuuuun or"L“ lam! Inpu| mlmg: urP003 , P007 P010 r»
x03
i
Max 0 1 x V00
IELECTRICAL CHARACTERISTICS
4 AC C1mr..c|:r.
(1) Mum Clock Timing
Th: specificuuun of"The BullHn CR use mum frequency” .: mnecwd
m 9
x
l
Mm 50km
ML 150m;
DataSheet
172 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Page Section Change Results
62, 97
■I/O MAP
Address: 00150EH, 001510H, 001511H, 001512H,
001513H
The registers are deleted.
SCSCR0, SCSTR30, SCSTR20, SCSTR10, SCSTR00
73, 108 ■I/O MAP
Address:00D310H
The initial value of MHDS is corrected.
-0000000 -0000000 -0000000 10000000
↓
-0000000 -0000000 -0000000 00000000
114 ■ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
The remark of "Operating temperature" is corrected.
*10
↓
*10, *11
115 ■ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
The explanatory note *11 is added.
*11: When it is used exceeding TA=125°C, contact your sales representative.
116 ■ELECTRICAL CHARACTERISTICS
2. Recommended operating conditions
"Smoothing capacitor" is changed.
Smoothing capacitor*
↓
Smoothing capacitor*1
116 ■ELECTRICAL CHARACTERISTICS
2. Recommended operating conditions
The remark of “Operating temperature” is added.
*2
116 ■ELECTRICAL CHARACTERISTICS
2. Recommended operating conditions
The explanatory note is corrected.
*: For connection of smoothing capacitor CS, see the figure below.
↓
*1: For connection of smoothing capacitor CS, see the figure below.
*2: When it is used exceeding TA=125°C, contact your sales representative.
117 ■ELECTRICAL CHARACTERISTICS
3. DC Characteristics
The specification of "H" level input voltage of P003 - P007, P010 is
corrected.
Min:0.65 ×Vcc
↓
Min: 0.7 × Vcc
118 ■ELECTRICAL CHARACTERISTICS
3. DC Characteristics
The specification of "L" level input voltage of P003 - P007, P010 is
corrected.
Max:0.35 ×Vcc
↓
Max: 0.3 × Vcc
124
■ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(1) Main Clock Timing
The remark of "CAN PLL jitter" is deleted.
124
■ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(1) Main Clock Timing
The specification of "The Built-in CR oscillation frequency" is corrected.
Min: 90kHz,
Max: 110kHz
↓
Min:50kHz
Max:150kHz,
/'\
SPANSION
‘
IELECTRICAL CHARACTERISTICS
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um
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IEXAMPLE CHARACTERISTICS
“-EXAMPLE CHARACTERISTICS \wa added
DataSheet
August 22, 2014, MB91F587LA_DS705-00012-2v0-E 173
CONFIDENTIAL
Page Section Change Results
137, 139,
141, 143
■ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(4) Multi-function Serial
(4-1) CSIO timing (SMR:MD2-0="010"b)
(4-1-5) When the serial chip select is used
(SCSCR:CSEN=1)
• Serial clock output signal detect level "H"
(SMR,SCSFR:SCINV=0)
• Serial chip select inactive level "H"
(SCSCR,SCSFR:CSLVL=1)
(4-1-6) When the serial chip select is used
(SCSCR:CSEN=1)
• Serial clock output signal detect level "L"
(SMR,SCSFR:SCINV=1)
• Serial chip select inactive level "H"
(SCSCR,SCSFR:CSLVL=1)
(4-1-7) When the serial chip select is used
(SCSCR:CSEN=1)
• Serial clock output signal detect level "H"
(SMR,SCSFR:SCINV=0)
• Serial chip select inactive level "L"
(SCSCR,SCSFR:CSLVL=0)
(4-1-8) When the serial chip select is used
(SCSCR:CSEN=1)
• Serial clock output signal detect level "L"
(SMR,SCSFR:SCINV=1)
• Serial chip select inactive level "L"
(SCSCR,SCSFR:CSLVL=0)
The specifications of tCSSI, tCSHI and tCSDI are corrected.
·tCSSI
Min: -50-tCSSU*1
Max: +0-tCSSU*1
↓
Min: tCSSU*1+0
Max: tCSSU*1+50
·tCSHI
Min: +0+tCSHD*2
Max: +50+tCSHD*2
↓
Min: tCSHD*2-50
Max: tCSHD*2+0
·tCSDI
Min: -50+tCSDS*3
Max: +50+tCSDS*3
↓
Min: -50+5tCPP+tCSDS*3
Max: +50+5tCPP+tCSDS*3
146
■ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(4) Multi-function Serial
(4-4) I2C timing (SMR:MD2-0="100"b)
The explanatory note *1 is corrected.
*1: R and C represent the pull-up resistance and load capacitance of the SCL
and SDA output lines, respectively. VP shows that the power supply voltage
of the pull-up resistor and IOL shows the VOL guarantee current.
↓
*1: R and CL represent the pull-up resistance and load capacitance of the
SCL and SDA output lines, respectively. VP shows that the power supply
voltage of the pull-up resistor and IOL shows the VOL guarantee current.
162 ■ELECTRICAL CHARACTERISTICS
7. Flash memory
Item name is changed.
(1) Main Flash
↓
(1) Electrical Characteristics
162 ■ELECTRICAL CHARACTERISTICS
7. Flash memory
The remark of " Erase cycle*2 / Data retention time " is corrected.
Temperature at writing/erasing
Tj <+105°C
Average temperature TA=+85°C *3
↓
Average temperature TA=+85°C
*3
164 ■ELECTRICAL CHARACTERISTICS
8. R/D Converter
The remark of " Amplitude" of "Resolver response signal*1 " is added.
More than 2Vp-p
165-168
■EXAMPLE CHARACTERISTICS
"■EXAMPLE CHARACTERISTICS" is newly added.
/\
SPANSION’
‘
Colophon
DataSheet
174 MB91F587LA_DS705-00012-2v0-E, August 22, 2014
CONFIDENTIAL
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use
where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not
be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the
products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire
protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in
this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and
Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the
prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a
Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any
product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to
its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party
rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind
arising out of the use of the information in this document.
Copyright © 2012-2014 Spansion All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® EclipseTM,
ORNANDTM and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States
and other countries. Other names used are for informational purposes only and may be trademarks of their respective
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