LTC2220-1 Datasheet by Analog Devices Inc.

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L7IM TECHNOLOGY ? l 4k I I | | mm mm L7LJHMEGB
LTC2220-1
1
2220_1fa
–
+
INPUT
S/H
CORRECTION
LOGIC
OUTPUT
DRIVERS
12-BIT
PIPELINED
ADC CORE
CLOCK/DUTY
CYCLE
CONTROL
FLEXIBLE
REFERENCE
D11
•
•
•
D0
ENCODE
INPUT
REFH
REFL
ANALOG
INPUT
22201 TA01
CMOS
OR
LVDS
0.5V
TO 3.6V
3.3V
VDD
OVDD
OGND
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
FEATURES
DESCRIPTIO
U
TYPICAL APPLICATIO
U
The LTC
®
2220-1 is a 185Msps, sampling 12-bit A/D
converter designed for digitizing high frequency, wide
dynamic range signals. The LTC2220-1 is perfect for
demanding communications applications with AC perfor-
mance that includes 67.5dB SNR and 80dB spurious free
dynamic range for signals up to 170MHz. Ultralow jitter of
0.15ps
RMS
allows undersampling of IF frequencies with
excellent noise performance.
DC specs include ±0.7LSB INL (typ), ±0.5LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.5LSB
RMS
.
The digital outputs can be either differential LVDS, or
single-ended CMOS. There are three format options for
the CMOS outputs: a single bus running at the full data rate
or two demultiplexed buses running at half data rate with
either interleaved or simultaneous update. A separate
output power supply allows the CMOS output swing to
range from 0.5V to 3.6V.
The ENC
+
and ENC
–
inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL, or CMOS
inputs. An optional clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
APPLICATIO S
U
SFDR vs Input Frequency
0 600500400
100 200 300
INPUT FREQUENCY (MHz)
SFDR (dBFS)
80
90
100
22201 TA01b
70
60
40
50
4th OR HIGHER
2nd OR 3rd
12-Bit,185Msps ADC
■
Sample Rate: 185Msps
■
67.5dB SNR up to 140MHz Input
■
80dB SFDR up to 170MHz Input
■
775MHz Full Power Bandwidth S/H
■
Single 3.3V Supply
■
Low Power Dissipation: 910mW
■
LVDS, CMOS, or Demultiplexed CMOS Outputs
■
Selectable Input Ranges: ±0.5V or ±1V
■
No Missing Codes
■
Optional Clock Duty Cycle Stabilizer
■
Shutdown and Nap Modes
■
Data Ready Output Clock
■
Pin Compatible Family
185Msps: LTC2220-1 (12-Bit)
170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit)
135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit)
■
64-Pin 9mm × 9mm QFN Package
■
Wireless and Wired Broadband Communication
■
Cable Head-End Systems
■
Power Amplifier Linearization
■
Communications Test Equipment
3;33;33133333331 Ur flflflflflflr "T‘F‘FV‘FV‘ m \NCLOGV LT
2
LTC2220-1
2220_1fa
CO VERTER CHARACTERISTICS
U
PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution (No Missing Codes) ●12 Bits
Integral Linearity Error Differential Analog Input (Note 5) ●–1.8 ±0.7 1.8 LSB
Differential Linearity Error Differential Analog Input ●–1 ±0.5 1.2 LSB
Integral Linearity Error Single-Ended Analog Input (Note 5) ±1.5 LSB
Differential Linearity Error Single-Ended Analog Input ±0.5 LSB
Offset Error (Note 6) ●–35 ±335 mV
Gain Error External Reference ●–2.5 ±0.5 2.5 %FS
Offset Drift ±10 µV/C
Full-Scale Drift Internal Reference ±30 ppm/C
External Reference ±15 ppm/C
Transition Noise SENSE = 1V 0.5 LSB
RMS
Supply Voltage (V
DD
) ................................................. 4V
Digital Output Ground Voltage (OGND) ....... –0.3V to 1V
Analog Input Voltage (Note 3) ..... –0.3V to (V
DD
+ 0.3V)
Digital Input Voltage .................... –0.3V to (V
DD
+ 0.3V)
Digital Output Voltage ............... –0.3V to (OV
DD
+ 0.3V)
Power Dissipation............................................ 1500mW
Operating Temperature Range
LTC2220-1C ............................................ 0°C to 70°C
LTC2220-1I .........................................–40°C to 85°C
Storage Temperature Range ..................–65°C to 125°C
ABSOLUTE AXI U RATI GS
W
WW
U
PACKAGE/ORDER I FOR ATIO
UUW
OVDD = VDD (Notes 1, 2)
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
T
JMAX
= 125°C, θ
JA
= 20°C/W
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB
ORDER PART NUMBER
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping container.
LTC2220CUP-1
LTC2220IUP-1
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
UP PART MARKING*
LTC2220UP-1
TOP VIEW
UP PACKAGE
64-LEAD (9mm × 9mm) PLASTIC QFN
A
IN+
1
A
IN+
2
A
IN–
3
A
IN–
4
REFHA 5
REFHA 6
REFLB
7
REFLB
8
REFHB 9
REFHB 10
REFLA 11
REFLA 12
V
DD
13
V
DD
14
V
DD
15
GND 16
48 D9
+
/DA6
47 D9
–
/DA5
46 D8
+
/DA4
45 D8
–
/DA3
44 D7
+
/DA2
43 D7
–
/DA1
42 OV
DD
41 OGND
40 D6
+
/DA0
39 D6
–
/CLOCKOUTA
38 D5
+
/CLOCKOUTB
37 D5
–
/OFB
36 CLOCKOUT
+
/DB11
35 CLOCKOUT
–
/DB10
34 OV
DD
33 OGND
64 GND
63 V
DD
62 V
DD
61 GND
60 V
CM
59 SENSE
58 MODE
57 LVDS
56 OF
+
/OFA
55 OF
–
/DA11
54 D11
+
/DA10
53 D11
–
/DA9
52 D10
+
/DA8
51 D10
–
/DA7
50 OGND
49 OV
DD
ENC
+
17
ENC
–
18
SHDN
19
OE
20
DO
–
/DB0 21
DO
+
/DB1 22
D1
–
/DB2 23
D1
+
/DB3 24
OGND 25
OV
DD
26
D2
–
/DB4 27
D2
+
/DB5 28
D3
–
/DB6 29
D3
+
/DB7 30
D4
–
/DB8 31
D4
+
/DB9 32
65
\JOLCGV
LTC2220-1
3
2220_1fa
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IN
Analog Input Range (A
IN+
– A
IN–
) 3.1V < V
DD
< 3.5V (Note 7) ●±0.5 to ±1V
V
IN, CM
Analog Input Common Mode (A
IN+
+ A
IN–
)/2 Differential Input (Note 7) ●1 1.6 1.9 V
Single Ended Input (Note 7) ●0.5 1.6 2.1 V
I
IN
Analog Input Leakage Current 0 < A
IN+
, A
IN–
< V
DD
●–1 1 µA
I
SENSE
SENSE Input Leakage 0V < SENSE < 1V ●–1 1 µA
I
MODE
MODE Pin Pull-Down Current to GND 10 µA
I
LVDS
LVDS Pin Pull-Down Current to GND 10 µA
t
AP
Sample and Hold Acquisition Delay Time 0 ns
t
JITTER
Sample and Hold Acquisition Delay Time Jitter 0.15 ps
RMS
CMRR Analog Input Common Mode Rejection Ratio 80 dB
Full Power Bandwidth Figure 8 Test Circuit 775 MHz
DY A IC ACCURACY
UW
The ● denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SNR Signal-to-Noise Ratio (Note 10) 5MHz Input (1V Range) 62.7 dB
5MHz Input (2V Range) 67.7 dB
70MHz Input (1V Range) 62.7 dB
70MHz Input (2V Range) ●65.2 67.6 dB
140MHz Input (1V Range) 62.4 dB
140MHz Input (2V Range) 67.5 dB
250MHz Input (1V Range) 61.8 dB
250MHz Input (2V Range) 66.1 dB
SFDR Spurious Free Dynamic Range 5MHz Input (1V Range) 80 dB
2nd or 3rd Harmonic (Note 11) 5MHz Input (2V Range) 80 dB
70MHz Input (1V Range) 80 dB
70MHz Input (2V Range) ●69 80 dB
140MHz Input (1V Range) 80 dB
140MHz Input (2V Range) 80 dB
250MHz Input (1V Range) 74 dB
250MHz Input (2V Range) 73 dB
SFDR Spurious Free Dynamic Range 5MHz Input (1V Range) 85 dB
4th Harmonic or Higher (Note 11) 5MHz Input (2V Range) 85 dB
70MHz Input (1V Range) 85 dB
70MHz Input (2V Range) ●74 85 dB
140MHz Input (1V Range) 84 dB
140MHz Input (2V Range) 84 dB
250MHz Input (1V Range) 83 dB
250MHz Input (2V Range) 83 dB
S/(N+D) Signal-to-Noise Plus 5MHz Input (1V Range) 62.7 dB
Distortion Ratio (Note 12) 5MHz Input (2V Range) 67.5 dB
70MHz Input (1V Range) 62.7 dB
70MHz Input (2V Range) ●64.2 67.3 dB
IMD Intermodulation Distortion f
IN1
= 138MHz, f
IN2
= 140MHz 81 dBc
A ALOG I PUT
UU
The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
”\ \NCLOGV L: r
4
LTC2220-1
2220_1fa
PARAMETER CONDITIONS MIN TYP MAX UNITS
V
CM
Output Voltage I
OUT
= 0 1.570 1.600 1.630 V
V
CM
Output Tempco ±25 ppm/°C
V
CM
Line Regulation 3.1V < V
DD
< 3.5V 3 mV/V
V
CM
Output Resistance –1mA < I
OUT
< 1mA 4 Ω
DIGITAL I PUTS A D DIGITAL OUTPUTS
UU
I TER AL REFERE CE CHARACTERISTICS
UU U
The ● denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
(Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ENCODE INPUTS (ENC
+
, ENC
–
)
V
ID
Differential Input Voltage ●0.2 V
V
ICM
Common Mode Input Voltage Internally Set 1.6 V
Externally Set (Note 7) ●1.1 1.6 2.5 V
R
IN
Input Resistance 6kΩ
C
IN
Input Capacitance (Note 7) 3 pF
LOGIC INPUTS (OE, SHDN)
V
IH
High Level Input Voltage V
DD
= 3.3V ●2V
V
IL
Low Level Input Voltage V
DD
= 3.3V ●0.8 V
I
IN
Input Current V
IN
= 0V to V
DD
●–10 10 µA
C
IN
Input Capacitance (Note 7) 3 pF
LOGIC OUTPUTS (CMOS MODE)
OV
DD
= 3.3V
C
OZ
Hi-Z Output Capacitance OE = High (Note 7) 3 pF
I
SOURCE
Output Source Current V
OUT
= 0V 50 mA
I
SINK
Output Sink Current V
OUT
= 3.3V 50 mA
V
OH
High Level Output Voltage I
O
= –10µA 3.295 V
I
O
= –200µA●3.1 3.29 V
V
OL
Low Level Output Voltage I
O
= 10µA 0.005 V
I
O
= 1.6mA ●0.09 0.4 V
OV
DD
= 2.5V
V
OH
High Level Output Voltage I
O
= –200µA 2.49 V
V
OL
Low Level Output Voltage I
O
= 1.6mA 0.09 V
OV
DD
= 1.8V
V
OH
High Level Output Voltage I
O
= –200µA 1.79 V
V
OL
Low Level Output Voltage I
O
= 1.6mA 0.09 V
LOGIC OUTPUTS (LVDS MODE)
V
OD
Differential Output Voltage 100Ω Differential Load ●247 350 454 mV
V
OS
Output Common Mode Voltage 100Ω Differential Load ●1.125 1.250 1.375 V
\JOLCGV
LTC2220-1
5
2220_1fa
TI I G CHARACTERISTICS
WU
POWER REQUIRE E TS
WU
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
DD
Analog Supply Voltage (Note 8) ●3.1 3.3 3.5 V
P
SHDN
Shutdown Power SHDN = High, OE = High, No CLK 2 mW
P
NAP
Nap Mode Power SHDN = High, OE = Low, No CLK 35 mW
LVDS OUTPUT MODE
OV
DD
Output Supply Voltage (Note 8) ●3 3.3 3.6 V
I
VDD
Analog Supply Current ●273 300 mA
I
OVDD
Output Supply Current ●55 70 mA
P
DISS
Power Dissipation ●1080 1221 mW
CMOS OUTPUT MODE
OV
DD
Output Supply Voltage (Note 8) ●0.5 3.3 3.6 V
I
VDD
Analog Supply Current ●273 300 mA
P
DISS
Power Dissipation 910 mW
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
S
Sampling Frequency (Note 8) ●1 185 MHz
t
L
ENC Low Time (Note 7) Duty Cycle Stabilizer Off ●2.5 2.7 500 ns
Duty Cycle Stabilizer On ●2 2.7 500 ns
t
H
ENC High Time (Note 7) Duty Cycle Stabilizer Off ●2.5 2.7 500 ns
Duty Cycle Stabilizer On ●2 2.7 500 ns
t
AP
Sample-and-Hold Aperture Delay 0 ns
t
OE
Output Enable Delay (Note 7) ●510 ns
LVDS OUTPUT MODE
t
D
ENC to DATA Delay (Note 7) ●1.3 2.2 3.5 ns
t
C
ENC to CLOCKOUT Delay (Note 7) ●1.3 2.2 3.5 ns
DATA to CLOCKOUT Skew (t
C
- t
D
) (Note 7) ●–0.6 0 0.6 ns
Rise Time 0.5 ns
Fall Time 0.5 ns
Pipeline Latency 5ns
CMOS OUTPUT MODE
t
D
ENC to DATA Delay (Note 7) ●1.3 2.1 3.5 ns
t
C
ENC to CLOCKOUT Delay (Note 7) ●1.3 2.1 3.5 ns
DATA to CLOCKOUT Skew (t
C
- t
D
) (Note 7) ●–0.6 0 0.6 ns
Pipeline Latency Full Rate CMOS 5 Cycles
Demuxed Interleaved 5 Cycles
Demuxed Simultaneous 5 and 6 Cycles
7T0 0 T024 2048 OUTPUT CODE 3072 4000 LTCZZZD-1:SNR us Input Frequency, —1u0, 2V Range, LVDS Mude an 0 100 200 300 400 500 500 tNPUT FREQUENCV (MHZ) 6 mun n “HM t' 7T 0 0 T024 2040 OUTPUT CODE 3072 4000 LTCZZZD-1:SNR us Input Frequency, —1u0, 1V Range, LVDS Mude an 0 T00 200 300 400 500 00 INPUT FREQUENCV (MHZ) srun mars, T00 an an 70 50 50 40 2057 2050 CODE 2050 2050 2000 LTCZZZD-1:SFDR(HDZ and H03) vs Input Frequency, —1IIB, 2V Range, LVDS Made 0 ma 200 mu 400 500 son tNPUT FREQUENCY (MHZ) zzzuue L7TELEJ‘B
6
LTC2220-1
2220_1fa
0 600500400
100 200 300
INPUT FREQUENCY (MHz)
SFDR (dBFS)
80
90
100
2220 G06
70
60
40
50
OUTPUT CODE
0
ERROR (LSB)
4096
2220 G01
1024 2048 3072
1.0
0.8
0.6
0.4
0.2
0
– 0.2
– 0.4
– 0.6
– 0.8
– 1.0
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above V
DD
, they will
be clamped by internal diodes. This product can handle input currents of
greater than 100mA below GND or above V
DD
without latchup.
Note 4: V
DD
= 3.3V, f
SAMPLE
= 185MHz, LVDS outputs, differential ENC
+
/ENC
–
= 2V
P-P
sine wave, input range = 2V
P-P
with differential drive, unless otherwise
noted.
Note 5: Integral nonlinearity is defined as the deviation of a code from a “best
straight line” fit to the transfer curve. The deviation is measured from the
center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when the
output code flickers between 0000 0000 0000 and 1111 1111 1111 in 2’s
complement output mode.
Note 7: Guaranteed by design, not subject to test.
Note 8: Recommended operating conditions.
Note 9: V
DD
= 3.3V, f
SAMPLE
= 185MHz, differential ENC
+
/ENC
–
= 2V
P-P
sine
wave, input range = 1V
P-P
with differential drive, output C
LOAD
= 5pF.
Note 10: SNR minimum and typical values are for LVDS mode. Typical values
for CMOS mode are typically 0.3dB lower.
Note 11: SFDR minimum values are for LVDS mode. Typical values are for
both LVDS and CMOS modes.
Note 12: SINAD minimum and typical values are for LVDS mode. Typical
values for CMOS mode are typically 0.3dB lower.
ELECTRICAL CHARACTERISTICS
LTC2220-1: INL, 2V Range LTC2220-1: DNL, 2V Range
LTC2220-1: Shorted Input Noise
Histogram
(TA = 25°C unless otherwise noted, Note 4)
LTC2220-1: SNR vs Input
Frequency, –1dB, 2V Range,
LVDS Mode
LTC2220-1: SFDR (HD2 and HD3)
vs Input Frequency, –1dB, 2V
Range, LVDS Mode
LTC2220-1: SNR vs Input
Frequency, –1dB, 1V Range,
LVDS Mode
2220 G02
OUTPUT CODE
0
ERROR (LSB)
4096
1024 2048 3072
1.0
0.8
0.6
0.4
0.2
0
– 0.2
– 0.4
– 0.6
– 0.8
– 1.0
CODE
2056
229 140
12866
24266
93571
COUNT
100000
80000
60000
40000
20000
–0 2060
2220 G03
2057 2058 2059
INPUT FREQUENCY (MHz)
0
SNR (dBFS)
70
69
68
67
66
65
64
63
62
61
60
600500400
2220 G04
100 200 300
SNR (dBFS)
70
69
68
67
66
65
64
63
62
61
60
INPUT FREQUENCY (MHz)
0 600500400
100 200 300
2220 G05
4U 40 u we zuu sun 400 see sun 0 INPUT FREQUENCV (MHZ) mp 200 300 Ann 500 600 mmu' INPUT FREflLlENCV (MHz) LTCZZZD-t SFDR and SNR vs Sample Rale,1V Range, II" = 30MH1,—1IlB, LVDS Mode LT02220-1:SFDR and SNR vs Sample Rate, 2V Range, II" = 30MH1,—1IlB, LVDS Mode LTCZZZD-I: 'qu vs Sample Rale, 5MH1 Sine Wave Inpul, —1dB LTCZZZD-I: Iowa vs Sample Hale, LTE2220-1:SFDR vs Input Level, 5MH1 Sine Wave Inpul, —1dB I." = 70MH1, 2V Range 2220 Ha L7,EL,QB 7
LTC2220-1
7
2220_1fa
LTC2220-1: SFDR (HD2 and HD3)
vs Input Frequency, –1dB, 1V
Range, LVDS Mode
LTC2220-1: SFDR (HD4+) vs Input
Frequency, –1dB, 2V Range,
LVDS Mode
LTC2220-1: SFDR (HD4+) vs Input
Frequency, –1dB, 1V Range,
LVDS Mode
TYPICAL PERFOR A CE CHARACTERISTICS
UW
LTC2220-1: SFDR and SNR
vs Sample Rate, 1V Range,
fIN = 30MHz, –1dB, LVDS Mode
LTC2220-1: SFDR and SNR
vs Sample Rate, 2V Range,
fIN = 30MHz, –1dB, LVDS Mode
LTC2220-1: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
LTC2220-1: IOVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
LTC2220-1: SFDR vs Input Level,
f
IN
= 70MHz, 2V Range
0 600500400
100 200 300
INPUT FREQUENCY (MHz)
SFDR (dBFS)
80
90
100
2220 G07
70
60
40
50
0 600500400
100 200 300
INPUT FREQUENCY (MHz)
SFDR (dBFS)
80
90
100
2220 G08
70
60
40
50
0 600500400
100 200 300
INPUT FREQUENCY (MHz)
SFDR (dBFS)
80
90
100
2220 G09
70
60
40
50
SFDR AND SNR (dBFS)
95
90
85
80
75
70
65
60
55
50
SAMPLE RATE (Msps)
2220 G10
04080 120 160 200
SFDR
SNR
SFDR AND SNR (dBFS)
95
90
85
80
75
70
65
60
55
50
SAMPLE RATE (Msps)
2220 G11
04080 120 160 200
SFDR
SNR
290
280
270
260
250
240
230
220
210
SAMPLE RATE (Msps)
2220 G12
04080 120 160 200
2V RANGE
1V RANGE
IVDD (mA)
SAMPLE RATE (Msps)
2220 G13
04080 120 160 200
I
OVDD
(mA)
60
50
40
30
20
10
0
LVDS OUTPUTS, 0V
DD
= 3.3V
CMOS OUTPUTS, 0V
DD
= 1.8V
INPUT LEVEL (dBFS)
–60
SFDR (dBc AND dBFS)
–50 –40 –30 –20
2220 G14
–10
100
90
80
70
60
50
40
30
20
10
0
0
dBFS
dBc
m \NCLOGV :
8
LTC2220-1
2220_1fa
AMPLITUDE (dB)
0
–20
–40
–60
–80
–100
–120
2220 G15
FREQUENCY (MHz)
0204050 9010 30 60 70 80
AMPLITUDE (dB)
0
–20
–40
–60
–80
–100
–120
2220 G17
FREQUENCY (MHz)
0204050 9010 30 60 70 80
AMPLITUDE (dB)
0
–20
–40
–60
–80
–100
–120
2220 G16
FREQUENCY (MHz)
0204050 9010 30 60 70 80
TYPICAL PERFOR A CE CHARACTERISTICS
UW
LTC2220-1: 8192 Point FFT,
fIN = 5MHz, –1dB, 2V Range,
LVDS Mode
LTC2220-1: 8192 Point FFT,
fIN = 70MHz, –1dB, 2V Range,
LVDS Mode
LTC2220-1: 8192 Point FFT,
fIN = 140MHz, –1dB, 2V Range,
LVDS Mode
LTC2220-1: 8192 Point FFT,
fIN = 250MHz, –1dB, 2V Range,
LVDS Mode
LTC2220-1: 8192 Point FFT,
fIN = 500MHz, –6dB, 1V Range,
LVDS Mode
AMPLITUDE (dB)
0
–20
–40
–60
–80
–100
–120
2220 G18
FREQUENCY (MHz)
0204050 9010 30 60 70 80
AMPLITUDE (dB)
0
–20
–40
–60
–80
–100
–120
2220 G19
FREQUENCY (MHz)
0204050 9010 30 60 70 80
\JOLCGV
LTC2220-1
9
2220_1fa
(CMOS Mode)
A
IN+
(Pins 1, 2): Positive Differential Analog Input.
A
IN–
(Pins 3, 4): Negative Differential Analog Input.
REFHA (Pins 5, 6): ADC High Reference. Bypass to
Pins 7, 8 with 0.1µF ceramic chip capacitor, to Pins 11, 12
with a 2.2µF ceramic capacitor and to ground with 1µF
ceramic capacitor.
REFLB (Pins 7, 8): ADC Low Reference. Bypass to Pins 5,
6 with 0.1µF ceramic chip capacitor. Do not connect to
Pins 11, 12.
REFHB (Pins 9, 10): ADC High Reference. Bypass to
Pins 11, 12 with 0.1µF ceramic chip capacitor. Do not
connect to Pins 5, 6.
REFLA (Pins 11, 12): ADC Low Reference. Bypass to
Pins 9, 10 with 0.1µF ceramic chip capacitor, to Pins 5, 6
with a 2.2µF ceramic capacitor and to ground with 1µF
ceramic capacitor.
V
DD
(Pins 13, 14, 15, 62, 63): 3.3V Supply. Bypass to
GND with 0.1µF ceramic chip capacitors.
GND (Pins 16, 61, 64): ADC Power Ground.
ENC
+
(Pin 17): Encode Input. Conversion starts on the
positive edge.
ENC
–
(Pin 18): Encode Complement Input. Conversion
starts on the negative edge. Bypass to ground with 0.1µF
ceramic for single-ended ENCODE signal.
SHDN (Pin 19): Shutdown Mode Selection Pin. Connect-
ing SHDN to GND and OE to GND results in normal
operation with the outputs enabled. Connecting SHDN to
GND and OE to V
DD
results in normal operation with the
outputs at high impedance. Connecting SHDN to V
DD
and
OE to GND results in nap mode with the outputs at high
impedance. Connecting SHDN to V
DD
and OE to V
DD
results in sleep mode with the outputs at high impedance.
OE (Pin 20): Output Enable Pin. Refer to SHDN pin
function.
DB0 - DB11 (Pins 21, 22, 23, 24, 27, 28, 29, 30, 31, 32,
35, 36): Digital Outputs, B Bus. DB11 is the MSB. At high
impedance in full rate CMOS mode.
OGND (Pins 25, 33, 41, 50): Output Driver Ground.
OV
DD
(Pins 26, 34, 42, 49): Positive Supply for the
Output Drivers. Bypass to ground with 0.1µF ceramic chip
capacitor.
UU
U
PI FU CTIO S
OFB (Pin 37): Over/Under Flow Output for B Bus. High
when an over or under flow has occurred. At high imped-
ance in full rate CMOS mode.
CLKOUTB (Pin 38): Data Valid Output for B Bus. In demux
mode with interleaved update, latch B bus data on the
falling edge of CLKOUTB. In demux mode with simulta-
neous update, latch B bus data on the rising edge of
CLKOUTB. This pin does not become high impedance in
full rate CMOS mode.
CLKOUTA (Pin 39): Data Valid Output for A Bus. Latch A
bus data on the falling edge of CLKOUTA.
DA0 - DA11 (Pins 40, 43, 44, 45, 46, 47, 48, 51, 52, 53,
54, 55): Digital Outputs, A Bus. DA11 is the MSB.
OFA (Pin 56): Over/Under Flow Output for A Bus. High
when an over or under flow has occurred.
LVDS (Pin 57): Output Mode Selection Pin. Connecting
LVDS to 0V selects full rate CMOS mode. Connecting
LVDS to 1/3V
DD
selects demux CMOS mode with simulta-
neous update. Connecting LVDS to 2/3V
DD
selects demux
CMOS mode with interleaved update. Connecting LVDS to
V
DD
selects LVDS mode.
MODE (Pin 58): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and turns the clock duty cycle
stabilizer off. Connecting MODE to 1/3V
DD
selects offset
binary output format and turns the clock duty cycle stabi-
lizer on. Connecting MODE to 2/3V
DD
selects 2’s comple-
ment output format and turns the clock duty cycle stabi-
lizer on. Connecting MODE to V
DD
selects 2’s complement
output format and turns the clock duty cycle stabilizer off.
SENSE (Pin 59): Reference Programming Pin. Connecting
SENSE to V
CM
selects the internal reference and a ±0.5V
input range. Connecting SENSE to V
DD
selects the internal
reference and a ±1V input range. An external reference
greater than 0.5V and less than 1V applied to SENSE
selects an input range of ±V
SENSE
. ±1V is the largest valid
input range.
V
CM
(Pin 60): 1.6V Output and Input Common Mode Bias.
Bypass to ground with 2.2µF ceramic chip capacitor.
GND (Exposed Pad): ADC Power Ground. The exposed
pad on the bottom of the package needs to be soldered to
ground.
10
LTC2220-1
2220_1fa
UU
U
PI FU CTIO S
(LVDS Mode)
AIN
+
(Pins 1, 2): Positive Differential Analog Input.
AIN
–
(Pins 3, 4): Negative Differential Analog Input.
REFHA (Pins 5, 6): ADC High Reference. Bypass to
Pins 7, 8 with 0.1µF ceramic chip capacitor, to Pins 11, 12
with a 2.2µF ceramic capacitor and to ground with 1µF
ceramic capacitor.
REFLB (Pins 7, 8): ADC Low Reference. Bypass to Pins 5,
6 with 0.1µF ceramic chip capacitor. Do not connect to
Pins 11, 12.
REFHB (Pins 9, 10): ADC High Reference. Bypass to
Pins 11, 12 with 0.1µF ceramic chip capacitor. Do not
connect to Pins 5, 6.
REFLA (Pins 11, 12): ADC Low Reference. Bypass to
Pins 9, 10 with 0.1µF ceramic chip capacitor, to Pins 5, 6
with a 2.2µF ceramic capacitor and to ground with 1µF
ceramic capacitor.
V
DD
(Pins 13, 14, 15, 62, 63): 3.3V Supply. Bypass to
GND with 0.1µF ceramic chip capacitors.
GND (Pins 16, 61, 64): ADC Power Ground.
ENC
+
(Pin 17): Encode Input. Conversion starts on the
positive edge.
ENC
–
(Pin 18): Encode Complement Input. Conversion
starts on the negative edge. Bypass to ground with 0.1µF
ceramic for single-ended ENCODE signal.
SHDN (Pin 19): Shutdown Mode Selection Pin. Connect-
ing SHDN to GND and OE to GND results in normal
operation with the outputs enabled. Connecting SHDN to
GND and OE to V
DD
results in normal operation with the
outputs at high impedance. Connecting SHDN to V
DD
and
OE to GND results in nap mode with the outputs at high
impedance. Connecting SHDN to V
DD
and OE to V
DD
results in sleep mode with the outputs at high impedance.
OE (Pin 20): Output Enable Pin. Refer to SHDN pin
function.
D0
–
/D0
+
to D11
–
/D11
+
(Pins 21, 22, 23, 24, 27, 28, 29,
30, 31, 32, 37, 38, 39, 40, 43, 44, 45, 46, 47, 48, 51, 52,
53, 54): LVDS Digital Outputs. All LVDS outputs require
differential 100Ω termination resistors at the LVDS re-
ceiver. D11
–
/D11
+
is the MSB.
OGND (Pins 25, 33, 41, 50): Output Driver Ground.
OV
DD
(Pins 26, 34, 42, 49): Positive Supply for the Output
Drivers. Bypass to ground with 0.1µF ceramic chip
capacitor.
CLKOUT
–
/CLKOUT
+
(Pins 35 to 36): LVDS Data Valid
Output. Latch data on rising edge of CLKOUT
–
, falling edge
of CLKOUT
+
.
OF
–
/OF
+
(Pins 55 to 56): LVDS Over/Under Flow Output.
High when an over or under flow has occurred.
LVDS (Pin 57): Output Mode Selection Pin. Connecting
LVDS to 0V selects full rate CMOS mode. Connecting
LVDS to 1/3V
DD
selects demux CMOS mode with simulta-
neous update. Connecting LVDS to 2/3V
DD
selects demux
CMOS mode with interleaved update. Connecting LVDS to
V
DD
selects LVDS mode.
MODE (Pin 58): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and turns the clock duty cycle
stabilizer off. Connecting MODE to 1/3V
DD
selects offset
binary output format and turns the clock duty cycle stabi-
lizer on. Connecting MODE to 2/3V
DD
selects 2’s comple-
ment output format and turns the clock duty cycle stabi-
lizer on. Connecting MODE to V
DD
selects 2’s complement
output format and turns the clock duty cycle stabilizer off.
SENSE (Pin 59): Reference Programming Pin. Connecting
SENSE to V
CM
selects the internal reference and a ±0.5V
input range. Connecting SENSE to V
DD
selects the internal
reference and a ±1V input range. An external reference
greater than 0.5V and less than 1V applied to SENSE
selects an input range of ±V
SENSE
. ±1V is the largest valid
input range.
V
CM
(Pin 60): 1.6V Output and Input Common Mode Bias.
Bypass to ground with 2.2µF ceramic chip capacitor.
GND (Exposed Pad): ADC Power Ground. The exposed
pad on the bottom of the package needs to be soldered to
ground.
EFL m \JOLCGV
LTC2220-1
11
2220_1fa
FUNCTIONAL BLOCK DIAGRA
UU
W
DIFF
REF
AMP
REF
BUF
2.2µF
1µF
0.1µF 0.1µF
1µF
INTERNAL CLOCK SIGNALSREFH REFL
DIFFERENTIAL
INPUT
LOW JITTER
CLOCK
DRIVER
RANGE
SELECT
1.6V
REFERENCE
FIRST PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
ENC
+
REFHAREFLB REFLA REFHB
ENC
–
SHIFT REGISTER
AND CORRECTION
OEM0DE
OGND
OF
OV
DD
D11
D0
CLKOUT
22201 F01
INPUT
S/H
SENSE
V
CM
A
IN–
A
IN+
2.2µF
THIRD PIPELINED
ADC STAGE
OUTPUT
DRIVERS
CONTROL
LOGIC
LVDS SHDN
•
•
•
+
–
+
–
+
–
+
–
V
DD
GND
Figure 1. Functional Block Diagram
XXXX [)er ______ \"u-x _____ X """ x _____X """ 7 _______ F x *r\ ------ /\/ ______ x "'"x ______ ,\ """ X ..... L7LJ§1WEI§B
12
LTC2220-1
2220_1fa
TI I G DIAGRA S
WUW
t
AP
N + 1
N + 2 N + 4
N + 3
N
ANALOG
INPUT
t
H
t
D
t
C
t
L
N – 5 N – 4 N – 3 N – 2 N – 1
ENC
–
ENC
+
CLOCKOUTB
CLOCKOUTA
DA0-DA11, OFA
DB0-DB11, OFB
22201 TD02
HIGH IMPEDANCE
Full-Rate CMOS Output Mode Timing
All Outputs Are Single-Ended and Have CMOS Levels
t
H
t
D
t
C
t
L
N – 5 N – 4 N – 3 N – 2 N – 1
t
AP
N + 1
N + 2 N + 4
N + 3
N
ANALOG
INPUT
ENC
–
ENC
+
CLOCKOUT
–
CLOCKOUT
+
D0-D11, OF
22201 TD01
LVDS Output Mode Timing
All Outputs Are Differential and Have LVDS Levels
L7LJHMEGB
LTC2220-1
13
2220_1fa
t
H
t
D
t
C
t
C
t
D
t
L
N – 5 N – 3 N – 1
N – 6 N – 4 N – 2
ENC
–
ENC
+
CLOCKOUTB
CLOCKOUTA
DA0-DA11, OFA
DB0-DB11, OFB
22201 TD03
t
AP
N + 1
N + 2 N + 4
N + 3
N
ANALOG
INPUT
tH
tD
tC
tD
tL
N – 6 N – 4 N – 2
N – 5 N – 3 N – 1
ENC–
ENC+
CLOCKOUTB
CLOCKOUTA
DA0-DA11, OFA
DB0-DB11, OFB
22201 TD04
tAP
N + 1
N + 2 N + 4
N + 3
N
ANALOG
INPUT
Demultiplexed CMOS Outputs with Interleaved Update
All Outputs Are Single-Ended and Have CMOS Levels
Demultiplexed CMOS Outputs with Simultaneous Update
All Outputs Are Single-Ended and Have CMOS Levels
TI I G DIAGRA S
WUW
14
LTC2220-1
2220_1fa
APPLICATIO S I FOR ATIO
WUUU
DYNAMIC PERFORMANCE
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band limited
to frequencies above DC to below half the sampling
frequency.
Signal-to-Noise Ratio
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC.
Total Harmonic Distortion
Total harmonic distortion is the ratio of the RMS sum of all
harmonics of the input signal to the fundamental itself. The
out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency. THD is
expressed as:
THD = 20Log (√(V2
2
+ V3
2
+ V4
2
+ . . . Vn
2
)/V1)
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through Vn are the amplitudes of the
second through nth harmonics. The THD calculated in this
data sheet uses all the harmonics up to the fifth.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at the sum and differ-
ence frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3,
etc. The 3rd order intermodulation products are 2fa + fb,
2fb + fa, 2fa – fb and 2fb – fa. The intermodulation
distortion is defined as the ratio of the RMS value of either
input tone to the RMS value of the largest 3rd order
intermodulation product.
Spurious Free Dynamic Range (SFDR)
Spurious free dynamic range is the peak harmonic or
spurious noise that is the largest spectral component
excluding the input signal and DC. This value is expressed
in decibels relative to the RMS value of a full scale input
signal.
Full Power Bandwidth
The full power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is re-
duced by 3dB for a full scale input signal.
Aperture Delay Time
The time from when a rising ENC
+
equals the ENC
–
voltage
to the instant that the input signal is held by the sample and
hold circuit.
Aperture Delay Jitter
The variation in the aperture delay time from conversion to
conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNR
JITTER
= –20log (2π • f
IN
• t
JITTER
)
CONVERTER OPERATION
As shown in Figure 1, the LTC2220-1 is a CMOS pipelined
multistep converter. The converter has five pipelined ADC
stages; a sampled analog input will result in a digitized
value five cycles later (see the Timing Diagram section).
For optimal AC performance the analog inputs should be
driven differentially. For cost sensitive applications, the
analog inputs can be driven single-ended with slightly
worse harmonic distortion. The encode input is differen-
tial for improved common mode noise immunity. The
LTC2220-1 has two phases of operation, determined by
the state of the differential ENC
+
/ENC
–
input pins. For
brevity, the text will refer to ENC
+
greater than ENC
–
as ENC
high and ENC
+
less than ENC
–
as ENC low.
LTLJDNEQE
LTC2220-1
15
2220_1fa
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When ENC is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that ENC transitions from low to high, the sampled input
is held. While ENC is high, the held input voltage is
buffered by the S/H amplifier which drives the first pipelined
ADC stage. The first stage acquires the output of the S/H
during this high phase of ENC. When ENC goes back low,
the first stage produces its residue which is acquired by
the second stage. At the same time, the input S/H goes
back to acquiring the analog input. When ENC goes back
high, the second stage produces its residue which is
acquired by the third stage. An identical process is re-
peated for the third and fourth stages, resulting in a fourth
stage residue that is sent to the fifth stage ADC for final
evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2220-1
CMOS differential sample-and-hold. The analog inputs are
connected to the sampling capacitors (C
SAMPLE
) through
NMOS transistors. The capacitors shown attached to each
input (C
PARASITIC
) are the summation of all other capaci-
tance associated with each input.
During the sample phase when ENC is low, the transistors
connect the analog inputs to the sampling capacitors and
they charge to, and track the differential input voltage.
When ENC transitions from low to high, the sampled input
voltage is held on the sampling capacitors. During the hold
phase when ENC is high, the sampling capacitors are
disconnected from the input and the held voltage is passed
to the ADC core for processing. As ENC transitions from
high to low, the inputs are reconnected to the sampling
capacitors to acquire a new sample. Since the sampling
capacitors still hold the previous sample, a charging glitch
proportional to the change in voltage between samples will
be seen at this time. If the change between the last sample
and the new sample is small, the charging glitch seen at
the input will be small. If the input change is large, such as
the change seen with input frequencies near Nyquist, then
a larger charging glitch will be seen.
CSAMPLE
1.6pF
VDD
VDD
LTC2220-1
AIN+
22201 F02
CSAMPLE
1.6pF
VDD
AIN–
ENC–
ENC+
1.6V
6k
1.6V
6k
CPARASITIC
1pF
CPARASITIC
1pF
15Ω
15Ω
Figure 2. Equivalent Input Circuit
Single-Ended Input
For cost sensitive applications, the analog inputs can be
driven single-ended. With a single-ended input the har-
monic distortion and INL will degrade, but the SNR and
DNL will remain unchanged. For a single-ended input, A
IN+
should be driven with the input signal and A
IN–
should be
connected to 1.6V or V
CM
.
Common Mode Bias
For optimal performance the analog inputs should be
driven differentially. Each input should swing ±0.5V for
APPLICATIO S I FOR ATIO
WUUU
L l— l1}: W9 I... ,_ T... ._ I. \ \NCLOGV :2 LT
16
LTC2220-1
2220_1fa
the 2V range or ±0.25V for the 1V range, around a
common mode voltage of 1.6V. The V
CM
output pin (Pin
60) may be used to provide the common mode bias level.
V
CM
can be tied directly to the center tap of a transformer
to set the DC input level or as a reference level to an op amp
differential driver circuit. The V
CM
pin must be bypassed to
ground close to the ADC with a 2.2µF or greater capacitor.
Input Drive Impedance
As with all high performance, high speed ADCs, the
dynamic performance of the LTC2220-1 can be influenced
by the input drive circuitry, particularly the second and
third harmonics. Source impedance and input reactance
can influence SFDR. At the falling edge of ENC, the sample-
and-hold circuit will connect the 1.6pF sampling capacitor
to the input pin and start the sampling period. The sam-
pling period ends when ENC rises, holding the sampled
input on the sampling capacitor. Ideally the input circuitry
should be fast enough to fully charge the sampling capaci-
tor during the sampling period 1/(2F
ENCODE
); however,
this is not always possible and the incomplete settling may
degrade the SFDR. The sampling glitch has been designed
to be as linear as possible to minimize the effects of
incomplete settling.
For the best performance, it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC2220-1 being driven by an RF
transformer with a center tapped secondary. The second-
ary center tap is DC biased with V
CM
, setting the ADC input
signal at its optimum DC level. Terminating on the trans-
former secondary is desirable, as this provides a common
mode path for charging glitches caused by the sample and
hold. Figure 3 shows a 1:1 turns ratio transformer. Other
turns ratios can be used if the source impedance seen by
the ADC does not exceed 100Ω for each ADC input. A
disadvantage of using a transformer is the loss of low
frequency response. Most small RF transformers have
poor performance at frequencies below 1MHz.
Figure 4 demonstrates the use of a differential amplifier to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides low
frequency input response; however, the limited gain bandwidth
of most op amps will limit the SFDR at high input frequencies.
Figure 5 shows a single-ended input circuit. The imped-
ance seen by the analog inputs should be matched. This
circuit is not recommended if low distortion is required.
The 25Ω resistors and 12pF capacitor on the analog inputs
serve two purposes: isolating the drive circuitry from the
sample-and-hold charging glitches and limiting the
wideband noise at the converter input. For input frequen-
cies higher than 100MHz, the capacitor may need to be
decreased to prevent excessive signal loss.
25Ω
25Ω25Ω
25Ω
0.1µFAIN+
AIN+
AIN–
AIN–
12pF
2.2µF
VCM
LTC2220-1
ANALOG
INPUT
0.1µFT1
1:1
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
22201 F03
Figure 3. Single-Ended to Differential
Conversion Using a Transformer
25Ω
25Ω
A
IN+
A
IN+
A
IN–
A
IN–
12pF
2.2µF
3pF
3pF
V
CM
LTC2220-1
22201 F04
––
++
CM
ANALOG
INPUT
HIGH SPEED
DIFFERENTIAL
AMPLIFIER
AMPLIFIER = LTC6600-20, LT1993, ETC.
Figure 4. Differential Drive with an Amplifier
APPLICATIO S I FOR ATIO
WUUU
Figure 5. Single-Ended Drive
25Ω
0.1µF
ANALOG
INPUT
VCM
AIN
+
AIN
+
AIN
–
AIN
–
1k
12pF
22201 F05
2.2µF
1k
25Ω
0.1µF
LTC2220-1
L I. I_ 1— [3:22 @- gll“ \JOLCGV
LTC2220-1
17
2220_1fa
The A
IN+
and A
IN–
inputs each have two pins to reduce
package inductance. The two A
IN+
and the two A
IN–
pins
should be shorted together.
For input frequencies above 100MHz the input circuits of
Figure 6, 7 and 8 are recommended. The balun trans-
former gives better high frequency response than a flux
coupled center tapped transformer. The coupling capaci-
tors allow the analog inputs to be DC biased at 1.6V. In
Figure 8 the series inductors are impedance matching
elements that maximize the ADC bandwidth.
Figure 7. Recommended Front End Circuit for
Input Frequencies Between 250MHz and 500MHz
Reference Operation
Figure 9 shows the LTC2220-1 reference circuitry consist-
ing of a 1.6V bandgap reference, a difference amplifier and
switching and control circuit. The internal voltage refer-
ence can be configured for two pin selectable input ranges
of 2V (±1V differential) or 1V (±0.5V differential). Tying the
SENSE pin to V
DD
selects the 2V range; typing the SENSE
pin to V
CM
selects the 1V range.
The 1.6V bandgap reference serves two functions: its
output provides a DC bias point for setting the common
mode voltage of any external input circuitry; additionally,
the reference is used with a difference amplifier to gener-
ate the differential reference levels needed by the internal
ADC circuitry. An external bypass capacitor is required for
the 1.6V reference output, V
CM
. This provides a high
frequency low impedance path to ground for internal and
external circuitry.
The difference amplifier generates the high and low refer-
ence for the ADC. High speed switching circuits are
connected to these outputs and they must be externally
bypassed. Each output has four pins: two each of REFHA
and REFHB for the high reference and two each of REFLA
and REFLB for the low reference. The multiple output pins
are needed to reduce package inductance. Bypass capaci-
tors must be connected as shown in Figure 9.
25Ω
25Ω
0.1µFA
IN+
A
IN+
A
IN–
A
IN–
2pF
2.2µF
V
CM
LTC2220-1
ANALOG
INPUT
0.1µF
0.1µF
T1
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
22201 F08
4.7nH
4.7nH
APPLICATIO S I FOR ATIO
WUUU
Figure 6. Recommended Front End Circuit for
Input Frequencies Between 100MHz and 250MHz
25Ω
25Ω12Ω
12Ω
0.1µFA
IN+
A
IN+
A
IN–
A
IN–
8pF
2.2µF
V
CM
LTC2220-1
ANALOG
INPUT
0.1µF
0.1µF
T1
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
22201 F06
Figure 8. Recommended Front End Circuit for
Input Frequencies Above 500MHz
25Ω
25Ω
0.1µFA
IN+
A
IN+
A
IN–
A
IN–
2.2µF
V
CM
LTC2220-1
ANALOG
INPUT
0.1µF
0.1µF
T1
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
22201 F07
V
CM
REFHA
REFLB
SENSE
TIE TO V
DD
FOR 2V RANGE;
TIE TO V
CM
FOR 1V RANGE;
RANGE = 2 • V
SENSE
FOR
0.5V < V
SENSE
< 1V
1.6V
REFLA
REFHB
2.2µF
2.2µF
INTERNAL ADC
HIGH REFERENCE
BUFFER
0.1µF
22201 F09
LTC2220-1
4Ω
DIFF AMP
1µF
1µF0.1µF
INTERNAL ADC
LOW REFERENCE
1.6V BANDGAP
REFERENCE
1V 0.5V
RANGE
DETECT
AND
CONTROL
Figure 9. Equivalent Reference Circuit
LTLJEJNOW
18
LTC2220-1
2220_1fa
Other voltage ranges in between the pin selectable ranges
can be programmed with two external resistors as shown
in Figure 10. An external reference can be used by applying
its output directly or through a resistor divider to SENSE.
It is not recommended to drive the SENSE pin with a logic
device. The SENSE pin should be tied to the appropriate
level as close to the converter as possible. If the SENSE pin
is driven externally, it should be bypassed to ground as
close to the device as possible with a 1µF ceramic capacitor.
2. Use as large an amplitude as possible; if transformer
coupled use a higher turns ratio to increase the amplitude.
3. If the ADC is clocked with a sinusoidal signal, filter the
encode signal to reduce wideband noise.
4. Balance the capacitance and series resistance at both
encode inputs so that any coupled noise will appear at both
inputs as common mode noise. The encode inputs have a
common mode range of 1.1V to 2.5V. Each input may be
driven from ground to V
DD
for single-ended drive.
APPLICATIO S I FOR ATIO
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V
DD
V
DD
LTC2220-1
22201 F11
V
DD
ENC–
ENC
+
1.6V BIAS
1.6V BIAS
1:4
0.1µF
CLOCK
INPUT
50Ω
6k
6k
TO INTERNAL
ADC CIRCUITS
Figure 11. Transformer Driven ENC+/ENC–
VCM
SENSE
1.6V
0.8V
2.2µF
12k
1µF
12k
22201 F10
LTC2220-1
Figure 10. 1.6V Range ADC
Input Range
The input range can be set based on the application. The
2V input range will provide the best signal-to-noise perfor-
mance while maintaining excellent SFDR. The 1V input
range will have better SFDR performance, but the SNR will
degrade by 5dB. See the Typical Performance Character-
istics section.
Driving the Encode Inputs
The noise performance of the LTC2220-1 can depend on
the encode signal quality as much as on the analog input.
The ENC
+
/ENC
–
inputs are intended to be driven differen-
tially, primarily for noise immunity from common mode
noise sources. Each input is biased through a 6k resistor
to a 1.6V bias. The bias resistors set the DC operating point
for transformer coupled drive circuits and can set the logic
threshold for single-ended drive circuits.
Any noise present on the encode signal will result in
additional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter.
In applications where jitter is critical (high input frequen-
cies) take the following into consideration:
1. Differential drive should be used.
Maximum and Minimum Encode Rates
The maximum encode rate for the LTC2220-1 is 185Msps.
For the ADC to operate properly, the encode signal should
have a 50% (±5%) duty cycle. Each half cycle must have
at least 2.5ns for the ADC internal circuitry to have enough
settling time for proper operation. Achieving a precise
50% duty cycle is easy with differential sinusoidal drive
using a transformer or using symmetric differential logic
such as PECL or LVDS.
An optional clock duty cycle stabilizer circuit can be used
if the input clock has a non 50% duty cycle. This circuit
uses the rising edge of the ENC
+
pin to sample the analog
input. The falling edge of ENC
+
is ignored and the internal
falling edge is generated by a phase-locked loop. The input
clock duty cycle can vary from 30% to 70% and the clock
duty cycle stabilizer will maintain a constant 50% internal
33v g % Mumuwmzz 13an um III“ in EL
LTC2220-1
19
2220_1fa
duty cycle. If the clock is turned off for a long period of
time, the duty cycle stabilizer circuit will require one
hundred clock cycles for the PLL to lock onto the input
clock. To use the clock duty cycle stabilizer, the MODE pin
should be connected to 1/3V
DD
or 2/3V
DD
using external
resistors.
The lower limit of the LTC2220-1 sample rate is deter-
mined by droop of the sample-and-hold circuits. The
pipelined architecture of this ADC relies on storing analog
signals on small valued capacitors. Junction leakage will
discharge the capacitors. The specified minimum operat-
ing frequency for the LTC2220-1 is 1Msps.
Digital Output Modes
The LTC2220-1 can operate in several digital output modes:
LVDS, CMOS running at full speed, and CMOS
demultiplexed onto two buses, each of which runs at half
speed. In the demultiplexed CMOS modes the two buses
(referred to as bus A and bus B) can either be updated on
alternate clock cycles (interleaved mode) or simultaneously
(simultaneous mode). For details on the clock timing, refer
to the timing diagrams.
The LVDS pin selects which digital output mode the part
uses. This pin has a four-level logic input which should be
connected to GND, 1/3V
DD
, 2/3V
DD
or V
DD
. An external
resistor divider can be used to set the 1/3V
DD
or 2/3V
DD
logic values. Table 2 shows the logic states for the LVDS
pin.
APPLICATIO S I FOR ATIO
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LTC2220-1
22201 F13a
OV
DD
V
DD
V
DD
0.1µF
43ΩTYPICAL
DATA
OUTPUT
OGND
OV
DD
0.5V
TO 3.6V
PREDRIVER
LOGIC
DATA
FROM
LATCH
OE
Figure 13a. Digital Output Buffer in CMOS Mode
Digital Output Buffers (CMOS Modes)
Figure 13a shows an equivalent circuit for a single output
buffer in the CMOS output mode. Each buffer is powered
by OV
DD
and OGND, which are isolated from the ADC
power and ground. The additional N-channel transistor in
the output driver allows operation down to voltages as low
as 0.5V. The internal resistor in series with the output
makes the output appear as 50Ω to external circuitry and
may eliminate the need for external damping resistors.
22201 F12a
ENC
–
1.6V
V
THRESHOLD
= 1.6V ENC
+
0.1µF
LTC2220-1
22201 F12b
ENC–
ENC+
130Ω
3.3V
3.3V
130Ω
D0
Q0
Q0
MC100LVELT22
LTC2220-1
83Ω83Ω
Figure 12a. Single-Ended ENC Drive,
Not Recommended for Low Jitter
Figure 12b. ENC Drive Using a CMOS to PECL Translator
Table 2. LVDS Pin Function
LVDS Digital Output Mode
GND Full-Rate CMOS
1/3V
DD
Demultiplexed CMOS, Simultaneous Update
2/3V
DD
Demultiplexed CMOS, Interleaved Update
V
DD
LVDS
DIGITAL OUTPUTS
Table 1. Output Codes vs Input Voltage
A
IN+
– A
IN–
D11 – D0 D11 – D0
(2V Range) OF (Offset Binary) (2’s Complement)
>+1.000000V 1 1111 1111 1111 0111 1111 1111
+0.999512V 0 1111 1111 1111 0111 1111 1111
+0.999024V 0 1111 1111 1110 0111 1111 1110
+0.000488V 0 1000 0000 0001 0000 0000 0001
0.000000V 0 1000 0000 0000 0000 0000 0000
–0.000488V 0 0111 1111 1111 1111 1111 1111
–0.000976V 0 0111 1111 1110 1111 1111 1110
–0.999512V 0 0000 0000 0001 1000 0000 0001
–1.000000V 0 0000 0000 0000 1000 0000 0000
<–1.000000V 1 0000 0000 0000 1000 0000 0000
L7LJ§1WEI§B
20
LTC2220-1
2220_1fa
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2220-1 should drive a minimal
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. The output
should be buffered with a device such as an ALVCH16373
CMOS latch. For full speed operation the capacitive load
should be kept under 10pF.
Lower OV
DD
voltages will also help reduce interference
from the digital outputs.
Digital Output Buffers (LVDS Mode)
Figure 13b shows an equivalent circuit for a differential
output pair in the LVDS output mode. A 3.5mA current is
steered from OUT
+
to OUT
–
or vice versa which creates a
±350mV differential voltage across the 100Ω termination
resistor at the LVDS receiver. A feedback loop regulates
the common mode output voltage to 1.25V. For proper
operation each LVDS output pair needs an external 100Ω
termination resistor, even if the signal is not used (such as
OF
+
/OF
–
or CLKOUT
+
/CLKOUT
–
). To minimize noise the
PC board traces for each LVDS output pair should be
routed close together. To minimize clock skew all LVDS PC
board traces should have about the same length.
APPLICATIO S I FOR ATIO
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Table 3. MODE Pin Function
Clock Duty
MODE Pin Output Format Cycle Stablizer
0 Offset Binary Off
1/3V
DD
Offset Binary On
2/3V
DD
2’s Complement On
V
DD
2’s Complement Off
Data Format
The LTC2220-1 parallel digital output can be selected for
offset binary or 2’s complement format. The format is
selected with the MODE pin. Connecting MODE to GND or
1/3V
DD
selects offset binary output format. Connecting
MODE to 2/3V
DD
or V
DD
selects 2’s complement output
format. An external resistor divider can be used to set the
1/3V
DD
or 2/3V
DD
logic values. Table 3 shows the logic
states for the MODE pin.
LTC2220-1
22201 F13b
OV
DD
LVDS
RECEIVER
OGND
1.25V
D
D
D
D
OUT
+
OUT
–
100Ω
+
–
3.5mA
10k 10k
Figure 13b. Digital Output in LVDS Mode
Overflow Bit
An overflow output bit indicates when the converter is
overranged or underranged. In CMOS mode, a logic high
on the OFA pin indicates an overflow or underflow on the
A data bus, while a logic high on the OFB pin indicates an
overflow or underflow on the B data bus. In LVDS mode,
a differential logic high on the OF
+
/OF
–
pins indicates an
overflow or underflow.
Output Clock
The ADC has a delayed version of the ENC
+
input available
as a digital output, CLKOUT. The CLKOUT pin can be used
to synchronize the converter data to the digital system. This
is necessary when using a sinusoidal encode. In all CMOS
modes, A bus data will be updated just after CLKOUTA rises
and can be latched on the falling edge of CLKOUTA. In demux
CMOS mode with interleaved update, B bus data will be
updated just after CLKOUTB rises and can be latched on the
falling edge of CLKOUTB. In demux CMOS mode with si-
multaneous update, B bus data will be updated just after
CLKOUTB falls and can be latched on the rising edge of
CLKOUTB. In LVDS mode, data will be updated just after
CLKOUT
+
/CLKOUT
–
rises and can be latched on the falling
edge of CLKOUT
+
/CLKOUT
–
.
\JOLCGV
LTC2220-1
21
2220_1fa
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OV
DD
, should be tied
to the same power supply as for the logic being driven. For
example if the converter is driving a DSP powered by a 1.8V
supply then OV
DD
should be tied to that same 1.8V supply.
In the CMOS output mode, OV
DD
can be powered with any
voltage up to 3.6V. OGND can be powered with any voltage
from GND up to 1V and must be less than OV
DD
. The logic
outputs will swing between OGND and OV
DD
.
In the LVDS output mode, OV
DD
should be connected to a
3.3V supply and OGND should be connected to GND.
Output Enable
The outputs may be disabled with the output enable pin, OE.
In CMOS or LVDS output modes OE high disables all data
outputs including OF and CLKOUT. The data access and bus
relinquish times are too slow to allow the outputs to be
enabled and disabled during full speed operation. The output
Hi-Z state is intended for use during long periods of
inactivity.
The Hi-Z state is not a truly open circuit; the output pins that
make an LVDS output pair have a 20k resistance between
them. Therefore in the CMOS output mode, adjacent data
bits will have 20k resistance in between them, even in the
Hi-Z state.
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting SHDN to GND results in
normal operation. Connecting SHDN to V
DD
and OE to V
DD
results in sleep mode, which powers down all circuitry
including the reference and typically dissipates 1mW. When
exiting sleep mode it will take milliseconds for the output
data to become valid because the reference capacitors have
to recharge and stabilize. Connecting SHDN to V
DD
and OE
to GND results in nap mode, which typically dissipates
APPLICATIO S I FOR ATIO
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35mW. In nap mode, the on-chip reference circuit is kept
on, so that recovery from nap mode is faster than that from
sleep mode, typically taking 100 clock cycles. In both sleep
and nap mode all digital outputs are disabled and enter the
Hi-Z state.
GROUNDING AND BYPASSING
The LTC2220-1 requires a printed circuit board with a clean
unbroken ground plane. A multilayer board with an inter-
nal ground plane is recommended. Layout for the printed
circuit board should ensure that digital and analog signal
lines are separated as much as possible. In particular, care
should be taken not to run any digital signal alongside an
analog signal or underneath the ADC.
High quality ceramic bypass capacitors should be used at
the V
DD
, OV
DD
, V
CM
, REFHA, REFHB, REFLA and REFLB pins
as shown in the block diagram on the front page of this data
sheet. Bypass capacitors must be located as close to the
pins as possible. Of particular importance are the capaci-
tors between REFHA and REFLB and between REFHB and
REFLA. These capacitors should be as close to the device
as possible (1.5mm or less). Size 0402 ceramic capacitors
are recommended. The 2.2µF capacitor between REFHA and
REFLA can be somewhat further away. The traces connect-
ing the pins and bypass capacitors must be kept short and
should be made as wide as possible.
The LTC2220-1 differential inputs should run parallel and
close to each other. The input traces should be as short as
possible to minimize capacitance and to minimize noise
pickup.
HEAT TRANSFER
Most of the heat generated by the LTC2220-1 is transferred
from the die through the bottom-side exposed pad and
package leads onto the printed circuit board. For good
electrical and thermal performance, the exposed pad should
be soldered to a large grounded pad on the PC board. It is
critical that all ground pins are connected to a ground plane
of sufficient area.
22
LTC2220-1
2220_1fa
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Clock Sources for Undersampling
Undersampling raises the bar on the clock source and the
higher the input frequency, the greater the sensitivity to
clock jitter or phase noise. A clock source that degrades
SNR of a full-scale signal by 1dB at 70MHz will degrade
SNR by 3dB at 140MHz, and 4.5dB at 190MHz.
In cases where absolute clock frequency accuracy is
relatively unimportant and only a single ADC is required,
a 3V canned oscillator from vendors such as Saronix or
Vectron can be placed close to the ADC and simply
connected directly to the ADC. If there is any distance to
the ADC, some source termination to reduce ringing that
may occur even over a fraction of an inch is advisable. You
must not allow the clock to overshoot the supplies or
performance will suffer. Do not filter the clock signal with
a narrow band filter unless you have a sinusoidal clock
source, as the rise and fall time artifacts present in typical
digital clock signals will be translated into phase noise.
The lowest phase noise oscillators have single-ended
sinusoidal outputs, and for these devices the use of a filter
close to the ADC may be beneficial. This filter should be
close to the ADC to both reduce roundtrip reflection times,
as well as reduce the susceptibility of the traces between
the filter and the ADC. If you are sensitive to close-in phase
noise, the power supply for oscillators and any buffers
must be very stable, or propagation delay variation with
supply will translate into phase noise. Even though these
clock sources may be regarded as digital devices, do not
operate them on a digital supply. If your clock is also used
to drive digital devices such as an FPGA, you should locate
the oscillator, and any clock fan-out devices close to the
ADC, and give the routing to the ADC precedence. The
clock signals to the FPGA should have series termination
at the source to prevent high frequency noise from the
FPGA disturbing the substrate of the clock fan-out device.
If you use an FPGA as a programmable divider, you must
re-time the signal using the original oscillator, and the re-
timing flip-flop as well as the oscillator should be close to
the ADC, and powered with a very quiet supply.
For cases where there are multiple ADCs, or where the
clock source originates some distance away, differential
clock distribution is advisable. This is advisable both from
the perspective of EMI, but also to avoid receiving noise
from digital sources both radiated, as well as propagated
in the waveguides that exist between the layers of multi-
layer PCBs. The differential pairs must be close together,
and distanced from other signals. The differential pair
should be guarded on both sides with copper distanced at
least 3x the distance between the traces, and grounded
with vias no more than 1/4 inch apart.
4:- IITIITxITIITI\TIITIIUHHHHIITIITIIIIII I Iflwfil E ] lll”l”1“l“l *Fglwl i l l lglllllilll“. 32 3a 1:3? u a H M $ ”F a I III sa 1 36_| 3 E i? 3" 1;? T T T T T T T T T 52 z ¢ 5 a w as as 35 3 2a an 2¢ L7LJHMEGB
LTC2220-1
23
2220_1fa
APPLICATIO S I FOR ATIO
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A
IN
+
A
IN
+
A
IN
–
A
IN
–
REFHA
REFHA
REFLB
REFLB
REFHB
REFHB
REFLA
REFLA
V
DD
V
DD
V
DD
V
DD
V
DD
ENC
+
ENC
–
SHDN
OEL
OGND
OGND
OGND
OGND
V
CM
SENSE
GND
GND
GND
MODE
LVDS
C16
0.1µF
C11
0.1µF
C39
0.1µF
C34
4.7µF
C33
0.1µF
C32
0.1µF
C30
0.1µF
C31
0.1µF
C17
1µF
C7
12pF
C18
1µF
C19
2.2µF
1
2
3
4
5
6
7
8
9
10
11
12
62
63
13
14
15
17
18
19
20
25
33
41
50
60
59
16
61
64
58
57
56
55
54
53
52
51
48
47
46
45
44
43
40
39
38
37
36
35
32
31
30
29
28
27
24
23
22
21
49
42
34
26
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CLK
CLK
C29
2.2µF
V
CM
V
CM
V
DD
V
CM
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
MODE
R28
1k
R29
1k R2
4.99k 1%
R3
4.99k 1%
R4
4.99k 1%
R30
1k
2/3V
DD
1/3V
DD
GND
JP7
JP20
C35
0.1µF
C21
0.1µF
C24
0.1µF
C36
4.7µF
C12
0.1µF
C10
0.1µF
C8
0.1µF
C9
0.1µF
C6
0.1µF
C5
0.1µF
C4
0.1µF
C5
4.7µF
C2
0.1µF
C1
0.1µF
SENSE
EXT
REF
GND
GND
EN/12
RIN1
–
RIN1
+
RIN2
+
RIN2
–
RIN3
–
RIN3
+
RIN4
+
RIN4
–
V
CC
EN
RIN5
–
RIN5
+
RIN6
+
RIN6
–
RIN7
–
RIN7
+
RIN8
+
RIN8
–
EN/34
GND
V
BB
V
CC
V
CC
EN/78
DOUT1
–
DOUT1
+
DOUT2
+
DOUT2
–
DOUT3
–
DOUT3
+
DOUT4
+
DOUT4
–
GND
GND
DOUT5
–
DOUT5
+
DOUT6
+
DOUT6
–
DOUT7
–
DOUT7
+
DOUT8+
DOUT8
–
EN/56
V
CC
V
CC
R13
100Ω
R1
100Ω
R26
100Ω
R25
100Ω
R24
100Ω
R23
100Ω
R21
100Ω
R14
100Ω
R15
100Ω
R16
100Ω
R17
100Ω
R20
100Ω
R18
100Ω
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
V
DD
V
DD
V
CC
V
SS
V
CC_IN
V
CC
V
CC
V
CC
OPT
V
CC
3.3V
L1
MURATA
BLM18BB470SN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
GND
GND
EN/12
RIN1
–
RIN1
+
RIN2
+
RIN2
–
RIN3
–
RIN3
+
RIN4
+
RIN4
–
V
CC
EN
RIN5
–
RIN5
+
RIN6
+
RIN6
–
RIN7
–
RIN7
+
RIN8
+
RIN8
–
EN/34
GND
V
BB
V
CC
V
CC
EN/78
DOUT1
–
DOUT1
+
DOUT2
+
DOUT2
–
DOUT3
–
DOUT3
+
DOUT4+
DOUT4
–
GND
GND
DOUT5
–
DOUT5
+
DOUT6
+
DOUT6
–
DOUT7
–
DOUT7
+
DOUT8
+
DOUT8
–
EN/56
V
CC
V
CC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
V
CC
V
CC
A0
A1
A2
A3
V
CC
WP
SCL
SDA
JP4
1
2
3
4
8
7
6
5
SCL
SDA
R19 100Ω
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
PWR GND
GND
V
DD
V
DD
3.3V C3
4.7µF
C22
0.1µF
C27
0.1µF
C23
0.1µF
R27
50Ω
R9
24.9Ω
R10
24.9Ω
R12
24.9Ω
R11
24.9Ω
V
CM
ANALOG
INPUT
AIN
+
AIN
+
AIN
–
AIN
–
C20
0.1µF
C25
33pF
C26
0.1µF
R8
100Ω
R7
100Ω
ENCODE
INPUT
CLK
CLK
T2
ETC1-1T
T1*
ETC1-1T
EDGE-CON-100
R6
4.7k
V
SS
SCL
SDA
V
CC_IN
V
CC
ENABLE
OF
+
/OFA
OF
–
/DA11
D11
+
/DA10
D11
–
/DA9
D10
+
/DA8
D10
–
/DA7
D9
+
/DA6
D9
–
/DA5
D8
+
/DA4
D8
–
/DA3
D7
+
/DA2
D7
–
/DA1
D6
+
/DA0
D6
–
/CLKOUTA
D5
+
/CLKOUTB
DB5
–
/OFB
CLKOUT
+
/DB11
CLKOUT
–
/DB10
D4
+
/DB9
D4
–
/DB8
D3
+
/DB7
D3
–
/DB6
D2
+
/DB5
D2
–
/DB4
D1
+
/DB3
D1
–
/DB2
D0
+
/DB1
D0
–
/DB0
OV
DD
OV
DD
OV
DD
OV
DD
ENABLE
LTC2220-1
JP3
JP1
SHDN GND
GND
0E
J9 J6
U4 24LCO25
* FOR AIN > 100MHz, REPLACE T1 WITH A ETC1-1-13
U3
U1 FINII08
U2 FINII08
O mung \NPUT LTCZZ ZUCUP ‘2 B_\ T/ No MSFS FWD m wan m finer" com swnw vvu vim ch cownwm A row cusram us: om I I b—d mm» 0 \NPVY DC750A - 45 J9 ADC m5 N E w a5 n SENSE “N” Rm R9 W” C; [IE3 ,3 - @vnu ¢33v {'3 C7 M MD m:/ :15 um FEEm' 0m R‘
24
LTC2220-1
2220_1fa
APPLICATIO S I FOR ATIO
WUUU
Silkscreen Top
LTC2220-1
25
2220_1fa
Layer 1 Component Side
APPLICATIO S I FOR ATIO
WUUU
Layer 2 GND Plane
vm Anewu an L7LJ§1WEI§B
26
LTC2220-1
2220_1fa
Layer 3 Power Plane
APPLICATIO S I FOR ATIO
WUUU
Layer 4 Bottom Side
f"fifififififlfifipfififififififi"" [A fifififififlflfi flflflflflflé 1‘ ““fififlfififififi anuom (A SLDEs) —“ r—' ORIN I TUP MARK (SEE NOTE 5) ULUUUU L U UUUUUU mwmmmmmmm mnmm \ i i T L i L i i flflflflflflflfl NOTE 1 DRAWWG cuNEuRMs TD JEDEC PACKAGE DUTLWE Morzzu vARLAnuN mes 2 ALL mMEMsLoMs ARE m MLLLLMETERS 3 mMEMsLoNs OF EXPUSED PAD um aormM OF PACKAGE DD NOT WCLUDE MuLD FLASH MoLDELAsR \FPRESEMT SHALL NOT EXCEED n 20mm 0" ANY 5qu \F A EXPUSED PAD SHALL BE SDLDER PLATED 5 sRADED AREA ‘5 DNLY A REFERENCE FOR 7W1 LucAnuN ON THE TUP AND BUTTOM a DRAWWG NOT TO SCALE ‘j‘t wavmanan kusneu by Lmem Technmagy I EAR Howevevnovesnonsmmty\sassumemumsu ‘ ’ T m NOLCGY Lammamaunevcaunecuauantsmmuas a
LTC2220-1
27
2220_1fa
UP Package
64-Lead Plastic QFN (9mm × 9mm)
(Reference LTC DWG # 05-08-1705)
PACKAGE DESCRIPTIO
U
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
9 .00 ± 0.10
(4 SIDES)
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
6. DRAWING NOT TO SCALE
PIN 1 TOP MARK
(SEE NOTE 5)
0.40 ± 0.10
6463
1
2
BOTTOM VIEW—EXPOSED PAD
7.15 ± 0.10
(4-SIDES)
0.75 ± 0.05 R = 0.115
TYP
0.25 ± 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UP64) QFN 1003
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.70 ±0.05
7.15 ±0.05
(4 SIDES) 8.10 ±0.05 9.50 ±0.05
0.25 ±0.05
0.50 BSC
PACKAGE OUTLINE
PIN 1
CHAMFER
m \NCLOGV :
28
LTC2220-1
2220_1fa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2005
LT 0106 REV A • PRINTED IN USA
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
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LT1993-2 High Speed Differential Op Amp 800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain
LT®1994 Low Noise, Low Distortion Fully Differential Input/ Low Distortion: –94dBc at 1MHz
Output Amplifier/Driver
LTC2202 16-Bit, 10Msps, 3.3V ADC, Lowest Noise 150mW, 81.6dB SNR, 100dB SFDR, 48-pin QFN
LTC2208 16-Bit, 130Msps, 3.3V ADC, LVDS Outputs 1250mW, 78dB SNR, 100dB SFDR, 64-pin QFN
LTC2220 12-Bit, 170Msps, 3.3V ADC, LVDS Outputs 890mW, 67.7dB SNR, 84dB SFDR, 64-pin QFN
LTC2220-1 12-Bit, 185Msps, 3.3V ADC, LVDS Outputs 910mW, 67.7dB SNR, 80dB SFDR, 64-pin QFN
LTC2221 12-Bit, 135Msps, 3.3V ADC, LVDS Outputs 660mW, 67.8dB SNR, 84dB SFDR, 64-pin QFN
LTC2224 12-Bit, 135Msps, 3.3V ADC, High IF Sampling 630mW, 67.6dB SNR, 84dB SFDR, 48-pin QFN
LTC2230 10-Bit, 170Msps, 3.3V ADC, LVDS Outputs 890mW, 61.2dB SNR, 78dB SFDR, 64-pin QFN
LTC2231 10-Bit, 135Msps, 3.3V ADC, LVDS Outputs 660mW, 61.2dB SNR, 78dB SFDR, 64-pin QFN
LTC2255 14-Bit, 125Msps, 3V ADC, Lowest Power 395mW, 72.5dB SNR, 88dB SFDR, 32-pin QFN
LTC2284 14-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk 540mW, 72.4dB SNR, 88dB SFDR, 64-pin QFN
LT5512 DC-3GHz High Signal Level Downconverting Mixer DC to 3GHz, 21dBm IIP3, Integrated LO Buffer
LT5514 Ultralow Distortion IF Amplifier/ADC Driver with Digitally 450MHz to 1dB BW, 47dB OIP3, Digital Gain Control
Controlled Gain 10.5dB to 33dB in 1.5dB/Step
LT5515 1.5GHz to 2.5GHz Direct Conversion Quadrature Demodulator High IIP3: 20dBm at 1.9GHz, Integrated LO Quadrature Generator
LT5516 800MHz to 1.5GHz Direct Conversion Quadrature Demodulator High IIP3: 21.5dBm at 900MHz, Integrated LO Quadrature Generator
LT5517 40MHz to 900MHz Direct Conversion Quadrature Demodulator High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator
LT5522 600MHz to 2.7GHz High Linearity Downconverting Mixer 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz. NF = 12.5dB, 50Ω
Single Ended RF and LO Ports

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