PL60208x Datasheet by Microchip Technology

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PL60208X
PCIe Octal, Ultra-Low Jitter,
HCSL Frequency Synthesizer
Micrel Inc. • 2180 Fortune DriveSan Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
December 11, 2013
Revision 1.1
hbwhelp@micrel.com or (408) 955-1690
General Description
The PL602081 and PL602082 are members of the PCI
Express family of devices from Micrel and provide an
extremely low-noise timing solution for PCI Express clock
signals. They are based upon a unique synthesizer
architecture that provides very low phase noise.
The devices operate from a 3.3V or 2.5V power supply
and synthesize eight HCSL output clocks. The PL602081
synthesizes 25MHz, 100MHz, or 200MHz and the
PL602082 synthesizes 25MHz, 125MHz, or 250MHz. The
PL60208x devices accept a 25MHz crystal or LVCMOS
reference clock.
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
Block Diagram
Features
Generates eight HCSL clock outputs.
PL602081 output frequencies: 25MHz, 100MHz, or
200MHz.
PL602082 output frequencies: 25MHz, 125MHz, or
250MHz.
2.5V or 3.3V operating range.
Typical phase jitter: 250fs for 12KHz to 20MHz.
Compliant with PCI Express Gen1, Gen2, and Gen3.
Industrial temperature range (40C to +85C).
RoHS and PFOS compliant.
Available in 44-pin 7mm 7mm QFN package.
Applications
Servers
Storage systems
Switches and routers
Gigabit Ethernet
Set-top boxes/DVRs
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PL60208X
December 11, 2013
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Ordering Information(1)
Part Number
Marking
Shipping
Junction Temperature Range
Package
PL602081UMG
PL602081UMG
Tray
40° to +85°C
44-Pin QFN
PL602081UMG TR
PL602081UMG
Tape and Reel
40° to +85°C
44-Pin QFN
PL602082UMG
PL602082UMG
Tray
40° to +85°C
44-Pin QFN
PL602082UMG TR
PL602082UMG
Tape and Reel
40° to +85°C
44-Pin QFN
Note:
1. Devices are RoHS and PFOS compliant.
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PL60208X
December 11, 2013
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Pin Configuration
44-Pin QFN
(Top View)
Pin Description
Pin Number
Pin Name
Pin Type
Pin Level
Pin Name
1, 2
4, 5
7, 8
25, 26
28, 29
32, 33
35, 36
41, 42
/Q5, Q5
/Q6, Q6
/Q7, Q7
/Q0, Q0
/Q1, Q1
/Q2, Q2
/Q3, Q3
/Q4, Q4
O, (DIF)
HCSL
Differential clock output.
14
FSEL
I, (SE)
LVCMOS
Frequency select, 1 = 100MHz, 0 = 200MHz, 45KΩ pull-up.
12, 13
VDD
PWR
Power supply.
31, 37, 38
VDDO1
PWR
Power supply for outputs Q0 Q3.
16, 43, 44
VDDO2
PWR
Power supply for outputs Q4 Q7.
21, 23
VSS
(exposed
pad)
PWR
Core power supply ground. The exposed pad must be
connected to the VSS ground plane.
24, 39
VSSO1
PWR
Power supply ground for outputs Q0 Q3.
3, 6, 40
VSSO2
PWR
Power supply ground for outputs Q4 Q7.
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PL60208X
December 11, 2013
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Revision 1.1
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Pin Description (Continued)
Pin Number
Pin Name
Pin Type
Pin Level
Pin Name
9
PLL_BYPASS
I, (SE)
LVCMOS
PLL bypass, selects output source.
0 = normal PLL operation
1 = output from input reference clock or crystal
45K pull down
10
XTAL_SEL
I, (SE)
LVCMOS
Selects PLL input reference source
0 = REF_IN, 1 = XTAL, 45K pull-up
11, 20, 27,
30, 34
TEST
Factory test pins. Do not connect anything to these pins.
17
REF_IN
I, (SE)
LVCMOS
Reference clock input
18
XTAL_IN
I, (SE)
10pF crystal
Crystal reference input, no load caps needed (see Figure 6)
19
XTAL_OUT
O, (SE)
10pF crystal
Crystal reference output, no load caps needed (see Figure
6)
15
OE1
I, (SE)
LVCMOS
Output enable, outputs Q0 Q3 disable to tri-state,
0 = disabled, 1 = enabled, 45K pull-up
22
OE2
I, (SE)
LVCMOS
Output enable, outputs Q4 Q7 disable to tri-state,
0 = disabled, 1 = enabled, 45K pull-up
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Micrel, Inc.
PL60208X
December 11, 2013
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Revision 1.1
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Absolute Maximum Ratings(2)
Supply Voltage (VDD, VDDO1/2) ...................................... +4.6V
Input Voltage (VIN) ............................... 0.50V to VDD +0.5V
Lead Temperature (soldering, 20s) ............................ 260°C
Case Temperature ..................................................... 115°C
Storage Temperature (TS) ......................... 65C to 150°C
Operating Ratings(3)
Supply Voltage (VDD, VDDO1/2) ............... +2.375V to +3.465V
Ambient Temperature (TA) .......................... 40°C to +85°C
Junction Thermal Resistance(4)
QFN (JA) Still-Air ............................................... 24°C/W
QFN (JB) Junction-to-Board ............................... 8°C/W
DC Electrical Characteristics(4)
VDD = VDDO1/2 = 3.3V 5% or 2.5V 5%
VDD = 3.3V 5%, VDDO1/2 = 3.3V 5% or 2.5V 5%
TA = 40C to 85C.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
VDD,
VDDO1/2
2.5V operating range
2.375
2.5
2.625
V
VDD,
VDDO1/2
3.3V operating range
3.135
3.3
3.465
V
IDD
Supply current VDD + VDDO
Eight outputs enabled, 100MHz
Outputs 50Ω to VSS
217
270
mA
Eight outputs enabled, 200MHz
Outputs 50Ω to VSS
229
285
Four outputs enabled, 100MHz
Outputs 50Ω to VSS, OE1 or OE2 = 0
149
185
Four outputs enabled, 200MHz
Outputs 50Ω to VSS, OE1 or OE2 = 0
158
197
HCSL DC Electrical Characteristics(4)
VDD = VDDO1/2 = 3.3V 5% or 2.5V 5%
VDD = 3.3V 5%, VDDO1/2 = 3.3V 5% or 2.5V 5%
TA = 40C to 85C. RL = 50Ω to VSS
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
VOH
Output high voltage
660
700
850
mV
VOL
Output low voltage
-150
0
27
mV
VCROSS
Crossing point voltage
250
350
550
mV
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Micrel, Inc.
PL60208X
December 11, 2013
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LVCMOS (PLL_BYPASS, XTAL_SEL, FSEL, OE1, OE2) DC Electrical Characteristics(4)
VDD = 3.3V 5% or 2.5V 5%, TA = 40C to 85C.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
VIH
Input high voltage
2
VDD + 0.3
V
ViL
Input low voltage
-0.3
0.8
V
IIH
Input high current
VDD = VIN = 3.465V
150
A
IIL
Input low current
VDD = 3.465V, VIN = 0V
-150
A
REF_IN DC Electrical Characteristics(4)
VDD = 3.3V 5% or 2.5V 5%, TA = 40C to 85C.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
VIH
Input high voltage
1.1
VDD + 0.3
V
ViL
Input low voltage
-0.3
0.6
V
IIN
Input current
XTAL_SEL = VIL, VIN = 0V to VDD
-5
5
A
XTAL_SEL = VIH, VIN = VDD
20
Crystal Characteristics
Parameter
Condition
Min.
Typ.
Max.
Units
Mode of oscillation
10pF load
Fundamental, parallel resonant
Frequency
25
MHz
Equivalent series resistance (ESR)
50
Shunt capacitor, C0
2
5
pF
Correlation drive level
10
100
W
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Micrel, Inc.
PL60208X
December 11, 2013
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Revision 1.1
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AC Electrical Characteristics(4, 6)
VDD = VDDO1/2 = 3.3V 5% or 2.5V 5%
VDD = 3.3V 5%, VDDO1/2 = 3.3V 5% or 2.5V 5%
TA = 40C to 85C. RL = 50Ω to VSS
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
TR/TF
HCSL output rise/fall time
20% - 80%
150
300
450
ps
ODC
Output duty cycle
48
50
52
%
TSKEW
Output-to-output skew
Note 7
45
ps
TLOCK
PLL lock time
20
ms
Tjit()
RMS phase jitter(8)
100MHz or 125MHz
Integration range (12kHz 20MHz)
Integration range (10kHz 1.5MHz)
Integration range (1.5MHz Nyquist)
200MHz or 250MHz
Integration range (12kHz 20MHz)
Integration range (10kHz 1.5MHz)
Integration range (1.5MHz Nyquist)
254
220
142
253
222
112
fs
Notes:
2. Exceeding the absolute maximum ratings may damage the device.
3. The device is not guaranteed to function outside its operating ratings.
4. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB.
5. Specification for packaged product only
6. All phase noise measurements were taken with an Agilent 5052B phase noise system.
7. Defined as skew between outputs at the same supply voltage and with equal load conditions; Measured at the output differential crossing points.
8. Measured using 25MHz crystal as the input reference source. If using an external reference input, use a low phase noise source. With an external
reference, the phase noise will follow the input source phase noise up to about 1MHz.
hbwhel cum
Micrel, Inc.
PL60208X
December 11, 2013
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Revision 1.1
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Truth Tables
PLL_BYPASS
XTAL_SEL
OE2
OE1
INPUT
OUTPUT
0
1
1
PLL
1
1
1
XTAL/REF_IN
0
1
1
REF_IN
1
1
1
XTAL
0
1
Q4-Q7 Tri-state
1
0
Q0-Q3 Tri-state
FSEL
PLL_BYPASS
Output Frequency (MHz)
PL602081
PL602082
0
0
200
250
1
0
100
125
X
1
25
25
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Micrel, Inc.
PL60208X
December 11, 2013
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Revision 1.1
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Phase Noise Plots
Phase Noise Plot: 100MHz, 1.875MHz 20MHz 101fs
Phase Noise Plot: 100MHz, 12kHz 20MHz 254fs
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Micrel, Inc.
PL60208X
December 11, 2013
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Phase Noise Plots (Continued)
Phase Noise Plot: 200MHz, 1.875MHz 20MHz 94fs
Phase Noise Plot: 200MHz, 12kHz 20MHz 253fs
one: T_‘x1oo% T; Vm RMS PHASE NOISE/JITTER PHASE NOISE PLOT / NOISE POWER PHASE NOISE MASK I fl f2 OFFSET FREQUENCY RMS JITTER = AREA UNDER THE MASKED PHASE NOISE PLOT hbwhengmwcrelcom
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PL60208X
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Figure 1. Duty Cycle Timing
Figure 2. All Outputs Rise/Fall Time
Figure 3. RMS Phase/Noise Jitter
VDDO OSCILLOSCOPE Q 5 l 20 = 500 /Q ) g 500 VSS R ' TWO 500 TRACES OR HCSL 1000 DIFFERENTIAL TRACE OUTPUT HCSL INPUT R5 = 300, DEBOUNCE RESISTOR RY RT: 500, TERMINATION RESISTOR XTALilN ‘IUpF PARALLEL CRYSTAL :I XTALioUT hbwhelQQmIcrelcom
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PL60208X
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Figure 4. HCSL Output Load and Test Circuit
Figure 5. HCSL recommended application termination (source terminated)
Figure 6. Crystal Input Interface
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PL60208X
December 11, 2013
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Application Information
Input Reference
When operating with a crystal input reference, do not
apply a switching signal to REF_IN.
Crystal Layout
Keep the layers under the crystal as open as possible
and do not place switching signals or noisy supplies
under the crystal.
Crystal load capacitance is built inside the die so no
external capacitance is needed. See the Selecting a
Quartz crystal for the Clockworks Flex I Family of
Precision Synthesizers application note for further details.
Contact Micrel’s TCG applications group if you need
assistance on selecting a suitable crystal for your
application at: hbwhelp@micrel.com.
Power Supply Decoupling
Place the smallest value decoupling capacitor (4.7nF
above) between the VDD and VSS pins, as close as
possible to those pins and at the same side of the PCB
as the IC. The shorter the physical path from VDD to
capacitor and back from capacitor to VSS, the more
effective the decoupling. Use one 4.7nF capacitor for
each VDD pin on the PL60208X.
HCSL Outputs
HCSL outputs are to be terminated with 50Ω to VSS. For
best performance load all outputs. If you want to AC-
couple or change the termination, contact Micrel’s
application group at: hbwhelp@micrel.com.
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PL60208X
December 11, 2013
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Package Information(9)
44-Pin QFN
Note:
9. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com.
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PL60208X
December 11, 2013
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MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This
information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry,
specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability
whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product
can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant
into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A
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© 2013 Micrel, Incorporated.

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