MICRQICHIP MCP3912
2014-2019 Microchip Technology Inc. DS20005348B-page 1
MCP3912
Features:
• Four Synchronous Sampling 24-Bit Resolution
Delta-Sigma A/D Converters
• 93.5 dB SINAD, -107 dBc Total Harmonic
Distortion (THD) (up to 35th Harmonic), 112 dBFS
SFDR for Each Channel
• Enables 0.1% Typical Active Power Measurement
Error Over a 10,000:1 Dynamic Range
• Advanced Security Features:
- 16-Bit Cyclic Redundancy Check (CRC)
Checksum on All Communications for Secure
Data Transfers
- 16-Bit CRC Checksum and Interrupt Alert for
Register Map Configuration
- Register Map Lock with 8-Bit Secure Key
• 2.7V-3.6V AVDD, DVDD
• Programmable Data Rate Up to 125 ksps:
- 4 MHz Maximum Sampling Frequency
- 16 MHz Maximum Master Clock
• Oversampling Ratio Up to 4096
• Ultra-Low Power Shutdown Mode with < 10 µA
• -122 dB Crosstalk Between Channels
• Low Drift 1.2V Internal Voltage Reference:
9 ppm/°C
• Differential Voltage Reference Input Pins
• High-Gain PGA on Each Channel (up to 32 V/V)
• Phase Delay Compensation with 1 µs Time
Resolution
• Separate Data Ready Pin for Easy
Synchronization
• Individual 24-Bit Digital Offset and Gain Error
Correction for Each Channel
• High-Speed 20 MHz SPI Interface with Mode 0,0
and 1,1 Compatibility
• Continuous Read/Write Modes for Minimum
Communication Time with Dedicated
16/32-Bit Modes
• Available in 28-Lead QFN and 28-Lead SSOP
Packages
• Extended Temperature Range: -40°C to +125°C
Description:
The MCP3912 is a 3V four-channel Analog Front End
(AFE) containing four synchronous sampling Delta-
Sigma Analog-to-Digital Converters (ADC), four PGAs,
phase delay compensation block, low-drift internal volt-
age reference, Digital Offset and Gain Error Calibration
registers, and high-speed 20 MHz SPI-compatible
serial interface.
The MCP3912 ADCs are fully configurable, with
features, such as 16/24-bit resolution, Oversampling
Ratio (OSR) from 32 to 4096, gain from 1x to 32x,
independent shutdown and Reset, dithering and auto-
zeroing. The communication is largely simplified with
8-bit commands, including various continuous Read/
Write modes and 16/24/32-bit data formats that can be
accessed by the Direct Memory Access (DMA) of an
8, 16 or 32-bit MCU. A separate Data Ready pin is also
included that can directly be connected to an Interrupt
Request (IRQ) input of an MCU.
The MCP3912 includes advanced security features to
secure the communications and the configuration set-
tings, such as a CRC-16 checksum on both serial data
outputs and static register map configuration. It also
includes a register map lock through an 8-bit secure key
to stop unwanted WRITE commands from processing.
The MCP3912 is capable of interfacing with a variety of
voltage and current sensors, including shunts, current
transformers, Rogowski coils and Hall effect sensors.
Applications:
• Polyphase Energy Meters
• Energy Metering and Power Measurement
• Automotive
• Portable Instrumentation
• Medical and Power Monitoring
• Audio/Voice Recognition
3V Four-Channel Analog Front End
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MCP3912
DS20005348B-page 2 2014-2019 Microchip Technology Inc.
Package Type
Functional Block Diagram
2
26
3
4
5
6
10 11 12 13 14
18
17
16
15
28 27 25
CH0+
CH0-
CH1-
DVDD
SDI
SDO
RESET
AGND
EP
29
7
CH1+
CH2+ 19
20
24
SCK
23
CS
OSC2
CH2-
22
OSC1/CLKI
1
89
NC
DGND
AVDD
DGND
21
AGND
REFIN-
DGND
AVDD
DVDD
CH3-
CH3+
MCP3912
5x5 QFN*
* Includes Exposed Thermal Pad (EP); see Tab l e 1 - 3 .
REFIN+/
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AVDD
CH0+
CH0-
CH3+
NC
NC
NC
NC
REFIN+/OUT
CH1-
CH1+
CH2+
CH2-
CH3-
DVDD
RESET
SDI
DGND
NC
DR
DGND
AGND
REFIN-
SDO
SCK
CS
OSC2
OSC1/CLKI
MCP3912
SSOP
OUT
DR
AMCLK
DMCLK/DRCLK
REFIN+/OUT
REFIN-
POR
AVDD
Monitoring
Vref+Vref-
VREFEXT
Voltage
Reference
Vref
+
-
Xtal Oscillator
MCLK OSC1
OSC2
Digital SPI
Interface
Clock
Generation
DMCLK OSR<2:0>
PRE<1:0>
ANALOG DIGITAL
SDO
SDI
SCK
DR
RESET
CS
AGND DGND
AVDD DVDD
CH0+
CH0- -
+
PGA
OSR/2-
PHASE1 <11:0>
MOD<3:0>
Modulator
+
OFFCAL_CH0
<23:0>
GAINCAL_CH0
<23:0>
X
DATA_CH0<23:0>
SINC3+
SINC1
Phase
Shifter
Offset
Cal.
Gain
Cal.
CH1+
CH1- -
+
PGA
OSR/2
MOD<7:4>
Modulator
+
OFFCAL_CH1
<23:0>
GAINCAL_CH1
<23:0>
X
DATA_CH1<23:0>
SINC3+
SINC1
Phase
Shifter
Offset
Cal.
Gain
Cal.
CH2+
CH2- -
+
PGA
OSR/2-
PHASE1 <23:12>
MOD<11:8>
Modulator
OFFCAL_CH2
<23:0>
GAINCAL_CH2
<23:0>
X
DATA_CH2<23:0>
SINC3+
SINC1
Phase
Shifter
Offset
Cal.
Gain
Cal.
CH3+
CH3- -
+
PGA
OSR/2
MOD<15:12>
Modulator
OFFCAL_CH3
<23:0>
GAINCAL_CH3
<23:0>
X
DATA_CH3<23:0>
SINC3+
SINC1
Phase
Shifter
Offset
Cal.
Gain
Cal.
POR
DVDD
Monitoring
2014-2019 Microchip Technology Inc. DS20005348B-page 3
MCP3912
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD ..................................................................... -0.3V to 4.0V
Digital inputs and outputs w.r.t. AGND................. -0.3V to 4.0V
Analog input w.r.t. AGND .........................................-2V to +2V
VREF input w.r.t. AGND ............................... -0.6V to VDD +0.6V
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
Soldering temperature of leads (10 seconds) ............. +300°C
ESD on all pins (HBM,MM) ....................................4 kV, 300V
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at those or any other condi-
tions, above those indicated in the operational listings
of this specification, is not implied. Exposure to
maximum rating conditions for extended periods may
affect device reliability.
1.1 Electrical Specifications
TABLE 1-1: ANALOG SPECIFICATIONS
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 3V; MCLK = 4 MHz;
PRE[1:0] = 00; OSR = 256; GAIN = 1; VREFEXT = 0; CLKEXT = 1; DITHER[1:0] = 11; BOOST[1:0] = 10; VCM =0V;
TA= -40°C to +125°C; VIN = -0.5 dBFS @ 50/60 Hz on all channels.
Characteristic Sym. Min. Typ. Max. Units Conditions
ADC Performance
Resolution
(No Missing Codes)
24 — — bits OSR = 256 or greater
Sampling Frequency fS(DMCLK) — 1 4 MHz For maximum condition,
BOOST[1:0] = 11
Output Data Rate fD(DRCLK) — 4 125 ksps For maximum condition,
BOOST[1:0] = 11,
OSR = 32
Analog Input Absolute
Voltage on CHn+/- Pins,
n between 0 and 3
CHn+/- -1 — +1 V All analog input channels
measured to AGND
Analog Input Leakage
Current
IIN — ±1 — nA RESET[3:0] = 1111,
MCLK running continuously
Differential Input
Voltage Range
(CHn+ – CHn-) -600/GAIN — +600/GAIN mV VREF =1.2V,
proportional to VREF
Offset Error VOS -1 0.2 1 mV Note 5
Offset Error Drift — 0.5 — µV/°C
Gain Error GE -5 — +5 % Note 5
Note 1: Dynamic performance specified at -0.5 dB below the maximum differential input value,
VIN = 1.2 VPP = 424 mVRMS @50/60Hz, V
REF =1.2V. See Section 4.0 “Terminology and Formulas” for
definition. This parameter is established by characterization and not 100% tested.
2: For these operating currents, the following Configuration bit settings apply: SHUTDOWN[3:0] = 0000,
RESET[3:0] = 0000, VREFEXT = 0, CLKEXT = 0.
3: For these operating currents, the following Configuration bit settings apply: SHUTDOWN[3:0] = 1111,
VREFEXT = 1, CLKEXT = 1.
4: Measured on one channel versus all others channels. The average of crosstalk performance over all
channels (see Figure 2-32 for individual channel performance).
5: Applies to all gains. Offset and gain errors depend on PGA gain setting; see typical performance curves for
typical performance.
6: Outside of this range, ADC accuracy is not specified. An extended input range of ±2V can be applied
continuously to the part with no damage.
7: For proper operation and for optimizing ADC accuracy, AMCLK should be limited to the maximum frequency
defined in Table 5-2, as a function of the BOOST and PGA settings chosen. MCLK can take larger values as
long as the prescaler settings (PRE[1:0]) limit AMCLK = MCLK/PRESCALE in the defined range in Table 5-2.
8: This parameter is established by characterization and not 100% tested.
MCP3912
DS20005348B-page 4 2014-2019 Microchip Technology Inc.
Gain Error Drift — 1 — ppm/°C
Integral Nonlinearity INL — 5 — ppm
Measurement Error ME — 0.1 — % Measured with a 10,000:1
dynamic range
(from 600 mVPeak to 60 µVPeak),
AVDD =DV
DD =3V,
measurement points averaging
time: 20 seconds, measured on
each channel pair (CH0/1, CH2/3)
Differential Input
Impedance
ZIN 232 — — kG = 1, proportional to 1/AMCLK
142 — — kG = 2, proportional to 1/AMCLK
72 — — kG = 4, proportional to 1/AMCLK
38 — — kG = 8, proportional to 1/AMCLK
36 — — kG = 16, proportional to 1/AMCLK
33 — — kG = 32, proportional to 1/AMCLK
Signal-to-Noise and
Distortion Ratio (Note 1)
SINAD 92 93.5 — dB
Total Harmonic Distortion
(Note 1)
THD — -107 -103 dBc Includes the first 35 harmonics
Signal-to-Noise Ratio
(Note 1)
SNR 92 94 — dB
Spurious-Free Dynamic
Range (Note 1)
SFDR — 112 — dBFS
Crosstalk (50, 60 Hz) CTALK — -122 — dB Note 4
AC Power
Supply Rejection
AC PSRR — -73 — dB AVDD =DV
DD =3V+0.6 V
PP
,
50/60 Hz, 100/120 Hz
DC Power Supply Rejection DC PSRR — -73 — dB AVDD = DVDD = 2.7V to 3.6V
DC Common-mode Rejection DC CMRR — -100 — dB VCM from -1V to +1V
TABLE 1-1: ANALOG SPECIFICATIONS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 3V; MCLK = 4 MHz;
PRE[1:0] = 00; OSR = 256; GAIN = 1; VREFEXT = 0; CLKEXT = 1; DITHER[1:0] = 11; BOOST[1:0] = 10; VCM =0V;
TA= -40°C to +125°C; VIN = -0.5 dBFS @ 50/60 Hz on all channels.
Characteristic Sym. Min. Typ. Max. Units Conditions
Note 1: Dynamic performance specified at -0.5 dB below the maximum differential input value,
VIN = 1.2 VPP = 424 mVRMS @50/60Hz, V
REF =1.2V. See Section 4.0 “Terminology and Formulas” for
definition. This parameter is established by characterization and not 100% tested.
2: For these operating currents, the following Configuration bit settings apply: SHUTDOWN[3:0] = 0000,
RESET[3:0] = 0000, VREFEXT = 0, CLKEXT = 0.
3: For these operating currents, the following Configuration bit settings apply: SHUTDOWN[3:0] = 1111,
VREFEXT = 1, CLKEXT = 1.
4: Measured on one channel versus all others channels. The average of crosstalk performance over all
channels (see Figure 2-32 for individual channel performance).
5: Applies to all gains. Offset and gain errors depend on PGA gain setting; see typical performance curves for
typical performance.
6: Outside of this range, ADC accuracy is not specified. An extended input range of ±2V can be applied
continuously to the part with no damage.
7: For proper operation and for optimizing ADC accuracy, AMCLK should be limited to the maximum frequency
defined in Table 5-2, as a function of the BOOST and PGA settings chosen. MCLK can take larger values as
long as the prescaler settings (PRE[1:0]) limit AMCLK = MCLK/PRESCALE in the defined range in Table 5-2.
8: This parameter is established by characterization and not 100% tested.
2014-2019 Microchip Technology Inc. DS20005348B-page 5
MCP3912
Internal Voltage Reference
Tole r an c e V REF 1.176 1.2 1.224 V VREFEXT = 0, TA = +25°C only
Temperature Coefficient TCVREF — 9 — ppm/°C TA = -40°C to +125°C,
VREFEXT = 0,
VREFCAL[7:0] = 0x50
Output Impedance ZOUTVREF —0.6— kVREFEXT = 0
Internal Voltage Reference
Operating Current
AIDDVREF — 54 — µA VREFEXT = 0,
SHUTDOWN[3:0] = 1111
Voltage Reference Input
Input Capacitance — — 10 pF
Differential Input Voltage
Range (VREF+ – VREF-)
VREF 1.1 — 1.3 V VREFEXT = 1
Absolute Voltage on
REFIN+ Pin
VREF+ VREF- +1.1 — V
REF- + 1.3 V VREFEXT = 1
Absolute Voltage
REFIN- Pin
VREF- -0.1 — +0.1 V REFIN- should be connected to
AGND when VREFEXT = 0
Master Clock Input
Master Clock Input
Frequency Range
fMCLK — — 20 MHz CLKEXT = 1 (Note 7)
Crystal Oscillator Operating
Frequency Range
fXTAL 1 — 20 MHz CLKEXT = 0 (Note 7)
Analog Master Clock AMCLK — — 16 MHz (Note 7)
Crystal Oscillator
Operating Current
DIDDXTAL — 80 — µA CLKEXT = 0
Power Supply
Operating Voltage, Analog AVDD 2.7 — 3.6 V
Operating Voltage, Digital DVDD 2.7 — 3.6 V
Operating Current, Analog
(Note 2)
IDD,A — 2.8 4 mA BOOST[1:0] = 00
— 3.4 4.5 mA BOOST[1:0] = 01
— 4.7 6.4 mA BOOST[1:0] = 10
— 8.1 11.8 mA BOOST[1:0] = 11
TABLE 1-1: ANALOG SPECIFICATIONS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 3V; MCLK = 4 MHz;
PRE[1:0] = 00; OSR = 256; GAIN = 1; VREFEXT = 0; CLKEXT = 1; DITHER[1:0] = 11; BOOST[1:0] = 10; VCM =0V;
TA= -40°C to +125°C; VIN = -0.5 dBFS @ 50/60 Hz on all channels.
Characteristic Sym. Min. Typ. Max. Units Conditions
Note 1: Dynamic performance specified at -0.5 dB below the maximum differential input value,
VIN = 1.2 VPP = 424 mVRMS @50/60Hz, V
REF =1.2V. See Section 4.0 “Terminology and Formulas” for
definition. This parameter is established by characterization and not 100% tested.
2: For these operating currents, the following Configuration bit settings apply: SHUTDOWN[3:0] = 0000,
RESET[3:0] = 0000, VREFEXT = 0, CLKEXT = 0.
3: For these operating currents, the following Configuration bit settings apply: SHUTDOWN[3:0] = 1111,
VREFEXT = 1, CLKEXT = 1.
4: Measured on one channel versus all others channels. The average of crosstalk performance over all
channels (see Figure 2-32 for individual channel performance).
5: Applies to all gains. Offset and gain errors depend on PGA gain setting; see typical performance curves for
typical performance.
6: Outside of this range, ADC accuracy is not specified. An extended input range of ±2V can be applied
continuously to the part with no damage.
7: For proper operation and for optimizing ADC accuracy, AMCLK should be limited to the maximum frequency
defined in Table 5-2, as a function of the BOOST and PGA settings chosen. MCLK can take larger values as
long as the prescaler settings (PRE[1:0]) limit AMCLK = MCLK/PRESCALE in the defined range in Table 5-2.
8: This parameter is established by characterization and not 100% tested.
DDSD
DD
MCP3912
DS20005348B-page 6 2014-2019 Microchip Technology Inc.
1.2 Serial Interface Characteristics
Operating Current, Digital IDD,D — 0.28 0.6 mA MCLK = 4 MHz,
proportional to MCLK (Note 2)
—1.1— mAMCLK = 16 MHz,
proportional to MCLK (Note 2)
Shutdown Current, Analog IDDS,A —0.01 2 µAAV
DD pin only (Notes 3 and 8)
Shutdown Current, Digital IDDS,D —0.01 4 µADV
DD pin only (Notes 3 and 8)
Pull-down Current on OSC2
Pin (External Clock mode
only)
IOSC2 — 35 — µA CLKEXT = 1
TABLE 1-2: SERIAL DC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, all parameters apply at DVDD = 2.7 to 3.6 V;
TA = -40°C to +125°C; CLOAD = 30 pF; applies to all digital I/Os.
Characteristic Sym. Min. Typ. Max. Units Conditions
High-Level Input Voltage VIH 0.7 DVDD — — V Schmitt triggered
Low-Level Input Voltage VIL ——0.3 DV
DD V Schmitt triggered
Input Leakage Current ILI — — ±1 µA CS = DVDD,
VIN = DGND to DVDD
Output Leakage Current ILO — — ±1 µA CS = DVDD,
VOUT = DGND or DVDD
Hysteresis of
Schmitt Trigger Inputs
VHYS —500— mVDV
DD = 3.3V only (Note 2)
Low-Level Output Voltage VOL ——0.2DV
DD VI
OL = +1.7 mA
High-Level Output Voltage VOH 0.75 DVDD —— VI
OH = -1.7 mA
Internal Capacitance
(All Inputs and Outputs)
CINT ——7 pFT
A = +25°C, SCK = 1.0 MHz,
DVDD =3.3V (Note 1)
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is established by characterization and not production tested.
TABLE 1-1: ANALOG SPECIFICATIONS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 3V; MCLK = 4 MHz;
PRE[1:0] = 00; OSR = 256; GAIN = 1; VREFEXT = 0; CLKEXT = 1; DITHER[1:0] = 11; BOOST[1:0] = 10; VCM =0V;
TA= -40°C to +125°C; VIN = -0.5 dBFS @ 50/60 Hz on all channels.
Characteristic Sym. Min. Typ. Max. Units Conditions
Note 1: Dynamic performance specified at -0.5 dB below the maximum differential input value,
VIN = 1.2 VPP = 424 mVRMS @50/60Hz, V
REF =1.2V. See Section 4.0 “Terminology and Formulas” for
definition. This parameter is established by characterization and not 100% tested.
2: For these operating currents, the following Configuration bit settings apply: SHUTDOWN[3:0] = 0000,
RESET[3:0] = 0000, VREFEXT = 0, CLKEXT = 0.
3: For these operating currents, the following Configuration bit settings apply: SHUTDOWN[3:0] = 1111,
VREFEXT = 1, CLKEXT = 1.
4: Measured on one channel versus all others channels. The average of crosstalk performance over all
channels (see Figure 2-32 for individual channel performance).
5: Applies to all gains. Offset and gain errors depend on PGA gain setting; see typical performance curves for
typical performance.
6: Outside of this range, ADC accuracy is not specified. An extended input range of ±2V can be applied
continuously to the part with no damage.
7: For proper operation and for optimizing ADC accuracy, AMCLK should be limited to the maximum frequency
defined in Table 5-2, as a function of the BOOST and PGA settings chosen. MCLK can take larger values as
long as the prescaler settings (PRE[1:0]) limit AMCLK = MCLK/PRESCALE in the defined range in Table 5-2.
8: This parameter is established by characterization and not 100% tested.
CS
CS
CS
RESET
DR
2014-2019 Microchip Technology Inc. DS20005348B-page 7
MCP3912
TABLE 1-3: SERIAL AC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, all parameters apply at DVDD = 2.7 to 3.6V;
TA = -40°C to +125°C; GAIN = 1; CLOAD = 30 pF.
Characteristic Sym. Min. Typ. Max. Units Conditions
Serial Clock Frequency fSCK —— 20MHz
CS Setup Time tCSS 25 — — ns
CS Hold Time tCSH 50 — — ns
CS Disable Time tCSD 50 — — ns
Data Setup Time tSU 5— —ns
Data Hold Time tHD 10 — — ns
Serial Clock High Time tHI 20 — — ns
Serial Clock Low Time tLO 20 — — ns
Serial Clock Delay Time tCLD 50 — — ns
Serial Clock Enable Time tCLE 50 — — ns
Output Valid from SCK Low tDO — — 25 ns
Output Hold Time tHO 0— —nsNote 1
Output Disable Time tDIS — — 25 ns Note 1
Reset Pulse Width (RESET)t
MCLR 100 — — ns
Data Transfer Time to DR
(Data Ready)
tDODR — — 25 ns Note 2
Data Ready Pulse Low Time tDRP —1/(2xDMCLK) — µs
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is established by characterization and not production tested.
TABLE 1-4: TEMPERATURE SPECIFICATIONS
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = 2.7 to 3.6V; DVDD = 2.7 to 3.6V.
Parameters Sym. Min. Typ. Max. Units. Conditions
Temperature Ranges
Operating Temperature Range TA-40 — +125 °C Note 1
Storage Temperature Range TA-65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 28-Lead SSOP JA —80 — °C/W
Thermal Resistance, 28-Lead QFN JA —41 — °C/W
Note 1: The internal junction temperature (TJ) must not exceed the absolute maximum specification of +150°C.
MCP3912
DS20005348B-page 8 2014-2019 Microchip Technology Inc.
FIGURE 1-1: Serial Output Timing Diagram.
FIGURE 1-2: Serial Input Timing Diagram.
FIGURE 1-3: Data Ready Pulse/Sampling Timing Diagram.
H
FIGURE 1-4: Timing Waveforms.
tCSH
tDIS
tHI tLO
fSCK
CS
SCK
SDO MSB Out LSB Out
SDI
Mode 1,1
Mode 0,0
tHO
tDO
DON’T CARE
CS
SCK
SDI LSB InMSB In
Mode 1,1
Mode 0,0
tCSS
tSU tHD
tCSD
tCSH tCLD
tCLE
SDO HIGH-Z
tHI tLO
fSCK
DR
SCK
tDRP
SDO
1/fD
tDODR
CS
VIH
Waveform for tDIS
HIGH-Z
90%
10%
SDO
SCK
SDO
tDO
Timing Waveform for tDO
tDIS
,_ 4n 05R = 255
u an
3
E-m
440
-1sn
FIGURE 2-1: Spectral Response. FIGURE 2-4: Spectral Response.
40 v." = .59 ms @ an m
E
E -1 20
450
0 5m) 1m") 15““ 200“
FIGURE 2-2: Spectral Response. FIGURE 2-5: Measurement Error
-140
FIGURE 2-3: Spectral Response. FIGURE 2-6: Measurement Error
2014-2019 Microchip Technology Inc. DS20005348B-page 9
MCP3912
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, AVDD = 3V; DVDD = 3V; TA = +25°C; MCLK = 4 MHz; PRESCALE = 1;
OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz on all channels; VREFEXT = 0;
CLKEXT = 1; BOOST[1:0] = 10.
FIGURE 2-1: Spectral Response.
FIGURE 2-2: Spectral Response.
FIGURE 2-3: Spectral Response.
FIGURE 2-4: Spectral Response.
FIGURE 2-5: Measurement Error
with 1-Point Calibration.
FIGURE 2-6: Measurement Error
with 2-Point Calibration.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
-
140
-120
-100
-80
-60
-40
-20
0
Amplitude (dB)
Vin = -0.5 dBFS @ 60 Hz
fD= 3.9 ksps
OSR = 256
Dithering = Off
16 ksamples FFT
-180
-160
140
0 500 1000 1500 2000
Frequency (Hz)
20
0Vin = -60 dBFS @ 60 Hz
-40
-
20
B
)
f
D= 3.9 ksps
OSR = 256
Dithering = Off
-80
-60
de (d
B
16 ksamples FFT
-120
-100
mplitu
-
160
-140
A
-180
-
160
0
500
1000
1500
2000
0
500
1000
1500
2000
Frequency (Hz)
-
140
-120
-100
-80
-60
-40
-20
0
Amplitude (dB)
V
in
= -0.5 dBFS @ 60 Hz
f
D
= 3.9 ksps
OSR = 256
Dithering = Maximum
16 ksamples FFT
-180
-160
140
0 500 1000 1500 2000
Frequency (Hz)
0
-40
-20
0
)
Vin = -60 dBFS @ 60 Hz
fD= 3.9 ksps
OSR = 256
-80
-60
d
e (dB
)
Dithering = Maximum
16 ksamples FFT
-120
-100
m
plitu
d
-160
-140
A
m
-180
0 500 1000 1500 2000
Frequency (Hz)
-1.0%
-0.5%
0.0%
0.5%
1.0%
0.01 0.1 1 10 100 1000
Measurement Error (%)
Current Channel Input Amplitude (mVPeak)
% Error Channel 0, 1
-1.0%
-0.5%
0.0%
0.5%
1.0%
0.01 0.1 1 10 100 1000
Measurement Error (%)
Current Channel Input Amplitude (mVPeak)
% Error Channel 0, 1
nenoe
a!
I E
Total Harmonic nimnian (-dBc)
FIGURE 2-7: THD Repeatability FIGURE 2-10: Output Noise Histogram.
. in
FIGURE 2-8: Spurious Free Dynamic FIGURE 2-11: THD vs.OSR.
3
E
E
o
O
o
a. —Dllherlng=Mnx\mu
Signal to Nnise and Distortion (an) oversampling Rllia (05R)
FIGURE 2-9: SINAD Repeatability FIGURE 2-12: SINAD vs. OSR.
MCP3912
DS20005348B-page 10 2014-2019 Microchip Technology Inc.
Note: Unless otherwise indicated, AVDD = 3V; DVDD = 3V; TA = +25°C; MCLK = 4 MHz; PRESCALE = 1;
OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz on all channels; VREFEXT = 0;
CLKEXT = 1; BOOST[1:0] = 10.
FIGURE 2-7: THD Repeatability
Histogram.
FIGURE 2-8: Spurious Free Dynamic
Range Repeatability Histogram.
FIGURE 2-9: SINAD Repeatability
Histogram.
FIGURE 2-10: Output Noise Histogram.
FIGURE 2-11: THD vs.OSR.
FIGURE 2-12: SINAD vs. OSR.
e
rrenc
e
f
Occu
e
ncy o
f
F
requ
e
-108.2 -107.8 -107.4 -107.0 -106.6 -106.2
F
Total Harmonic Distortion (
dBc)
Total Harmonic Distortion (
-
dBc)
q
uency of Occurrence
111.7 112.3 112.9 113.5 114.1 114.7 115.3 115.9
Fre
q
Spurious Free Dynamic Range (dBFS)
e
u
rrenc
e
o
f Occ
u
ency
o
Frequ
93.3 93.4 93.5 93.6 93.7 93.8
Signal to Noise and Distortion (dB)
Signal to Noise and Distortion (dB)
u
ency of Occurrence
Standar deviation = 78 LSB
Noise = 7.4ȝVrms
16 ksamples
448
481
514
548
581
614
647
680
714
747
780
813
846
880
913
946
979
1,012
1,046
1,079
1,112
Freq
u
Output Noise (LSB)
-120
-115
-110
-105
-100
-95
-90
al Harmonic Distortion
(dBc)
Dithering=Maximum
Dithering=Medium
Dithering=Minimum
Dithering=Off
-130
-125
32 64 128 256 512 1024 2048 4096
Tot
Oversampling Ratio (OSR)
110
95
100
105
nd
d
B)
85
90
95
N
oise a
R
atio (
d
75
80
85
al-to-
N
o
rtion
R
Dithering
=
Maximu
65
70
Sign
Dist
o
Dithering Maximu
m
Dithering=Medium
60
32 64 128 256 512 1024 2048 4096
Oversampling Ratio (OSR)
Oversampling Ratio (OSR)
'55
85
75 —DllherIng=Maxlmum
iDllherIng=OH
nal -ln-
0 li Rali (05R)
IgnaI-m-Nolse
:1
7301251 = 01
a 1n12141s
1B
FIGURE 2-13: SNR vs.OSR.
FIGURE 2-16: SINAD vs. MCLK.
= -110 ..
5 g
E. ‘100 - A
.° K —Dllhermg=Maxlmum
i :
(II iDllhering=Ofl (II
2 4 6 B 1|] 12 14 15 18
o Ii Rali (05R)
FIGURE 2-14: SFDR VS. OSR. FIGURE 2-17: SNR VS. MCLK.
E n.
n.
-E
E »1nn m:
2 A a 8101214151820
FIGURE 2-15: THD vs. MCLK. FIGURE 2-18: SFDR VS. MCLK.
2014-2019 Microchip Technology Inc. DS20005348B-page 11
MCP3912
Note: Unless otherwise indicated, AVDD = 3V; DVDD = 3V; TA = +25°C; MCLK = 4 MHz; PRESCALE = 1;
OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz on all channels; VREFEXT = 0;
CLKEXT = 1; BOOST[1:0] = 10.
L
FIGURE 2-13: SNR vs.OSR.
FIGURE 2-14: SFDR vs. OSR.
FIGURE 2-15: THD vs. MCLK.
FIGURE 2-16: SINAD vs. MCLK.
FIGURE 2-17: SNR vs. MCLK.
FIGURE 2-18: SFDR vs. MCLK.
110
95
100
105
(
dB)
85
90
95
Ratio
(
75
80
85
-
Noise
Dithering
=
Maximum
65
70
75
nal-to
-
Dithering Maximum
Dithering=Medium
Dithering=Minimum
Dithering=Off
60
32 64 128 256 512 1024 2048 4096
Sig
O li R ti (OSR)
O
versamp
li
ng
R
a
ti
o
(OSR)
120
110
115
n
amic
)
100
105
110
e
e Dy
n
(
dBFS
)
95
100
o
us Fr
e
R
ange
(
Ditherin
g
=Maximum
85
90
Spuri
o
R
g
Dithering=Medium
Dithering=Minimum
Dithering
=
Off
80
32 64 128 256 512 1024 2048 4096
O li R ti (OSR)
Dithering Off
O
versamp
li
ng
R
a
ti
o
(OSR)
100
-95
-90
-85
-80
-75
-70
-65
-60
a
l Harmonic Distortion
(dB)
Boost = 00
Boost = 01
Boost = 10
Boost = 11
-110
-105
-
100
2 4 6 8 10 12 14 16 18 20
Tot
a
MCLK Frequency (MHz)
100
90
95
e
and
80
85
o
-Nois
e
t
ortion
dB)
75
80
g
nal-t
o
Dis
t
(
65
70
Si
g
Boost = 00
Boost = 01
60
2 4 6 8 10 12 14 16 18
Boost = 10
MCLK Frequency (MHz)
100
90
95
t
io
80
85
ise Ra
t
)
75
80
-to-No
(dB
)
65
70
Signal
Boost = 00
Boost = 01
Boost = 10
60
2 4 6 8 1012141618
Boost = 10
Boost = 11
MCLK Frequency (MHz)
120
110
amic
90
100
e
e Dyn
ge
F
S)
80
90
o
us Fr
e
Ran
(dB
F
70
80
Spuri
o
Boost = 00
Boost = 01
Boost = 10
60
2
4
6
8
10
12
14
16
18
20
Boost = 11
2
4
6
8
10
12
14
16
18
20
MCLK Frequency (MHz)
I
FIGURE 2-19: THD VS. GAIN. FIGURE 2-22: SFDR VS. GAIN.
\ I
\ _
\ :
~§
, E i
_ \
FIGURE 2-20: SINAD VS. GAIN. FIGURE 2-23: THD VS. Input Signal
\ /
—\
r
7‘ mun w
FIGURE 2-21: SNR VS. GAIN. FIGURE 2-24: SINAD VS. Input Signal
MCP3912
DS20005348B-page 12 2014-2019 Microchip Technology Inc.
Note: Unless otherwise indicated, AVDD = 3V; DVDD = 3V; TA = +25°C; MCLK = 4 MHz; PRESCALE = 1;
OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz on all channels; VREFEXT = 0;
CLKEXT = 1; BOOST[1:0] = 10.
FIGURE 2-19: THD vs. GAIN.
FIGURE 2-20: SINAD vs. GAIN.
FIGURE 2-21: SNR vs. GAIN.
FIGURE 2-22: SFDR vs. GAIN.
FIGURE 2-23: THD vs. Input Signal
Amplitude.
FIGURE 2-24: SINAD vs. Input Signal
Amplitude.
-140
-120
-100
-80
-60
-40
-20
0
12481632
Total Harmonic DistorWion (dB)
Gain (V/V)
OSR = 32
OSR = 64
OSR = 128
OSR = 256
OSR = 512
OSR = 1024
OSR = 2048
OSR = 4096
0
20
40
60
80
100
120
12481632
Signal-to-Noise and Distortion
Ratio (dB)
Gain (V/V)
OSR = 32
OSR = 64
OSR = 128
OSR = 256
OSR = 512
OSR = 1024
OSR = 2048
OSR = 4096
0
20
40
60
80
100
120
12481632
Signal-to-Noise Ratio (dB)
Gain (V/V)
OSR = 32
OSR = 64
OSR = 128
OSR = 256
OSR = 512
OSR = 1024
OSR = 2048
OSR = 4096
0
20
40
60
80
100
120
140
12481632
SpuriousFree Dynamic Range
(dBFS)
Gain (V/V)
OSR = 32
OSR = 64
OSR = 128
OSR = 256
OSR = 512
OSR = 1024
OSR = 2048
OSR = 4096
-120
-100
-80
-60
-40
-20
0.001 0.01 0.1 1 10 100 1000
Total Harmonic Distortion (dB)
Input Signal Amplitude (mVPK)
GAIN = 1x
GAIN = 2x
GAIN = 4x
GAIN = 8x
GAIN = 16x
GAIN = 32x
-20
0
20
40
60
80
100
0.001 0.01 0.1 1 10 100 1000
Signal-to-Noise and Distortion
Ratio (dB)
Input Signal Amplitude (mVPK)
GAIN = 1x
GAIN = 2x
GAIN = 4x
GAIN = 8x
GAIN = 16x
GAIN = 32x
FIGURE 2-25: SNR vs. Input Signal FIGURE 2-28: THD vs. Temperature.
FIGURE 2-26: SFDR vs. Input Signal FIGURE 2-29: SINAD vs. Temperature.
FIGURE 2-27: SINAD vs. Input Frequency. FIGURE 2-30: SNR vs. Temperature.
2014-2019 Microchip Technology Inc. DS20005348B-page 13
MCP3912
Note: Unless otherwise indicated, AVDD = 3V; DVDD = 3V; TA = +25°C; MCLK = 4 MHz; PRESCALE = 1;
OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz on all channels; VREFEXT = 0;
CLKEXT = 1; BOOST[1:0] = 10.
FIGURE 2-25: SNR vs. Input Signal
Amplitude.
FIGURE 2-26: SFDR vs. Input Signal
Amplitude.
FIGURE 2-27: SINAD vs. Input Frequency.
FIGURE 2-28: THD vs. Temperature.
FIGURE 2-29: SINAD vs. Temperature.
FIGURE 2-30: SNR vs. Temperature.
-20
0
20
40
60
80
100
0.001 0.01 0.1 1 10 100 1000
Signal-to-Noise Ratio (dB)
Input Signal Amplitude (mVPK)
GAIN = 1x
GAIN = 2x
GAIN = 4x
GAIN = 8x
GAIN = 16x
GAIN = 32x
0
20
40
60
80
100
120
140
0.001 0.01 0.1 1 10 100 1000
SpuriousFree Dyanmic Range
(dBFS)
Input Signal Amplitude (mVPK)
GAIN = 1x
GAIN = 2x
GAIN = 4x
GAIN = 8x
GAIN = 16x
GAIN = 32x
0
20
40
60
80
100
120
10 100 1000 10000 100000
Signal-to-Noise and Distortion
Ratio (dB)
Signal Frequency (Hz)
OSR = 32
OSR = 64
OSR = 128
OSR = 256
OSR = 512
OSR = 1024
OSR = 2048
OSR = 4096
-120
-100
-80
-60
-40
-20
0
-50 -25 0 25 50 75 100 125
Total Harmonic Distortion (dB)
Temperature (°C)
GAIN = 1x
GAIN = 2x
GAIN = 4x
GAIN = 8x
GAIN = 16x
GAIN = 32x
0
10
20
30
40
50
60
70
80
90
100
-50 -25 0 25 50 75 100 125
Signal-to-Noise and Distortion
Ratio (dB)
Temperature (°C)
GAIN = 1x
GAIN = 2x
GAIN = 4x
GAIN = 8x
GAIN = 16x
GAIN = 32x
0
10
20
30
40
50
60
70
80
90
100
-50 -25 0 25 50 75 100 125
Signal-to-Noise Ratio (dB)
Temperature (°C)
GAIN = 1x
GAIN = 2x
GAIN = 4x
GAIN = 8x
GAIN = 16x
GAIN = 32x
FIGURE 2-31: SFDR vs. Temperature.
FIGURE 2-34:
Channel Offset Matching
FIGURE 2-32: Crosstalk vs. Measured
FIGURE 2-35:
Gain Error vs. Temperature
FIGURE 2-33: Offset vs. Temperature vs.
FIGURE 2-36:
Internal Voltage Reference
MCP3912
DS20005348B-page 14 2014-2019 Microchip Technology Inc.
Note: Unless otherwise indicated, AVDD = 3V; DVDD = 3V; TA = +25°C; MCLK = 4 MHz; PRESCALE = 1;
OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz on all channels; VREFEXT = 0;
CLKEXT = 1; BOOST[1:0] = 10.
FIGURE 2-31: SFDR vs. Temperature.
FIGURE 2-32: Crosstalk vs. Measured
Channel.
FIGURE 2-33: Offset vs. Temperature vs.
Gain.
FIGURE 2-34: Channel Offset Matching
vs. Temperature.
FIGURE 2-35: Gain Error vs. Temperature
vs. Gain.
FIGURE 2-36: Internal Voltage Reference
vs. Temperature.
0
20
40
60
80
100
120
-50 -25 0 25 50 75 100 125
SpuriousFree Dyanmic Range
(dBFS)
Temperature (°C)
GAIN = 1x
GAIN = 2x
GAIN = 4x
GAIN = 8x
GAIN = 16x
GAIN = 32x
-140
-120
-100
-80
-60
-40
-20
0
0123
Crosstalk (dB)
Measured Channel*
28LD SSOP
28LD QFN
* All other channels at maximum amplitude VIN =600mV
PK @60Hz
-1000
-800
-600
-400
-200
0
200
400
600
800
1000
-40 -20 0 20 40 60 80 100 120
Offset (µV)
Temperature (°C)
GAIN = 1x
GAIN = 2x
GAIN = 4x
GAIN = 8x
GAIN = 16x
GAIN = 32x
-1000
-800
-600
-400
-200
0
200
400
600
800
1000
-40-20 0 20406080100120
Channel Offset (µV)
Temperature (°C)
Channel 0
Channel 1
Channel 2
Channel 3
-5
-3
-1
1
3
5
7
9
-40 -20 0 20 40 60 80 100 120
Gain Error (%)
Temperature (°C)
GAIN = 1x
GAIN = 2x
GAIN = 4x
GAIN = 8x
GAIN = 16x
GAIN = 32x
1.197
1.198
1.199
1.2
-40 -20 0 20 40 60 80 100 120 140
Internal Voltage Reference (V)
Temperature (°C)
FIGURE 2-37: Internal Voltage Reference FIGURE 2-40: Operating Current vs. MCLK
FIGURE 2-38: Integral Nonlmearity
FIGURE 2-39: Integral Nonlmearity
2014-2019 Microchip Technology Inc. DS20005348B-page 15
MCP3912
Note: Unless otherwise indicated, AVDD = 3V; DVDD = 3V; TA = +25°C; MCLK = 4 MHz; PRESCALE = 1;
OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz on all channels; VREFEXT = 0;
CLKEXT = 1; BOOST[1:0] = 10.
FIGURE 2-37: Internal Voltage Reference
vs. Supply Voltage.
FIGURE 2-38: Integral Nonlinearity
(Dithering Maximum).
FIGURE 2-39: Integral Nonlinearity
(Dithering Off).
FIGURE 2-40: Operating Current vs. MCLK
Frequency vs. Boost, VDD = 3V.
1.1961
1.1962
1.1963
1.1964
1.1965
1.1966
1.1967
1.1968
1.1969
2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6
Internal Voltage Reference (V)
AVDD (V)
-10
-8
-6
-4
-2
0
2
4
6
8
10
-0.6 -0.4 -0.2 0.0 0.2 0.4 0.6
Integral NonLinearity Error
(ppm)
Input Voltage (V)
-10
-8
-6
-4
-2
0
2
4
6
8
10
-0.6 -0.4 -0.2 0.0 0.2 0.4 0.6
Integral NonLinearity Error
(ppm)
Input Voltage (V)
0
2
4
6
8
10
12
14
246810121416182022242628
I
DD
(mA)
MCLK (MHz)
AIDD Boost =0.5x
AIDD Boost =0.66x
AIDD Boost =1x
AIDD Boost =2x
DIDD
MCP3912
DS20005348B-page 16 2014-2019 Microchip Technology Inc.
NOTES:
2014-2019 Microchip Technology Inc. DS20005348B-page 17
MCP3912
3.0 PIN DESCRIPTION
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1: FOUR-CHANNEL MCP3912 PIN FUNCTION TABLE
MCP3912
SSOP
MCP3912
QFN Symbol Function
125, 11 AV
DD Analog Power Supply Pin
2 27 CH0+ Noninverting Analog Input Pin for Channel 0
3 28 CH0- Inverting Analog Input Pin for Channel 0
4 29 CH1- Inverting Analog Input Pin for Channel 1
5 2 CH1+ Noninverting Analog Input Pin for Channel 1
6 3 CH2+ Noninverting Analog Input Pin for Channel 2
7 4 CH2- Inverting Analog Input Pin for Channel 2
8 5 CH3- Inverting Analog Input Pin for Channel 3
9 6 CH3+ Noninverting Analog Input Pin for Channel 3
10, 11, 12,
13, 19
7 NC No Connect (for better EMI results, connect to AGND)
14 8 REFIN+/OUT Noninverting Voltage Reference Input and Internal Reference Output Pin
15 9 REFIN- Inverting Voltage Reference Input Pin
16 10, 26 AGND Analog Ground Pin, Return Path for Internal Analog Circuitry
17, 20 13, 15, 23 DGND Digital Ground Pin, Return Path for Internal Digital Circuitry
18 14 DR Data Ready Signal Output Pin
21 16 OSC1/CLKI Oscillator Crystal Connection Pin or External Clock Input Pin
22 17 OSC2 Oscillator Crystal Connection Pin
23 18 CS Serial Interface Chip Select Input Pin
24 19 SCK Serial Interface Clock Input Pin for SPI
25 20 SDO Serial Interface Data Output Pin
26 21 SDI Serial Interface Data Input Pin
27 22 RESET Master Reset Logic Input Pin
28 12, 14 DVDD Digital Power Supply Pin
— 29 EP Exposed Thermal Pad, Must be connected to AGND or floating
DR_HIZ
DR_H|Z
MCP3912
DS20005348B-page 18 2014-2019 Microchip Technology Inc.
3.1 Analog Power Supply (AVDD)
AVDD is the power supply voltage for the analog
circuitry within the MCP3912. It is distributed on several
pins (pins 11 and 25 in the 28-lead QFN package, one
pin only in the 28-lead SSOP package). For optimal
performance, connect these pins together using a star
connection and connect the appropriate bypass capac-
itors (typically a 10 µF in parallel with a 0.1 µF ceramic).
AVDD should be maintained between 2.7V and 3.6V for
specified operation.
To ensure proper functionality of the device, at least
one of these pins must be properly connected. To
ensure optimal performance of the device, all the pins
must be properly connected. If any of these pins are left
floating, the accuracy and noise specifications are not
ensured.
3.2 ADC Differential Analog Inputs
(CHn+/CHn-)
The CHn+/- pins (n comprised between 0 and 3) are
the four fully-differential analog voltage inputs for the
Delta-Sigma ADCs.
The linear and specified region of the channels is
dependent on the PGA gain. This region corresponds
to a differential voltage range of ±600 mV/GAIN with
VREF = 1.2V.
The maximum absolute voltage, with respect to AGND,
for each CHn+/- input pin is ±1V with no distortion, and
±2V with no breaking after continuous voltage. This
maximum absolute voltage is not proportional to the
VREF voltage.
3.3 Noninverting Reference Input,
Internal Reference Output
(REFIN+/OUT)
This pin is the noninverting side of the differential
voltage reference input for all ADCs or the internal
voltage reference output.
When VREFEXT = 1, an external voltage reference
source can be used and the internal voltage reference
is disabled. When using an external differential voltage
reference, it should be connected to its VREF+ pin.
When using an external single-ended reference, it
should be connected to this pin.
When VREFEXT = 0, the internal voltage reference is
enabled and connected to this pin through a switch.
This voltage reference has minimal drive capability and
thus needs proper buffering and bypass capacitances
(a 0.1 µF ceramic capacitor is sufficient in most cases)
if used as a voltage source.
If the voltage reference is only used as an internal VREF
,
adding bypass capacitance on REFIN+/OUT is not
necessary for keeping ADC accuracy. To avoid
EMI/EMC susceptibility issues due to the antenna,
created by the REFIN+/OUT pin, if left floating, a minimal
0.1 µF ceramic capacitance can be connected.
3.4 Inverting Reference Input (REFIN-)
This pin is the inverting side of the differential voltage
reference input for all ADCs. When using an external
differential voltage reference, it should be connected to
its VREF- pin. When using an external single-ended
voltage reference, or when VREFEXT = 0 (default) and
using the internal voltage reference, the pin should be
directly connected to AGND.
3.5 Analog Ground (AGND)
AGND is the ground reference voltage for the analog
circuitry within the MCP3912. It is distributed on several
pins (pins 10 and 26 in the 28-lead QFN package, one
pin only in the 28-lead SSOP package). For optimal
performance, it is recommended to connect these pins
together using a star connection, and to connect them
to the same ground node voltage as DGND with a star
connection.
At least one of these pins needs to be properly
connected to ensure proper functionality of the device.
All of these pins need to be properly connected to
ensure optimal performance of the device. If any of
these pins are left floating, the accuracy and noise
specifications are not ensured. If an analog ground
plane is available, it is recommended that these pins be
tied to this plane of the PCB. This plane should also
reference all other analog circuitry in the system.
3.6 Digital Ground (DGND)
DGND is the ground reference voltage for the digital
circuitry within the MCP3912. It is distributed on several
pins (pins 13, 15 and 23 in the 28-lead QFN package,
two pins only in the 28-lead SSOP package). For opti-
mal performance, connect these pins together using a
star connection and connect them to the same ground
node voltage as AGND with a star connection.
At least one of these pins needs to be properly
connected to ensure proper functionality of the device.
All of these pins need to be properly connected to
ensure optimal performance of the device. If any of
these pins are left floating, the accuracy and noise
specifications are not ensured. If a digital ground plane
is available, it is recommended that these pins be tied
to this plane of the Printed Circuit Board (PCB). This
plane should also reference all other digital circuitry in
the system.
3.7 Data Ready Output (DR)
The Data Ready pin indicates if a new conversion
result is ready to be read. The default state of this pin
is logic high when DR_HIZ = 1 and is high-impedance
when DR_HIZ = 0 (default). After each conversion is
finished, a logic low pulse will take place on the Data
DR_H|Z
connected Io DVDD
v.12 1 ‘1 E
CS RESET
CS RESET
2014-2019 Microchip Technology Inc. DS20005348B-page 19
MCP3912
Ready pin to indicate the conversion result is ready as
an interrupt. This pulse is synchronous with the master
clock and has a defined and constant width.
The Data Ready pin is independent of the SPI interface
and acts like an interrupt output. The Data Ready pin
state is not latched, and the pulse width (and period)
are both determined by the MCLK frequency,
oversampling rate and internal clock prescale settings.
The data ready pulse width is equal to half a DMCLK
period and the frequency of the pulses is equal to
DRCLK (see Figure 1-3).
3.8 Oscillator and Master Clock
Input Pin (OSC1/CLKI)
OSC1/CLKI and OSC2 provide the master clock for the
device. When CLKEXT = 0, a resonant crystal or clock
source with a similar sinusoidal waveform must be
placed across the OSC1 and OSC2 pins to ensure
proper operation.
The typical clock frequency specified is 4 MHz. For
proper operation and for optimizing ADC accuracy,
AMCLK should be limited to the maximum frequency
defined in Ta b l e 5 -2 for the function of the BOOST and
PGA setting chosen. MCLK can take larger values as
long as the prescaler settings (PRE[1:0]) limit
AMCLK = MCLK/PRESCALE in the defined range in
Ta b l e 5 - 2 . Appropriate load capacitance should be
connected to these pins for proper operation.
3.9 Crystal Oscillator (OSC2)
When CLKEXT = 0, a resonant crystal or clock source
with a similar sinusoidal waveform must be placed
across the OSC1 and OSC2 pins to ensure proper
operation. Appropriate load capacitance should be
connected to these pins for proper operation.
When CLKEXT = 1, this pin should be connected to
DGND at all times (an internal pull-down operates this
function if the pin is left floating).
3.10 Chip Select (CS)
This pin is the Serial Peripheral Interface (SPI) Chip
Select that enables serial communication. When this
pin is logic high, no communication can take place. A
chip select falling edge initiates serial communication
and a chip select rising edge terminates the communi-
cation. No communication can take place, even when
CS is logic low if RESET is also logic low.
This input is Schmitt triggered.
3.11 Serial Data Clock (SCK)
This is the Serial Data Clock pin for SPI communication.
Data are clocked into the device on the rising edge of
SCK. Data are clocked out of the device on the falling
edge of SCK.
The MCP3912 SPI interface is compatible with SPI 0,0
and 1,1 modes. SPI modes can be changed during a
CS high time.
The maximum clock speed specified is 20 MHz. SCK
and MCLK are two different and asynchronous clocks;
SCK is only required when a communication happens,
while MCLK is continuously required when the part is
converting analog inputs.
This input is Schmitt triggered.
3.12 Serial Data Output (SDO)
This is the SPI Data Output pin. Data are clocked out of
the device on the falling edge of SCK.
This pin remains in a high-impedance state during the
command byte. It also stays high-impedance during the
entire communication for WRITE commands when the
CS pin is logic high or when the RESET pin is logic low.
This pin is active only when a READ command is
processed. The interface is half-duplex (inputs and
outputs do not happen at the same time).
3.13 Serial Data Input (SDI)
This is the SPI Data Input pin. Data are clocked into the
device on the rising edge of SCK. When CS is logic low,
this pin is used to communicate with a series of 8-bit
commands. The interface is half-duplex (inputs and
outputs do not happen at the same time).
Each communication starts with a chip select falling
edge followed by an 8-bit command word entered
through the SDI pin. Each command is either a read or
a write command. Toggling SDI after a read command
or when CS is logic high has no effect.
This input is Schmitt-triggered.
Note: This pin should not be left floating when the
DR_HIZ bit is low; a 100 k pull-up resistor
connected to DVDD is recommended.
Note: When CLKEXT = 1, the crystal oscillator is
disabled. OSC1 becomes the master clock
input, CLKI, a direct path for an external
clock source. One example would be a
clock source generated by an MCU.
nRESETi
RESET
RESET
RESET
RESET
MCP3912
DS20005348B-page 20 2014-2019 Microchip Technology Inc.
3.14 Master Reset (RESET)
This pin is active-low and places the entire chip in a
Reset state when active.
When RESET is logic low, all registers are reset to their
default value, no communication can take place and no
clock is distributed inside the part, except in the input
structure if MCLK is applied (if MCLK is Idle, then no
clock is distributed). This state is equivalent to a Power-on
Reset (POR) state.
Since the default state of the ADCs is on, the analog
power consumption when RESET is logic low is equiv-
alent to when RESET is logic high. Only the digital
power consumption is largely reduced, because this
current consumption is essentially dynamic and is
reduced drastically when there is no clock running.
All the analog biases are enabled during a Reset, so
that the part is fully operational just after a RESET
rising edge if MCLK is applied when RESET is logic
low. If MCLK is not applied, there is a time after a Hard
Reset when the conversion may not accurately
correspond to the start-up of the input structure.
This input is Schmitt triggered.
3.15 Digital Power Supply (DVDD)
DVDD is the power supply voltage for the digital circuitry
within the MCP3912. It is distributed on several pins (pins
12 and 24 in the 28-lead QFN package, one pin only in
the 28-lead SSOP package). For optimal performance, it
is recommended to connect these pins together using a
star connection and to connect appropriate bypass
capacitors (typically a 10 µF in parallel with a 0.1 µF
ceramic). DVDD should be maintained between 2.7V and
3.6V for specified operation.
At least one of these pins needs to be properly
connected to ensure proper functionality of the device.
All of these pins need to be properly connected to
ensure optimal performance of the device. If any of
these pins are left floating, the accuracy and noise
specifications are not ensured.
3.16 Exposed Thermal Pad
This pin must be connected to AGND or left floating for
proper operation. Connecting it to AGND is preferable for
lowest noise performance and best thermal behavior.
FIGURE 4-1:
Clock Sub-Circuitry,
2014-2019 Microchip Technology Inc. DS20005348B-page 21
MCP3912
4.0 TERMINOLOGY AND
FORMULAS
This section defines the terms and formulas used
throughout this data sheet. The following terms are
defined:
•MCLK – Master Clock
•AMCLK – Analog Master Clock
•DMCLK – Digital Master Clock
•DRCLK – Data Rate Clock
•OSR – Oversampling Ratio
•Offset Error
•Gain Error
•Integral Nonlinearity Error
•Signal-to-Noise Ratio (SNR)
•Signal-to-Noise Ratio and Distortion (SINAD)
•Total Harmonic Distortion (THD)
•Spurious-Free Dynamic Range (SFDR)
•MCP3912 Delta-Sigma Architecture
•Idle Tones
•Dithering
•Crosstalk
•PSRR
•CMRR
•ADC Reset Mode
•Hard Reset Mode (RESET = 0)
•ADC Shutdown Mode
•Full Shutdown Mode
•Measurement Error
4.1 MCLK – Master Clock
This is the fastest clock present on the device. This is
the frequency of the crystal placed at the OSC1/OSC2
inputs when CLKEXT = 0 or the frequency of the clock
input at the OSC1/CLKI when CLKEXT = 1. See
Figure 4-1.
4.2 AMCLK – Analog Master Clock
AMCLK is the clock frequency that is present on the
analog portion of the device after prescaling has
occurred via the CONFIG0 PRE[1:0] register bits (see
Equation 4-1). The analog portion includes the PGAs
and the Delta-Sigma modulators.
EQUATION 4-1:
FIGURE 4-1: Clock Sub-Circuitry.
TABLE 4-1: MCP3912 OVERSAMPLING
RATIO SETTINGS
CONFIG0 Analog Master Clock
Prescale
PRE[1:0]
00 AMCLK = MCLK/1 (default)
01 AMCLK = MCLK/2
10 AMCLK = MCLK/4
11 AMCLK = MCLK/8
AMCLK MCLK
PRESCALE
-------------------------------=
Xtal Oscillator
MCLK
OSC1
OSC2 Multiplexer
OUT
0
1
1/PRESCALE 1/4 1/OSR
AMCLK DMCLK DRCLK
Clock Divider Clock Divider Clock Divider
OSR[2:0]PRE[1:0]CLKEXT
MCP3912
DS20005348B-page 22 2014-2019 Microchip Technology Inc.
4.3 DMCLK – Digital Master Clock
This is the clock frequency that is present on the digital
portion of the device after prescaling and division by four
(Equation 4-2). This is also the sampling frequency,
which is the rate at which the modulator outputs are
refreshed. Each period of this clock corresponds to one
sample and one modulator output. See Figure 4-1.
EQUATION 4-2:
4.4 DRCLK – Data Rate Clock
This is the output data rate (i.e., the rate at which the
ADCs output new data). New data are signaled by a
data ready pulse on the DR pin.
This data rate is dependent on the OSR and the
prescaler with the formula in Equation 4-3.
EQUATION 4-3:
Since this is the output data rate, and because the
decimation filter is a SINC (or notch) filter, there is a
notch in the filter transfer function at each integer
multiple of this rate.
Table 4-2 describes the various combinations of OSR
and PRESCALE, and their associated AMCLK,
DMCLK and DRCLK rates.
DMCLK AMCLK
4
---------------------MCLK
4 PRESCALE
----------------------------------------==
DRCLK DMCLK
OSR
---------------------- AMCLK
4OSR
--------------------- MCLK
4 OSR PRESCALE
-----------------------------------------------------------===
2014-2019 Microchip Technology Inc. DS20005348B-page 23
MCP3912
TABLE 4-2: DEVICE DATA RATES IN FUNCTION OF MCLK, OSR AND PRESCALE,
MCLK = 4 MHz
PRE[1:0] OSR[2:0] OSR AMCLK DMCLK DRCLK DRCLK
(ksps)
SINAD
(dB)(1)
ENOB from
SINAD (bits)(1)
111114096 MCLK/8 MCLK/32 MCLK/131072 .035 102.5 16.7
111112048 MCLK/8 MCLK/32 MCLK/65536 .061 100 16.3
111111024 MCLK/8 MCLK/32 MCLK/32768 .122 97 15.8
11111512 MCLK/8 MCLK/32 MCLK/16384 .244 96 15.6
11011256 MCLK/8 MCLK/32 MCLK/8192 0.488 94 15.3
11010128 MCLK/8 MCLK/32 MCLK/4096 0.976 90 14.7
11001 64 MCLK/8 MCLK/32 MCLK/2048 1.95 83 13.5
11000 32 MCLK/8 MCLK/32 MCLK/1024 3.9 70 11.3
101114096 MCLK/4 MCLK/16 MCLK/65536 .061 102.5 16.7
101112048 MCLK/4 MCLK/16 MCLK/32768 .122 100 16.3
101111024 MCLK/4 MCLK/16 MCLK/16384 .244 97 15.8
10111512 MCLK/4 MCLK/16 MCLK/8192 .488 96 15.6
10011256 MCLK/4 MCLK/16 MCLK/4096 0.976 94 15.3
10010128 MCLK/4 MCLK/16 MCLK/2048 1.95 90 14.7
10001 64 MCLK/4 MCLK/16 MCLK/1024 3.9 83 13.5
10000 32 MCLK/4 MCLK/16 MCLK/512 7.8125 70 11.3
011114096 MCLK/2 MCLK/8 MCLK/32768 .122 102.5 16.7
011112048 MCLK/2 MCLK/8 MCLK/16384 .244 100 16.3
011111024 MCLK/2 MCLK/8 MCLK/8192 .488 97 15.8
01111512 MCLK/2 MCLK/8 MCLK/4096 .976 96 15.6
01011256 MCLK/2 MCLK/8 MCLK/2048 1.95 94 15.3
01010128 MCLK/2 MCLK/8 MCLK/1024 3.9 90 14.7
01001 64 MCLK/2 MCLK/8 MCLK/512 7.8125 83 13.5
01000 32 MCLK/2 MCLK/8 MCLK/256 15.625 70 11.3
001114096 MCLK MCLK/4 MCLK/16384 .244 102.5 16.7
001102048 MCLK MCLK/4 MCLK/8192 .488 100 16.3
001011024 MCLK MCLK/4 MCLK/4096 .976 97 15.8
00100512 MCLK MCLK/4 MCLK/2048 1.95 96 15.6
00011256 MCLK MCLK/4 MCLK/1024 3.9 94 15.3
00010128 MCLK MCLK/4 MCLK/512 7.8125 90 14.7
00001 64 MCLK MCLK/4 MCLK/256 15.625 83 13.5
00000 32 MCLK MCLK/4 MCLK/128 31.25 70 11.3
Note 1: For OSR = 32 and 64, DITHER = None. For OSR = 128 and higher, DITHER = Maximum. The SINAD
values are given from GAIN = 1.
MCP3912
DS20005348B-page 24 2014-2019 Microchip Technology Inc.
4.5 OSR – Oversampling Ratio
This is the ratio of the sampling frequency to the output
data rate; OSR = DMCLK/DRCLK. The default OSR[2:0]
is 256, or with MCLK = 4 MHz, PRESCALE = 1,
AMCLK = 4 MHz, fS = 1 MHz and fD = 3.90625 ksps. The
OSR[2:0] bits in Table 4-3 in the CONFIG0 register are
used to change the Oversampling Ratio (OSR).
4.6 Offset Error
This is the error induced by the ADC when the inputs
are shorted together (VIN = 0V). The specification
incorporates both PGA and ADC offset contributions.
This error varies with PGA and OSR settings. The
offset is different on each channel and varies from chip-
to-chip. The offset is specified in µV. The offset error
can be digitally compensated independently on each
channel through the OFFCAL_CHn registers with a
24-bit Calibration Word.
The offset on the MCP3912 has a low-temperature
coefficient.
4.7 Gain Error
This is the error induced by the ADC on the slope of the
transfer function. It is the deviation expressed in a per-
centage, compared to the ideal transfer function
defined in Equation 5-3. The specification incorporates
both PGA and ADC gain error contributions, but not the
VREF contribution (it is measured with an external
VREF).
This error varies with PGA and OSR settings. The gain
error can be digitally compensated independently on
each channel through the GAINCAL_CHn registers
with a 24-bit Calibration Word.
The gain error on the MCP3912 has a low-temperature
coefficient.
4.8 Integral Nonlinearity Error
Integral nonlinearity error is the maximum deviation of
an ADC transition point from the corresponding point of
an ideal transfer function, with the offset and gain
errors removed or with the end points equal to zero.
It is the maximum remaining error after calibration of
offset and gain errors for a DC input signal.
4.9 Signal-to-Noise Ratio (SNR)
For the MCP3912 ADCs, the Signal-to-Noise ratio is a
ratio of the output fundamental signal power to the
noise power (not including the harmonics of the signal)
when the input is a sine wave at a predetermined
frequency (see Equation 4-4). It is measured in dB.
Usually, only the maximum Signal-to-Noise ratio is
specified. The SNR figure depends mainly on the OSR
and DITHER settings of the device.
EQUATION 4-4: SIGNAL-TO-NOISE RATIO
4.10 Signal-to-Noise Ratio and
Distortion (SINAD)
The most important Figure of Merit for analog perfor-
mance of the ADCs present on the MCP3912 is the
Signal-to-Noise and Distortion (SINAD) specification.
The Signal-to-Noise and Distortion ratio is similar to
Signal-to-Noise ratio, with the exception that you must
include the harmonic’s power in the noise power calcu-
lation (see Equation 4-5). The SINAD specification
depends mainly on the OSR and DITHER settings.
EQUATION 4-5: SINAD EQUATION
The calculated combination of SNR and THD per the
following formula also yields SINAD (see Equation 4-6).
EQUATION 4-6: SINAD, THD AND SNR
RELATIONSHIP
TABLE 4-3: MCP3912 OVERSAMPLING
RATIO SETTINGS
OSR[2:0] Oversampling Ratio
OSR
000 32
001 64
010 128
011 256 (Default)
100 512
101 1024
110 2048
111 4096
SNR dB 10 SignalPower
NoisePower
----------------------------------
log=
SINAD dB 10 SignalPower
Noise HarmonicsPower+
---------------------------------------------------------------------
log=
SINAD dB 10 10
SNR
10
-----------
10
THD–
10
----------------
+log=
2014-2019 Microchip Technology Inc. DS20005348B-page 25
MCP3912
4.11 Total Harmonic Distortion (THD)
The Total Harmonic Distortion is the ratio of the output
harmonics power to the fundamental signal power for a
sine wave input and is defined in Equation 4-7.
EQUATION 4-7:
The THD calculation includes the first 35 harmonics for
the MCP3912 specifications. The THD is usually
measured only with respect to the ten first harmonics,
which leads artificially to better figures. THD is
sometimes expressed in a percentage. Equation 4-8
converts the THD in percentages.
EQUATION 4-8:
This specification depends mainly on the DITHER
setting.
4.12 Spurious-Free Dynamic Range
(SFDR)
Spurious-Free Dynamic Range, or SFDR, is the ratio
between the output power of the fundamental and the
highest spur in the frequency spectrum (see
Equation 4-9). The spur frequency is not necessarily a
harmonic of the fundamental, even though it is usually
the case. This figure represents the dynamic range of the
ADC when a full-scale signal is used at the input. This
specification depends mainly on the DITHER setting.
EQUATION 4-9:
4.13 MCP3912 Delta-Sigma
Architecture
The MCP3912 incorporates four Delta-Sigma ADCs with
a multibit architecture. A Delta-Sigma ADC is an over-
sampling converter that incorporates a built-in modulator,
which digitizes the quantity of charges integrated by the
modulator loop (see Figure 5-1). The quantizer is the
block that is performing the Analog-to-Digital conversion.
The quantizer is typically 1 bit, or a simple comparator,
which helps maintain the linearity performance of the
ADC (the DAC structure is, in this case, inherently linear).
Multibit quantizers help to lower the quantization error
(the error fed back in the loop can be very large with
1-bit quantizers) without changing the order of the mod-
ulator or the OSR, which leads to better SNR figures.
However, typically the linearity of such architectures is
more difficult to achieve since the DAC linearity is as
difficult to attain and its linearity limits the THD of such
ADCs.
The quantizer present in each ADC channel in the
MCP3912 is a Flash ADC, composed of four compara-
tors, arranged with equally spaced thresholds and a
thermometer coding. The MCP3912 also includes
proprietary five-level DAC architecture that is inherently
linear for improved THD figures.
4.14 Idle Tones
A Delta-Sigma converter is an integrating converter. It
also has a finite quantization step (LSB) that can be
detected by its quantizer. A DC input voltage that is
below the quantization step should only provide an
all zeros result, since the input is not large enough to be
detected. As an integrating device, any Delta-Sigma
ADC will show Idle tones. This means that the output will
have spurs in the frequency content that depend on the
ratio between quantization step voltage and the input
voltage. These spurs are the result of the integrated sub-
quantization step inputs that will eventually cross the
quantization steps after a long enough integration. This
will induce an AC frequency at the output of the ADC and
can be shown in the ADC output spectrum.
These Idle tones are residues that are inherent to the
quantization process and the fact that the converter is
integrating at all times without being reset. They are
residues of the finite resolution of the conversion
process. They are very difficult to attenuate and they
are heavily signal-dependent. They can degrade the
SFDR and THD of the converter, even for DC inputs.
They can be localized in the baseband of the converter
and are thus difficult to filter from the actual input signal.
For power metering applications, Idle tones can be very
disturbing because energy can be detected, even at
the 50 or 60 Hz frequency, depending on the DC offset
of the ADCs, while no power is really present at the
inputs. The only practical way to suppress or attenuate
the Idle tones phenomenon is to apply dithering to the
ADC. The amplitudes of the Idle tones are a function of
the order of the modulator, the OSR and the number of
levels in the quantizer of the modulator. A higher order,
a higher OSR or a higher number of levels for the
quantizer will attenuate the amplitudes of the Idle
tones.
THD dB 10 HarmonicsPower
FundamentalPower
-----------------------------------------------------
log=
THD % 100 10
THD dB
20
------------------------
=
SFDR dB 10 FundamentalPower
HighestSpurPower
-----------------------------------------------------
log=
MCP3912
DS20005348B-page 26 2014-2019 Microchip Technology Inc.
4.15 Dithering
In order to suppress or attenuate the Idle tones present
in any Delta-Sigma ADCs, dithering can be applied to
the ADC. Dithering is the process of adding an error to
the ADC feedback loop in order to “decorrelate” the
outputs and “break” the Idle tone’s behavior. Usually, a
random, or pseudorandom generator, adds an analog
or digital error to the feedback loop of the Delta-Sigma
ADC in order to ensure that no tonal behavior can
happen at its outputs. This error is filtered by the feed-
back loop and typically has a zero average value, so
that the converter static transfer function is not dis-
turbed by the dithering process. However, the dithering
process slightly increases the noise floor (it adds noise
to the part) while reducing its tonal behavior and thus
improving SFDR and THD. The dithering process
scrambles the Idle tones into baseband white noise
and ensures that dynamic specs (SNR, SINAD, THD,
SFDR) are less signal-dependent. The MCP3912
incorporates a proprietary dithering algorithm on all
ADCs in order to remove Idle tones and improve THD,
which is crucial for power metering applications.
4.16 Crosstalk
Crosstalk is defined as the perturbation caused on one
ADC channel by all the other ADC channels present in
the chip. It is a measurement of the isolation between
each channel present in the chip.
This measurement is a two-step procedure:
1. Measure one ADC input with no perturbation on
the other ADC (ADC inputs shorted).
2. Measure the same ADC input with a
perturbation sine wave signal on all the other
ADCs at a certain predefined frequency.
Crosstalk is the ratio between the output power of the
ADC when the perturbation is and is not present,
divided by the power of the perturbation signal. A lower
crosstalk value implies more independence and
isolation between the channels.
The measurement of this signal is performed under the
default conditions of MCLK = 4 MHz:
•GAIN = 1
• PRESCALE = 1
• OSR = 256
• MCLK = 4 MHz
Step 1 for CH0 Crosstalk Measurement:
• CH0+ = CH0- = AGND
• CHn+ = CHn- = AGND
n comprised between 1 and 3
Step 2 for CH0 Crosstalk Measurement:
• CH0+ = CH0- = AGND
• CHn+ – CHn- = 1.2VP-P @ 50/60 Hz (full-scale
sine wave), n comprised between 1 and 3
The crosstalk for Channel 0 is then calculated with the
formula in Equation 4-10.
EQUATION 4-10:
The crosstalk depends slightly on the position of the
channels in the MCP3912 device. This dependency is
shown in the Figure 2-32, where the inner channels
show more crosstalk than the outer channels since
they are located closer to the perturbation sources. The
outer channels have the preferred locations to
minimize crosstalk.
4.17 PSRR
This is the ratio between a change in the power supply
voltage and the ADC output codes. It measures the
influence of the power supply voltage on the ADC
outputs.
The PSRR specification can be DC (the power supply
is taking multiple DC values) or AC (the power supply
is a sine wave at a certain frequency with a certain
Common-mode). In AC, the amplitude of the sine wave
represents the change in the power supply; it is defined
in Equation 4-11.
EQUATION 4-11:
Where: VOUT is the equivalent input voltage that the
output code translates to with the ADC transfer
function.
In the MCP3912 specification for DC PSRR, AVDD
varies from 2.7V to 3.6V; for AC PSRR, a 50/60 Hz sine
wave is chosen centered around 3.0V with a maximum
300 mV amplitude. The PSRR specification is measured
with AVDD = DVDD.
4.18 CMRR
CMRR is the ratio between a change in the
Common-mode input voltage and the ADC output
codes. It measures the influence of the Common-mode
input voltage on the ADC outputs.
The CMRR specification can be DC (the
Common-mode input voltage is taking multiple DC
values) or AC (the Common-mode input voltage is a
sine wave at a certain frequency with a certain common
mode). In AC, the amplitude of the sine wave
represents the change in the power supply; it is defined
in Equation 4-12.
CTalk dB 10
CH0Power
CHnPower
---------------------------------
log=
PSRR dB 20
VOUT
AVDD
-------------------
log=
RESET RESET
2014-2019 Microchip Technology Inc. DS20005348B-page 27
MCP3912
EQUATION 4-12:
Where: VCM = (CHn+ + CHn-)/2 is the Common-mode
input voltage and VOUT is the equivalent input voltage
that the output code translates to with the ADC transfer
function.
In the MCP3912 specification, VCM varies from -1V
to +1V.
4.19 ADC Reset Mode
ADC Reset mode (also called Soft Reset mode) can
only be entered through setting the RESET[3:0] bits
high in the Configuration register. This mode is defined
as the condition where the converters are active, but
their output is forced to zero.
The Flash ADC output of the corresponding channel
will be reset to its default value (‘0011’) in the MOD
register.
The ADCs can immediately output meaningful codes
after leaving Reset mode (and after the SINC filter
settling time). This mode is both entered and exited
through bit settings in the Configuration register.
Each converter can be placed in Soft Reset mode
independently. The Configuration registers are not
modified by the Soft Reset mode. A data ready pulse
will not be generated by an ADC channel in Reset
mode.
When an ADC exits ADC Reset mode, any phase delay
present before Reset was entered will still be present.
If one ADC was not in Reset, the ADC leaving Reset
mode will automatically resynchronize the phase delay
relative to the other ADC channel per the phase delay
register block, and give data ready pulses accordingly.
If an ADC is placed in Reset mode while others are
converting, it does not shut down the internal clock.
When coming out of Reset, it will be automatically
resynchronized with the clock, which did not stop
during Reset.
If all ADCs are in Soft Reset mode, the clock is no longer
distributed to the digital core for low-power operation.
Once any of the ADCs is back to normal operation, the
clock is automatically distributed again.
However, when the four channels are in Soft Reset
mode, the input structure is still clocking, if MCLK is
applied, in order to properly bias the inputs so that no
leakage current is observed. If MCLK is not applied,
large analog input leakage currents can be observed
for highly negative input voltages (typically below -0.6V,
referred to AGND).
4.20 Hard Reset Mode (RESET = 0)
This mode is only available during a POR or when the
RESET pin is pulled logic low. The RESET pin logic low
state places the device in Hard Reset mode. In this
mode, all internal registers are reset to their default
state.
The DC biases for the analog blocks are still active (i.e.,
the MCP3912 is ready to convert). However, this pin
clears all conversion data in the ADCs. The compara-
tors’ outputs of all ADCs are forced to their Reset state
(‘0011’). The SINC filters are all reset, as well as their
double-output buffers. The Hard Reset mode requires
a minimum pulse low time (see Section 1.0 “Electrical
Characteristics”). During a Hard Reset, no communi-
cation with the part is possible. The digital interface is
maintained in a Reset state.
During this state, the clock, MCLK, can be applied to
the part in order to properly bias the input structures of
all channels. If not applied, large analog input leakage
currents can be observed for highly negative input sig-
nals, and after removing the Hard Reset state, a certain
start-up time is necessary to bias the input structure
properly. During this delay, the ADC conversions can
be inaccurate.
4.21 ADC Shutdown Mode
ADC Shutdown mode is defined as a state where the
converters and their biases are off, consuming only
leakage current. When one of the SHUTDOWN[3:0]
bits is reset to ‘0’, the analog biases of the correspond-
ing channel will be enabled, as well as the clock and the
digital circuitry. The ADC of the corresponding channel
will give a data ready after the SINC filter settling time
has occurred. However, since the analog biases are
not completely settled at the beginning of the conver-
sion, the sampling may not be accurate during about
1 ms (corresponding to the settling time of the biasing
in worst-case conditions). In order to ensure accuracy,
the data ready pulse within the delay of 1 ms + settling
time of the SINC filter should be discarded.
Each converter can be placed in Shutdown mode
independently. The Configuration registers are not
modified by the Shutdown mode. This mode is only
available through programming the SHUTDOWN[3:0]
bits of the CONFIG1 register.
The output data are flushed to all zeros while in ADC
Shutdown mode. No data ready pulses are generated
by any ADC while in ADC Shutdown mode.
CMRR dB 20
VOUT
VCM
-----------------
log=
MCP3912
DS20005348B-page 28 2014-2019 Microchip Technology Inc.
When an ADC exits ADC Shutdown mode, any phase
delay present before shutdown was entered will still be
present. If one ADC was not in Shutdown, the ADC leav-
ing Shutdown mode will automatically resynchronize the
phase delay, relative to the other ADC channel, per the
Phase Delay register block and give data ready pulses
accordingly.
If an ADC is placed in Shutdown mode while others are
converting, it does not shut down the internal clock.
When coming back out of Shutdown mode, it will auto-
matically be resynchronized with the clock that did not
stop during Reset.
If all ADCs are in ADC Shutdown mode, the clock is not
distributed to the input structure, or to the digital core, for
low-power operation. This can potentially cause high
analog input leakage currents at the analog inputs if the
input voltage is highly negative (typically below -0.6V,
referred to AGND). Once either of the ADCs is back to
normal operation, the clock is automatically distributed
again.
4.22 Full Shutdown Mode
The lowest power consumption can be achieved when
SHUTDOWN[3:0] = 1111, VREFEXT = CLKEXT = 1.
This mode is called Full Shutdown mode, and no
analog circuitry is enabled. In this mode, both AVDD
and DVDD POR monitoring are also disabled and no
clock is propagated throughout the chip. All ADCs are
in Shutdown mode and the internal voltage reference is
disabled. This mode does not reset the writable part of
the register map to its default values.
The clock is no longer distributed to the input structure as
well. This can potentially cause high analog input leak-
age currents at the analog inputs if the input voltage is
highly negative (typically below -0.6V, referred to AGND).
The only circuit that remains active is the SPI interface,
but this circuit does not induce any static power con-
sumption. If SCK is Idle, the only current consumption
comes from the leakage currents induced by the
transistors.
This mode can be used to power down the chip
completely and avoid power consumption when there
is no data to convert at the analog inputs. Any SCK or
MCLK edge occurring while in this mode will induce
dynamic power consumption.
Once any of the SHUTDOWN[3:0], CLKEXT and
VREFEXT bits return to ‘0’, the two POR monitoring
blocks are operational, and AVDD and DVDD monitoring
can take place.
4.23 Measurement Error
The measurement error specification is typically used
in power meter applications. This specification is a
measurement of the linearity of the active energy of a
given power meter across its dynamic range.
For this measurement, the goal is to measure the
active energy of one phase when the voltage Root
Mean Square (RMS) value is fixed and the current
RMS value is sweeping across the dynamic range
specified by the meter. The measurement error is the
nonlinearity error of the energy power across the cur-
rent dynamic range. It is expressed as a percentage.
Equation 4-13 shows the formula that calculates the
measurement error:
EQUATION 4-13:
In the present device, the calculation of the active energy
is done externally as a post-processing step that typically
happens in the microcontroller, considering, for example,
the even channels as current channels and the odd chan-
nels as voltage channels. The odd channels (voltages)
are fed with a full-scale sine wave at 600 mV peak, and
are configured with GAIN = 1 and DITHER = Maximum.
To obtain the active energy measurement error graphs,
the even channels are fed with sine waves with
amplitudes that vary from 600 mV peak to 60 µV peak,
representing a 10000:1 dynamic range. The offset is
removed on both current and voltage channels, and the
channels are multiplied together to give instantaneous
power. The active energy is calculated by multiplying
the current and voltage channel, and averaging the
results of this power during 20 seconds to extract the
active energy. The sampling frequency is chosen as a
multiple integer of line frequency (coherent sampling).
Therefore, the calculation does not take into account
any residue coming from bad synchronization.
The measurement error is a function of IRMS and varies
with the OSR, averaging time and MCLK frequency,
and is tightly coupled with the noise and linearity spec-
ifications. The measurement error is a function of the
linearity and THD of the ADCs, while the standard devi-
ation of the measurement error is a function of the
noise specification of the ADCs. Overall, the low THD
specification enables low measurement error on a very
large dynamic range (e.g. 10,000:1). A low noise and
high SNR specification enables the decreasing of the
measurement time, and therefore, the calibration time,
to obtain a reliable measurement error specification.
Figure 2-5 shows the typical measurement error curves
obtained with the samples acquired by the MCP3912,
using the default settings with a 1-point and 2-point cal-
ibration. These calibrations are detailed in Section 7.0
“Basic Application Recommendations”.
Measurement Error IRMS
Measured Active Energy Active Energy present at inputs–
Active Energy present at inputs
-------------------------------------------------------------------------------------------------------------------------------------------- 1 0 0 %
=
w
FIGURE 5-1: Simplified Delta-Sigma ADC
2014-2019 Microchip Technology Inc. DS20005348B-page 29
MCP3912
5.0 DEVICE OVERVIEW
5.1 Analog Inputs (CHn+/-)
The MCP3912 analog inputs can be connected directly
to current and voltage transducers (such as shunts,
current transformers, or Rogowski coils). Each input
pin is protected by specialized ESD structures that
allow bipolar ±2V continuous voltage, with respect to
AGND, to be present at their inputs without the risk of
permanent damage.
All channels have fully differential voltage inputs for
better noise performance. The absolute voltage at each
pin, relative to AGND, should be maintained in the ±1V
range during operation in order to ensure the specified
ADC accuracy. The Common-mode signals should be
adapted to respect both the previous conditions and
the differential input voltage range. For best
performance, the Common-mode signals should be
maintained to AGND.
5.2 Programmable Gain Amplifiers
(PGAs)
The four Programmable Gain Amplifiers (PGAs)
reside at the front end of each Delta-Sigma ADC.
They have two functions: translate the Common-mode
voltage of the input from AGND to an internal level
between AGND and AVDD, and amplify the input differ-
ential signal. The translation of the Common-mode
voltage does not change the differential signal, but
recenters the Common-mode so that the input signal
can be properly amplified.
The PGA block can be used to amplify very low signals,
but the differential input range of the Delta-Sigma
modulator must not be exceeded. The PGA on each
channel is independent and is controlled by the
PGA_CHn[2:0] bits in the GAIN register. Table 5-1
displays the gain settings for the PGA.
5.3 Delta-Sigma Modulator
5.3.1 ARCHITECTURE
All ADCs are identical in the MCP3912 and they include
a proprietary second-order modulator with a multibit
5-level DAC architecture (see Figure 5-1). The quantizer
is a Flash ADC composed of four comparators with
equally spaced thresholds and a thermometer output
coding. The proprietary 5-level architecture ensures
minimum quantization noise at the outputs of the
modulators without disturbing linearity or inducing
additional distortion. The sampling frequency is
DMCLK (typically 1 MHz with MCLK = 4 MHz), so the
modulators are refreshed at a DMCLK rate.
Figure 5-1 represents a simplified block diagram of the
Delta-Sigma ADC present on MCP3912.
FIGURE 5-1: Simplified Delta-Sigma ADC
Block Diagram.
Note: If the analog inputs are held to a potential
of -0.6 to -1V for extended periods of time,
MCLK must be present inside the device
in order to avoid large leakage currents at
the analog inputs. This is true even during
Hard Reset mode or the Soft Reset of all
ADCs. However, during the Shutdown
mode of all the ADCs or POR state, the
clock is not distributed inside the circuit.
During these states, it is recommended to
keep the analog input voltages above
-0.6V, referred to AGND, to avoid high
analog input leakage currents.
TABLE 5-1: PGA CONFIGURATION
SETTING
Gain
PGA_CHn[2:0]
Gain
(V/V)
Gain
(dB)
VIN = (CHn+) – (CHn-)
Differential
Input Range (V)
000 10±0.6
001 26±0.3
010 4 12 ±0.15
011 8 18 ±0.075
10016 24 ±0.0375
10132 30 ±0.01875
Note: The two undefined settings are G = 1. This table
is defined with VREF = 1.2V.
Second-
Order
Integrator
Loop
Filter
Quantizer
DAC
Differential
Voltage Input
Output
Bitstream
5-Level
Flash ADC
MCP3912 Delta-Sigma Modulator
MCP3912
DS20005348B-page 30 2014-2019 Microchip Technology Inc.
5.3.2 MODULATOR INPUT RANGE AND
SATURATION POINT
For a specified voltage reference value of 1.2V, the
specified differential input range is ±600 mV. The input
range is proportional to VREF and scales according to
the VREF voltage. This range ensures the stability of the
modulator over amplitude and frequency. Outside of
this range, the modulator is still functional; however, its
stability is no longer ensured, and therefore, it is not
recommended to exceed this limit. The saturation point
for the modulator is VREF/1.5, since the transfer
function of the ADC includes a gain of 1.5 by default
(independent from the PGA setting). See Section 5.5
“ADC Output Coding”).
5.3.3 BOOST SETTINGS
The Delta-Sigma modulators include a programmable
biasing circuit in order to further adjust the power
consumption to the sampling speed applied through
the MCLK. This can be programmed through the
BOOST[1:0] bits, which are applied to all channels
simultaneously.
The maximum achievable analog master clock speed
(AMCLK), the maximum sampling frequency (DMCLK)
and the maximum achievable data rate (DRCLK) highly
depend on BOOST[1:0] and PGA_CHn[2:0] settings.
Table 5-2 specifies the maximum AMCLK possible to
keep optimal accuracy in the function of BOOST[1:0]
and PGA_CHn[2:0] settings.
TABLE 5-2: MAXIMUM AMCLK LIMITS AS A FUNCTION OF BOOST AND PGA GAIN
Conditions V
DD
= 3.0V to 3.6V,
T
A
from -40°C to +125°C
V
DD
= 2.7V to 3.6V,
T
A
from -40°C to +125°C
Boost Gain
Maximum AMCLK (MHz)
(SINAD within -3 dB
from its maximum)
Maximum AMCLK (MHz)
(SINAD within -5 dB
from its maximum)
Maximum AMCLK (MHz)
(SINAD within -3 dB
from its maximum)
Maximum AMCLK (MHz)
(SINAD within -5 dB
from its maximum)
0.5x 1 4 4 4 4
0.66x 1 6.4 7.3 6.4 7.3
1x 1 11.4 11.4 10.6 10.6
2x 1 16 16 16 16
0.5x 2 4 4 4 4
0.66x 2 6.4 7.3 6.4 7.3
1x 2 11.4 11.4 10.6 10.6
2x 2 16 16 13.3 14.5
0.5x 4 2.9 2.9 2.9 2.9
0.66x 4 6.4 6.4 6.4 6.4
1x 4 10.7 10.7 9.4 10.7
2x 4 16 16 16 16
0.5x 8 2.9 4 2.9 4
0.66x 8 7.3 8 6.4 7.3
1x 8 11.4 12.3 8 8.9
2x 8 16 16 10 11.4
0.5x 16 2.9 2.9 2.9 2.9
0.66x 16 6.4 7.3 6.4 7.3
1x 16 11.4 11.4 9.4 10.6
2x 16 13.3 16 8.9 11.4
0.5x 32 2.9 2.9 2.9 2.9
0.66x 32 7.3 7.3 7.3 7.3
1x 32 10.6 12.3 9.4 10,6
2x 32 13.3 16 10 11.4
Filte
Out ut
FIGURE 5-2: MCP3912 Decimalion Filler Block Diagram.
2014-2019 Microchip Technology Inc. DS20005348B-page 31
MCP3912
5.3.4 DITHER SETTINGS
All modulators include a dithering algorithm that can be
enabled through the DITHER[1:0] bits in the Configura-
tion register. This dithering process improves THD and
SFDR (for high OSR settings), while slightly increasing
the noise floor of the ADCs. For power metering appli-
cations and applications that are distortion-sensitive, it
is recommended to keep the dither at maximum
settings for best THD and SFDR performance. In the
case of power metering applications, THD and SFDR
are critical specifications. Optimizing SNR (noise floor)
is not problematic due to the large averaging factor at
the output of the ADCs. Therefore, even for low OSR
settings, the dithering algorithm will show a positive
impact on the performance of the application.
5.4 SINC3 + SINC1 Filter
The decimation filter present in all channels of the
MCP3912 is a cascade of two SINC filters
(SINC3+SINC
1): a third-order SINC filter with a decima-
tion ratio of OSR3, followed by a first-order SINC filter
with a decimation ratio of OSR1 (moving average of
OSR1 values). Figure 5-2 represents the decimation
filter architecture.
FIGURE 5-2: MCP3912 Decimation Filter Block Diagram.
Equation 5-1 calculates the filter z-domain transfer
function.
EQUATION 5-1: SINC FILTER TRANSFER
FUNCTION
Equation 5-2 calculates the settling time of the ADC as
a function of DMCLK periods.
EQUATION 5-2:
The SINC1 filter, following the SINC3 filter, is only
enabled for the high OSR settings (OSR > 512). This
SINC1 filter provides additional rejection at a low cost
with little modification to the -3 dB bandwidth. The
resolution (number of possible output codes expressed
in powers of two or in bits) of the digital filter is 24-bit
maximum for any OSR and data format choice. The
resolution depends only on the OSR[2:0] bits settings
in the CONFIG0 register per Table 5-3. Once the
OSR is chosen, the resolution is fixed and the output
code respects the data format defined by the
WIDTH_DATA[1:0] bits setting in the STATUSCOM
register (see Section 5.5 “ADC Output Coding”).
Modulator
Output
SINC
3
SINC
1
Decimation
Filter Output
OSR
3
OSR
1
416 (WIDTH = 0)
24 (WIDTH = 1)
Decimation Filter
OSR
1
=1
Hz
1z
- OSR3
–
3
OSR31z
1–
–
3
----------------------------------------------
1z
- OSR1OSR3
–
OSR11z
- OSR3
–
---------------------------------------------------------
=
Where z EXP 2
jf
in
DMCLK
=
SettlingTime DMCLKperiods3OSR
3
OSR11–OSR3
+=
\
‘ W
” U W!
FIGURE 5-3: SINC Filter Frequency FIGURE 5-4: SINC Filter Frequency
MCP3912
DS20005348B-page 32 2014-2019 Microchip Technology Inc.
The gain of the transfer function of this filter is one at
each multiple of DMCLK (typically 1 MHz), so a proper
anti-aliasing filter must be placed at the inputs. This will
attenuate the frequency content around DMCLK and
keep the desired accuracy over the baseband of the
converter. This anti-aliasing filter can be a simple, first-
order RC network with a sufficiently low time constant
to generate high rejection at the DMCLK frequency.
Any unsettled data are automatically discarded to avoid
data corruption. Each data ready pulse corresponds to
fully settled data at the output of the decimation filter.
The first data available at the output of the decimation
filter is present after the complete settling time of the
filter (see Table 5-3). After the first data have been
processed, the delay between two data ready pulses
coming from the same ADC channel is one DRCLK
period. The data stream from input to output is delayed
by an amount equal to the settling time of the filter
(which is the group delay of the filter).
The achievable resolution, the -3 dB bandwidth and the
settling time at the output of the decimation filter (the
output of the ADC) are dependent on the OSR of each
SINC filter and are summarized in Tabl e 5 -3.
FIGURE 5-3: SINC Filter Frequency
Response, OSR = 256, MCLK = 4 MHz,
PRE[1:0] = 00.
FIGURE 5-4: SINC Filter Frequency
Response, OSR = 4096 (in pink), OSR = 512 (in
blue), MCLK = 4 MHz, PRE[1:0] = 00.
TABLE 5-3: OVERSAMPLING RATIO AND SINC FILTER SETTLING TIME
OSR[2:0] OSR3OSR1Total OSR Resolution in Bits
(No Missing Code) Settling Time -3 dB Bandwidth
000 32 1 32 17 96/DMCLK 0.26 * DRCLK
001 64 1 64 20 192/DMCLK 0.26 * DRCLK
010 128 1 128 23 384/DMCLK 0.26 * DRCLK
011 256 1 256 24 768/DMCLK 0.26 * DRCLK
100 512 1 512 24 1536/DMCLK 0.26 * DRCLK
101 512 2 1024 24 2048/DMCLK 0.37 * DRCLK
110 512 4 2048 24 3072/DMCLK 0.42 * DRCLK
111 512 8 4096 24 5120/DMCLK 0.43 * DRCLK
-80
-60
-40
-20
0
a
gnitude (dB)
-120
-100
1 10 100 1000 10000 100000
M
a
Input Frequency (Hz)
-100
-80
-60
-40
-20
0
gnitude (dB)
-160
-140
-120
1 100 10000 1000000
Ma
Input Frequency (Hz)
‘5
31
2014-2019 Microchip Technology Inc. DS20005348B-page 33
MCP3912
5.5 ADC Output Coding
The second-order modulator, SINC3 + SINC1 filter,
PGA, VREF and the analog input structure all work
together to produce the device transfer function for the
Analog-to-Digital conversion (see Equation 5-3).
Channel data are calculated on 24-bit (23-bit plus
sign) and coded in two’s complement format, MSB
first. The output format can then be modified by the
WIDTH_DATA[1:0] bits setting in the STATUSCOM
register to allow 16-/24-/32-bit format compatibility (see
Section 8.5 “STATUSCOM Register – Status and
Communication Register” for more information).
In case of positive saturation (CHn+ – CHn- > VREF/1.5),
the output is locked to 7FFFFF for 24-bit mode. In case of
negative saturation (CHn+ – CHn- < -VREF/1.5), the
output code is locked to 800000 for 24-bit mode.
Equation 5-3 is only true for DC inputs. For AC inputs,
this transfer function needs to be multiplied by the
transfer function of the SINC3 + SINC1 filter (see
Equation 5-1 and Equation 5-3).
EQUATION 5-3:
For other than the default 24-bit data formats,
Equation 5-3 should be multiplied by a scaling factor
depending on the data format used (defined by
WIDTH_DATA[1:0]). The data format and associated
scaling factors are given in Figure 5-5.
FIGURE 5-5: Output Data Formats.
DATA_CHn
CHn+ CHn-
–
VREF+ VREF-
–
-----------------------------------------
8,388,608 G 1.5
=
For 24-Bit Mode, WIDTH_Data[1:0] = 01 (Default)
DATA
<7>
WIDTH_DATA[1:0] = 11
32-bit with Sign Extension DATA
[23] DATA
[23:16]
31 0
DATA
[15:8] DATA
[7:0]
WIDTH_DATA[1:0] = 10
32-bit with Zeros Padded 0x00
31 0
DATA
[23:16] DATA
[7:0]
DATA
[15:8]
WIDTH_DATA[1:0] = 01
24-bit DATA
[23:16] DATA
[15:8] DATA
[7:0]
23 0
WIDTH_DATA[1:0] = 00
16-bit DATA
[15:8]
15 0
DATA
[23:16]
Rounded
Unformatted ADC Data DATA
[23:16] DATA
[15:8] DATA
[7:0]
23 0
x1/256
x1
x256
x1
Scaling
Factor
MCP3912
DS20005348B-page 34 2014-2019 Microchip Technology Inc.
The ADC resolution is a function of the OSR
(Section 5.4 “SINC3 + SINC1 Filter”). The resolution
is the same for all channels. No matter what the
resolution is, the ADC output data are always
calculated in 24-bit words, with added zeros at the end
if the OSR is not large enough to produce 24-bit
resolution (left justification).
TABLE 5-4: OSR = 256 (AND HIGHER) OUTPUT CODE EXAMPLES
ADC Output Code (MSB First) Hexadecimal Decimal,
24-Bit Resolution
0111 1111 1111 1111 1111 1111 0x7FFFFF + 8,388,607
0111 1111 1111 1111 1111 1110 0x7FFFFE + 8,388,606
0000 0000 0000 0000 0000 0000 0x000000 0
1111 1111 1111 1111 1111 1111 0xFFFFFF – 1
1000 0000 0000 0000 0000 0001 0x800001 - 8,388,607
1000 0000 0000 0000 0000 0000 0x800000 - 8,388,608
TABLE 5-5: OSR = 128 OUTPUT CODE EXAMPLES
ADC Output Code (MSB First) Hexadecimal Decimal,
23-Bit Resolution
0111 1111 1111 1111 1111 11100x7FFFFE + 4,194,303
0111 1111 1111 1110 1111 11000x7FFFFC + 4,194,302
0000 0000 0000 0000 0000 0000 0x000000 0
1111 1111 1111 1111 1111 11100xFFFFFE – 1
1000 0000 0000 0000 0000 00100x800002 – 4,194,303
1000 0000 0000 0000 0000 00000x800000 – 4,194,304
TABLE 5-6: OSR = 64 OUTPUT CODE EXAMPLES
ADC Output Code (MSB First) Hexadecimal Decimal,
20-Bit resolution
0111 1111 1111 1111 1111 0 0 0 0 0x7FFFF0 + 524, 287
0111 1111 1111 1111 1110 0 0 0 0 0x7FFFE0 + 524, 286
0000 0000 0000 0000 0000 0 0 0 0 0x000000 0
1111 1111 1111 1111 1111 0 0 0 0 0xFFFFF0 – 1
1000 0000 0000 0000 0001 0 0 0 0 0x800010 – 524,287
1000 0000 0000 0000 0000 0 0 0 0 0x800000 – 524, 288
TABLE 5-7: OSR = 32 OUTPUT CODE EXAMPLES
ADC Output Code (MSB First) Hexadecimal Decimal,
17-Bit resolution
0111 1111 1111 1111 1000 0000 0x7FFF80 + 65, 535
0111 1111 1111 1111 0000 0000 0x7FFF00 + 65, 534
0000 0000 0000 0000 0000 0000 0x000000 0
1111 1111 1111 1111 1000 0000 0xFFFF80 – 1
1000 0000 0000 0000 1000 0000 0x800080 – 65,535
1000 0000 0000 0000 0000 0000 0x800000 – 65, 536
2014-2019 Microchip Technology Inc. DS20005348B-page 35
MCP3912
5.6 Voltage Reference
5.6.1 INTERNAL VOLTAGE REFERENCE
The MCP3912 contains an internal voltage reference
source specially designed to minimize drift over tempera-
ture. In order to enable the internal voltage reference, the
VREFEXT bit in the Configuration register must be set to
‘0’ (default mode). This internal VREF supplies reference
voltage to all channels. The typical value of this voltage
reference is 1.2V, ±2%. The internal reference has a very
low typical temperature coefficient of ±9 ppm/°C, allowing
the output to have minimal variation with respect to
temperature, since they are proportional to (1/VREF).
The noise of the internal voltage reference is low
enough not to significantly degrade the SNR of the
ADC if compared to a precision external low noise
voltage reference. The output pin for the internal
voltage reference is REFIN+/OUT.
If the voltage reference is only used as an internal
VREF
, adding bypass capacitance on REFIN+/OUT is
not necessary for keeping ADC accuracy, but a minimal
0.1 µF ceramic capacitance can be connected to avoid
EMI/EMC susceptibility issues due to the antenna
created by the REFIN+/OUT pin, if left floating.
The bypass capacitors also help applications where the
voltage reference output is connected to other circuits.
In this case, additional buffering may be needed since
the output drive capability of this output is low.
Adding too much capacitance on the REFIN+/OUT pin
may slightly degrade the THD performance of the ADCs.
5.6.2 DIFFERENTIAL EXTERNAL
VOLTAGE INPUTS
When the VREFEXT bit is set to ‘1’, the two reference
pins (REFIN+/OUT, REFIN-) become a differential
voltage reference input. The voltage at the
REFIN+/OUT is noted VREF+ and the voltage at the
REFIN- pin is noted VREF-. The differential voltage
input value is shown in Equation 5-4.
EQUATION 5-4:
The specified VREF range is from 1.1V to 1.3V. The
REFIN- pin voltage (VREF-) should be limited to ±0.1V,
with respect to AGND. Typically, for single-ended refer-
ence applications, the REFIN- pin should be directly
connected to AGND, with its own separate track to avoid
any spike due to switching noise.
These buffers are injecting a certain quantity of
1/f noise into the system. This noise can be modulated
with the incoming input signals and can limit the SNR
at very high OSR (OSR > 256). To overcome this
limitation, these buffers include an auto-zeroing algo-
rithm that greatly diminishes their 1/f noise, as well as
their offset, so that the SNR of the system is not limited
by this noise component, even at maximum OSR. This
auto-zeroing algorithm is performed synchronously
with the MCLK coming to the device.
5.6.3 TEMPERATURE COMPENSATION
(VREFCAL[7:0])
The internal voltage reference consists of a proprietary
circuit and algorithm to compensate first-order and
second-order temperature coefficients (tempco).
The compensation enables very low-temperature
coefficients (typically 9 ppm/°C) on the entire range of
temperatures, from -40°C to +125°C. This temperature
coefficient varies from part to part.
This temperature coefficient can be adjusted on each
part through the VREFCAL[7:0] bits present in the
CONFIG0 register (bits 7 to 0). These register settings
are only for advanced users. VREFCAL[7:0] should not
be modified unless the user wants to calibrate the
temperature coefficient of the whole system or applica-
tion. The default value of this register is set to 0x50.
The default value (0x50) was chosen to optimize the
standard deviation of the tempco across process varia-
tion. The value can be slightly improved to around
7 ppm/°C if the VREFCAL[7:0] bits are written at 0x42,
but this setting degrades the standard deviation of the
VREF tempco. The typical variation of the temperature
coefficient of the internal voltage reference, with
respect to the VREFCAL register code, is shown in
Figure 5-6. Modifying the value stored in the VREF-
CAL[7:0] bits may also vary the voltage reference, in
addition to the temperature coefficient.
FIGURE 5-6: VREF Tempco vs. VREFCAL
Trim Code Chart.
5.6.4 VOLTAGE REFERENCE BUFFERS
Each channel includes a voltage reference buffer tied to
the REFIN+/OUT pin, which allows the internal capaci-
tors to properly charge with the voltage reference signals,
even in the case of an external voltage reference connec-
tion with weak load regulation specifications. This
ensures the correct amount of current is sourced to each
channel to ensure their accuracy specifications and
diminishes the constraints on the voltage reference load
regulation.
VREF =V
REF+–V
REF-
0
10
20
30
40
50
60
0 64 128 192
256
V
REF
Drift (ppm)
VREFCAL Register Trim Code (decimal)
FIGURE 5-7:
Power-on Reset Operation.
MCP3912
DS20005348B-page 36 2014-2019 Microchip Technology Inc.
5.7 Power-on Reset
The MCP3912 contains an internal POR circuit that
monitors both analog and digital supply voltages during
operation. The typical threshold for a power-up event
detection is 2.0V, ±10% and a typical start-up time (tPOR)
of 50 µs. The POR circuit has a built-in hysteresis for
improved transient spike immunity that has a typical
value of 200 mV. Proper decoupling capacitors (0.1 µF
in parallel with 10 µF) should be mounted as close as
possible to the AVDD and DVDD pins, providing
additional transient immunity.
Figure 5-7 illustrates the different conditions at a
power-up and a power-down event in typical condi-
tions. All internal DC biases are not settled until at least
1 ms, in worst-case conditions, after a system POR.
Any data ready pulse occurring within 1 ms, plus the
SINC filter settling time after system Reset, should be
ignored to ensure proper accuracy. After POR, data
ready pulses are present at the pin with all the default
conditions in the Configuration registers.
Both AVDD and DVDD are monitored, so either power
supply can sequence first.
FIGURE 5-7: Power-on Reset Operation.
Note: In order to ensure a proper power-up
sequence, the ramp rate of DVDD should
not exceed 3V/µs when coming out of the
POR state.
Additionally, the user should try to lower
the DVDD residual voltage as close to 0V
as possible when the device is kept in a
POR state (below DVDD POR threshold)
for a long time to ensure a proper power-
up sequence. The user can verify if the
power-up sequence has been correctly
performed by reading the default state of
all the registers in the register map right
after powering up the device. If one or
more of the registers do not show the
proper default settings when being read, a
new power-up cycle should be launched
to recover from this condition.
POR
State Power-up Normal POR
State
Biases are
unsettled.
Conversions
started here may
not be accurate
Biases are settled.
Conversions started
here are accurate.
Analog Biases
Settling Time
SINC Filter
Settling
Time
Voltage
(AVDD, DVDD)
Time
POR Threshold
Up (2.0V typical)
(1.8V typical)
tPOR
Operation
Any data ready pulse occurring
during this time can yield
inaccurate output data. It is
recommended to discard them.
RESET
RESET
RESET
2014-2019 Microchip Technology Inc. DS20005348B-page 37
MCP3912
5.8 Hard Reset Effect on Delta-Sigma
Modulator/SINC Filter
When the RESET pin is logic low, all ADCs will be in
Reset and output code 0x000000h. The RESET pin
performs a Hard Reset (DC biases are still on, the part
is ready to convert) and clears all charges contained in
the Delta-Sigma modulators. The comparator’s output
is ‘0011’ for each ADC.
The SINC filters are all reset, as well as their double-
output buffers. This pin is independent of the serial
interface. It brings all the registers to the default state.
When RESET is logic low, any write with the SPI
interface will be disabled and will have no effect. All
output pins (SDO, DR) are high-impedance.
If an external clock (MCLK) is applied, the input struc-
ture is enabled and is properly biasing the substrate of
the input transistors. In this case, the leakage current
on the analog inputs is low if the analog input voltages
are kept between -1V and +1V.
If MCLK is not applied when in Reset mode, the leakage
can be high if the analog inputs are below -0.6V, as
referred to AGND.
5.9 Phase Delay Block
The MCP3912 incorporates a phase delay generator
which ensures that each pair of ADCs (CH0/1, CH2/3) is
converting the inputs with a fixed delay between them.
The four ADCs are synchronously sampling, but the aver-
aging of modulator outputs is delayed so that the SINC
filter outputs (thus the ADC outputs) show a fixed phase
delay as determined by the PHASE register setting. The
odd channels (CH1,3) are the reference channels for the
phase delays of each pair and set the time reference.
Typically, these channels can be the voltage channels for
a polyphase energy metering application. These odd
channels are synchronous at all times, so they become
ready and output a data ready pulse at the same time.
The even channels (CH0/2) are delayed compared to the
time reference (CH1/3) by a fixed amount of time defined
for each pair channel in the PHASE register.
The PHASE register is split into two 12-bit banks that
represent the delay between each pair of channels.
The equivalence is defined in Tabl e 5 -8 . Each phase
value (PHASEA/B) represents the delay of the even
channel, with respect to the associated odd channel,
with an 11-bit plus sign, MSB first, two’s complement
code. This code indicates how many DMCLK periods
there are between each channel in the pair (see
Equation 5-5). Since the odd channels are the time
reference, when PHASEx[11:0] are positive, the even
channel of the pair is lagging and the odd channel is
leading. When PHASEx[11:0] are negative, the even
channel of the pair is leading and the odd channel is
lagging.
EQUATION 5-5:
The timing resolution of the phase delay is 1/DMCLK or
1 µs in the default configuration, with MCLK = 4 MHz.
Given the definition of DMCLK, the phase delay is
affected by a change in the prescaler settings
(PRE[1:0]) and the MCLK frequency.
The data ready signals are affected by the phase delay
settings. Typically, the time difference between the data
ready pulses of odd and even channels is equal to the
associated phase delay setting.
Each ADC conversion start, and therefore, each data
ready pulse is delayed by a timing of OSR/2 x DMCLK
periods (equal to half a DRCLK period). This timing
allows for the odd channel’s data ready signals to be
located at a fixed time reference (OSR/2 x DMCLK
periods from the Reset), while the even channel can be
leading or lagging around this time reference with the
corresponding PHASEx[11:0] delay value.
5.9.1 PHASE DELAY LIMITS
The limits of the phase delays are determined by the
OSR settings; the phase delays can only go from
-OSR/2 to +OSR/2-1 DMCLK periods.
If larger delays between the two channels are needed,
they can be implemented externally to the chip with an
MCU. A FIFO in the MCU can save incoming data from
the leading channel for a number N of DRCLK clocks.
In this case, DRCLK would represent the coarse timing
resolution and DMCLK the fine timing resolution. The
total delay will then be equal to:
EQUATION 5-6:
TABLE 5-8: PHASE DELAYS
EQUIVALENCE
Pair of
Channels Phase Bank Register Map
Position
CH1/CH0 PHASEA[11:0] PHASE[11:0]
CH3/CH2 PHASEB[11:0] PHASE[23:12]
Note: For a detailed explanation of the Data
Ready pin (DR) with phase delay, see
Section 5.11 “Data Ready Status Bits”.
Note: Rewriting the PHASE registers with the
same value automatically resets and
restarts all ADCs.
Where: x = A/B
Total Delay = PHASEx[11:0] Decimal Code
DMCLK
Total Delay = N/DRCLK + PHASE/DMCLK
MCP3912
DS20005348B-page 38 2014-2019 Microchip Technology Inc.
The Phase Delay registers can be programmed once
with the OSR = 4096 setting and will adjust the OSR
automatically afterwards without the need to change
the value of the PHASE registers.
• OSR = 4096: The delay can go from -2048 to
+2047. PHASEx[11] is the sign bit. PHASEx[10] is
the MSB and PHASEx[0] the LSB.
• OSR = 2048: The delay can go from -1024 to
+1023. PHASEx[10] is the sign bit. PHASEx[9] is
the MSB and PHASEx[0] the LSB.
• OSR = 1024: The delay can go from -512 to +511.
PHASEx[9] is the sign bit. PHASEx[8] is the MSB
and PHASEx[0] the LSB.
• OSR = 512: The delay can go from -256 to +255
PHASEx[8] is the sign bit. PHASEx[7] is the MSB
and PHASEx[0] the LSB.
•OSR = 256: The delay can go from -128 to +127.
PHASEx[7] is the sign bit. PHASEx[6] is the MSB
and PHASEx[0] the LSB.
•OSR = 128: The delay can go from -64 to +63.
PHASEx[6] is the sign bit. PHASEx[5] is the MSB
and PHASEx[0] the LSB.
•OSR = 64: The delay can go from -32 to +31.
PHASEx[5] is the sign bit. PHASEx[4] is the MSB
and PHASEx[0] the LSB.
•OSR = 32: The delay can go from -16 to +15.
PHASEx[4] is the sign bit. PHASEx[3] is the MSB
and PHASEx[0] the LSB.
5.10 Data Ready Link
There are two modes defined with the DR_LINK bit in
the STATUSCOM register that control the data ready
pulses. The position of the data ready pulses varies
with respect to this mode, to the OSR[2:0] and to the
PHASE register settings. Section 5.11 “Data Ready
Status Bits” represents the behavior of the Data
Ready pin with the two DR_LINK configurations.
• DR_LINK = 0: Data ready pulses from all enabled
channels are output on the DR pin.
• DR_LINK = 1 (Recommended and Default mode):
Only the data ready pulses from the most lagging
ADC between all the active ADCs are present on
the DR pin.
The lagging ADC data ready position depends on the
PHASE register, the PRE[1:0] and the OSR[2:0] set-
tings. In this mode, the active ADCs are linked together,
so their data are latched together when the lagging
ADC output is ready. For power metering applications,
DR_LINK = 1 is recommended (Default mode); it
allows the host MCU to gather all channels synchro-
nously within a unique interrupt pulse and it ensures
that all channels have been latched at the same time so
that no data corruption is happening.
5.11 Data Ready Status Bits
In addition to the Data Ready pin indicator, the
MCP3912 device includes a separate data ready status
bit for each channel. Each ADC channel CHn is asso-
ciated to the corresponding DRSTATUS[n] that can be
read at all times in the STATUSCOM register. These
status bits can be used to synchronize the data retrieval
in case the DR pin is not connected (see Section 6.8
“ADC Channels Latching and Synchronization”).
The DRSTATUS[3:0] bits are not writable; writing on
them has no effect. They have a default value of ‘1’,
which indicates that the data of the corresponding ADC
are not ready. This means that the ADC Output register
has not been updated since the last reading (or since the
last Reset). The DRSTATUS bits take the ‘0’ state once
the ADC Channel register is updated (which happens at
a DRCLK rate). A simple read of the STATUSCOM
register clears all the DRSTATUS bits to their default
value (‘1’).
In the case of DR_LINK = 1, the DRSTATUS[3:0] bits
are all updated synchronously, with the most lagging
channel, at the same time the DR pulse is generated.
In the case of DR_LINK = 0, each DRSTATUS bit is
updated independently and synchronously with its
corresponding channel.
TABLE 5-9: PHASE VALUES WITH
MCLK = 4 MHz, OSR = 4096,
PRE[1:0] = 00
PHASEx[11:0] for the
Channel Pair
CH[n/n+1]
Hex
Delay
(CH[n] relative
to CH[n+1])
0 11111111111 0x7FF + 2047 µs
0 11111111110 0x7FE + 2046 µs
0 00000000001 0x001 + 1 µs
0 00000000000 0x000 0 µs
1 11111111111 0xFFF – 1 µs
1 00000000001 0x801 – 2047 µs
1 00000000000 0x800 – 2048 µs
U
2014-2019 Microchip Technology Inc. DS20005348B-page 39
MCP3912
5.12 Crystal Oscillator
The MCP3912 includes a Pierce-type crystal oscillator
with very high stability, and ensures very low tempco and
jitter for the clock generation. This oscillator can handle
crystal frequencies up to 20 MHz, provided proper load
capacitances and quartz quality factors are used. The
crystal oscillator is enabled when CLKEXT = 0 in the
CONFIG1 register.
For a proper start-up, the load capacitors of the crystal
should be connected between OSC1 and DGND, and
between OSC2 and DGND. They should also respect
Equation 5-7.
EQUATION 5-7:
When CLKEXT = 1, the crystal oscillator is bypassed
by a digital buffer to allow direct clock input for an
external clock (see Figure 4-1). In this case, the OSC2
pin is pulled down internally to DGND and should be
connected to DGND externally for better EMI/EMC
immunity.
FIGURE 5-8: DR_LINK Configurations.
The external clock should not be higher than 20 MHz
before prescaling (MCLK < 20 MHz) for proper
operation.
RM1.6 106
1
fCLOAD
------------------------
2
<
Where:
f = Crystal frequency in MHz
CLOAD = Load capacitance in pF including
parasitics from the PCB
RM= Motional resistance in ohms of the quartz
DR
One DRCLK Period (OSR times DMCLK periods)
DR_LINK = 1
Only the MostLagging Data Ready is Present,
All Channels are Latched Together at DR
Falling Edge
DR
DR_LINK = 0
All Channels Data
Ready are Present
Data Ready Pulse from Odd
Channels (reference)
PHASE = 0
Data Ready Pulse from Odd
Channels (reference)
PHASE = 0
PHASE < 0 PHASE > 0
Data Ready Pulse from
Most Lagging ADC Channel Data Ready Pulse from
Most Lagging ADC Channel
Note: In addition to the conditions defining the
maximum MCLK input frequency range,
the AMCLK frequency should be main-
tained inferior to the maximum limits
defined in Table 5-2 to ensure the accuracy
of the ADCs. If these limits are exceeded, it
is recommended to choose either a larger
OSR or a larger prescaler value so that
AMCLK can respect these limits.
MCP3912
DS20005348B-page 40 2014-2019 Microchip Technology Inc.
5.13 Digital System Offset and Gain
Calibration Registers
The MCP3912 incorporates two sets of additional
registers per channel to perform system digital offset
and gain error calibration. Each channel has its own set
of associated registers that will modify the output result
of the channel if calibration is enabled. The gain and
offset calibrations can be enabled or disabled through
two CONFIG0 bits (EN_OFFCAL and EN_GAINCAL).
These two bits enable or disable system calibration on
all channels at the same time. When both calibrations
are enabled, the output of the ADC is modified per
Section 5.13.1 “Digital Offset Error Calibration”.
5.13.1 DIGITAL OFFSET ERROR
CALIBRATION
The OFFCAL_CHn registers are 23-bit plus two’s
complement registers, and whose LSB value is the
same as the channel ADC data. These registers are
added, bit by bit, to the ADC output codes if the
EN_OFFCAL bit is enabled. Enabling the EN_OFFCAL
bit does not create a pipeline delay; the offset addition
is instantaneous. For low OSR values, only the signifi-
cant digits are added to the output (up to the resolution
of the ADC; for example, at OSR = 32, only the 17 first
bits are added).
The offset is not added when the corresponding channel
is in Reset or Shutdown mode. The corresponding
input voltage offset value added by each LSB in these
24-bit registers is:
EQUATION 5-8:
These registers are a “Don’t Care” if EN_OFFCAL = 0
(offset calibration disabled), but their value is not
cleared by the EN_OFFCAL bit.
5.13.2 DIGITAL GAIN ERROR
CALIBRATION
These registers are signed 24-bit MSB first registers
coded with a range of -1x to +(1 – 2-23)x (from
0x800000 to 0x7FFFFF). The gain calibration adds 1x
to this register and multiplies it to the output code of the
channel, bit by bit, after offset calibration. The range of
the gain calibration is thus from 0x to 1.9999999x (from
0x800000 to 0x7FFFFF). The LSB corresponds to
a2
-23 increment in the multiplier.
Enabling EN_GAINCAL creates a pipeline delay of
24 DMCLK periods on all channels. All data ready
pulses are delayed by 24 DMCLK periods, starting from
the data ready following the command enabling the
EN_GAINCAL bit. The gain calibration is effective on
the next data ready following the command enabling
the EN_GAINCAL bit.
The digital gain calibration does not function when the
corresponding channel is in Reset or Shutdown mode.
The gain multiplier value for an LSB in these 24-bit
registers is:
EQUATION 5-9:
This register is a “Don’t Care” if EN_GAINCAL = 0
(offset calibration disabled), but its value is not cleared
by the EN_GAINCAL bit.
The output data on each channel are kept to either
7FFF or 8000 (16-bit mode), or 7FFFFF or 800000
(24-bit mode) if the output results are out of bounds
after all calibrations are performed.
EQUATION 5-10: DIGITAL OFFSET AND GAIN ERROR CALIBRATION REGISTERS CALCULATIONS
OFFSET(1LSB) = VREF/(PGA_CHn x 1.5 x 8388608)
GAIN (1 LSB) = 1/8388608
DATA_CHn post cal–DATA_CHn pre cal–OFFCAL_CHn+1 GAINCAL_CHn+
=
cs .Anyfi
RESET fl
DR
RESET
E‘
2014-2019 Microchip Technology Inc. DS20005348B-page 41
MCP3912
6.0 SPI SERIAL INTERFACE
DESCRIPTION
6.1 Overview
The MCP3912 device includes a four-wire (CS, SCK,
SDI, SDO) digital serial interface that is compatible with
SPI Modes 0,0 and 1,1. Data are clocked out of the
MCP3912 on the falling edge of SCK and data are
clocked into the MCP3912 on the rising edge of SCK.
In these modes, the SCK clock can Idle either
high (1,1) or low (0,0). The digital interface is asynchro-
nous with the MCLK clock that controls the ADC
sampling and digital filtering. All the digital input pins are
Schmitt triggered to avoid system noise perturbations on
the communications.
Each SPI communication starts with a CS falling edge
and stops with the CS rising edge. Each SPI communi-
cation is independent. When CS is logic high, SDO is in
high-impedance, and transitions on SCK and SDI have
no effect. Changing from an SPI Mode 1,1 to an SPI
Mode 0,0 and vice versa is possible, and can be done
while the CS pin is logic high. Any CS rising edge clears
the communication and resets the SPI digital interface.
Additional control pins (RESET
, DR) are also provided
on separate pins for advanced communication
features. The Data Ready (DR) pin outputs pulses
when new ADC channel data are available for reading,
which can be used as an interrupt for an MCU. The
Master Reset pin (RESET) acts like a Hard Reset and
can reset the part to its default power-up configuration
(equivalent to a POR state).
The MCP3912 interface has a simple command
structure. Every command is either a READ command
from a register or a WRITE command to a register. The
MCP3912 device includes 32 registers, defined in the
register map (Ta bl e 8 - 1 ). The first byte (8-bit wide)
transmitted is always the control byte that defines the
address of the register and the type of command (READ
or WRITE). It is followed by the register itself, which can
be in a 16, 24 or 32-bit format, depending on the
multiple format settings defined in the STATUSCOM
register. The MCP3912 is compatible with multiple
formats that help reduce overhead in the data handling
for most MCUs and processors available on the market
(8, 16 or 32-bit MCUs), and improve MCU code
compaction and efficiency.
The MCP3912 digital interface is capable of handling
various continuous Read and Write modes, which
allows it to perform ADC data streaming or full register
map writing within only one communication (and there-
fore, with only one unique control byte). The internal
registers can be grouped together with various config-
urations through the READ[1:0] and WRITE bits. The
internal address counter of the serial interface can be
automatically incremented, with no additional control
byte needed, in order to loop through the various
groups of registers within the register map. The groups
are defined in Ta bl e 8- 2.
The MCP3912 device also includes advanced security
features. These features secure each communication
in order to avoid unwanted WRITE commands being
processed to change the desired configuration and to
alert the user in case of a change in the desired
configuration.
Each SPI read communication can be secured through
a selectable CRC-16 checksum provided on the SDO
pin at the end of every communication sequence. This
CRC-16 computation is compatible with the DMA CRC
hardware of the PIC24 and PIC32 MCUs, resulting in
no additional overhead for the added security.
For securing the entire configuration of the device, the
MCP3912 includes an 8-bit lock code (LOCK[7:0]),
which blocks all WRITE commands to the full register
map if the value of the LOCK[7:0] bits are not equal to
a defined password (0xA5). The user can protect its
configuration by changing the LOCK[7:0] value to 0x00
after the full programming, so that any unwanted
WRITE command will not result in a change to the
configuration (because the LOCK[7:0] bits are different
than the password 0xA5).
An additional CRC-16 calculation is also running
continuously in the background to ensure the integrity
of the full register map. All writable registers of the
register map (except the MOD register) are processed
through a CRC-16 calculation engine and give a
CRC-16 checksum that depends on the configuration.
This checksum is readable on the LOCK/CRC register
and updated at all times. If a change in this checksum
happens, a selectable interrupt can give a flag on the
DR pin (DR pin becomes logic low) to warn the user
that the configuration is corrupted.
6.2 Control Byte
The control byte of the MCP3912 contains two device
Address bits (A[6:5]), five register Address bits (A[4:0])
and a Read/Write bit (R/W). The first byte transmitted
to the MCP3912 in any communication is always the
control byte. During the control byte transfer, the SDO
pin is always in a high-impedance state. The MCP3912
interface is device-addressable (through A[6:5]) so that
multiple chips can be present on the same SPI bus with
no data bus contention. Even if they use the same CS
pin, they use a provided half-duplex SPI interface
with a different address identifier. This functionality
enables, for example, a serial EEPROM, such as
24AAXXX/24LCXXX or 24FCXXX and the MCP3912,
to share all the SPI pins and consume less I/O pins in
the application processor, since all these serial
EEPROM circuits use A[6:5] = 00.
.
FIGURE 6-1: Control Byte.
A[6] A[5] A[4] A[3] A[2] A[1] A[0] R/W
Device
Address
Register Address Read/
Write
FIGURE 6-2:
Read on a Single Register with 24-B/‘t Format (WIDTHiDATA[1:0] = ,
HJH
FIGURE 6-3:
Read on a Single Register with 24-B/‘t Format (WIDTHiDATA[1:0] = ,
MCP3912
DS20005348B-page 42 2014-2019 Microchip Technology Inc.
The default device address bits are A[6:5] = 01 (contact
the Microchip factory for other available device address
bits). For more information, see the Product Identifi-
cation System section. The register map is defined in
Table 8-1.
6.3 Reading from the Device
The first register read on the SDO pin is the one defined
by the address (A[4:0]) given in the control byte. After
this first register is fully transmitted, if the CS pin is
maintained logic low, the communication continues
without an additional control byte and the SDO pin
transmits another register with the address automati-
cally incremented or not, depending on the READ[1:0]
bits settings.
Four different Read mode configurations can be defined
through the READ[1:0] bits in the STATUSCOM register
for the address increment (see Section 6.5, Continu-
ous Communications, Looping on Register Sets
and Ta b l e 8 - 2 ). The data on SDO are clocked out of the
MCP3912 on the falling edge of SCK. The reading
format for each register is defined in Section 6.5 “Con-
tinuous Communications, Looping on Register
Sets”.
FIGURE 6-2: Read on a Single Register with 24-Bit Format (WIDTH_DATA[1:0] = 01,
SPI Mode 1,1).
FIGURE 6-3: Read on a Single Register with 24-Bit Format (WIDTH_DATA[1:0] = 01,
SPI Mode 0,0).
Read Communication (SPI Mode 1,1)
Don’t careDon’t care
A[6]
DATA[22]
SCK
SDI
SDO
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
CS
DATA[21]
DATA[20]
DATA[19]
DATA[18]
DATA[17]
DATA[16]
DATA[15]
DATA[14]
DATA[13]
DATA[12]
DATA[11]
DATA[10]
DATA[9]
DATA[8]
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
DATA[2]
DATA[1]
DATA[0]
High-Z High-Z
Device latches SDI on rising edge Device latches SDO on falling edge
R/W
DATA[23]
Read Communication (SPI Mode 0,0)
Don‘t careDon’t care
Don’t care
A[6]
DATA[22]
SCK
SDI
SDO
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
R/W
CS
DATA[23]
DATA[21]
DATA[20]
DATA[19]
DATA[18]
DATA[17]
DATA[16]
DATA[15]
DATA[14]
DATA[13]
DATA[12]
DATA[11]
DATA[10]
DATA[9]
DATA[8]
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
DATA[2]
DATA[1]
DATA [0]
High-Z High-Z
Device latches SDI on rising edge Device latches SDO on falling edge
7JJJHHfHHHHHMHHHHHJi
AUHJJJJHHHHHHHHMHH
2014-2019 Microchip Technology Inc. DS20005348B-page 43
MCP3912
6.4 Writing to the Device
The first register written from the SDI pin to the device
is the one defined by the address (A[4:0]) given in the
control byte. After this first register is fully transmitted,
if the CS pin is maintained logic low, the communica-
tion continues without an additional control byte and
the SDI pin transmits another register with the
address automatically incremented or not, depending
on the WRITE bit setting.
Two different Write mode configurations for the address
increment can be defined through the WRITE bit in the
STATUSCOM register (see Section 6.5, Continuous
Communications, Looping on Register Sets and
Tabl e 8 -2 ). The SDO pin stays in a high-impedance state
during a write communication. The data on SDI are
clocked into the MCP3912 on the rising edge of SCK.
The writing format for each register is defined in
Section 6.5 “Continuous Communications, Looping
on Register Sets”. A write on an undefined or non-
writable address, such as the ADC channel’s register
addresses, will have no effect and also will not increment
the address counter.
FIGURE 6-4: Write to a Single Register with 24-Bit Format (SPI Mode 1,1).
FIGURE 6-5: Write to a Single Register with 24-Bit Format (SPI Mode 0,0).
Write Communication (SPI mode 1,1)
Don’t care
A[6]
SCK
SDI
SDO
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
CS
High-Z
Device latches SDI on rising edge
R/W
DATA[22]
DATA[21]
DATA[20]
DATA[19]
DATA[18]
DATA[17]
DATA[16]
DATA[15]
DATA[14]
DATA[13]
DATA[12]
DATA[11]
DATA[10]
DATA[9]
DATA[8]
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
DATA[2]
DATA[1]
DATA[23]
Don’t
care
DATA[0]
Write Communication (SPI Mode 1,1)
Write Communication (SPI mode 0,0)
Don’t care
A[6]
SCK
SDI
SDO
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
R/W
CS
High-Z
Device latches SDI on rising edge
Don’t care
DATA[22]
DATA[23]
DATA[21]
DATA[20]
DATA[19]
DATA[18]
DATA[17]
DATA[16]
DATA[15]
DATA[14]
DATA[13]
DATA[12]
DATA[11]
DATA[10]
DATA[9]
DATA[8]
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
DATA[2]
DATA[1]
DATA[0]
Write Communication (SPI Mode 0,0)
MCP3912
DS20005348B-page 44 2014-2019 Microchip Technology Inc.
6.5 Continuous Communications,
Looping on Register Sets
The MCP3912 digital interface can process communi-
cations in Continuous mode without having to enter an
SPI command between each read or write to a register.
This feature allows the user to reduce communication
overhead to the strict minimum, which diminishes EMI
emissions and reduces switching noise in the system.
The registers can be grouped into multiple sets for con-
tinuous communications. The grouping of the registers
in the different sets is defined by the READ[1:0] and
WRITE bits that control the internal SPI Communica-
tion Address Pointer. For a graphical representation of
the register map sets in the function of the READ[1:0]
and WRITE bits, please see Table 8-2.
In the case of a continuous communication, there is
only one control byte on SDI to start the communication
after a CS pin falling edge. The part stays within the
same communication loop until the CS pin returns logic
high. The SPI internal Register Address Pointer starts
by transmitting/receiving the address defined in the
control byte. After this first transmission/reception, the
SPI internal Register Address Pointer automatically
increments to the next available address in the register
set for each transmission/reception. When it reaches
the last address of the set, the communication
sequence is finished. The Address Pointer automati-
cally loops back to the first address of the defined set
and restarts a new sequence with auto-increment (see
Table 6-6). This internal Address Pointer automatic
selection allows the following functionality:
• Read one ADC channel data, pairs of ADC
channels or all ADC channels continuously
• Continuously read the entire register map
• Continuously read or write each separate register
• Continuously read or write all Configuration
registers
FIGURE 6-6: Continuous Communication Sequences.
Don’t care
Continuous Read Communication (24-bit format)
Don’t care
SCK
SDI
SDO
CS
High-Z
8x
CONTROL
BYTE
24x
ADDR ... ADDR + n
Starts Read Sequence
at Address ADDR
Complete READ Sequence
ADDR + 1
24x ... 24x 24x
ADDR ...
Complete READ Sequence
ADDR + 1
24x ... 24x
ADDR + n
Continuous Write Communication (24-bit format)
Don’t care
SCK
SDI
SDO
CS
High-Z
8x
CONTROL
BYTE
24x
ADDR ... ADDR + n
Starts Write Sequence
at Address ADDR
Complete WRITE Sequence
ADDR + 1
24x ... 24x 24x
ADDR ...
Complete WRITE Sequence
ADDR + 1
24x ... 24x
ADDR + n
ADDR
ADDR + 1
...
ADDR + n
Complete
READ
Sequence
Rollover
ADDRESS SET
ADDR
ADDR + 1
...
ADDR + n
Complete
WRITE
Sequence
Rollover
ADDRESS SET
2014-2019 Microchip Technology Inc. DS20005348B-page 45
MCP3912
6.5.1 CONTINUOUS READ
The STATUSCOM register contains the read communica-
tion loop settings for the internal Register Address Pointer
(READ[1:0] bits). For continuous Read modes, the
address selection can take the following four values:
Any SDI data coming after the control byte are not consid-
ered during a continuous read communication. The
following figures represent a typical continuous read
communication on all four ADC channels in TYPES mode
with the default settings (DR_LINK = 1, READ[1:0] = 10,
WIDTH_DATA[1:0] = 01) in the case of SPI Mode 0,0
(Figure 6-7) and SPI Mode 1,1 (Figure 6-8).
In SPI Mode (1,1), the SDO pin stays in the last state (LSB
of previous data) after a complete reading, which also
allows seamless continuous Read mode (see Figure 6-8).
FIGURE 6-7: Typical Continuous Read Communication (WIDTH_DATA[1:0] = 01, SPI Mode 0,0).
FIGURE 6-8: Typical Continuous Read Communication (WIDTH_DATA[1:0] = 01, SPI Mode 1,1).
TABLE 6-1: ADDRESS SELECTION IN
CONTINUOUS READ
READ[1:0]
Register Address Set Grouping
for Continuous Read
Communications
00 Static (no incrementation)
01 Groups
10 Types (default)
11 Full Register Map
Note: For continuous reading of ADC data in
SPI Mode 0,0 (see Figure 6-7), once the
data have been completely read after a
data ready, the SDO pin will take the MSB
value of the previous data at the end of the
reading (falling edge of the last SCK
clock). If SCK stays Idle at logic low (by
definition of Mode 0,0), the SDO pin will
be updated at the falling edge of the next
data ready pulse (synchronously with the
DR pin falling edge with an output timing
of tDODR) with the new MSB of the data
corresponding to the data ready pulse.
This mechanism allows the MCP3912 to
continuously read ADC data outputs
seamlessly, even in SPI Mode (0,0).
Don’t Care
SCK
SDI
SDO
CS
High-Z
8x
0x01
24x
DATA_CH0 ... DATA_CH3
Starts Read Sequence
at Address 00000
Complete READ Sequence on ADC Outputs Channels 0 to 3
DATA_CH1
24x ... 24x 24x
DATA_CH0 ...DATA_CH1
24x ... 24x
DATA_CH3
Don’t Care
DR
DATA_CH0[23]
New Data
DATA_CH0[23]
Old Data
Complete READ Sequence on New ADC Outputs Channels 0 to 3
Don’t Care
SCK
SDI
SDO
CS
High-Z
8x
0x01
24x
DATA_CH0 ... DATA_CH3
Starts Read Sequence
at Address 00000
Complete READ Sequence on ADC Outputs Channels 0 to 3
DATA_CH1
24x ... 24x 24x
DATA_CH0 ...DATA_CH1
24x ... 24x
DATA_CH3
Don’t Care
DR
Complete READ Sequence on New ADC Outputs, Channels 0 to 3
Stays at
DATA_CH3[0]
DR_H|Z
DR_H|Z
DR_H|Z
MCP3912
DS20005348B-page 46 2014-2019 Microchip Technology Inc.
6.5.2 CONTINUOUS WRITE
The STATUSCOM register contains the write loop
settings for the internal Register Address Pointer
(WRITE). For a continuous write, the address selection
can take the following two values:
SDO is always in a high-impedance state during a
continuous write communication. Writing to a non-
writable address (such as addresses 0x00 to 0x07) has
no effect and does not increment the Address Pointer. In
this case, the user needs to stop the communication and
restart a communication with a control byte pointing to a
writable address (0x08 to 0x1F).
6.6 Situations that Reset and Restart
Active ADCs
Immediately after the following actions, the active
ADCs (the ones not in Soft Reset or Shutdown modes)
are reset and automatically restarted in order to provide
proper operation:
1. Change in PHASE register.
2. Overwrite of the same PHASE register value.
3. Change in the OSR[2:0] bits setting.
4. Change in the PRE[1:0] bits setting.
5. Change in the CLKEXT bit setting.
6. Change in the VREFEXT bit setting.
After these temporary Resets, the ADCs go back to
normal operation with no need for an additional com-
mand. Each ADC Data Output register is cleared
during this process. The PHASE register can be used
to serially soft reset the ADCs, without using the
RESET[3:0] bits in the Configuration register, if the
same value is written in the PHASE register.
6.7 Data Ready Pin (DR)
To communicate when channel data are ready for
transmission, the data ready signal is available on the
Data Ready (DR) pin at the end of a channel conver-
sion. The Data Ready pin outputs an active-low pulse
with a pulse width equal to half a DMCLK clock period.
After a data ready pulse falling edge has occurred, the
ADC output data are updated within the tDODR timing
and can then be read through SPI communication.
The first data ready pulse after a Hard or a Soft Reset
is located after the settling time of the SINC filter (see
Table 5-3) plus the phase delay of the corresponding
channel (see Section 5.9 “Phase Delay Block”).
Each subsequent pulse is then periodic and the period
is equal to a DRCLK clock period (see Equation 4-3
and Figure 1-3). The data ready pulse is always
synchronous with the internal DRCLK clock.
The DR pin can be used as an interrupt pin when
connected to an MCU or DSP, which will synchronize
the readings of the ADC data outputs. When not active-
low, this pin can either be in high-impedance (when
DR_HIZ = 0) or in a defined logic high state (when
DR_HIZ = 1). This is controlled through the
STATUSCOM register. This allows multiple devices to
share the same Data Ready pin (with a pull-up resistor
connected between DR and DVDD). If only the
MCP3912 device is connected on the interrupt bus, the
DR pin does not require a pull-up resistor, and
therefore, it is recommended to use DR_HIZ = 1
configuration for such applications.
The CS pin has no effect over the DR pin, which means
even if the CS pin is logic high, the data ready pulses
coming from the active ADC channels will still be pro-
vided; the DR pin behavior is independent from the SPI
interface. While the RESET pin is logic low, the DR pin
is not active. The DR pin is latched in the logic low state
when the interrupt flag on CRCREG is present to signal
that the desired register’s configuration has been cor-
rupted (see Section 6.11 “Detecting Configuration
Change Through CRC-16 Checksum on Register
Map and its Associated Interrupt Flag”).
TABLE 6-2: ADDRESS SELECTION IN
CONTINUOUS WRITE
WRITE Register Address Set Grouping for
Continuous Read Communications
0Static (no incrementation)
1Types (default)
Note: When the LOCK[7:0] bits are different than
0xA5, all the addresses, except 0x1F,
become nonwritable (see Section 4.13
“MCP3912 Delta-Sigma Architecture”).
Once a falhng edge occurs on the W
2014-2019 Microchip Technology Inc. DS20005348B-page 47
MCP3912
6.8 ADC Channels Latching and
Synchronization
The ADC Channel Data Output registers (addresses
0x00 to 0x03) have a double-buffer output structure.
The two sets of latches in series are triggered by the
data ready signal and an internal signal indicating the
beginning of a read communication sequence (read
start).
The first set of latches holds each ADC Channel Data
Output register when the data are ready and latches all
active outputs together when DR_LINK = 1. This
behavior is synchronous with the DMCLK clock.
The second set of latches ensures that when reading
starts on an ADC output, the corresponding data are
latched so that no data corruption can occur within a
read. This behavior is synchronous with the SCK clock.
If an ADC read has started, in order to read the follow-
ing ADC output, the current reading needs to be fully
completed (all bits must be read on the SDO pin from
the ADC Output Data registers).
Since the double-output buffer structure is triggered
with two events that depend on two asynchronous
clocks (data ready with DMCLK and read start with
SCK), one of the three following methods on the MCU
or processor should be implemented in order to
synchronize the reading of the channels:
1. Use the Data Ready pin pulses as an interrupt:
Once a falling edge occurs on the DR pin, the data
are available for reading on the ADC Output
registers after the tDODR timing. If this timing is not
respected, data corruption can occur.
2. Use a timer clocked with MCLK as a synchro-
nization event: Since the Data Ready pin is
synchronous with DMCLK, the user can calculate
the position of the Data Ready pin depending on
the PHASE register, the OSR[2:0] and the
PRE[1:0] bits setting for each channel. Again, the
tDODR timing needs to be added to this calculation,
to avoid data corruption.
3. Poll the DRSTATUS[3:0] bits in the
STATUSCOM register: This method consists of
continuously reading the STATUSCOM register
and waiting for the DRSTATUS bits to be equal to
‘0’. When this event happens, the user can start a
new communication to read the desired ADC data.
In this case, no additional timing is required.
The first method is the preferred one, as it can be used
without adding additional MCU code space, but
requires connecting the DR pin to an I/O pin of the
MCU. The last two methods require more MCU code
space and execution time, but they allow synchronized
reading of the channels without connecting the DR pin,
which saves one I/O pin on the MCU.
6.9 Securing Read Communications
Through CRC-16 Checksum
Since power/energy metering systems can generate or
receive large EMI/EMC interferences and large
transient spikes, it is helpful to secure SPI communica-
tions as much as possible to maintain data integrity and
desired configurations during the lifetime of the
application.
The communication data on the SDO pin can be
secured through the insertion of a Cyclic Redundancy
Check (CRC) checksum at the end of each continuous
reading sequence. The CRC checksum on communi-
cations can be enabled or disabled through the
EN_CRCCOM bit in the STATUSCOM register. The
CRC message ensures the integrity of the read
sequence bits transmitted on the SDO pin and the CRC
checksum is inserted in between each read sequence
(see Figure 6-9).
MCP3912
DS20005348B-page 48 2014-2019 Microchip Technology Inc.
FIGURE 6-9: Continuous Read Sequences with and without CRC Checksum Enabled.
The CRC checksum in the MCP3912 device uses the
16-bit CRC-16 ANSI polynomial, as defined in the
IEEE 802.3 standard: x16 + x15 + x2 + 1. This polynomial
can also be noted as 0x8005. CRC-16 detects all single
and double-bit errors, all errors with an odd number of
bits, all burst errors of length 16 or less and most errors
for longer bursts. This allows an excellent coverage of the
SPI communication errors that can happen in the system
and heavily reduces the risk of a miscommunication,
even under noisy environments.
The CRC-16 format displayed on the SDO pin depends
on the WIDTH_CRC bit in the STATUSCOM register
(see Figure 6-10). It can be either 16-bit or 32-bit format,
to be compatible with both 16-bit and 32-bit MCUs. The
CRCCOM[15:0] bits, calculated by the MCP3912
device, are not dependent on the format (the device
always calculates only a 16-bit CRC checksum). If a
32-bit MCU is used in the application, it is recommended
to use 32-bit formats (WIDTH_CRC = 1) only.
FIGURE 6-10: CRC Checksum Format.
The CRC calculation computed by the MCP3912
device is fully compatible with CRC hardware
contained in the Direct Memory Access (DMA) of the
PIC24 and PIC32 MCU product lines. The CRC
message that should be considered in the PIC® device
DMA is the concatenation of the read sequence and its
associated checksum. When the DMA CRC hardware
computes this extended message, the resulted check-
sum should be 0x0000. Any other result indicates that
a miscommunication has happened and that the
current communication sequence should be stopped
and restarted.
Continuous READ Communication without CRC Checksum (EN_CRCCOM = 0)
Don’t care
SCK
SDI
SDO
CS
High-Z
8x
CONTROL
BYTE
16x/24x/32x
Depending on
Data Format
ADDR ... ADDR + n
Starts Read Sequence
at Address ADDR
Complete READ Sequence
ADDR + 1
16x/24x/32x
Depending on
Data Format
...
16x/24x/32x
Depending on
Data Format
16x/24x/32x
Depending on
Data Format
ADDR ...
Complete READ Sequence
ADDR + 1
16x/24x/32x
Depending on
Data Format
...
16x/24x/32x
Depending on
Data Format
ADDR + n
Don’t care
ADDR
ADDR + 1
...
ADDR + n*
Complete
READ
Sequence
Rollover
ADDRESS SET
Continuous READ Communication with CRC Checksum (EN_CRCCOM = 1)
Don’t care
SCK
SDI
SDO
CS
High-Z
8x
CONTROL
BYTE
16x/24x/32x
Depending on
Data Format
ADDR ... ADDR + n
Starts Read Sequence
at Address ADDR
Complete READ Sequence = Message for CRC Calculation
ADDR + 1
16x/24x/32x
Depending on
Data Format
...
16x/24x/32x
Depending on
Data Format
16x/24x/32x
Depending on
Data Format
ADDR ...
New Message
ADDR + 1
16x/24x/32x
Depending on
Data Format
...
16x/24x/32x
Depending on
Data Format
ADDR + n
Don’t care
ADDR
ADDR + 1
...
ADDR + n*
Complete
READ
Sequence
Rollover
ADDRESS SET
CRC Checksum CRC Checksum
16x or 32x
Depending on
CRC Format
16x or 32x
Depending on
CRC Format
CRC Checksum (not part of register map)
New ChecksumChecksum
*n Depends on the READ[1:0] bits.
WIDTH_DATA[1] = 0
16-Bit Format CRCCOM
[15:8] CRCCOM
[7:0]
15 0
WIDTH_DATA[1] = 1
32-Bit Format CRCCOM
[15:8] CRCCOM
[7:0]
31 0
0x00 0x00
Note: The CRC will be generated only at the end
of the selected address set, before the
rollover of the Address Pointer occurs
(see Figure 6-9).
inlerrupl sends a flag by semng the W
2014-2019 Microchip Technology Inc. DS20005348B-page 49
MCP3912
6.10 Locking/Unlocking Register Map
Write Access
The MCP3912 digital interface includes an advanced
security feature that permits locking or unlocking the
register map write access. This feature prevents the
miscommunications that can corrupt the desired
configuration of the device, especially an SPI read
becoming an SPI write because of the noisy
environment.
The last register address of the register map
(0x1F: LOCK/CRC) contains the LOCK[7:0] bits. If
these bits are equal to the password value (which is
equal to the default value of 0xA5), the register map
write access is not locked. Any write can take place and
the communications are not protected.
When the LOCK[7:0] bits are different than 0xA5, the
register map write access is locked. The register map,
and therefore, the full device configuration, is write-
protected. Any write to an address other than 0x1F will
yield no result. All the register addresses, except the
address 0x1F, become read-only. In this case, if the
user wants to change the configuration, the LOCK[7:0]
bits have to be reprogrammed back to 0xA5 before
sending the desired WRITE command.
The LOCK[7:0] bits are located in the last register so
the user can program the whole register map, starting
from 0x09 to 0x1E, within one continuous write
sequence, and then lock the configuration at the end of
the sequence by writing all zeros in the address 0x1F,
for example.
6.11 Detecting Configuration Change
Through CRC-16 Checksum on
Register Map and its Associated
Interrupt Flag
In order to prevent internal corruption of the register and
to provide additional security on the register map config-
uration, the MCP3912 device includes an automatic and
continuous CRC checksum calculation on the full register
map Configuration bits. This calculation is not the same
as the communication CRC checksum described in
Section 6.9 “Securing Read Communications
Through CRC-16 Checksum”. This calculation takes
the full register map as the CRC message and outputs a
checksum on the CRCREG[15:0] bits located in the
LOCK/CRC register (address 0x1F).
Since this feature is intended for protecting the
configuration of the device, this calculation is run
continuously only when the register map is locked
(LOCK[7:0] bits are different than 0xA5, see
Section 6.10, Locking/Unlocking Register Map
Write Access). If the register map is unlocked, the
CRCREG[15:0] bits are cleared and no CRC is
calculated.
The calculation is fully completed in 16 DMCLK periods
and refreshed every 16 DMCLK periods continuously.
The CRCREG[15:0] bits are reset when a POR or a
Hard Reset occurs. All the bits contained in the regis-
ters, from addresses 0x09-0x1F, are processed by the
CRC engine to give the CRCREG[15:0] bits. The
DRSTATUS[3:0] bits are set to ‘1’ (default) and the
CRCREG[15:0] bits are set to ‘0’ (default) for this
calculation engine, as they could vary during the
calculation.
An interrupt flag can be enabled through the EN_INT
bit in the STATUSCOM register and provided on the DR
pin when the configuration has changed without a
WRITE command being processed. This interrupt is a
logic low state. This interrupt is cleared when the
register map is unlocked (since the CRC calculation is
not processed).
At power-up, the interrupt is not present and the register
map is unlocked. As soon as the user finishes writing its
configuration, the user needs to lock the register map
(writing 0x00, for example, in the LOCK bits) to be able
to use the interrupt flag. The CRCREG[15:0] bits will be
calculated for the first time in 16 DMCLK periods. This
first value will then be the reference checksum value and
will be latched internally until a Hard Reset, a POR
or an unlocking of the register map happens. The
CRCREG[15:0] bits will then be calculated continuously
and checked against the reference checksum. If the
CRCREG[15:0] bits are different than the reference, the
interrupt sends a flag by setting the DR pin to a logic low
state until it is cleared.
MCP3912
DS20005348B-page 50 2014-2019 Microchip Technology Inc.
NOTES:
2014-2019 Microchip Technology Inc. DS20005348B-page 51
MCP3912
7.0 BASIC APPLICATION
RECOMMENDATIONS
7.1 Typical Application Examples
The application schematic referenced in Figure 7-1 can
be used as a starting point for MCP3912 applica-
tions.The most common solution is to use one channel
for voltage measurement and the rest of the channels for
current measurement. Since all current lines are at the
same potential, shunts can be used as current sensors,
even if they do not provide any galvanic isolation.
Since all channels are identical in the MCP3912, any
channel can be chosen as the voltage channel (prefer-
ably CH0 or CH3 since they are on the edges and can
lead to a cleaner layout).
FIGURE 7-1: MCP3912 Application Example Schematic.
RG9/3912_CS
RG7/3912_SDO
RG6/3912_SCK
RG8/3912_SDI
GND
RA5/3912_RESET
XTAL
RD3/3912_CLKIN
XTAL
GNDA
GND
ADC CLOCK SELECT
10MHz
X1
18pF
0603
C7
18pF
0603
C6 GND
1%1M
0603
R20
10R
0603
R17
10R
0603
R7
0.1uF
0603
C3
10R
0603
R9
0.1uF
0603
C4
10R
0603
R6
10R
0603
R8
10R
0603
R10
10R
0603
R12
100R
0603
R5
10R
0603
R14
GNDA
GNDA
GNDA
0.1uF
0603
C5
2x3
X
X
1
2
3
4
5
6
J3
ECCP3
3.3D3.3A
GND
GND GNDA GNDA
GNDA
GNDA
CH0-
CH0+
1%1k
0603
R18
1%1k
0603
R65
GNDA
1%1k
0603
R67
1%1k
0603
R16
0.1uF
0603
C50
0.1uF
0603
C47
2x3
1
2
3
4
5
6
J7
1x3
123
J20
1%1k
0603
R66
1%1k
0603
R64
GND GNDA GNDA
GNDA
GNDA
CH1+
CH1-
1%1k
0603
R69
1%1k
0603
R71
GNDA
1%1k
0603
R73
1%1k
0603
R68
0.1uF
0603
C52
0.1uF
0603
C51
2x3
1
2
3
4
5
6
J21
1x3
123
J22
1%1k
0603
R72
1%1k
0603
R70
GND GNDA GNDA
GNDA
GNDA
CH2-
CH2+
1%1k
0603
R75
1%1k
0603
R77
GNDA
1%1k
0603
R79
1%1k
0603
R74
0.1uF
0603
C54
0.1uF
0603
C53
2x3
1
2
3
4
5
6
J23
1x3
123
J24
1%1k
0603
R78
1%1k
0603
R76
GND GNDA GNDA
GNDA
GNDA
CH3+
CH3-
1%1k
0603
R81
1%1k
0603
R83
GNDA
1%1k
0603
R85
1%1k
0603
R80
0.1uF
0603
C56
0.1uF
0603
C55
2x3
1
2
3
4
5
6
J25
1x3
123
J26
1%1k
0603
R84
1%1k
0603
R82
RA14/3912_DR
NC 10
CH2-
7
REFIN+
14
CH2+
6
CH3-
8
CH3+
9
REFIN-
15
N
C
C
H
2-
REFIN
+
C
H2
+
C
H
3-
C
H
3+
REFIN-
DGND 20
DR 18
OSC1/CLKI 21
OSC2 22
CS 23
SCK 24
SDO 25
SDI 26
RESET 27
DGND 17
DVDD 28
AVDD
1
AGND
16
CH0+
2
CH0-
3
CH1-
4
CH1+
5
NC 11
NC 12
NC 13
NC 19
MCP3912
U5
ADC
CH0+
CH0-
CH1-
CH1+
CH2+
CH2-
CH3-
CH3+
FIGURE 7-2:
All Analog and Digital
m
mmnome
, V :
w»: cw rm». (Mm
FIGURE 7-3:
Power Supply with Separate Lines forAna/og and Digital Sections. Note the "Net Tie"
MCP3912
DS20005348B-page 52 2014-2019 Microchip Technology Inc.
7.2 Power Supply Design and
Bypassing
The MCP3912 device was designed to measure posi-
tive and negative voltages that might be generated by
a current-sensing device. This current-sensing device,
with a Common-mode voltage close to 0V, is referred to
as AGND, which is a shunt or Current Transformer (CT)
with burden resistors attached to ground. The high per-
formance and good flexibility that characterize this
ADC enables it to be used in other applications, as long
as the absolute voltage on each pin, referred to AGND,
stays in the -1V to +1V interval.
In any system, the analog ICs (such as references or
operational amplifiers) are always connected to the
analog ground plane. The MCP3912 should also be
considered as a sensitive analog component and con-
nected to the analog ground plane. The ADC features
two pairs of pins: AGND and AVDD, DGND and DVDD. For
best performance, it is recommended to keep the two
pairs connected to two different networks (Figure 7-2).
This way, the design will feature two ground traces and
two power supplies (Figure 7-3).
This means the analog circuitry (including MCP3912)
and the digital circuitry (MCU) should have separate
power supplies and return paths to the external ground
reference, as described in Figure 7-2. An example of a
typical power supply circuit, with different lines for
analog and digital power, is shown in Figure 7-3. A pos-
sible split example is shown in Figure 7-4, where the
ground star connection can be done at the bottom of
the device with the exposed pad. The split here
between analog and digital can be done under the
device, and AVDD and DVDD can be connected
together with lines coming under the ground plane.
Another possibility, sometimes easier to implement in
terms of PCB layout, is to consider the MCP3912 as an
analog component, and therefore, connect both AVDD
and DVDD together, and AGND and DGND together with
a star connection. In this scheme, the decoupling
capacitors may be larger due to the ripple on the digital
power supply (caused by the digital filters and the SPI
interface of the MCP3912) now causing glitches on the
analog power supply.
FIGURE 7-2: All Analog and Digital
Return Paths Need to Stay Separate with Proper
Bypass Capacitors.
FIGURE 7-3: Power Supply with Separate Lines for Analog and Digital Sections. Note the “Net Tie”
Object NT2 that Represents the Start Ground Connection.
VAVD
MCU
“Star” Point
IA
ID
ID
IA
AV
DD
DV
DD
A
GND
D
GND
D- = A- =
0.1 μF
MCP39XX
0.1 μF
C
2014-2019 Microchip Technology Inc. DS20005348B-page 53
MCP3912
FIGURE 7-4: Separation of Analog and
Digital Circuits on Layout.
Figure 7-5 shows a more detailed example with a direct
connection to a high-voltage line (e.g., a two-wire 120V
or 220V system). A current-sensing shunt is used for
current measurement on the high side/line side that
also supplies the ground for the system. This is neces-
sary as the shunt is directly connected to the channel
input pins of the MCP3912. To reduce sensitivity to
external influences, such as EMI, these two wires
should form a twisted pair, as noted in Figure 7-5. The
power supply and MCU are separated on the right side
of the PCB, surrounded by the digital ground plane.
The MCP3912 is kept on the left side, surrounded by
the analog ground plane. There are two separate
power supplies going to the digital section of the sys-
tem and the analog section, including the MCP3912.
With this placement, there are two separate current
supply paths and current return paths, IA and ID.
FIGURE 7-5: Connection Diagram.
The ferrite bead between the digital and analog ground
planes helps keep high-frequency noise from entering
the device. This ferrite bead is recommended to be low
resistance; most often it is a THT component. Ferrite
beads are typically placed on the shunt inputs and into
the power supply circuit for additional protection.
7.3 SPI Interface Digital Crosstalk
The MCP3912 incorporates a high-speed 20 MHz SPI
digital interface. This interface can induce a crosstalk,
especially with the outer channels (CH0, for example),
if it is running at its full speed without any precautions.
The crosstalk is caused by the switching noise created
by the digital SPI signals (also called ground bouncing).
This crosstalk would negatively impact the SNR in this
case. The noise is attenuated if a proper separation
between the analog and digital power supplies is put in
place (see Section 7.2 “Power Supply Design and
Bypassing”).
In order to further remove the influence of the SPI
communication on measurement accuracy, it is recom-
mended to add series resistors on the SPI lines to
reduce the current spikes caused by the digital switch-
ing noise (see Figure 7-5 where these resistors have
been implemented). The resistors also help to keep the
level of electromagnetic emissions low.
The measurement graphs provided in this MCP3912
data sheet have been performed with 100 series
resistors connected on each SPI I/O pin. Measurement
accuracy disturbances have not been observed, even
at the full speed of 20 MHz interfacing.
The crosstalk performance is dependent on the package
choice due to the difference in the pin arrangement
(dual in-line or quad) and is improved in the 28-lead
QFN package.
2
26
3
4
5
6
10 11 12 13 14
18
17
16
15
28 27 25
CH0+
CH0-
CH1-
DVDD
SDI
SDO
RESET
AGND
EP
29
7
CH1+
CH2+ 19
20
24
SCK
23
CS
OSC2
CH2-
22
OSC1/CLKI
1
89
NC
DGND
AVDD
DGND
21
AGND
REFIN-
DGND
AVDD
DVDD
CH3-
CH3+
REFIN+/
OUT
DR
ANALOG DIGITAL
Power Supply
Circuitry
LINE
NEUTRAL
SHUNT
Twisted
Pair
IA
ID
ID
IA
“Star” Point
VA
VD
Analog Ground Plane Digital Ground Plane
MCP3912 MCU
Um V
530" :‘Lr
z E)” (PW EDW
Mi
Re
MCP3912
DS20005348B-page 54 2014-2019 Microchip Technology Inc.
7.4 Sampling Speed and Bandwidth
If ADC power consumption is not a concern in the
design, the boost settings can be increased for best
performance so that the OSR is always kept at the
maximum settings to improve the SINAD performance
(see Table 7-1). If the MCU cannot generate a clock
fast enough, it is possible to tap the OSC1/OSC2 pins
of the MCP3912 crystal oscillator directly to the crystal
of the microcontroller. When the sampling frequency is
enlarged, the phase resolution is improved, and with
the OSR increased, the phase compensation range
can be kept in the same range as the default settings.
7.5 Differential Inputs
Anti-Aliasing Filter
Due to the nature of the ADCs used in the MCP3912
(oversampling converters), each differential input of the
ADC channels requires an anti-aliasing filter so that the
oversampling frequency (DMCLK) is largely attenuated
and does not generate any disturbances on the ADC
accuracy. This anti-aliasing filter also needs to have a
gain close to one in the signal bandwidth of interest.
Typically for 50/60 Hz measurement and default
settings (DMCLK = 1 MHz), a simple RC filter with 1 k
and 100 nF can be used. The anti-aliasing filter used
for the measurement graphs is a first-order RC filter
with 1 k and 15 nF. The typical schematic for connect-
ing a current transformer to the ADC is shown in
Figure 7-6. If wires are involved, twisting them is also
recommended.
FIGURE 7-6: First-Order Anti-Aliasing
Filter for CT-Based Designs.
The di/dt current sensors, such as Rogowski coils, can
be an alternative to current transformers. Since these
sensing elements are highly sensitive to high-
frequency electromagnetic fields, using a second-order
anti-aliasing filter is recommended to increase the
attenuation of potential perturbing RF signals.
FIGURE 7-7: Second-Order Anti-Aliasing
Filter for Rogowski Coil-Based Designs.
The MCP3912 is highly recommended in applications
using di/dt as current sensors because of the extremely
low noise floor at low frequencies. In such applications,
a Low-Pass Filter (LPF) with a cutoff frequency much
lower than the signal frequency (50-60 Hz for metering)
is used to compensate for the 90-degree shift and for
the 20 db/decade attenuation induced by the di/dt
sensor. Because of this filter, the SNR will be
decreased, since the signal will attenuate by a few
orders of magnitude, while the low-frequency noise will
not be attenuated. Usually, a high-order High-Pass Filter
(HPF) is used to attenuate the low-frequency noise in
order to prevent a dramatic degradation of the SNR,
which can be very important in other parts. A high-order
filter will also consume a significant portion of the com-
putation power of the MCU. When using the MCP3912,
such a high-order HPF is not required since this part has
a low noise floor at low frequencies. A first-order HPF is
enough to achieve very good accuracy.
TABLE 7-1: SAMPLING SPEED vs.
MCLK AND OSR,
ADC PRESCALE 1:1
MCLK
(MHz) BOOST[1:0] OSR
Sampling
Speed
(ksps)
16 11 1024 3.91
14 11 1024 3.42
12 11 1024 2.93
10 10 1024 2.44
810 512 3.91
601 512 2.93
401 256 3.91
2014-2019 Microchip Technology Inc. DS20005348B-page 55
MCP3912
7.6 Energy Measurement
Error Considerations
The measurement error is a typical representation of the
nonlinearity of a pair of ADCs (see Section 4.0 “Termi-
nology and Formulas” for the definition of measurement
error). The measurement error is dependent on the THD
and on the noise floor of the ADCs.
Improving the measurement error specification on the
MCP3912 can be realized by increasing the OSR (to
get a better SINAD and THD performance), and to
some extent, the BOOST settings (if the bandwidth of
the measurements is too limited by the bandwidth of
the amplifiers in the Sigma-Delta ADCs). In most of the
energy metering AC applications, High-Pass Filters are
used to cancel the offset on each ADC channel (current
and voltage channels), and therefore, a single point
calibration is necessary to calibrate the system for
active energy measurement. This calibration is a
system gain calibration, and the user can utilize the
EN_GAINCAL bit and the GAINCAL_CHn registers to
perform this digital calibration. After such calibration,
typical measurement error curves, such as in Figure 2-7,
can be generated by sweeping the current channel
amplitude and measuring the energy at the outputs (the
energy calculations here are being realized off-chip).
The error is measured using a gain of 1x, as it is
commonly used in most CT-based applications.
At low signal amplitude values (typically 1000:1
dynamic range and higher), the crosstalk between
channels, mainly caused by the PCB, becomes a
significant part of the perturbation as the measurement
error increases. The 1-point measurement error curves
in Figure 2-5 have been performed with a full-scale
sine wave on all the inputs that are not measured,
which means that these channels induce a maximum
amount of crosstalk on the measurement error curve.
In order to avoid such behavior, a 2-point calibration
can be put in place in the calculation section.
This 2-point calibration can be a simple linear inter-
polation between two calibration points (one at high
amplitudes, one at low amplitudes at each end of the
dynamic range) and helps to significantly lower the
effect of crosstalk between channels. A 2-point calibra-
tion is very effective in maintaining the measurement
error close to zero on the whole dynamic range, since
the nonlinearity and distortion of the MCP3912 are very
low. Figure 2-6 shows the measurement error curves
obtained with the same ADC data taken for Figure 2-5,
but where a 2-point calibration has been applied. The
difference is significant only at the low end of the
dynamic range, where all the perturbing factors are a
bigger part of the ADC output signals. These curves
show extremely tight measurement error across the full
dynamic range (here, typically 10,000:1), which is
required in high-accuracy class meters.
MCP3912
DS20005348B-page 56 2014-2019 Microchip Technology Inc.
NOTES:
2014-2019 Microchip Technology Inc. DS20005348B-page 57
MCP3912
8.0 MCP3912 INTERNAL
REGISTERS
The addresses associated with the internal registers
are listed in Table 8-1. This section also describes the
registers in detail. All registers are 24-bit long registers,
which can be addressed and read separately.
The format of the data registers (0x00 to 0x03) can be
changed with the WIDTH_DATA[1:0] bits in the
STATUSCOM register. The READ[1:0] and WRITE bits
define the groups and types of registers for continuous
read/write communication or looping on address sets,
as shown in Tab l e 8-2.
TABLE 8-1: MCP3912 REGISTER MAP
Address Name Bits R/W Description
0x00 CHANNEL0 24 R Channel 0 ADC Data[23:0], MSB First
0x01 CHANNEL1 24 R Channel 1 ADC Data[23:0], MSB First
0x02 CHANNEL2 24 R Channel 2 ADC Data[23:0], MSB First
0x03 CHANNEL3 24 R Channel 3 ADC Data[23:0], MSB First
0x04 Unused 24 U Unused
0x05 Unused 24 U Unused
0x06 Unused 24 U Unused
0x07 Unused 24 U Unused
0x08 MOD 24 R/W Delta-Sigma Modulators Output Value
0x09 Unused 24 R/W Unused
0x0A PHASE 24 R/W Phase Delay Configuration Register – Channel Pairs 0/1 and 2/3
0x0B GAIN 24 R/W Gain Configuration Register
0x0C STATUSCOM 24 R/W Status and Communication Register
0x0D CONFIG0 24 R/W Configuration Register
0x0E CONFIG1 24 R/W Configuration Register
0x0F OFFCAL_CH0 24 R/W Offset Correction Register – Channel 0
0x10 GAINCAL_CH0 24 R/W Gain Correction Register – Channel 0
0x11 OFFCAL_CH1 24 R/W Offset Correction Register – Channel 1
0x12 GAINCAL_CH1 24 R/W Gain Correction Register – Channel 1
0x13 OFFCAL_CH2 24 R/W Offset Correction Register – Channel 2
0x14 GAINCAL_CH2 24 R/W Gain Correction Register – Channel 2
0x15 OFFCAL_CH3 24 R/W Offset Correction Register – Channel 3
0x16 GAINCAL_CH3 24 R/W Gain Correction Register – Channel 3
0x17 Unused 24 U Unused
0x18 Unused 24 U Unused
0x19 Unused 24 U Unused
0x1A Unused 24 U Unused
0x1B Unused 24 U Unused
0x1C Unused 24 U Unused
0x1D Unused 24 U Unused
0x1E Unused 24 U Unused
0x1F LOCK/CRC 24 R/W Security Register (Password and CRC-16 on Register Map)
MCP3912
DS20005348B-page 58 2014-2019 Microchip Technology Inc.
TABLE 8-2: REGISTER MAP GROUPING FOR ALL CONTINUOUS READ/WRITE MODES
Function Address
READ[1:0] WRITE
= 11 = 10 = 01 = 00 = 1= 0
CHANNEL 0 0x00
LOOP ENTIRE REGISTER MAP
TYPE
GROUP Static
Not Writable
(Address undefined
for Write access)
Not Writable
(Address undefined
for Write access)
CHANNEL 1 0x01 Static
CHANNEL 2 0x02 GROUP Static
CHANNEL 3 0x03 Static
MOD 0x08
TYPE
GROUP Static
LOOP ONLY ON WRITABLE REGISTERS
Static
PHASE 0x0A Static Static
GAIN 0x0B Static Static
STATUSCOM 0x0C GROUP Static Static
CONFIG0 0x0D Static Static
CONFIG1 0x0E Static Static
OFFCAL_CH0 0x0F GROUP Static Static
GAINCAL_CH0 0x10 Static Static
OFFCAL_CH1 0x11 GROUP Static Static
GAINCAL_CH1 0x12 Static Static
OFFCAL_CH2 0x13 GROUP Static Static
GAINCAL_CH2 0x14 Static Static
OFFCAL_CH3 0x15 GROUP Static Static
GAINCAL_CH3 0x16 Static Static
LOCK/CRC 0x1F GROUP Static Static
2014-2019 Microchip Technology Inc. DS20005348B-page 59
MCP3912
8.1 CHANNEL Registers –
ADC Channel Data
Output Registers
The ADC Channel Data Output registers always
contain the most recent A/D conversion data for each
channel. These registers are read-only. They can be
accessed independently or linked together (with the
READ[1:0] bits). These registers are latched when an
ADC read communication occurs. When a data ready
event occurs during a read communication, the most
current ADC data are also latched to avoid data cor-
ruption issues. These registers are updated and
latched together if DR_LINK = 1, synchronously with
the data ready pulse (toggling on the most lagging
ADC channel data ready event).
Name Bits Address Cof.
CHANNEL0 24 0x00 R
CHANNEL1 24 0x01 R
CHANNEL2 24 0x02 R
CHANNEL3 24 0x03 R
REGISTER 8-1: MCP3912 CHANNEL REGISTERS
R-0 (MSB) R-0 R-0 R-0 R-0 R-0 R-0 R-0
DATA_CHn[23:16]
bit 23 bit 16
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
DATA_CHn[15:8]
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
DATA_CHn[7:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 23-0 DATA_CHn[23:0]: ADC Channel n Output Code bits
These data are post-calibration if the EN_OFFCAL or EN_GAINCAL bits are enabled. These data can
be formatted in 16-/24-/32-bit modes depending on the WIDTH_DATA[1:0] bits setting (see
Section 5.5 “ADC Output Coding”).
MCP3912
DS20005348B-page 60 2014-2019 Microchip Technology Inc.
8.2 MOD Register – Modulators
Output Register
The MOD register contains the most recent modulator
data output and is updated at a DMCLK rate. The
default value corresponds to an equivalent input of 0V
on all ADCs. Each bit in this register corresponds to
one comparator output on one of the channels. Do not
write to this register to ensure the accuracy of each
ADC.
Name Bits Address Cof.
MOD 24 0x08 R/W
REGISTER 8-2: MOD REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 23 bit 16
R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1 R/W-1
COMP3_CH3 COMP2_CH3 COMP1_CH3 COMP0_CH3 COMP3_CH2 COMP2_CH2 COMP1_CH2 COMP0_CH2
bit 15 bit 8
R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1 R/W-1
COMP3_CH1 COMP2_CH1 COMP1_CH1 COMP0_CH1 COMP3_CH0 COMP2_CH0 COMP1_CH0 COMP0_CH0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 23-16 Unimplemented: Read as ‘0’
bit 15-12 COMPn_CH3: Comparator Outputs from ADC Channel 3 bits
bit 11-8 COMPn_CH2: Comparator Outputs from ADC Channel 2 bits
bit 7-4 COMPn_CH1: Comparator Outputs from ADC Channel 1 bits
bit 3-0 COMPn_CH0: Comparator Outputs from ADC Channel 0 bits
2014-2019 Microchip Technology Inc. DS20005348B-page 61
MCP3912
8.3 PHASE Register – Phase
Configuration Register for
Channel Pairs 2/3 and 0/1
Any write to this register automatically resets and
restarts all active ADCs.
Name Bits Address Cof.
PHASE 24 0x0A R/W
REGISTER 8-3: PHASE REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PHASEB[11] PHASEB<10> PHASEB<9> PHASEB<8> PHASEB<7> PHASEB<6> PHASEB<5> PHASEB<4>
bit 23 bit 16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PHASEB[3] PHASEB<2] PHASEB<1] PHASEB<0] PHASEA<11] PHASEA<10] PHASEA<9] PHASEA<8]
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PHASEA[7] PHASEA<6] PHASEA<5] PHASEA<4] PHASEA<3] PHASEA<2] PHASEA<1] PHASEA<0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 23-12 PHASEB[11:0]: Phase Delay Between Channels CH2 and CH3 (reference) bits
Delay = PHASEB[11:0] decimal code/DMCLK.
bit 11-0 PHASEA[11:0]: Phase Delay Between Channels CH0 and CH1 (reference) bits
Delay = PHASEA[11:0] decimal code/DMCLK.
MCP3912
DS20005348B-page 62 2014-2019 Microchip Technology Inc.
8.4 GAIN Register – PGA Gain
Configuration Register
Name Bits Address Cof.
GAIN 24 0x0B R/W
REGISTER 8-4: GAIN REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 23 bit 16
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
———— PGA_CH3[2] PGA_CH3[1] PGA_CH3[0] PGA_CH2[2]
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PGA_CH2[1] PGA_CH2[0] PGA_CH1[2] PGA_CH1[1] PGA_CH1[0] PGA_CH0[2] PGA_CH0[1] PGA_CH0[0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 23-12 Unimplemented: Read as ‘0’
bit 11-0 PGA_CHn[2:0]: PGA Setting for Channel n bits
111 = Reserved (Gain = 1)
110 = Reserved (Gain = 1)
101 = Gain is 32
100 = Gain is 16
011 = Gain is 8
010 = Gain is 4
001 = Gain is 2
000 = Gain is 1 (default)
‘ DR_HIZ ‘
2014-2019 Microchip Technology Inc. DS20005348B-page 63
MCP3912
8.5 STATUSCOM Register – Status
and Communication Register
Name Bits Address Cof.
STATUSCOM 24 0x0C R/W
REGISTER 8-5: STATUSCOM REGISTER
R/W-1 R/W-0 R/W-1 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1
READ[1] READ[0] WRITE DR_HIZ DR_LINK WIDTH_ CRC WIDTH_ DATA[1] WIDTH_ DATA[0]
bit 23 bit 16
R/W-0 R/W-0 r-0 r-0 U-0 U-0 U-0 U-0
EN_CRCCOM EN_INT — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R-1 R-1 R-1 R-1
— — — — DRSTATUS[3] DRSTATUS[2] DRSTATUS[1] DRSTATUS[0]
bit 7 bit 0
Legend: r = Reserved bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 23-22 READ[1:0]: Address Counter Increment Setting for Read Communication bits
11 = Address counter auto-increments and loops on the entire register map
10 = Address counter auto-increments and loops on register TYPES (default)
01 = Address counter auto-increments and loops on register GROUPS
00 = Address is not incremented and continually reads the same single register address
bit 21 WRITE: Address Counter Increment Setting for Write Communication bit
1 = Address counter auto-increments and loops on writable part of the register map (default)
0 = Address is not incremented and continually writes to the same single register address
bit 20 DR_HIZ: Data Ready Pin Inactive State Control bit
1 = The DR pin state is a logic high when data are NOT ready
0 = The DR pin state is high-impedance when data are NOT ready (default)
bit 19 DR_LINK: Data Ready Link Control bit
1 = Data ready link enabled; only one pulse is generated on the DR pin for all ADC channels,
corresponding to the data ready pulse of the most lagging ADC (default)
0 = Data ready link disabled; each ADC produces its own data ready pulse on the DR pin
bit 18 WIDTH_CRC Format for CRC-16 on Communications bit
1 = 32-bit (CRC-16 code is followed by zeros); this coding is compatible with CRC implementation in
most 32-bit MCUs (including PIC32 MCUs)
0 = 16-bit (default)
bit 17-16 WIDTH_DATA[1:0]: ADC Data Format Settings for all ADCs bits
(see Section 5.5 “ADC Output Coding”)
11 = 32-bit with sign extension
10 = 32-bit with zeros padding
01 = 24-bit (default)
00 = 16-bit (with rounding)
MCP3912
DS20005348B-page 64 2014-2019 Microchip Technology Inc.
bit 15 EN_CRCCOM: CRC-16 Checksum on Serial Communications Enable bit
1 = CRC-16 checksum is provided at the end of each communication sequence (therefore, each com-
munication is longer); the CRC-16 message is the complete communication sequence (see
Section 6.9 “Securing Read Communications Through CRC-16 Checksum” for more details)
0 = Disabled (default)
bit 14 EN_INT: CRCREG Interrupt Function Enable bit
1 = The interrupt flag for the CRCREG checksum verification is enabled. The Data Ready pin (DR) will
become logic low and stays logic low if a CRCREG checksum error happens. This interrupt is
cleared if the LOCK[7:0] value is made equal to the password value (0xA5).
0 = The interrupt flag for the CRCREG checksum verification is disabled. The CRCREG[15:0] bits are
still calculated properly and can still be read in this mode. No interrupt is generated, even when a
CRCREG checksum error happens (default).
bit 13-12 Reserved: Keep equal to ‘0’ at all times
bit 11-4 Unimplemented: Read as ‘0’
bit 3-0 DRSTATUS[3:0]: Individual ADC Channel Data Ready Status bit
DRSTATUS[n] = 1 – Channel CHn data are not ready (default)
DRSTATUS[n] = 0 – Channel CHn data are ready. The status bit is set back to ‘1’ after reading the
STATUSCOM register. The status bit is not set back to ‘1’ by the read of the corresponding channel ADC data.
REGISTER 8-5: STATUSCOM REGISTER (CONTINUED)
2014-2019 Microchip Technology Inc. DS20005348B-page 65
MCP3912
8.6 CONFIG0 Register –
Configuration Register 0
Name Bits Address Cof.
CONFIG0 24 0x0D R/W
REGISTER 8-6: CONFIG0 REGISTER
R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0
EN_OFFCAL EN_GAINCAL DITHER[1] DITHER[0] BOOST[1] BOOST[0] PRE[1] PRE[0]
bit 23 bit 16
R/W-0 R/W-1 R/W-1 U-0 U-0 U-0 U-0 U-0
OSR[2] OSR[1] OSR[0] — — — — —
bit 15 bit 8
R/W-0 R/W-1 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0
VREFCAL[7] VREFCAL[6] VREFCAL[5] VREFCAL[4] VREFCAL[3] VREFCAL[2] VREFCAL[1] VREFCAL[0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 23 EN_OFFCAL: 24-Bit Digital Offset Error Calibration on All Channels Enable bit
1 = Enabled, this mode does not add any group delay to the ADC data
0 = Disabled (default)
bit 22 EN_GAINCAL: 24-Bit Digital Gain Error Calibration on All Channels Enable/Disable bit
1 = Enabled, this mode adds a group delay on all channels of 24 DMCLK periods; all data ready pulses
are delayed by 24 DMCLK clock periods compared to the mode with EN_GAINCAL = 0
0 = Disabled (default)
bit 21-20 DITHER[1:0]: Dithering Circuit for Idle Tone’s Cancellation and Improved THD on All Channels Control bits
11 = Dithering on, Strength = Maximum (default)
10 = Dithering on, Strength = Medium
01 = Dithering on, Strength = Minimum
00 = Dithering turned off
bit 19-18 BOOST[1:0]: Bias Current Selection for all ADCs bits
(impacts achievable maximum sampling speed, see Tab le 5 -2)
11 = All channels have current x 2
10 = All channels have current x 1 (default)
01 = All channels have current x 0.66
00 = All channels have current x 0.5
bit 17-16 PRE[1:0] Analog Master Clock (AMCLK) Prescaler Value bits
11 = AMCLK = MCLK/8
10 = AMCLK = MCLK/4
01 = AMCLK = MCLK/2
00 = AMCLK = MCLK (default)
MCP3912
DS20005348B-page 66 2014-2019 Microchip Technology Inc.
bit 15-13 OSR[2:0] Oversampling Ratio for Delta-Sigma A/D Conversion bits (all channels, fd/fS)
111 = 4096 (fd= 244 sps for MCLK = 4 MHz, fs=AMCLK=1MHz)
110 = 2048 (fd= 488 sps for MCLK = 4 MHz, fs=AMCLK=1MHz)
101 = 1024 (fd= 976 sps for MCLK = 4 MHz, fs=AMCLK=1MHz)
100 = 512 (fd= 1.953 ksps for MCLK = 4 MHz, fs= AMCLK = 1 MHz)
011 = 256 (fd= 3.90625 ksps for MCLK = 4 MHz, fs= AMCLK = 1 MHz) (default)
010 = 128 (fd= 7.8125 ksps for MCLK = 4 MHz, fs=AMCLK=1MHz)
001 = 64 (fd= 15.625 ksps for MCLK = 4 MHz, fs= AMCLK = 1 MHz)
000 = 32 (fd= 31.25 ksps for MCLK = 4 MHz, fs=AMCLK=1MHz)
bit 12-8 Unimplemented: Read as ‘0’
bit 7-0 VREFCAL[7:0]: Internal Voltage Temperature Coefficient VREFCAL[7:0] Value bits
See Section 5.6.3 “Temperature Compensation (VREFCAL[7:0])” for complete description.
REGISTER 8-6: CONFIG0 REGISTER (CONTINUED)
2014-2019 Microchip Technology Inc. DS20005348B-page 67
MCP3912
8.7 CONFIG1 Register –
Configuration Register 1
Name Bits Address Cof.
CONFIG1 24 0x0E R/W
REGISTER 8-7: CONFIG1 REGISTER
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — RESET[3] RESET[2] RESET[1] RESET[0]
bit 23 bit 16
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — SHUTDOWN[3] SHUTDOWN[2] SHUTDOWN[1] SHUTDOWN[0]
bit 15 bit 8
R/W-0 R/W-1 U-0 U-0 U-0 U-0 U-0 U-0
VREFEXT CLKEXT — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 23-20 Unimplemented: Read as ‘0’
bit 19-16 RESET[3:0]: Each Individual ADC Soft Reset Mode Setting bits
RESET[n] = 1: Channel CHn is in Soft Reset mode
RESET[n] = 0: Channel CHn is not in Soft Reset mode
bit 15-12 Unimplemented: Read as ‘0’
bit 11-8 SHUTDOWN[3:0]: Each Individual ADC Shutdown Mode Setting bits
SHUTDOWN[n] = 1: ADC Channel CHn is in Shutdown mode
SHUTDOWN[n] = 0: ADC Channel CHn is not in Shutdown mode
bit 7 VREFEXT: Internal Voltage Reference Selection bit
1 = Internal Voltage Reference Disabled: An external reference voltage needs to be applied across the
REFIN+/- pins; the analog power consumption (AIDD) is slightly diminished in this mode since the
internal voltage reference is placed into Shutdown mode
0 = Internal Reference Enabled: For optimal accuracy, the REFIN+/OUT pin needs proper decoupling
capacitors; REFIN- pin should be connected to AGND when in this mode
bit 6 CLKEXT: Internal Clock Selection bit
1 = MCLK is generated externally and should be provided on the OSC1 pin; the crystal oscillator is
disabled and consumes no current (default)
0 = Crystal oscillator is enabled; a crystal must be placed between OSC1 and OSC2 with proper decoupling
capacitors, the digital power consumption (DIDD) is increased in this mode due to the oscillator
bit 5-0 Unimplemented: Read as ‘0’
MCP3912
DS20005348B-page 68 2014-2019 Microchip Technology Inc.
8.8 OFFCAL_CHn and GAINCAL_CHn
Registers – Digital Offset and Gain
Error Calibration Registers
Name Bits Address Cof.
OFFCAL_CH0 24 0x0F R/W
GAINCAL_CH0 24 0x10 R/W
OFFCAL_CH1 24 0x11 R/W
GAINCAL_CH1 24 0x12 R/W
OFFCAL_CH2 24 0x13 R/W
GAINCAL_CH2 24 0x14 R/W
OFFCAL_CH3 24 0x15 R/W
GAINCAL_CH3 24 0x16 R/W
REGISTER 8-8: OFFCAL_CHn REGISTERS
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OFFCAL_CHn[23:16]
bit 23 bit 16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OFFCAL_CHn[15:8]
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OFFCAL_CHn[7:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 23-0 OFFCAL_CHn[23:0]: Corresponding Channel CHn Digital Offset Calibration Value bits
This register is simply added to the output code of the channel, bit-by-bit. This register is a 24-bit two’s
complement MSB first coding register. CHn Output Code = OFFCAL_CHn + ADC CHn Output Code.
This register is a Don’t Care if EN_OFFCAL = 0 (offset calibration disabled), but its value is not cleared
by the EN_OFFCAL bit.
2014-2019 Microchip Technology Inc. DS20005348B-page 69
MCP3912
REGISTER 8-9: GAINCAL_CHn REGISTERS
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GAINCAL_CHn[23:16]
bit 23 bit 16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GAINCAL_CHn[15:8]
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GAINCAL_CHn[7:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 23-0 GAINCAL_CHn[23:0]: Corresponding Channel CHn Digital Gain Error Calibration Value bits
This register is a 24-bit signed MSB first coding with a range of -1x to +0.9999999x (from 0x800000 to
0x7FFFFF). The gain calibration adds 1x to this register and multiplies it to the output code of the
channel, bit-by-bit, after offset calibration. The range of the gain calibration is thus from 0x to
1.9999999x (from 0x800000 to 0x7FFFFF). The LSB corresponds to a 2-23 increment in the multiplier.
CHn Output Code = (GAINCAL_CHn + 1) * ADC CHn Output Code. This register is a Don’t Care if
EN_GAINCAL = 0 (gain calibration disabled), but its value is not cleared by the EN_GAINCAL bit.
MCP3912
DS20005348B-page 70 2014-2019 Microchip Technology Inc.
8.9 SECURITY Register – Password
and CRC-16 on Register Map
Name Bits Address Cof.
LOCK/CRC 24 0x1F R/W
REGISTER 8-10: LOCK/CRC REGISTER
R/W-1 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1
LOCK[7:0]
bit 23 bit 16
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
CRCREG[15:8]
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
CRCREG[7:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 23-16 LOCK[7:0]: Lock Code for Writable Part of Register Map bits
LOCK[7:0] = Password = 0xA5 (default value): The entire register map is writable. The CRCREG[15:0]
bits and the CRC interrupt are cleared. No CRC-16 checksum on register map is calculated.
LOCK[7:0] Bits are Different than 0xA5: The only writable register is the LOCK/CRC register. All other
registers will appear as undefined while in this mode. The CRCREG checksum is calculated continu-
ously and can generate interrupts if the CRC interrupt EN_INT bit has been enabled. If a write to a
register needs to be performed, the user needs to unlock the register map beforehand by writing 0xA5
to the LOCK[7:0] bits.
bit 15-0 CRCREG[15:0]: CRC-16 Checksum Calculated with Writable Part of Register Map as a Message bits
This is a read-only 16-bit code. This checksum is continuously recalculated and updated every
16 DMCLK periods. It is reset to its default value (0x0000) when LOCK[7:0] = 0xA5.
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2014-2019 Microchip Technology Inc. DS20005348B-page 71
MCP3912
9.0 PACKAGING INFORMATION
9.1 Package Marking Information
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
3
e
3
e
28-Lead QFN (5x5x0.9 mm)
PIN 1
XXXXXXX
XXXXXXX
XXXXXXX
YYWWNNN
Example
PIN 1
MCP3912
A1
E/MQ
1930256
XXXXXXXXXXXX
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XXXXXXXXXXXX
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DS20005348B-page 72 2014-2019 Microchip Technology Inc.
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2014-2019 Microchip Technology Inc. DS20005348B-page 73
MCP3912
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DS20005348B-page 74 2014-2019 Microchip Technology Inc.
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2014-2019 Microchip Technology Inc. DS20005348B-page 75
MCP3912
B
A
0.10 C
0.10 C
0.10 C A B
0.05 C
(DATUM B)
(DATUM A)
NOTE 1
2X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
NOTE 1
1
2
N
0.10 C A B
0.10 C A B
0.10 C
0.08 C
Microchip Technology Drawing C04-140C Sheet 1 of 2
28-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5x0.9 mm Body [QFN or VQFN]
2X
28X
D
E
1
2
N
e
28X L
28X K
E2
D2
28X b
A3
A
C
SEATING
PLANE
A1
MCP3912
DS20005348B-page 76 2014-2019 Microchip Technology Inc.
Microchip Technology Drawing C04-140C Sheet 2 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
28-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5x0.9 mm Body [QFN or VQFN]
Dimension Limits
Units
D
Overall Width
Overall Length
Exposed Pad Length
Exposed Pad Width
Contact Thickness
D2
E2
E
3.35
MILLIMETERS
0.20 REF
MIN
A3
MAX
5.00 BSC
3.25
Contact Length
Contact Width
L
b
0.45
0.30
Notes:
1.
KContact-to-Exposed Pad 0.20
NOM
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
3.
2.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Standoff A1 0.02
Overall Height A 0.90
Pitch e0.50 BSC
Number of Pins N28
0.35
0.18
3.15
3.15
0.00
0.80
0.25
0.40
-
3.25
5.00 BSC
3.35
0.05
1.00
-
Pin 1 visual index feature may vary, but must be located within the hatched area.
Dimensioning and tolerancing per ASME Y14.5M.
Package is saw singulated.
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2014-2019 Microchip Technology Inc. DS20005348B-page 77
MCP3912
RECOMMENDED LAND PATTERN
28-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5x0.9 mm Body
Dimension Limits
Units
C1
Optional Center Pad Width
Contact Pad Spacing
Contact Pad Spacing
Optional Center Pad Length
Contact Pitch
C2
T2
W2
3.35
3.35
MILLIMETERS
0.50 BSC
MIN
E
MAX
4.90
4.90
Contact Pad Length (X28)
Contact Pad Width (X28)
Y1
X1
0.85
0.30
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
Microchip Technology Drawing No. C04-2140A
NOM
C1
C2 Y2
X2
Y1
G1
E
G1 0.35Contact Pad Length (X28)
SILK SCREEN
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
X1
[QFN or VQFN]
MCP3912
DS20005348B-page 78 2014-2019 Microchip Technology Inc.
NOTES:
2014-2019 Microchip Technology Inc. DS20005348B-page 80
MCP3912
NOTES:
PART No.
Xx
DE]
41x
2014-2019 Microchip Technology Inc. DS20005348B-page 81
MCP3912
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: MCP3912: Four-Channel Analog Front-End Converter
Address Options: XX A6 A5
A0 = 0 0
A1* = 0 1
A2 = 1 0
A3 = 1 1
* Default option. Contact Microchip factory for other address
options.
Tape and Reel Option: Blank = Standard packaging (tube or tray)
T = Tape and Reel(1)
Temperature Range: E = -40°C to +125°C
Package: MQ
SS
=
=
Plastic Quad Flat, No Lead Package (QFN)
Plastic Shrink Small Outline, 5.30 mm Body (SSOP)
Examples:
a) MCP3912A1-E/SS: Address Option A1,
Extended Temperature,
28-Lead SSOP package
b) MCP3912A1T-E/SS: Address Option A1,
Tape and Reel,
Extended Temperature,
28-Lead SSOP package
c) MCP3912A1-E/MQ: Address Option A1,
Extended Temperature,
28-Lead QFN package
d) MCP3912A1T-E/MQ: Address Option A1,
Tape and Reel,
Extended Temperature,
28-Lead QFN package
PART NO. X
Temperature
Range
Device
/XX
Package
[X](1)
Tape and
Reel
Note 1: Tape and Reel identifier only appears in the
catalog part number description. This identi-
fier is used for ordering purposes and is not
printed on the device package. Check with
your Microchip sales office for package
availability for the Tape and Reel option.
XX
Address
Option
2014-2019 Microchip Technology Inc. DS20005348B-page 82
MCP3912
NOTES:
YSTEM
2014-2019 Microchip Technology Inc. DS20005348B-page 83
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo,
CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo,
JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo,
SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity,
JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,
PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon,
QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O,
SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2019, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-4362-9
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
6‘
MICROCHIP
AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
DS20005348B-page 84 2014-2019 Microchip Technology Inc.
AMERICAS
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Austin, TX
Tel: 512-257-3370
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
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Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
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Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Novi, MI
Tel: 248-848-4000
Houston, TX
Tel: 281-894-5983
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Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Tel: 317-536-2380
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Tel: 949-462-9523
Fax: 949-462-9608
Tel: 951-273-7800
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Tel: 919-844-7510
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Tel: 631-435-6000
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Tel: 408-735-9110
Tel: 408-436-4270
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Tel: 905-695-1980
Fax: 905-695-2078
ASIA/PACIFIC
Australia - Sydney
Tel: 61-2-9868-6733
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Tel: 86-10-8569-7000
China - Chengdu
Tel: 86-28-8665-5511
China - Chongqing
Tel: 86-23-8980-9588
China - Dongguan
Tel: 86-769-8702-9880
China - Guangzhou
Tel: 86-20-8755-8029
China - Hangzhou
Tel: 86-571-8792-8115
China - Hong Kong SAR
Tel: 852-2943-5100
China - Nanjing
Tel: 86-25-8473-2460
China - Qingdao
Tel: 86-532-8502-7355
China - Shanghai
Tel: 86-21-3326-8000
China - Shenyang
Tel: 86-24-2334-2829
China - Shenzhen
Tel: 86-755-8864-2200
China - Suzhou
Tel: 86-186-6233-1526
China - Wuhan
Tel: 86-27-5980-5300
China - Xian
Tel: 86-29-8833-7252
China - Xiamen
Tel: 86-592-2388138
China - Zhuhai
Tel: 86-756-3210040
ASIA/PACIFIC
India - Bangalore
Tel: 91-80-3090-4444
India - New Delhi
Tel: 91-11-4160-8631
India - Pune
Tel: 91-20-4121-0141
Japan - Osaka
Tel: 81-6-6152-7160
Japan - Tokyo
Tel: 81-3-6880- 3770
Korea - Daegu
Tel: 82-53-744-4301
Korea - Seoul
Tel: 82-2-554-7200
Malaysia - Kuala Lumpur
Tel: 60-3-7651-7906
Malaysia - Penang
Tel: 60-4-227-8870
Philippines - Manila
Tel: 63-2-634-9065
Singapore
Tel: 65-6334-8870
Taiwan - Hsin Chu
Tel: 886-3-577-8366
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Taiwan - Taipei
Tel: 886-2-2508-8600
Thailand - Bangkok
Tel: 66-2-694-1351
Vietnam - Ho Chi Minh
Tel: 84-28-5448-2100
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
Finland - Espoo
Tel: 358-9-4520-820
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Garching
Tel: 49-8931-9700
Germany - Haan
Tel: 49-2129-3766400
Germany - Heilbronn
Tel: 49-7131-67-3636
Germany - Karlsruhe
Tel: 49-721-625370
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Germany - Rosenheim
Tel: 49-8031-354-560
Israel - Ra’anana
Tel: 972-9-744-7705
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Padova
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Norway - Trondheim
Tel: 47-7288-4388
Poland - Warsaw
Tel: 48-22-3325737
Romania - Bucharest
Tel: 40-21-407-87-50
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Gothenberg
Tel: 46-31-704-60-40
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Worldwide Sales and Service
08/15/18
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