PIC16(L)F170x Program Spec Datasheet by Microchip Technology

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6‘ ‘ MICRDCHIP P|C16(L)F170X MCLR e MCLR MCLR , MCLR MCLR MCLR MCLR MCLR MCLR
2013 Microchip Technology Inc. DS40001683B-page 1
PIC16(L)F170X
This document includes the
programming specifications for the
following devices:
1.0 OVERVIEW
The device can be programmed using either the high-
voltage In-Circuit Serial Programming™ (ICSP™)
method or the low-voltage ICSP method.
1.1 Hardware Requirements
1.1.1 HIGH-VOLTAGE ICSP
PROGRAMMING
In High-Voltage ICSP mode, the device requires two
programmable power supplies: one for VDD and one for
the MCLR/VPP pin.
1.1.2 LOW-VOLTAGE ICSP
PROGRAMMING
In Low-Voltage ICSP mode, the PIC16(L)F170X
devices can be programmed using a single VDD source
in the operating range. The MCLR/VPP pin does not
have to be brought to a different voltage, but can
instead be left at the normal operating voltage.
1.1.2.1 Single-Supply ICSP Programming
The LVP bit in Configuration Word 2 enables single-
supply (low-voltage) ICSP programming. The LVP bit
defaults to a ‘1’ (enabled) from the factory. The LVP bit
may only be programmed to ‘0’ by entering the High-
Voltage ICSP mode, where the MCLR/VPP pin is raised
to VIHH. Once the LVP bit is programmed to a ‘0’, only
the High-Voltage ICSP mode is available and only the
High-Voltage ICSP mode can be used to program the
device.
1.2 Pin Utilization
Five pins are needed for ICSP programming. The pins
are listed in Ta b l e 1 - 1 .
• PIC16F1703 • PIC16LF1703
• PIC16F1704 • PIC16LF1704
• PIC16F1705 • PIC16LF1705
• PIC16F1707 • PIC16LF1707
• PIC16F1708 • PIC16LF1708
• PIC16F1709 • PIC16LF1709
Note 1: The High-Voltage ICSP mode is always
available, regardless of the state of the
LVP bit, by applying VIHH to the MCLR/
VPP pin.
2: While in Low-Voltage ICSP mode, MCLR
is always enabled, regardless of the
MCLRE bit, and the port pin can no
longer be used as a general purpose
input.
TABLE 1-1: PIN DESCRIPTIONS DURING PROGRAMMING FOR PIC16(L)F170X
Pin Name
During Programming
Function Pin Type Pin Description
ICSPCLK ICSPCLK I Clock Input – Schmitt Trigger Input
ICSPDAT ICSPDAT I/O Data Input/Output – Schmitt Trigger Input
MCLR/VPP Program/Verify mode P(1) Program Mode Select/Programming Power Supply
VDD VDD P Power Supply
VSS VSS P Ground
Legend: I = Input, O = Output, P = Power
Note 1: The programming high voltage is internally generated. To activate the Program/Verify mode, high voltage
needs to be applied to MCLR input. Since the MCLR is used for a level source, MCLR does not draw any
significant current.
PIC16(L)F170X Memory Programming Specification
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PIC16(L)F170X
DS40001683B-page 2 2013 Microchip Technology Inc.
2.0 DEVICE PINOUTS
The pin diagrams for the PIC16(L)F170X family are
shown in Figure 2-1 to Figure 2-4. The pins that are
required for programming are listed in Table 1-1 and
shown in bold lettering in the pin diagrams.
FIGURE 2-1: 14-PIN DIAGRAM FOR PIC16(L)F1703/4/5
FIGURE 2-2: 16-PIN PACKAGE DIAGRAM FOR PIC16(L)F1703/4/5
PDIP, SOIC, TSSOP
PIC16(L)F1703/4/5
1
2
3
4
5
6
7
VDD
RA5
RA4
VPP/MCLR/RA3
RC5
RC4
RC3
RA0/ICSPDAT
RA1/ICSPCLK
RA2
RC0
RC1
RC2
14
13
12
11
10
9
8
VSS
2
3
1
9
10
11
12
RC4
4
VSS
RA0/ICSPDAT
RA1/ICSPCLK
RA2
RC0
NC
NC
VDD
RA5
RA4
RA3/MCLR/VPP
RC5
RC3
RC2
RC1
6758
151416 13
PIC16(L)F1703/4/5
QFN
_|:|:|:|:|:|:|:|:|:J v [[[EEEEEEE 19 17 m. 9. 5. 7. s.
2013 Microchip Technology Inc. DS40001683B-page 3
PIC16(L)F170X
FIGURE 2-3: 20-PIN PACKAGE DIAGRAM FOR PIC16(L)F1707/8/9
FIGURE 2-4: 20-PIN PACKAGE DIAGRAM FOR PIC16(L)F1707/8/9
PDIP, SOIC, SSOP
PIC16(L)F1707/8/9
2
3
4
5
6
7
8
9
10
VDD
RA5
RA4
VPP/MCLR/RA3
RC5
RC4
RC3
RC6
RC7
RB7
ICSPDAT/RA0
ICSPCLK/RA1
RA2
RC0
RC1
RC2
RB4
RB5
RB6
20
19
18
17
16
15
14
13
12
11
VSS
1
QFN
2
3
4
5
1
6789
20 19181716
10
12
13
14
15
11
PIC16(L)F1707/8/9
RB4
RB5
RB6
RB7
RC7
VPP/MCLR/RA3
RC5
RC4
RC3
RC6
RA4
RA5
VDD
VSS
RA0/ICSPDAT
RA1/ICSPCLK
RA2
RC0
RC1
RC2
PIC16(L)F170X
DS40001683B-page 4 2013 Microchip Technology Inc.
3.0 MEMORY MAP
The memory is broken into two sections: program
memory and configuration memory.
FIGURE 3-1: PIC16(L)F1703/7 PROGRAM MEMORY MAPPING
7FFF
h
8000
h
8200
h
FFFF
h
Implemented
2 KW
Implemented
07FF
h
Maps to
0-07FFh
Maps to
Program Memory
Configuration Memory
8000-81FF
User ID Location
User ID Location
User ID Location
User ID Location
Reserved
Revision ID
Device ID
Configuration Word 1
Configuration Word 2
Calibration Word 1
Calibration Word 2
Calibration Word 3
Calibration Word 4
Reserved
8000h
8001h
8002h
8003h
8004h
8005h
8006h
8007h
8009h
8008h
800Ah
0000h
800Bh
800Ch
800Dh-81FFh
2013 Microchip Technology Inc. DS40001683B-page 5
PIC16(L)F170X
FIGURE 3-2: PIC16(L)F1704/8 PROGRAM MEMORY MAPPING
7FFF
h
8000
h
8200
h
FFFF
h
Implemented
4 KW
Implemented
0FFF
h
Maps to
0-0FFFh
Maps to
Program Memory
Configuration Memory
8000-81FF
User ID Location
User ID Location
User ID Location
User ID Location
Reserved
Revision ID
Device ID
Configuration Word 1
Configuration Word 2
Calibration Word 1
Calibration Word 2
Calibration Word 3
Calibration Word 4
Reserved
Reserved
Calibration Word 5
Calibration Word 6
Reserved
8000h
8001h
8002h
8003h
8004h
8005h
8006h
8007h
8009h
8008h
800Ah
0000h
800Bh
800Ch
800Dh
800Eh
800Fh
8010h
8011h-81FFh
PIC16(L)F170X
DS40001683B-page 6 2013 Microchip Technology Inc.
FIGURE 3-3: PIC16(L)F1705/9 PROGRAM MEMORY MAPPING
7FFF
h
8000
h
8200
h
FFFF
h
Implemented
8 KW
Implemented
1FFF
h
Maps to
0-1FFFh
Maps to
Program Memory
Configuration Memory
8000-81FF
User ID Location
User ID Location
User ID Location
User ID Location
Reserved
Revision ID
Device ID
Configuration Word 1
Configuration Word 2
Calibration Word 1
Calibration Word 2
Calibration Word 3
Calibration Word 4
Reserved
Reserved
Calibration Word 5
Calibration Word 6
Reserved
8000h
8001h
8002h
8003h
8004h
8005h
8006h
8007h
8009h
8008h
800Ah
0000h
800Bh
800Ch
800Dh
800Eh
800Fh
8010h
8011h-81FFh
AB®
2013 Microchip Technology Inc. DS40001683B-page 7
PIC16(L)F170X
3.1 User ID Location
A user may store identification information (user ID) in
four designated locations. The user ID locations are
mapped to 8000h-8003h. Each location is 14 bits in
length. Code protection has no effect on these memory
locations. Each location may be read with code
protection enabled or disabled.
Note: MPLAB® IDE only displays the seven
Least Significant bits (LSb) of each user
ID location. The upper bits are not read. It
is recommended that only the seven LSbs
be used if MPLAB IDE is the primary tool
used to read these addresses.
PIC16(L)F170X
DS40001683B-page 8 2013 Microchip Technology Inc.
3.2 Device/Revision ID
The 14-bit device ID word is located at 8006h and the
14-bit revision ID is located at 8005h. These locations
are read-only and cannot be erased or modified.
REGISTER 3-1: DEVICEID: DEVICE ID REGISTER(1)
RRRRRR
DEV<13:8>
bit 13 bit 8
RRRRRRRR
DEV<7:0>
bit 7 bit 0
Legend:
x = Bit is unknown
R = Readable bit
‘0’ = Bit is cleared ‘1’ = Bit is set
bit 13-0 DEV<13:0>: Device ID bits
Refer to Tabl e 3 -1 to determine what these bits will read on which device. A value of 3FFFh is invalid.
Note 1: This location cannot be written.
REGISTER 3-2: REVISIONID: REVISION ID REGISTER(1)
RRRRRR
REV<13:8>
bit 13 bit 8
RRRRRRRR
REV<7:0>
bit 7 bit 0
Legend:
x = Bit is unknown
R = Readable bit
‘0’ = Bit is cleared ‘1’ = Bit is set
bit 13-0 REV<13:0>: Revision ID bits
These bits are used to identify the device revision.
Note 1: This location cannot be written.
2013 Microchip Technology Inc. DS40001683B-page 9
PIC16(L)F170X
TABLE 3-1: DEVICE ID VALUES (PIC16(L)F170X)
DEVICE Device ID Revision ID
PIC16F1703 3061h 2xxxh
PIC16LF1703 3063h 2xxxh
PIC16F1704 3043h 2xxxh
PIC16LF1704 3045h 2xxxh
PIC16F1705 3055h 2xxxh
PIC16LF1705 3057h 2xxxh
PIC16F1707 3060h 2xxxh
PIC16LF1707 3062h 2xxxh
PIC16F1708 3042h 2xxxh
PIC16LF1708 3044h 2xxxh
PIC16F1709 3054h 2xxxh
PIC16LF1709 3056h 2xxxh
CLKOUTEN CP PWRTE (3) MCLR If LVP bxl : (am If LVP m: D (on) MCLR/VPP pin funciion is MCLR MCLR/VPP pin funcfion is digita‘ input MCLR
PIC16(L)F170X
DS40001683B-page 10 2013 Microchip Technology Inc.
3.3 Configuration Words
The device has two Configuration Words, Configuration
Word 1 (8007h) and Configuration Word 2 (8008h). The
individual bits within these Configuration Words are
used to enable or disable device functions such as the
Brown-out Reset, code protection and Power-up Timer.
3.4 Calibration Words
The internal calibration values are factory calibrated
and stored in the Calibration Word locations. See
Figure 3-1 for address information.
The Calibration Words do not participate in erase
operations. The device can be erased without affecting
the Calibration Words.
REGISTER 3-3: CONFIGURATION WORD 1
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1
FCMEN IESO CLKOUTEN BOREN<1:0>
bit 13 bit 8
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1(3) R/P-1 R/P-1
CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared ‘1’ = Bit is set n = Value when blank or after Bulk Erase
bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit
1 = ON Fail-Safe Clock Monitor is enabled
0 = OFF Fail-Safe Clock Monitor is disabled
bit 12 IESO: Internal External Switchover bit
1 = ON Internal/External Switchover mode is enabled
0 = OFF Internal/External Switchover mode is disabled
bit 11 CLKOUTEN: Clock Out Enable bit
1 = OFF CLKOUT function is disabled. I/O or oscillator function on CLKOUT
0 = ON CLKOUT function is enabled on CLKOUT
bit 10-9 BOREN<1:0>: Brown-out Reset Enable bits(1)
11 = ON Brown-out Reset enabled
10 = SLEEP Brown-out Reset enabled during operation and disabled in Sleep
01 = SBODEN Brown-out Reset controlled by SBOREN bit of the BORCON register
00 = OFF Brown-out Reset disabled
bit 8 Unimplemented: Read as1
bit 7 CP: Code Protection bit(2)
1 = OFF Program memory code protection is disabled
0 = ON Program memory code protection is enabled
bit 6 MCLRE: MCLR/VPP Pin Function Select bit
If LVP bit = 1 (ON):
This bit is ignored.
If LVP bit = 0 (OFF):
1 = ON MCLR/VPP pin function is MCLR; Weak pull-up enabled.
0 = OFF MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control
of port pin’s WPU control bit.
bit 5 PWRTE: Power-up Timer Enable bit(1)
1 = OFF PWRT disabled
0 = ON PWRT enabled
Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.
2: The entire program memory will be erased when the code protection is turned off.
3: Bit 2 of Configuration Word 1 is unimplemented and reads ‘1’ on PIC16(L)F1703/7 devices.
2013 Microchip Technology Inc. DS40001683B-page 11
PIC16(L)F170X
bit 4-3 WDTE<1:0>: Watchdog Timer Enable bit
11 = ON WDT enabled
10 = SLEEP WDT enabled while running and disabled in Sleep
01 = SWDTEN WDT controlled by the SWDTEN bit in the WDTCON register
00 = OFF WDT disabled
bit 2-0 FOSC<2:0>: Oscillator Selection bits (PIC16(L)F1704/8 and PIC16(L)F1705/9)
111 = ECH External Clock, High-Power mode: CLKIN on OSC1/CLKIN
110 = ECM External Clock, Medium-Power mode: CLKIN on OSC1/CLKIN
101 = ECL External Clock, Low-Power mode: CLKIN on OSC1/CLKIN
100 = INTOSC Internal HFINTOSC, I/O function on OSC1/CLKIN
011 = EXTRC External RC oscillator, RC function on OSC1/CLKIN
010 = HS High-speed crystal/resonator on OSC2/CLKOUT pin and OSC1/CLKIN
001 = XT Crystal/resonator on OSC2/CLKOUT pin and OSC1/CLKIN
000 = LP Low-power crystal on OSC2/CLKOUT pin and OSC1/CLKIN
FOSC<1:0>(3): Oscillator Selection bits (PIC16(L)F1703/7)
11 = ECH External Clock, High-Power mode: CLKIN on OSC1/CLKIN
10 = ECM External Clock, Medium-Power mode: CLKIN on OSC1/CLKIN
01 = ECL External Clock, Low-Power mode: CLKIN on OSC1/CLKIN
00 = INTOSC Internal HFINTOSC, I/O function on OSC1/CLKIN
REGISTER 3-3: CONFIGURATION WORD 1 (CONTINUED)
Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.
2: The entire program memory will be erased when the code protection is turned off.
3: Bit 2 of Configuration Word 1 is unimplemented and reads ‘1’ on PIC16(L)F1703/7 devices.
DEBUG LPBOR
PIC16(L)F170X
DS40001683B-page 12 2013 Microchip Technology Inc.
REGISTER 3-4: CONFIGURATION WORD 2
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
LVP DEBUG LPBOR BORV STVREN PLLEN
bit 13 bit 8
R/P-1 U-1 U-1 U-1 U-1 R/P-1 R/P-1 R/P-1
ZCDDIS ———— PPS1WAY WRT<1:0>
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared ‘1’ = Bit is set n = Value when blank or after Bulk Erase
bit 13 LVP: Low-Voltage Programming Enable bit(1)
1 = ON Low-voltage programming enabled
0 = OFF MCLR/VPP must be used for programming high voltage
bit 12 DEBUG: In-Circuit Debugger Mode bit
1 = OFF In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins
0 = ON In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger
bit 11 LPBOR: Low-Power Brown-out Reset Enable bit
1 = OFF Low-Power Brown-out is disabled
0 = ON Low-Power Brown-out is enabled
bit 10 BORV: Brown-out Reset Voltage Selection bit(2)
1 = LOW Brown-out Reset voltage (Vbor), low trip point selected
0 = HIGH Brown-out Reset voltage (Vbor), high trip point selected
bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit
1 = ON Stack Overflow or Underflow will cause a Reset
0 = OFF Stack Overflow or Underflow will not cause a Reset
bit 8 PLLEN: PLL Enable bit
1 = ON 4xPLL enabled
0 = OFF 4xPLL disabled
bit 7 ZCDDIS: Zero-Cross Detect Disable bit
1 = ON Zero-cross detection is disabled on POR. Zero cross detection can be controlled by soft-
ware.
0 = OFF Zero-cross detection is always enabled. Software cannot disable zero cross detection.
bit 6-3 Unimplemented: Read as ‘1
bit 2 PPS1WAY: PPSLOCK One-Way Set Enable bit
1 = ON The PPSLOCK bit is permanently set after the first access sequence that sets it.
0 = OFF The PPSLOCK bit can be set and cleared as needed by the PPSLOCK access sequence.
Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.
2: See Vbor parameter for specific trip point voltages.
WRT<1:0>: Flash Memory SelfrWriIe P 2 kW Flash memom. PlClB L Fl703/7 4 kW Flash memom. PlClB L Fl704/8 8 kW Flash memom. PlClB L Fl705/9
2013 Microchip Technology Inc. DS40001683B-page 13
PIC16(L)F170X
bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits
2 kW Flash memory: (PIC16(L)F1703/7):
11 = OFF Write protection off
10 = BOOT 000h to 0FFh write-protected, 100h to 7FFh may be modified by PMCON control
01 = HALF 000h to 3FFh write-protected, 400h to 7FFh may be modified by PMCON control
00 = ALL 000h to 7FFh write-protected, no addresses may be modified by PMCON control
4 kW Flash memory: (PIC16(L)F1704/8):
11 = OFF Write protection off
10 = BOOT 000h to 1FFh write-protected, 200h to FFFh may be modified by PMCON control
01 = HALF 000h to 7FFh write-protected, 800h to FFFh may be modified by PMCON control
00 = ALL 000h to FFFh write-protected, no addresses may be modified by PMCON control
8 kW Flash memory: (PIC16(L)F1705/9)
11 = OFF Write protection off
10 = BOOT 0000h to 01FFh write-protected, 0200h to 1FFFh may be modified by PMCON
control
01 = HALF 0000h to 0FFFh write-protected, 1000h to 1FFFh may be modified by PMCON
control
00 = ALL 0000h to 1FFFh write-protected, no addresses may be modified by PMCON control
REGISTER 3-4: CONFIGURATION WORD 2 (CONTINUED)
Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.
2: See Vbor parameter for specific trip point voltages.
MCLR MCLR MCLR MCLR MCLR MCLR PWRTE MCLR
PIC16(L)F170X
DS40001683B-page 14 2013 Microchip Technology Inc.
4.0 PROGRAM/VERIFY MODE
In Program/Verify mode, the program memory and the
configuration memory can be accessed and
programmed in serial fashion. ICSPDAT and
ICSPCLK are used for the data and the clock,
respectively. All commands and data words are
transmitted LSb first. Data changes on the rising edge
of the ICSPCLK and is latched on the falling edge. In
Program/Verify mode, both the ICSPDAT and
ICSPCLK are Schmitt Trigger inputs. The sequence
that enters the device into Program/Verify mode
places all other logic into the Reset state. Upon
entering Program/Verify mode, all I/Os are
automatically configured as high-impedance inputs
and the address is cleared.
4.1 High-Voltage Program/Verify Mode
Entry and Exit
There are two different methods of entering Program/
Verify mode via high-voltage:
•VPP – First entry mode
•V
DD – First entry mode
4.1.1 VPP – FIRST ENTRY MODE
To enter Program/Verify mode via the VPP-first method,
the following sequence must be followed:
1. Hold ICSPCLK and ICSPDAT low. All other pins
should be unpowered.
2. Raise the voltage on MCLR from 0V to VIHH.
3. Raise the voltage on VDD from 0V to the desired
operating voltage.
The VPP-first entry prevents the device from executing
code prior to entering Program/Verify mode. For
example, when the Configuration Word has MCLR
disabled (MCLRE = 0), the power-up time is disabled
(PWRTE =0), the internal oscillator is selected
(FOSC =100), and RA0 and RA1 are driven by the user
application, the device will execute code. Since this
may prevent entry, VPP-first entry mode is strongly
recommended. See the timing diagram in Figure 8-2.
4.1.2 VDD – FIRST ENTRY MODE
To enter Program/Verify mode via the VDD-first method,
the following sequence must be followed:
1. Hold ICSPCLK and ICSPDAT low.
2. Raise the voltage on VDD from 0V to the desired
operating voltage.
3. Raise the voltage on MCLR from VDD or below
to VIHH.
The VDD-first method is useful when programming the
device when VDD is already applied, for it is not
necessary to disconnect VDD to enter Program/Verify
mode. See the timing diagram in Figure 8-1.
4.1.3 PROGRAM/VERIFY MODE EXIT
To exit Program/Verify mode take MCLR to VDD or
lower (VIL). See Figures 8-3 and 8-4.
4.2 Low-Voltage Programming (LVP)
Mode
The Low-Voltage Programming mode allows the
PIC16(L)F170X devices to be programmed using VDD
only, without high voltage. When the LVP bit of the
Configuration Word 2 register is set to ‘1’, the low-
voltage ICSP programming entry is enabled. To disable
the Low-Voltage ICSP mode, the LVP bit must be
programmed to ‘0’. This can only be done while in the
High-Voltage Entry mode.
Entry into the Low-Voltage ICSP Program/Verify mode
requires the following steps:
1. MCLR is brought to VIL.
2. A 32-bit key sequence is presented on
ICSPDAT, while clocking ICSPCLK.
The key sequence is a specific 32-bit pattern, '0100
1101 0100 0011 0100 1000 0101 0000' (more
easily remembered as MCHP in ASCII). The device will
enter Program/Verify mode only if the sequence is
valid. The Least Significant bit of the Least Significant
nibble must be shifted in first.
Once the key sequence is complete, MCLR must be
held at VIL for as long as Program/Verify mode is to be
maintained.
For low-voltage programming timing, see Figures 8-8
and 8-9.
Exiting Program/Verify mode is done by no longer
driving MCLR to VIL. See Figures 8-8 and 8-9.
Note: To enter LVP mode, the LSb of the Least
Significant nibble must be shifted in first.
This differs from entering the key
sequence on other parts.
2013 Microchip Technology Inc. DS40001683B-page 15
PIC16(L)F170X
4.3 Program/Verify Commands
These devices implement 13 programming commands,
each six bits in length. The commands are summarized
in Table 4-1.
Commands that have data associated with them are
specified to have a minimum delay of TDLY between the
command and the data. After this delay, 16 clocks are
required to either clock in or clock out the 14-bit data
word. The first clock is for the Start bit and the last clock
is for the Stop bit.
TABLE 4-1: COMMAND MAPPING FOR PIC16(L)F170X
Command
Mapping Data/Note
Binary (MSb … LSb) Hex
Load Configuration x00000 00h 0, data (14), 0
Load Data For Program Memory x00010 02h 0, data (14), 0
Read Data From Program Memory x00100 04h 0, data (14), 0
Increment Address x00110 06h —
Reset Address x10110 16h —
Begin Internally Timed Programming x01000 08h —
Begin Externally Timed Programming x11000 18h —
End Externally Timed Programming x010100Ah —
Bulk Erase Program Memory x01001 09h Internally Timed
Row Erase Program Memory x10001 11h Internally Timed
PIC16(L)F170X
DS40001683B-page 16 2013 Microchip Technology Inc.
4.3.1 LOAD CONFIGURATION
The Load Configuration command is used to access
the configuration memory (User ID Locations,
Configuration Words, Calibration Words). The Load
Configuration command sets the address to 8000h and
loads the data latches with one word of data (see
Figure 4-1).
After issuing the Load Configuration command, use the
Increment Address command until the proper address
to be programmed is reached. The address is then
programmed by issuing either the Begin Internally
Timed Programming or Begin Externally Timed
Programming command.
The only way to get back to the program memory
(address 0) is to exit Program/Verify mode or issue the
Reset Address command after the configuration memory
has been accessed by the Load Configuration command.
FIGURE 4-1: LOAD CONFIGURATION
4.3.2 LOAD DATA FOR PROGRAM
MEMORY
The Load Data for Program Memory command is used to
load one 14-bit word into the data latches. The word
programs into program memory after the Begin Internally
Timed Programming or Begin Externally Timed
Programming command is issued (see Figure 4-2).
FIGURE 4-2: LOAD DATA FOR PROGRAM MEMORY
Note: Externally timed writes are not supported
for Configuration and Calibration bits. Any
externally timed write to the Configuration
or Calibration Word will have no effect on
the targeted word.
X00
LSb MSb 0
1234561
215 16
ICSPCLK
ICSPDAT 0000
TDLY
ICSPCLK
ICSPDAT
12345612 15 16
X00
LSb MSb 0
0100
TDLY
2013 Microchip Technology Inc. DS40001683B-page 17
PIC16(L)F170X
4.3.3 READ DATA FROM PROGRAM
MEMORY
The Read Data from Program Memory command will
transmit data bits out of the program memory map
currently accessed, starting with the second rising edge
of the clock input. The ICSPDAT pin will go into Output
mode on the first falling clock edge, and it will revert to
Input mode (high-impedance) after the 16th falling edge
of the clock. If the program memory is code-protected
(CP), the data will be read as zeros (see Figure 4-3).
FIGURE 4-3: READ DATA FROM PROGRAM MEMORY
4.3.4 INCREMENT ADDRESS
The address is incremented when this command is
received. It is not possible to decrement the address.
To reset this counter, the user must use the Reset
Address command or exit Program/Verify mode and
re-enter it.
If the address is incremented from address 7FFFh, it
will wrap-around to location 0000h. If the address is
incremented from FFFFh, it will wrap-around to location
8000h (see Figure 4-4).
FIGURE 4-4: INCREMENT ADDRESS
1 2 3 4 5 6 1 2 15 16
LSb MSb
TDLY
ICSPCLK
ICSPDAT
Input Input
Output
x
(from Programmer)
X
0
0010
ICSPDAT
(from device)
X
0
123 45612
ICSPCLK
ICSPDAT
011
3
XXX
TDLY
Next Command
0
Address + 1
Address
PIC16(L)F170X
DS40001683B-page 18 2013 Microchip Technology Inc.
4.3.5 RESET ADDRESS
The Reset Address command will reset the address to
0000h, regardless of the current value. The address is
used in program memory or the configuration memory
(see Figure 4-5).
FIGURE 4-5: RESET ADDRESS
4.3.6 BEGIN INTERNALLY TIMED
PROGRAMMING
A Load Configuration or Load Data for Program
Memory command must be given before every Begin
Programming command. Programming of the
addressed memory will begin after this command is
received. An internal timing mechanism executes the
write. The user must allow for the program cycle time,
TPINT, in order for the programming to complete.
The End Externally Timed Programming command is
not needed when the Begin Internally Timed
Programming is used to start the programming.
The program memory address that is being
programmed is not erased prior to being programmed
(see Figure 4-6).
FIGURE 4-6: BEGIN INTERNALLY TIMED PROGRAMMING
X
0
123 45612
ICSPCLK
ICSPDAT
011
3
XXX
TDLY
Next Command
1
0000h
N
Address
123 45612
ICSPCLK
ICSPDAT
3
TPINT
X
1
000XXX
0
Next Command
2013 Microchip Technology Inc. DS40001683B-page 19
PIC16(L)F170X
4.3.7 BEGIN EXTERNALLY TIMED
PROGRAMMING
A Load Configuration or Load Data for Program
Memory command must be given before every Begin
Programming command. Programming of the
addressed memory will begin after this command is
received. To complete the programming, the End
Externally Timed Programming command must be sent
in the specified time window defined by TPEXT (see
Figure 4-7).
Externally timed writes are not supported for
Configuration and Calibration bits. Any externally timed
write to the Configuration or Calibration Word will have
no effect on the targeted word.
FIGURE 4-7: BEGIN EXTERNALLY TIMED PROGRAMMING
4.3.8 END EXTERNALLY TIMED
PROGRAMMING
This command is required after a Begin Externally
Timed Programming command is given. This
command must be sent within the time window
specified by TPEXT after the Begin Externally Timed
Programming command is sent.
After sending the End Externally Timed Programming
command, an additional delay (TDIS) is required before
sending the next command. This delay is longer than
the delay ordinarily required between other commands
(see Figure 4-8).
FIGURE 4-8: END EXTERNALLY TIMED PROGRAMMING
X
10
123 4561
2
ICSPCLK
ICSPDAT 00 0110
End Externally Timed Programming
Command
TPEXT
3
123 4561
2
ICSPCLK
ICSPDAT
3
TDIS
X
1
010XXX
1
Next Command
PIC16(L)F170X
DS40001683B-page 20 2013 Microchip Technology Inc.
4.3.9 BULK ERASE PROGRAM MEMORY
The Bulk Erase Program Memory command performs
two different functions dependent on the current state
of the address.
A Bulk Erase Program Memory command should not
be issued when the address is greater than 8008h.
After receiving the Bulk Erase Program Memory
command, the erase will not complete until the time
interval, T
ERAB, has expired.
FIGURE 4-9: BULK ERASE PROGRAM MEMORY
4.3.10 ROW ERASE PROGRAM MEMORY
The Row Erase Program Memory command will erase
an individual row. Refer to Ta b l e 4 - 2 for row sizes of
specific devices and the PC bits used to address them.
If the program memory is code-protected, the Row
Erase Program Memory command will be ignored.
When the address is 8000h-8008h, the Row Erase
Program Memory command will only erase the user ID
locations regardless of the setting of the CP
Configuration bit.
After receiving the Row Erase Program Memory
command, the erase will not complete until the time
interval, T
ERAR, has expired (see Figure 4-10).
FIGURE 4-10: ROW ERASE PROGRAM MEMORY
Address 0000h-7FFFh:
Program Memory is erased
Configuration Words are erased
Address 8000h-8008h:
Program Memory is erased
Configuration Words are erased
User ID Locations are erased
Note: The code protection Configuration bit
(CP) has no effect on the Bulk Erase
Program Memory command.
123 4561
2
ICSPCLK
ICSPDAT
3
TERAB
X
1
100XXX
0
Next Command
12345612
ICSPCLK
ICSPDAT
3
TERAR
X
0
100XXX
1
Next Command
2013 Microchip Technology Inc. DS40001683B-page 21
PIC16(L)F170X
TABLE 4-2: PROGRAMMING ROW AND LATCH SIZES
Devices PC Erase Row Size
(Number of 14-bit Words)
Write Row Size
(Number of 14-bit Latches)
PIC16F1703
<15:5> 16 16
PIC16F1707
PIC16LF1703
PIC16LF1707
PIC16F1704
<15:5> 32 32
PIC16F1705
PIC16F1708
PIC16F1709
PIC16LF1704
PIC16LF1705
PIC16LF1708
PIC16LF1709
PIC16(L)F170X
DS40001683B-page 22 2013 Microchip Technology Inc.
5.0 PROGRAMMING ALGORITHMS
The devices use internal latches to temporarily store
the 14-bit words used for programming. Refer to
Table 4-2 for specific latch information. The data
latches allow the user to write the program words with
a single Begin Externally Timed Programming or Begin
Internally Timed Programming command. The Load
Program Data or the Load Configuration command is
used to load a single data latch. The data latch will hold
the data until the Begin Externally Timed Programming
or Begin Internally Timed Programming command is
given.
The data latches are aligned with the LSbs of the
address. The PS address bits indicated in Ta bl e 4 - 2 at
the time the Begin Externally Timed Programming or
Begin Internally Timed Programming command is
given will determine which memory row is written.
Writes cannot cross a physical row boundary. For
example, attempting to write from address 0002h-
0021h in a 32-latch device will result in data being
written to 0020h-003Fh.
If more than the maximum number of latches are
written without a Begin Externally Timed Programming
or Begin Internally Timed Programming command, the
data in the data latches will be overwritten. The
following figures show the recommended flowcharts for
programming.
2013 Microchip Technology Inc. DS40001683B-page 23
PIC16(L)F170X
FIGURE 5-1: DEVICE PROGRAM/VERIFY FLOWCHART
Done
Start
Bulk Erase
Device
Write User IDs
Enter
Programming Mode
Write Program
Memory(1)
Verify User IDs
Write Configuration
Words(2)
Verify Configuration
Words
Exit Programming
Mode
Verify Program
Memory
Note 1: See Figure 5-2.
2: See Figure 5-5.
PIC16(L)F170X
DS40001683B-page 24 2013 Microchip Technology Inc.
FIGURE 5-2: PROGRAM MEMORY FLOWCHART
Start
Read Data
Program Memory
Data Correct?
Report
Programming
Failure
All Locations
Done?
No
No
Increment
Address
Command
from
Bulk Erase
Program
Yes
Memory(1, 2)
Done
Yes
Note 1: This step is optional if the device has already been erased or has not been previously programmed.
2: If the device is code-protected or must be completely erased, then Bulk Erase the device per Figure 5-6.
3: See Figure 5-3 or Figure 5-4.
Program Cycle
(3)
2013 Microchip Technology Inc. DS40001683B-page 25
PIC16(L)F170X
FIGURE 5-3: ONE-WORD PROGRAM CYCLE
Begin
Programming
Wait TDIS
Load Data
for
Program Memory
Command
(Internally timed)
Begin
Programming
Wait TPEXT
Command
(Externally timed)
(1)
End
Programming
Wait TPINT
Program Cycle
Command
Note 1: Externally timed writes are not supported for Configuration and Calibration bits.
PIC16(L)F170X
DS40001683B-page 26 2013 Microchip Technology Inc.
FIGURE 5-4: MULTIPLE-WORD PROGRAM CYCLE
Begin
Programming
Wait TPINT
Load Data
for
Program Memory
Command
(Internally timed)
Wait TPEXT
End
Programming
Wait TDIS
Load Data
for
Program Memory
Increment
Address
Command
Load Data
for
Program Memory
Begin
Programming
Command
(Externally timed)
Latch 1
Latch 2
Latch 32
Increment
Address
Command
Program Cycle
Command
Yes Rep Address : 30mm Dara Currecw narw
2013 Microchip Technology Inc. DS40001683B-page 27
PIC16(L)F170X
FIGURE 5-5: CONFIGURATION MEMORY PROGRAM FLOWCHART
Start
Load
Configuration
Program Cycle(2)
Read Data
Memory Command
Data Correct? Report
Programming
Failure
Address =
8004h?
Data Correct?
Report
Programming
Failure
Yes
No
Yes
Yes
No
Increment
Address
Command
No Increment
Address
Command
Done
One-word
One-word
Program Cycle(2)
(Config. Word 1)
Increment
Address
Command
Increment
Address
Command
(User ID)
From Program
Read Data
Memory Command
From Program
Program
Bulk Erase
Memory(1)
Data Correct?
Report
Programming
Failure
Yes
No
One-word
Program Cycle(2)
(Config. Word 2)
Increment
Address
Command
Read Data
Memory Command
From Program
Note 1: This step is optional if the device is erased or not previously programmed.
2: See Figure 5-3.
C9
PIC16(L)F170X
DS40001683B-page 28 2013 Microchip Technology Inc.
FIGURE 5-6: ERASE FLOWCHART
Start
Load Configuration
Done
Bulk Erase
Program Memory
Note: This sequence does not erase the Calibration Words.
2013 Microchip Technology Inc. DS40001683B-page 29
PIC16(L)F170X
6.0 CODE PROTECTION
Code protection is controlled using the CP bit in
Configuration Word 1. When code protection is
enabled, all program memory locations (0000h-7FFFh)
read as ‘0. Further programming is disabled for the
program memory (0000h-7FFFh). Program memory
can still be programmed and read during program
execution.
The user ID locations and Configuration Words can be
programmed and read out regardless of the code
protection settings.
6.1 Program Memory
Code protection is enabled by programming the CP bit
in Configuration Word 1 register to0’.
The only way to disable code protection is to use the
Bulk Erase Program Memory command.
7.0 HEX FILE USAGE
In the hex file there are two bytes per program word
stored in the Intel® INHX32 hex format. Data is stored
LSB first, MSB second. Because there are two bytes
per word, the addresses in the hex file are 2x the
address in program memory. (Example: The
Configuration Word 1 is stored at 8007h. In the hex file
this will be referenced as 1000Eh-1000Fh).
7.1 Configuration Word
To allow portability of code, it is strongly recommended
that the programmer is able to read the Configuration
Words and user ID locations from the hex file. If the
Configuration Words information was not present in the
hex file, a simple warning message may be issued.
Similarly, while saving a hex file, Configuration Words
and user ID information should be included.
7.2 Device ID
If a device ID is present in the hex file at 1000Ch-
1000Dh (8006h on the part), the programmer should
verify the device ID against the value read from the
part. On a mismatch condition, the programmer should
generate a warning message.
7.3 Checksum Computation
The checksum is calculated by two different methods
dependent on the setting of the CP Configuration bit.
7.3.1 PROGRAM CODE PROTECTION
DISABLED
With the program code protection disabled, the
checksum is computed by reading the contents of the
PIC16(L)F170X program memory locations and adding
up the program memory data starting at address 0000h,
up to the maximum user addressable location (e.g.,
FFFh for the PIC16F1704). Any Carry bits exceeding 16
bits are ignored. Additionally, the relevant bits of the
Configuration Words are added to the checksum. All
unimplemented Configuration bits are masked to0’.
TABLE 7-1: CONFIGURATION WORD
MASK VALUES
Device Config. Word 1
Mask
Config. Word 2
Mask
PIC16F1703 0EFBh 3F87h
PIC16LF1703 0EFBh 3F87h
PIC16F1704 3EFFh 3F87h
PIC16LF1704 3EFFh 3F87h
PIC16F1705 3EFFh 3F87h
PIC16LF1705 3EFFh 3F87h
PIC16F1707 0EFBh 3F87h
PIC16LF1707 0EFBh 3F87h
PIC16F1708 3EFFh 3F87h
PIC16LF1708 3EFFh 3F87h
PIC16F1709 3EFFh 3F87h
PIC16LF1709 3EFFh 3F87h
PIC16(L)F170X
DS40001683B-page 30 2013 Microchip Technology Inc.
7.3.2 PROGRAM CODE PROTECTION
ENABLED
When the MPLAB IDE check box for Configure->ID
Memory...-> Use Unprotected Checksum is checked,
then the 16-bit checksum of the equivalent
unprotected device is computed and stored in the user
ID. Each nibble of the unprotected checksum is stored
in the Least Significant nibble of each of the four user
ID locations. The Most Significant checksum nibble is
stored in the user ID at location 8000h, the second
Most Significant nibble is stored at location 8001h, and
so forth for the remaining nibbles and ID locations.
The protected checksums in Ta b l e 7 - 2 assume that
the Use Unprotected Checksum box is checked.
The checksum of a code-protected device is computed
in the following manner: the Least Significant nibble of
each user ID is used to create a 16-bit value. The Least
Significant nibble of user ID location 8000h is the Most
Significant nibble of the 16-bit value. The Least
Significant nibble of user ID location 8001h is the
second Most Significant nibble, and so forth for the
remaining user IDs and 16-bit value nibbles. The
resulting 16-bit value is summed with the Configuration
Words. All unimplemented Configuration bits are
masked to0’.
TABLE 7-2: CHECKSUMS
Device
Config1 Config2 Checksum
Unprotected Protected Mask Word Mask
Unprotected Code-protected
Blank
00AAh
First and
Last
Blank
00AAh
First and
Last
PIC16F1703 3FFFh 3F7Fh 0EFBh 3FFFh 3F87h 4682h C7D8h 9484h 15DAh
PIC16F1704 3FFFh 3F7Fh 3EFFh 3FFFh 3F87h 6E86h EFDCh EC8Ch 6DE2h
PIC16F1705 3FFFh 3F7Fh 3EFFh 3FFFh 3F87h 5E86h DFDCh DC8Ch 5DE2h
PIC16F1707 3FFFh 3F7Fh 0EFBh 3FFFh 3F87h 4682h C7D8h 9484h 15DAh
PIC16F1708 3FFFh 3F7Fh 3EFFh 3FFFh 3F87h 6E86h EFDCh EC8Ch 6DE2h
PIC16F1709 3FFFh 3F7Fh 3EFFh 3FFFh 3F87h 5E86h DFDCh DC8Ch 5DE2h
PIC16LF1703 3FFFh 3F7Fh 0EFBh 3FFFh 3F87h 4682h C7D8h 9484h 15DAh
PIC16LF1704 3FFFh 3F7Fh 3EFFh 3FFFh 3F87h 6E86h EFDCh EC8Ch 6DE2h
PIC16LF1705 3FFFh 3F7Fh 3EFFh 3FFFh 3F87h 5E86h DFDCh DC8Ch 5DE2h
PIC16LF1707 3FFFh 3F7Fh 0EFBh 3FFFh 3F87h 4682h C7D8h 9484h 15DAh
PIC16LF1708 3FFFh 3F7Fh 3EFFh 3FFFh 3F87h 6E86h EFDCh EC8Ch 6DE2h
PIC16LF1709 3FFFh 3F7Fh 3EFFh 3FFFh 3F87h 5E86h DFDCh DC8Ch 5DE2h
Standard Operating Cund ons Programming Supply Voltages and Currents Suppiy Voltage FlCtELFWUX 1,30 3,50 V F c ; t6 MHz FlCtEFWUX 2,30 550 V F c ; t6 MHz V Read/Write and Raw Erase operations V 7 V V V Buik Erase operations 2.7 7 V V ICSFDAT eutput high Ievei V -0,7 I H = 3,5 mAi V = 5V ICSFDAT eutput iow Ievei v 5+0}; I H = a mAi V D : 5V Brown-nut Reset Voitage Programming Mode Entry and Exit Programing made entry setup time, ICSFCLK‘ Programing made entry mid time, ICSPCLK‘ Serial PrugramNeriiy T Ciock Low Pulse Width too 7 7 ns T Ciock High Fuise Width too 7 7 ns T Data in setup time before cleckt too 7 7 ns T Data in Wild time aflEl’C‘DCkv too 7 7 ns CiockT tn data out Valid (during a Ciocxt tn data law-impedance (during a Ciocxt tn data nigh-impedance (during a Nuts 1: Externaiiy timed writes are not supported lur Centiguratien and Caimratien nits.
2013 Microchip Technology Inc. DS40001683B-page 31
PIC16(L)F170X
8.0 ELECTRICAL SPECIFICATIONS
Refer to device specific data sheet for absolute
maximum ratings.
TABLE 8-1: AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE
AC/DC CHARACTERISTICS Standard Operating Conditions
Production tested at 25°C
Sym. Characteristics Min. Typ. Max. Units Conditions/Comments
Programming Supply Voltages and Currents
VDD
Supply Voltage
(VDDMIN(2), VDDMAX)
PIC16LF170X 1.80
2.70 3.60
3.60
V
V
FOSC 16 MHz
FOSC 32 MHz
PIC16F170X 2.30
2.70 5.50
5.50
V
V
FOSC 16 MHz
FOSC 32 MHz
VPEW Read/Write and Row Erase operations VDDMIN —VDDMAX V
VBE Bulk Erase operations 2.7 VDDMAX V
IDDI Current on VDD, Idle 1.0 mA
IDDP Current on VDD, Programming 3.0 mA
IPP
VPP
Current on MCLR/VPP 600 A
VIHH High voltage on MCLR/VPP for
Program/Verify mode entry 8.0 — 9.0 V
TVHHR MCLR rise time (VIL to VIHH) for
Program/Verify mode entry ——1.0s
I/O pins
VIH (ICSPCLK, ICSPDAT, MCLR/VPP) input high level 0.8 VDD —— V
VIL (ICSPCLK, ICSPDAT, MCLR/VPP) input low level 0.2 VDD V
VOH
ICSPDAT output high level VDD-0.7
VDD-0.7
VDD-0.7
—— V
IOH = 3.5 mA, VDD = 5V
IOH = 3 mA, VDD = 3.3V
IOH = 2 mA, VDD = 1.8V
VOL
ICSPDAT output low level
——
VSS+0.6
VSS+0.6
VSS+0.6
V
IOH = 8 mA, VDD = 5V
IOH = 6 mA, VDD = 3.3V
IOH = 3 mA, VDD = 1.8V
VBOR
Brown-out Reset Voltage:
BORV = 0 (high trip)
BORV = 1 (low trip)
2.70
2.40
1.90
V
V
V
PIC16(L)F170X
PIC16F170X
PIC16LF170X
Programming Mode Entry and Exit
TENTS Programing mode entry setup time: ICSPCLK,
ICSPDAT setup time before VDD or MCLR 100 — — ns
TENTH Programing mode entry hold time: ICSPCLK,
ICSPDAT hold time after VDD or MCLR 250 s
Serial Program/Verify
TCKL Clock Low Pulse Width 100 ns
TCKH Clock High Pulse Width 100 ns
TDS Data in setup time before clock100 ns
TDH Data in hold time after clock100 ns
TCO Clock to data out valid (during a
Read Data command) 0 — 80 ns
TLZD Clock to data low-impedance (during a
Read Data command) 0 — 80 ns
THZD Clock to data high-impedance (during a
Read Data command) 0 — 80 ns
Note 1: Externally timed writes are not supported for Configuration and Calibration bits.
2: Bulk-erased devices default to brown-out enabled. VDDMIN is 2.85 volts when performing low-voltage programming on a
bulk-erased device, to ensure that the device is not held in Brown-out Reset.
Standard Operating Cund Data mm not driven to nex: duck mum (de‘ay T Bu‘k Erase cycle “me 7 7 5 m5 7 7 m5 Tune de‘ay from program to compare T Tune de‘ay when exmng Program/Venvy mode 1 7 7 us Nate 1: Externany timed wnms are nm supponed for Cunhgurallon and Cahbratlon ms
PIC16(L)F170X
DS40001683B-page 32 2013 Microchip Technology Inc.
8.1 AC Timing Diagrams
FIGURE 8-1: PROGRAMMING MODE
ENTRY – VDD FIRST
FIGURE 8-2: PROGRAMMING MODE
ENTRY – VPP FIRST
FIGURE 8-3: PROGRAMMING MODE
EXIT – VPP LAST
FIGURE 8-4: PROGRAMMING MODE
EXIT – VDD LAST
TDLY
Data input not driven to next clock input (delay
required between command/data or command/
command)
1.0 s
TERAB Bulk Erase cycle time 5 ms
TERAR Row Erase cycle time 2.5 ms
TPINT Internally timed programming operation time
2.5
5
ms
ms
Program memory
Configuration Words
TPEXT Externally timed programming pulse 1.0 2.1 ms Note 1
TDIS Time delay from program to compare
(HV discharge time) 300 s
TEXIT Time delay when exiting Program/Verify mode 1 s
Note 1: Externally timed writes are not supported for Configuration and Calibration bits.
2: Bulk-erased devices default to brown-out enabled. VDDMIN is 2.85 volts when performing low-voltage programming on a
bulk-erased device, to ensure that the device is not held in Brown-out Reset.
TABLE 8-1: AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE
AC/DC CHARACTERISTICS Standard Operating Conditions
Production tested at 25°C
Sym. Characteristics Min. Typ. Max. Units Conditions/Comments
VPP
TENTH
VDD
TENTS
ICSPDAT
ICSPCLK
VIHH
VIL
TENTH
ICSPDAT
ICSPCLK
VDD
TENTS
VPP
VIHH
VIL
TEXIT
VPP
VDD
ICSPDAT
ICSPCLK
VIHH
VIL
TEXIT
VPP
VDD
ICSPDAT
ICSPCLK
VIHH
VIL
>‘47
2013 Microchip Technology Inc. DS40001683B-page 33
PIC16(L)F170X
FIGURE 8-5: CLOCK AND DATA
TIMING
FIGURE 8-6: WRITE COMMAND – PAYLOAD TIMING
FIGURE 8-7: READ COMMAND – PAYLOAD TIMING
as
ICSPCLK
TCKH TCKL
TDH
TDS
ICSPDAT
output
TCO
ICSPDAT
ICSPDAT
ICSPDAT
TLZD
THZD
input
as
from input
from output
to input
to output
1234561215 16
X0LSb MSb 0
TDLY
Command Next
Command
Payload
ICSPCLK
ICSPDAT
XXXXX
123 4561215 16
X
TDLY
Command Next
Command
Payload
ICSPCLK
ICSPDAT
XXXXX
(from Programmer)
LSb MSb 0
ICSPDAT
(from Device)
x
4 S) n I n if A \F W\ f /_$( / \ / \ ‘m - rflx—H—x _C$i
PIC16(L)F170X
DS40001683B-page 34 2013 Microchip Technology Inc.
FIGURE 8-8: LVP ENTRY (POWERING UP)
FIGURE 8-9: LVP ENTRY (POWERED)
TCKLTCKH
33 clocks
012... 31
TDH
TDS
TENTH
LSb of Pattern MSb of Pattern
VDD
MCLR
ICSPCLK
ICSPDAT
TENTS
TCKH TCKL
33 Clocks
Note 1: Sequence matching can start with no edge on MCLR first.
0 1 2 ... 31
TDH
TDS
TENTH
LSb of Pattern MSb of Pattern
VDD
MCLR
ICSPCLK
ICSPDAT
2013 Microchip Technology Inc. DS40001683B-page 35
PIC16(L)F170X
APPENDIX A: REVISION HISTORY
Revision A (02/2013)
Initial release of this document.
Revision B (06/2013)
Changed PIC16(L)F1704/8 to PIC16(L)F170x in the
document title; Added PIC16(L)F1703/7 and
PIC16(L)F1705/9 devices.
PIC16(L)F170X
DS40001683B-page 36 2013 Microchip Technology Inc.
NOTES:
YSTEM
2013 Microchip Technology Inc. DS40001683B-page 37
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
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PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
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Company are registered trademarks of Microchip Technology
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Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2013, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620772898
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
6‘ MICROCHIP AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
DS40001683B-page 38 2013 Microchip Technology Inc.
AMERICAS
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
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Web Address:
www.microchip.com
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Mississauga, Ontario,
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Tel: 905-673-0699
Fax: 905-673-6509
ASIA/PACIFIC
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Suites 3707-14, 37th Floor
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Tel: 61-2-9868-6733
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China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
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Tel: 86-28-8665-5511
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Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
ASIA/PACIFIC
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
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India - Pune
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Fax: 91-20-2566-1513
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Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
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Tel: 60-4-227-8870
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Tel: 44-118-921-5869
Fax: 44-118-921-5820
Worldwide Sales and Service
11/29/12

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