—
FAIRGHlI—D
—
SEM‘CUNDUDTURYM
mum mm
:Evm
r—’% w. cum/l
M mm m =2 m w ”.57 m
.6 ‘5 u n .2 u m Ix
. z x A 5 s 7 I a
immu mm m P5 » n WW um)
um] %_/ m
(m
mmm mm;
© 2002 Fairchild Semiconductor Corporation DS005897 www.fairchildsemi.com
October 1987
Revised May 2002
MM74C165 Parallel-Load 8-Bit Shift Register
MM74C165
Parallel-Load 8-Bit Shift Register
General Description
The MM74C165 functions as an 8-bit parallel-load, serial
shift register. Data is loaded into the register independent
of the state of the clock(s) when PARALLEL LOAD (PL) is
low. Shifting is inhibited as long as PL is low. Data is
sequentially shifted from complementary outputs, Q7 and
Q7, highest-order bit (P7) first. New serial data may be
entered via the SERIAL DATA (Ds) input. Serial shifting
occurs on the rising edge of CLOCK1 or CLOCK2. Clock
inputs may be used separately or together for combined
clocking from independent sources. Either clock input may
be used also as an active-low clock enable. To prevent
double-clocking when a clock input is used as an enable,
the enable must be changed to a high level (disabled) only
while the clock is HIGH.
Features
■Wide supply voltage range: 3V to 15V
■Guaranteed noise margin: 1V
■High noise immunity: 0.45 VCC (typ.)
■Low power TTL compatibility: fan out of 2 driving 74L
■Parallel loading independent of clock
■Dual clock inputs
■Fully static operation
Ordering Code:
Connection Diagram
Top View
Order Number Package Number Package Description
MM74165N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
ELDEKI 2
.5
men
Tug ‘
mino—
(m
-—Do—Do—>s/L
—>o—>m
s/Ic
MC
m I I I I I I I
muoLn an n m n D) n m m n n! ni—
(as)
,0 1 1 1 1 1 1 I
W n I: I: u l I s E
o o u u u u u
m .I .2 n p. u n n
Pun H mm
www.fairchildsemi.com 2
MM74C165
Block Diagrams
*Please look into Section 8, Appendix D for availability of various package types.
Truth Table
X = Don’t Care
H = VIN(1)
L = VIN(0)
↑ = Clock transition from VIN(0) to VIN(1)
P0 thru P7 = Data present (and loaded into) parallel inputs
Q0 thru Q6 = Internal flip-flop outputs
State Inputs Internal Outputs
PL Clock1 Clock2 Ds P0 thru P7 Q0 Q1 Q7 Q7
(as enable)
Parallel Load L X X X P0…P7 P0 P1 P7 P7
Enable H L L X X P0P1P7P7
Shift (with Ds) H ↑L H X H P0 P6 P6
Shift (with Ds) H ↑LLXLHP5P5
Hold (Disable) H ↑HXXLHP5P5
3 www.fairchildsemi.com
MM74C165
Absolute Maximum Ratings(Note 1)
Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Tempera-
ture Range” they are not meant to imply that the devices should be oper-
ated at these limits. The Electrical Characteristics table provides conditions
for actual device operation.
DC Electrical Characteristics
Min/Max limits apply across temperature range unless otherwise noted
Voltage at Any Pin −0.3V to VCC + 0.3V
Operating Temperature Range −55°C to +125°C
Storage Temperature Range −65°C to +150°C
Absolute Maximum VCC 18V
Power Dissipation
Dual-In-Line 700 mW
Small Outline 500 mW
Operating VCC Range 3V to 15V
Lead Temperature
(Soldering, 10 seconds) 260°C
Symbol Parameter Conditions Min Typ Max Units
CMOS TO CMOS
VIN(1) Logical “1” Input Voltage VCC = 5V 3.5 V
VCC = 10V 8.0
VIN(0) Logical “0” Input Voltage VCC = 5V 1.5 V
VCC = 10V 2.0
VOUT(1) Logical “1” Output Voltage VCC = 5V, IO = −10 µA4.5 V
VCC = 10V, IO = −10 µA9.0
VOUT(0) Logical “0” Output Voltage VCC = 5V, IO = +10 µA0.5
V
VCC = 10V, IO = +10 µA1.0
IIN(1) Logical “1” Input Current VCC = 15V, VIN = 15V 0.005 1.0 µA
IIN(0) Logical “0” Input Current VCC = 15V, VIN = 0V −1.0 −0.005 µA
ICC Supply Current VCC = 15V 0.05 300 µA
CMOS TO LPTTL INTERFACE
VIN(1) Logical “1” Input Voltage VCC = 4.75V VCC − 1.5 V
VIN(0) Logical “0” Input Voltage VCC = 4.75V 0.8 V
VOUT(1) Logical “1” Output Voltage VCC = 4.75V, IO = −360 µA2.4 V
VOUT(0) Logical “0” Output Voltage VCC = 4.75V, IO = 360 µA0.4V
OUTPUT DRIVE (See Family Characteristics Data Sheet) (short circuit current)
ISOURCE Output Source Current VCC = 5V −1.75 −3.3 mA
(P-Channel) TA = 25°C, VOUT = 0V
ISOURCE Output Source Current VCC = 10V −8.0 −15 mA
(P-Channel) TA = 25°C, VOUT = 0V
ISINK Output Sink Current VCC = 5V 1.75 3.6 mA
(N-Channel) TA = 25°C, VOUT = VCC
ISINK Output Sink Current VCC = 10V 8.0 16 mA
(N-Channel) TA = 25°C, VOUT = VCC
mom
Var:
\ 05v
(Asmmml/ g5 / ‘ T |
m , mm
Vrt
mom a s vm \
w
M(cwck)~
SEEM Vcc
mm. a 5 v“
(55} av—
kn '«mn
v —
cc
w W a 5 MW (m W
W7
-‘wumw
[EL LCAD v“
mm flaw“
m, W—
V ‘ um ‘ km
E:—
m 0.5%: W; /
rw
- um ¢
7 '05*
m 05er
W
_}
www.fairchildsemi.com 4
MM74C165
AC Electrical Characteristics (Note 2)
TA = 25°C, CL = 50 pF, unless otherwise noted
Note 2: AC Parameters are guaranteed by DC correlated testing.
Note 3: Capacitance is guaranteed by periodic testing.
Note 4: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics application note
AN-90.
Switching Time Waveform
Note A: The remaining six data and the serial input are LOW.
Note B: Prior to test, HIGH level data is loaded into the P7 input.
Symbol Parameter Conditions Min Typ Max Units
tpd0, tpd1 Propagation Delay Time to a Logical “0” or VCC = 5V 200 400 ns
Logical “1” from Clock or Load to Q or Q VCC = 10V 80 200
tpd0, tpd1 Propagation Delay Time to a Logical “0” or VCC = 5V 200 400 ns
Logical “1” from H to Q or Q VCC = 10V 80 200
tSClock Inhibit Set-up Time VCC = 5V 150 75 ns
VCC = 10V 60 30
tSSerial Input Set-up Time VCC = 5V 50 25 ns
VCC = 10V 30 15
tHSerial Input Hold Time VCC = 5V 50 0 ns
VCC = 10V 30 0
tSParallel Input Set-Up Time VCC = 5V 150 75 ns
VCC = 10V 60 30
tHParallel Input Hold Time VCC = 5V 50 0 ns
VCC = 10V 30 0
tWMinimum Clock Pulse Width VCC = 5V 70 200 ns
VCC = 10V 30 100
tWMinimum Load Pulse Width VCC = 5V 85 180 ns
VCC = 10V 30 90
fMAX Maximum Clock Frequency VCC = 5V 2.5 6 MHz
VCC = 10V 5 12
tr, tfMaximum Clock Rise and Fall Time VCC = 5V 10 µs
VCC = 10V 5
CIN Input Capacitance (Note 3) 5 pF
CPD Power Dissipation Capacitance (Note 4) 65 pF
cmcm I I I I I I I I I I I
cum
(AS Emmi) _l INDI—
l
05
H U
m
m r
a:
mu m r
as
dedd
52
—|
own 07
OUYFUI 0—7
L. _.
mm)
5 www.fairchildsemi.com
MM74C165
Logic Waveform
om 130 am
(man—19,31) +1 *W
INDEX
Am“
momma
(—5‘35umsll
mu no. I FIN NOV ‘
mm! mmmmmmmw mm!
oPmN m 0mm n2 M5
M ovnan BTW 0,300 mm (Last)
‘ (mnzmm) ’1 rum“? /'\ mom m!“ i
. | \ \
nus mo
(3633- JIBO) i \ f
1 saw m m
a p
3° ' m H mu (ma-om)”
0.125- J50 mmmnls um)
. ‘ ‘ (0752:1351) MIN
0.100: ma (0315mm
(ovxsfiV-Povsw ow , 0 W (stpmso - ‘5 W (m r)
1 .z7nxn2w (mssfi‘dg‘afi)
m
www.fairchildsemi.com 6
MM74C165 Parallel-Load 8-Bit Shift Register
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
Products related to this Datasheet
IC SHIFT REGISTER 8BIT 16DIP