Si5350C-B Datasheet by Silicon Labs

$9 SILIEIJN LABS Si53SOC (10-MSOP) Si5350C (ZOQFN) 5mm vnpon cum cm vnooa CLKZ CLKA vDDoc CLKA chs vDDOD CLKS chv

Si5350C-B

FACTORY-PROGRAMMABLE ANY-FREQUENCY CMOS

CLOCK GENERATOR + PLL

Features

Applications

Description

The Si5350C generates free-running and/or synchronized clocks selectable on each

of its outputs. A dual PLL + high resolution MultiSynthTM fractional divider

architecture enables this user-definable custom timing device to generate any of the

specified output frequencies at any of its outputs. This allows the Si5350C to replace

a combination of crystals, crystal oscillators, and synchronized clocks (PLL). Custom

pin-controlled Si5350C devices can be requested using the ClockBuilder web-based

part number utility (www.silabs.com/ClockBuilder).

Functional Block Diagram

www.silabs.com/custom-timing

Generates up to 8 non-integer-related

frequencies from 2.5 kHz to 200 MHz

Exact frequency synthesis at each

output (0 ppm error)

Glitchless frequency changes

Low output period jitter: < 70 ps pp, typ

Configurable Spread Spectrum

selectable at each output

User-configurable control pins:

Output Enable (OEB_0/1/2)

Power Down (PDN)

Frequency Select (FS_0/1)

Spread Spectrum Enable (SSEN)

Loss of Lock Status (LOLB)

Supports static phase offset

Rise/fall time control

Operates from a low-cost, fixed

frequency crystal: 25 or 27 MHz

Separate voltage supply pins provide

level translation:

Core VDD: 1.8V, 2.5 V or 3.3 V

Output VDDO: 1.8 V, 2.5 V, or 3.3 V

Excellent PSRR eliminates external

power supply filtering

Very low power consumption (25 mA

core, typ)

Available in 2 packages types:

10-MSOP: 3 outputs

20-QFN (4x4 mm): 8 outputs

PCIE Gen 1 compliant

Supports HCSL compatible swing

HDTV, DVD/Blu-ray, set-top box

Audio/video equipment, gaming

Printers, scanners, projectors

Handheld instrumentation

Residential gateways

Networking/communication

Servers, storage

XO replacement

Ordering Information:

See Page 18

10-MSOP

20-QFN

($9 SILICON LABS

Si5350C-B

2 Rev. 1.1

Table 1. The Complete Si5350/51 Clock Generator Family

Part Number I2C or Pin Frequency Reference Programmed? Outputs Datasheet

Si5351A-B-GT I2C XTAL only Blank 3 Si5351-B

Si5351A-B-GM I2C XTAL only Blank 8 Si5351-B

Si5351B-B-GM I2C XTAL and/or Voltage Blank 8 Si5351-B

Si5351C-B-GM I2C XTAL and/or CLKIN Blank 8 Si5351-B

Si5351A-Bxxxxx-GT I2C XTAL only Factory Pre-Programmed 3 Si5351-B

Si5351A-Bxxxxx-GM I2C XTAL only Factory Pre-Programmed 8 Si5351-B

Si5351B-Bxxxxx-GM I2C XTAL and/or Voltage Factory Pre-Programmed 8 Si5351-B

Si5351C-Bxxxxx-GM I2C XTAL and/or CLKIN Factory Pre-Programmed 8 Si5351-B

Si5350A-Bxxxxx-GT Pin XTAL only Factory Pre-Programmed 3 Si5350A-B

Si5350A-Bxxxxx-GM Pin XTAL only Factory Pre-Programmed 8 Si5350A-B

Si5350B-Bxxxxx-GT Pin XTAL and/or Voltage Factory Pre-Programmed 3 Si5350B-B

Si5350B-Bxxxxx-GM Pin XTAL and/or Voltage Factory Pre-Programmed 8 Si5350B-B

Si5350C-Bxxxxx-GT Pin XTAL and/or CLKIN Factory Pre-Programmed 3 Si5350C-B

Si5350C-Bxxxxx-GM Pin XTAL and/or CLKIN Factory Pre-Programmed 8 Si5350C-B

Notes:

1. XTAL = 25/27 MHz, Voltage = 0 to VDD, CLKIN = 10 to 100 MHz. "xxxxx" = unique custom code.

2. Create custom, factory pre-programmed parts at www.silabs.com/ClockBuilder.

Section 659' SILIEIJN LABS

Si5350C-B

Rev. 1.1 3

TABLE OF CONTENTS

Section Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

2.1. Si5350C Replaces Multiple Clocks and XOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

2.2. Applying a Reference Clock at XTAL Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

2.3. HCSL Compatible Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

4. Configuring the Si5350C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

4.1. Crystal Inputs (XA, XB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

4.2. External Clock Input Pin (CLKIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

4.3. Output Clocks (CLK0–CLK7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

4.4. Programmable Control Pins (P0–P3) Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

4.5. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

5.1. 20-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

5.2. 10-pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

6. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

7.1. 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

7.2. 10-Pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

8. Land Pattern: 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

9. 10-pin MSOP Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

10. Land Pattern: 10-Pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

11. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

11.1. 20-Pin QFN Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

11.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

11.3. 10-Pin MSOP Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

11.4. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

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Si5350C-B

4 Rev. 1.1

1. Electrical Specifications

Table 2. Recommended Operating Conditions

Parameter Symbol Test Condition Min Typ Max Unit

Ambient Temperature TA–40 25 85 °C

Core Supply Voltage VDD

1.71 1.8 1.89 V

2.25 2.5 2.75 V

3.0 3.3 3.60 V

Output Buffer Voltage VDDOx

1.71 1.8 1.89 V

2.25 2.5 2.75 V

3.0 3.3 3.60 V

Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.

Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted. VDD

and VDDOx can be operated at independent voltages. Power supply sequencing for VDD and VDDOx requires that all

VDDOx be powered up either before or at the same time as VDD.

Table 3. DC Characteristics

(VDD = 1.8 V ±5%, 2.5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Core Supply Current* IDD

Enabled 3 outputs — 20 35 mA

Enabled 8 outputs — 25 45 mA

Power Down (PDN = VDD)——50µA

Output Buffer Supply

Current (Per Output)* IDDOx CL=5pF — 2.2 5.6 mA

Input Current IP1-P3 Pins P1, P2, P3

VP1-P3 <3.6V ——10 µA

IP0 Pin P0 — — 30 µA

Output Impedance ZOI 3.3 V VDDO, default high

drive. —50— 

*Note: Output clocks less than or equal to 100 MHz.

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Si5350C-B

Rev. 1.1 5

Table 4. AC Characteristics

(VDD = 1.8 V ±5%, 2.5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Power-Up Time TRDY

From VDD =V

DDmin to valid

output clock, CL=5pF,

fCLKn > 1 MHz —210ms

Powerup Time, PLL Bypass

Mode TBYP

From VDD =V

DDmin to valid

output clock, CL=5pF,

fCLKn >1MHz —0.5 1 ms

Output Enable Time TOE

From OEB assertion to valid

clock output, CL = 5 pF, fCLKn

> 1 MHz ——10µs

Output Frequency Transition

Time TFREQ fCLKn >1MHz — — 10 µs

Spread Spectrum Frequency

Deviation SSDEV Down Spread

Selectable in 0.1% steps –0.1 — –2.5 %

Spread Spectrum

Modulation Rate SSMOD_C 30 31.5 33 kHz

Table 5. Input Characteristics

(VDD = 1.8 V ±5%, 2.5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Units

Crystal Frequency fXTAL 25 — 27 MHz

P0-P3 Input Low Voltage VIL_P0-3 –0.1 — 0.3 x VDD V

P0-P3 Input High Voltage VIH_P0-3

VDD = 2.5 V or 3.3 V 0.7 x VDD —3.60V

VDD = 1.8 V 0.8 x VDD —3.60V

CLKIN Frequency Range fCLKIN 10 — 100 MHz

CLKIN Input Low Voltage VIL_CLKIN –0.1 — 0.3 x VDD V

CLKIN Input High Voltage VIH_CLKIN 0.7 x VDD —3.60V

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Si5350C-B

6 Rev. 1.1

Table 6. Output Characteristics

VDD = 1.8 V ±5%, 2.5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Units

Frequency Range1FCLK 0.0025 — 200 MHz

Load Capacitance CLFCLK < 100 MHz — — 15 pF

Duty Cycle DC

FCLK < 160 MHz, Measured

at VDD/2 45 50 55 %

FCLK > 160 MHz, Measured

at VDD/2 40 50 60 %

Rise/Fall Time tr/tf20%–80%, CL= 5 pF — 1 1.5 ns

Output High Voltage VOH CL=5pF VDD – 0.6 — — V

Output Low Voltage VOL ——0.6V

Period Jitter2,3 JPER 20-QFN, 4 outputs running,

1 per VDDO ‐40 95 ps,pk‐pk

10-MSOP or 20-QFN, all

outputs running ‐70 155 ps,pk‐pk

Cycle-to-cycle Jitter2,3 JCC 20-QFN, 4 outputs running,

1 per VDDO —5090ps, pk

10-MSOP or 20-QFN, all

outputs running — 70 150 ps, pk

Notes:

1. Only two unique frequencies above 112.5 MHz can be simultaneously output.

2. Measured over 10k cycles. Jitter is only specified at the default high drive strength (50  output impedance).

3. Jitter is highly dependent on device frequency configuration. Specifications represent a “worst case, real world”

frequency plan; actual performance may be substantially better. Three-output 10MSOP package measured with clock

outputs of 74.25, 24.576, and 48 MHz. Eight-output 20QFN package measured with clock outputs of 33.33, 74.25, 27,

24.576, 22.5792, 28.322, 125, and 48 MHz.

Table 7. 25 MHz Crystal Requirements1,2

Parameter Symbol Min Typ Max Unit

Crystal Frequency fXTAL —25—MHz

Load Capacitance CL6—12pF

Equivalent Series Resistance rESR ——150

Crystal Max Drive Level dL100 — — µW

Notes:

1. Crystals which require load capacitances of 6, 8, or 10 pF should use the device’s internal load capacitance for

optimum performance. See register 183 bits 7:6. A crystal with a 12 pF load capacitance requirement should use a

combination of the internal 10 pF load capacitance in addition to external 2 pF load capacitance (e.g., by using 4 pF

capacitors on XA and XB).

2. Refer to “AN551: Crystal Selection Guide” for more details.

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Si5350C-B

Rev. 1.1 7

Table 8. 27 MHz Crystal Requirements1,2

Parameter Symbol Min Typ Max Unit

Crystal Frequency fXTAL —27—MHz

Load Capacitance CL6—12pF

Equivalent Series Resistance rESR ——150

Crystal Max Drive Level dL100 — — µW

Notes:

1. Crystals which require load capacitances of 6, 8, or 10 pF should use the device’s internal load capacitance for

optimum performance. See register 183 bits 7:6. A crystal with a 12 pF load capacitance requirement should use a

combination of the internal 10 pF load capacitance in addition to external 2 pF load capacitance (e.g., by using 4 pF

capacitors on XA and XB).

2. Refer to “AN551: Crystal Selection Guide” for more details.

Table 9. Thermal Characteristics

Parameter Symbol Test Condition Package Value Unit

Thermal Resistance

Junction to Ambient JA Still Air 10-MSOP 131 °C/W

20-QFN 119 °C/W

Thermal Resistance

Junction to Case JC Still Air 20-QFN 16 °C/W

Table 10. Absolute Maximum Ratings

Parameter Symbol Test Condition Value Unit

DC Supply Voltage VDD_max –0.5 to 3.8 V

Input Voltage

VIN_P1-3 Pins P1, P2, P3 –0.5 to 3.8 V

VIN_P0 P0 –0.5 to (VDD+0.3) V

VIN_XA/B Pins XA, XB –0.5 to 1.3 V V

Junction Temperature TJ–55 to 150 °C

Note: Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be

restricted to the conditions specified in the operational sections of this data sheet. Exposure to absolute maximum

rating conditions for extended periods may affect device reliability.

/' V ‘\ K 125 mu 1mg El \ ~/' @ / \_ 24.57.; mm \ ,/' ($9 SILICON LABS

Si5350C-B

8 Rev. 1.1

2. Typical Application

2.1. Si5350C Replaces Multiple Clocks and XOs

The Si5350C is a clock generation device that provides both synchronous and free-running clocks for applications

where power, board size, and cost are critical. An example application is shown in Figure 1. Any other combination

is possible.

Figure 1. Replacing multiple XTAL/XOs and PLLs with one Si5350C

2.2. Applying a Reference Clock at XTAL Input

The Si5350C can be driven with a clock signal through the XA input pin. This is especially useful when in need of

generating clock outputs in two synchronization domains; one reference clock can be provided at the CLKIN pin

and at XA.

Figure 2. Si5350C Driven by a Clock Signal

Ethernet

PHY

USB

Controller

HDMI

Port

28.322 MHz

48 MHz

125 MHz

Video/Audio

Processor

74.25/1.001 MHz

24.576 MHz

OSC

CLK0

CLK1

CLK2

CLK3

CLK4

CLK5

PLL

Multi

Synth

Multi

Synth

Multi

Synth

74.25 MHz

CLKIN

27 MHz

Si5350C

Multi

Synth

Multi

Synth

Multi

Synth

54 MHz

Free-running

Clocks

Synchronous

Clocks

Multi

Synth

Multi

Synth

Multi

Synth

PLLB

PLLA

OSC

VIN = 1 VPP

25/27 MHz

Note: Float the XB input while driving

the XA input with a clock

0.1 µF

Si5350C-B

Rev. 1.1 9

2.3. HCSL Compatible Outputs

The Si5350C can be configured to support HCSL compatible swing when the VDDO of the output pair of interest is

set to 2.5 V (i.e., VDDOA must be 2.5 V when using CLK0/1; VDDOB must be 2.5 V for CLK2/3 and so on).

The circuit in the figure below must be applied to each of the two clocks used, and one of the clocks in the pair

must also be inverted to generate a differential pair.

Figure 3. Si5350C Output is HCSL Compatible

Multi

Synth

Multi

Synth

Multi

Synth

PLLB

PLLA

OSC

Note: The complementary -180 degree

out of phase output clock is generated

using the INV function

511 

240 R2

ZO = 50 

0 

HCSL

CLKIN

511 

240 R2

ZO = 50 

0 

Si5350C-B

10 Rev. 1.1

3. Functional Description

The architecture of the Si5350C generates up to eight non-integer-related frequencies in any combination of free-

running and/or synchronous clocks. A block diagram of both the 3-output and the 8-output versions are shown in

Figure 4. Free-running clocks are generated using the on-chip oscillator + PLL, and the clock input pin (CLKIN)

provides an external input reference for the synchronous clocks. Each MultiSynthTM is configurable with two

frequencies (F1_x, F2_x). This allows a pin controlled glitchless frequency change at each output (CLK0 to CLK5).

Figure 4. Block Diagrams of the Si5350C Devices with 3 and 8 outputs

10-MSOP

MultiSynth 3

F1_2

F2_2 R2

MultiSynth 2

VDD

GND

CLK2

F1_0

F2_0 R0

MultiSynth 0

F1_1

F2_1 R1

MultiSynth 1

CLK0

CLK1

VDDO

F1_3

F2_3 R3

MultiSynth 3

F1_2

F2_2 R2

MultiSynth 2

20-QFN

VDD

GND

CLK2

CLK3

VDDOB

Control

Logic

F1_0

F2_0 R0

MultiSynth 0

F1_1

F2_1 R1

MultiSynth 1

CLK0

CLK1

VDDOA

CLK6

CLK7

VDDOD

F1_4

F2_4 R4

MultiSynth 4

F1_5

F2_5 R5

MultiSynth 5

CLK4

CLK5

VDDOC

F1_6

MultiSynth 6

F1_7

MultiSynth 7

Control

Logic

PLL

OSC

CLKIN

PLL

OSC

CLKIN

PLL

, . SILIEDN LABS

Si5350C-B

Rev. 1.1 11

4. Configuring the Si5350C

The Si5350C is a factory-programmed custom clock generator that is user definable with a simple to use web-

based utility (www.silabs.com/ClockBuilder). The ClockBuilder utility provides a simple graphical interface that

allows the user to enter input and output frequencies along with other custom features as described in the following

sections. All synthesis calculations are automatically performed by ClockBuilder to ensure an optimum

configuration. A unique part number is assigned to each custom configuration.

4.1. Crystal Inputs (XA, XB)

The Si5350C uses an optional fixed-frequency non-pullable standard AT-cut crystal as a reference to generate

free-running output clocks. Note that a XTAL is not required for generating synchronous clocks that are locked to

CLKIN.

4.1.1. Crystal Frequency

The Si5350C can operate using either a 25 MHz or a 27 MHz crystal.

4.1.2. Internal XTAL Load Capacitors

Internal load capacitors are provided to eliminate the need for external components when connecting a XTAL to the

Si5350C. The total internal XTAL load capacitance (CL) can be selected to be 0, 6, 8 or 10 pF. XTALs with alternate

load capacitance requirements are supported using additional external load capacitance  2 pF (e.g., by using  4

pF capacitors on XA and XB) as shown in Figure 5.

Figure 5. External XTAL with Optional Load Capacitors

4.2. External Clock Input Pin (CLKIN)

The external clock input is used as a reference for generating synchronous clocks. The input frequency can be

specified from 10 to 100 MHz including fractional frequencies (e.g., 74.25 MHz x 1000/1001). The ClockBuilder

utility automatically determines the exact synthesis ratio to guarantee an output frequency with 0 ppm error with

respect to its reference.

4.3. Output Clocks (CLK0–CLK7)

The Si5350C is orderable as a 3-output (10-MSOP) or 8-output (20-QFN) clock generator. Output clocks CLK0 to

CLK5 can be ordered with two clock frequencies (F1_x, F2_x) which are selectable with the optional frequency

select pins (FS0/1). See “4.4.3. Frequency Select (FS_0, FS_1)” for more details on the operation of the frequency

select pins. Each output clock can select its reference for either of the PLLs.

4.3.1. Output Clock Frequency

Outputs can be configured at any frequency from 2.5 kHz up to 200 MHz. However, only two unique frequencies

above 112.5 MHz can be simultaneously output. For example, 125 MHz (CLK0), 130 MHz (CLK1), and 150 MHz

(CLKx) is not allowed. Note that multiple copies of frequencies above 112.5 MHz can be provided, for example,

125 MHz could be provided on four outputs (CLKS0-3) simultaneously with 130 MHz on four different outputs

(CLKS4-7).

Optional internal

load capacitance

0, 6, 8,10 pF

Optional additional

external load

capacitance

(< 2 pF)

SILICON LABS

Si5350C-B

12 Rev. 1.1

4.3.2. Spread Spectrum

Spread spectrum can be enabled on any of the clock outputs that use PLLA as its reference. Spread spectrum is

useful for reducing electromagnetic interference (EMI). Enabling spread spectrum on an output clock modulates its

frequency, which effectively reduces the overall amplitude of its radiated energy. Note that spread spectrum is not

available on clocks synchronized to PLLB.

The Si5350C supports several levels of spread spectrum allowing the designer to choose an ideal compromise

between system performance and EMI compliance. If the CLKIN pin already has spread spectrum applied to it, it

will get passed through to the outputs that are referenced to it. In this case, do not configure the synchronous

outputs for spread spectrum as the device will erroneously try to add additional spread to them.

An optional spread spectrum enable pin (SSEN) is configurable to enable or disable the spread spectrum feature.

See “4.4.1. Spread Spectrum Enable (SSEN)” for details.

Figure 6. Available Spread Spectrum Profiles

4.3.3. Invert/Non-Invert

By default, each of the output clocks are generated in phase (non-inverted) with respect to each other. An option to

invert any of the clock outputs is also available.

4.3.4. Output State When Disabled

There are up to three output enable pins configurable on the Si5350C as described in “4.4.4. Output Enable

(OEB_0, OEB_1, OEB_2)” . The output state when disabled for each of the outputs is configurable as output high,

output low, or high-impedance.

4.3.5. Powering Down Unused Outputs

Unused clock outputs can be completely powered down to conserve power.

4.4. Programmable Control Pins (P0–P3) Options

Up to four programmable control pins (P0-P3) are configurable allowing direct pin control of the following features:

4.4.1. Spread Spectrum Enable (SSEN)

An optional control pin allows disabling the spread spectrum feature for all outputs that were configured with

spread spectrum enabled. Hold SSEN low to disable spread spectrum. The SSEN pin provides a convenient

method of evaluating the effect of using spread spectrum clocks during EMI compliance testing.

4.4.2. Power Down (PDN)

An optional power down control pin allows a full shutdown of the Si5350C to minimize power consumption when its

output clocks are not being used. The Si5350C is in normal operation when the PDN pin is held low and is in power

down mode when held high. Power consumption when the device is in power down mode is indicated in Table 3 on

page 4.

4.4.3. Frequency Select (FS_0, FS_1)

The Si5350C offers the option of configuring up to two frequencies per clock output (CLK0-CLK5) for either free-

running or synchronous clocks. This is a useful feature for applications that need to support more than one free-

running or synchronous clock rate on the same output. An example of this is shown in Figure 7. The FS pins select

which frequency is generated from the clock output. In this example, FS0 selects the output frequency on CLK0

Reduced

Amplitude

and EMI

Down Spread

No Spread

Spectrum

Center

Frequency

Amplitude

, . SILIEDN LABS

Si5350C-B

Rev. 1.1 13

and FS1 selects the frequency on CLK1.

Figure 7. Example of Generating Two Clock Frequencies from the Same Clock Output

Up to two frequency select pins are available on the Si5350C. Each of the frequency select pins can be linked to

any of the clock outputs as shown in Figure 8. For example, FS_0 can be linked to control clock frequency

selection on CLK0, CLK3, and CLK5; FS_1 can be used to control clock frequency selection on CLK1, CLK2, and

CLK4. Any other combination is also possible. The frequency select feature is not available for CLKs 6 and 7.

The Si5350C uses control circuitry to ensure that frequency changes are glitchless. This ensures that the clock

always completes its last cycle before starting a new clock cycle of a different frequency.

Figure 8. Example Configuration of a Pin-Controlled Frequency Select (FS)

74.25 MHz or 74.25

1.001 MHz

27 MHz

XA XB

CLK0

FS0

Si5350C

Free-running Clock

FS1

CLKIN

24.576 MHz or 22.5792 MHz

CLK1

Synchronous Clock Video/Audio

Processor

Free-running Frequency

FS0

Bit Level

74.25 MHzF1_0:

F2_0: 74.25

1.001 MHz

Synchronous Frequency

FS1

Bit Level

24.576 MHzF1_1:

F2_1: 22.5792 MHz

54MHz

CLK0

CLK1

CLK2

CLK3

CLK4

CLK5

CLK6

CLK7

FS_0

FS_1

FS_0

F1_0, F1_3, F1_5

F2_0, F2_3, F2_5

Output Frequency

FS_1

F1_1, F1_2, F1_4

Output Frequency

CLKx

Frequency_A Frequency_B

Full cycle completes before

changing to a new frequency

Frequency_A

New frequency starts

at its leading edge

Glitchless Frequency Changes

Cannot be controlled

by FS pins

Customizable FS Control

F2_1, F2_2, F2_4

MultiSynth 0

MultiSynth 1

MultiSynth 2

MultiSynth 3

MultiSynth 4

MultiSynth 5

SILICON LABS

Si5350C-B

14 Rev. 1.1

4.4.4. Output Enable (OEB_0, OEB_1, OEB_2)

Up to three output enable pins (OEB_0/1/2) are available on the Si5350C. Similar to the FS pins, each OEB pin

can be linked to any of the output clocks. In the example shown in Figure 9, OEB_0 is linked to control CLK0,

CLK3, and CLK5; OEB_1 is linked to control CLK6 and CLK7, and OEB_2 is linked to control CLK1, CLK2, CLK4,

and CLK5. Any other combination is also possible. If more than one OEB pin is linked to the same CLK output, the

pin forcing a disable state will be dominant. Clock outputs are enabled when the OEB pin is held low.

The output enable control circuitry ensures glitchless operation by starting the output clock cycle on the first leading

edge after OEB is asserted (OEB = low). When OEB is released (OEB = high), the clock is allowed to complete its

full clock cycle before going into a disabled state. This is shown in Figure 9. When disabled, the output state is

configurable as disabled high, disabled low, or disabled in high-impedance.

Figure 9. Example Configuration of a Pin-Controlled Output Enable

4.4.5. Loss Of Lock (LOLB)

A loss of lock pin (LOLB) is available to indicate the status of the synchronous clock outputs. The LOLB pin is set to

a high state when the synchronous clock outputs are locked to the clock input (CLKIN). This is the normal

operating state for the synchronous clocks. The LOLB pin will go low when the reference clock at the CLKIN input

is removed or if its frequency deviates by more than 2000 ppm from its defined center frequency. In this case, the

synchronous clocks will continue to free-run. An option to disable the synchronous output clocks during an LOLB

condition (LOLB pin = low) is available. This only affects the clock outputs that were designated as synchronous

clock outputs. An external pull up resistor (recommended 10 kohms) is needed on LOLB as it is an open-drain

signal, not a push-pull output.

4.5. Design Considerations

The Si5350C is a self-contained clock generator that requires very few external components. The following general

guidelines are recommended to ensure optimum performance.

4.5.1. Power Supply Decoupling/Filtering

The Si5350C has built-in power supply filtering circuitry to help keep the number of external components to a

minimum. All that is recommended is one 0.1 to 1.0 µF decoupling capacitor per power supply pin. This capacitor

should be mounted as close to the VDD and VDDO pins as possible without using vias.

4.5.2. Power Supply Sequencing

The VDD and VDDOx (i.e., VDDO0, VDDO1, VDDO2, VDDO3) power supply pins have been separated to allow

flexibility in output signal levels. Power supply sequencing for VDD and VDDOx requires that all VDDOx be

powered up either before or at the same time as VDD. Unused VDDOx pins should be tied to VDD.

CLK0

CLK1

CLK2

CLK3

CLK4

CLK5

CLK6

CLK7

OEB_0

OEB_1

OEB_0

CLK Enabled

CLK Disabled

Output State

OEB_2

OEB_1

CLK Enabled

CLK Disabled

Output State

OEB_2

CLK Enabled

CLK Disabled

Output State

Clock continues until

cycle is complete

CLKx

OEBx

Clock starts on the

first leading edge

Glitchless Output Enable

Customizable OEB Control

OEB

, . SILIEDN LABS

Si5350C-B

Rev. 1.1 15

4.5.3. External Crystal

The external crystal should be mounted as close to the pins as possible using short PCB traces. The XA and XB

traces should be kept away from other high-speed signal traces. See “AN551: Crystal Selection Guide” for more

details.

4.5.4. External Crystal Load Capacitors

The Si5350C provides the option of using internal and external crystal load capacitors. If external load capacitors

are used, they should be placed as close to the XA/XB pads as possible. See “AN551: Crystal Selection Guide” for

more details.

4.5.5. Unused Pins

Unused control pins (P0–P3) should be tied to GND.

Unused CLKIN pin should be tied to GND.

Unused XA/XB pins should be left floating. Refer to "2.2. Applying a Reference Clock at XTAL Input" on page 8

when using XA as a clock input pin.

Unused output pins (CLK0–CLK7) should be left unconnected.

4.5.6. Trace Characteristics

The Si5350C features various output drive strength settings. It is recommended to configure the trace

characteristics as shown in Figure 10 when the default high output drive setting is used.

Figure 10. Recommended Trace Characteristics with Default Drive Strength Setting

ZO = 50 ohms

CLK

(Optional resistor for

EMI management)

R = 0 ohms

($9 SILICON LABS

Si5350C-B

16 Rev. 1.1

5. Pin Descriptions

5.1. 20-pin QFN

Figure 11. Si5350C 20-QFN Top View

Table 11. Si5350C 20-QFN Pin Descriptions

Pin Name Pin Number Pin Type Function

XA 1 I Input pin for external XTAL

XB 2 I Input pin for external XTAL

CLKIN 6 I External reference clock input

CLK0 13 O Output clock 0

CLK1 12 O Output clock 1

CLK2 9 O Output clock 2

CLK3 8 O Output clock 3

CLK4 19 O Output clock 4

CLK5 17 O Output clock 5

CLK6 16 O Output clock 6

CLK7 15 O Output clock 7

P0 3 I User configurable pin 0. See 4.5.5

P1 4 I User configurable pin 1. See 4.5.5

P2 5 I User configurable pin 2. See 4.5.5

P3 7 I User configurable pin 3. See 4.5.5

VDD 20 P Core voltage supply pin. See 4.5.2

VDDOA 11 P Output voltage supply pin for CLK0 and CLK1. See 4.5.2

VDDOB 10 P Output voltage supply pin for CLK2 and CLK3. See 4.5.2

VDDOC 18 P Output voltage supply pin for CLK4 and CLK5. See 4.5.2

VDDOD 14 P Output voltage supply pin for CLK6 and CLK7. See 4.5.2

GND Center Pad P Ground

Note: Pin Types: I = Input, O = Output, P = Power

GND

PAD

CLK3

CLK2

VDDOB

CLKIN

CLK6

CLK5

VDDOC

CLK4

VDD

VDDOA

CLK1

CLK0

VDDOD

CLK7

, . SILIEDN LABS

Si5350C-B

Rev. 1.1 17

5.2. 10-pin MSOP

Figure 12. Si5350C 10-MSOP Top View

Table 12. Si5350C 10-MSOP Pin Descriptions

Pin Name Pin Number Pin Type Function

XA 2 I Input pin for external XTAL

XB 3 I Input pin for external XTAL

CLKIN 5 I External reference clock input

CLK0 10 O Output clock 0

CLK1 9 O Output clock 1

CLK2 6 O Output clock 2

P0 4 I User configurable pin 0. See 4.5.5

VDD 1 P Core voltage supply pin. See 4.5.2

VDDO 7 P Output voltage supply pin for CLK0, CLK1, and CLK2. See 4.5.2

GND 8 P Ground

Note: Pin Types: I = Input, O = Output, P = Power

VDD

CLK1

CLK0

VDDO

GND

CLKIN 5CLK2

($9 SILICON LABS

Si5350C-B

18 Rev. 1.1

6. Ordering Information

Factory-programmed Si5350C devices can be requested using the ClockBuilder web-based utility available at:

www.silabs.com/ClockBuilder. A unique part number is assigned to each custom configuration as indicated in

Figure 13.

Figure 13. Custom Clock Part Numbers

Si5350C BXXXXX XXX

B = Product Revision B

XXXXX = Unique Custom Code. A five character code will be

assigned for each unique custom configuration

GT =10-MSOP

GM =2 0-QF N

Blank = Coil Tape

R = Tape and Reel

For evaluation of

Si5350C-Bxxxxx-GM (20 QFN)

Evaluation Boards

Si535x-B20QFN-EVB

WT i W ccecc w W U W H JﬁL’Lq U W H FiU‘ ““““““ W+ “““““““ m U W m‘Lr 33633 e 1333 A » E E E E E WV £ SILIEDN LABS

Si5350C-B

Rev. 1.1 19

7. Package Outline

7.1. 20-Pin QFN

Figure 14. 20-pin QFN Package Drawing

Seating Plane

D2/2

E2/2

($9 SILICON LABS

Si5350C-B

20 Rev. 1.1

Table 13. Package Dimensions

Dimension Min Nom Max

A 0.80 0.85 0.90

A1 0.00 — 0.05

b 0.20 0.25 0.30

D 4.00 BSC

D2 2.65 2.70 2.75

e 0.50 BSC

E 4.00 BSC

E2 2.65 2.70 2.75

L 0.35 0.40 0.45

aaa — — 0.10

bbb — — 0.10

ccc — — 0.08

ddd — — 0.10

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to JEDEC Outline MO-220, variation VGGD-5.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for

Small Body Components.

‘ i 7 ,7 + 77 7 [:1 i I 4 \ “an E—T ﬂ} I-Ill W A ' , x ‘ x I, , n , . SILIEDN LABS

Si5350C-B

Rev. 1.1 21

7.2. 10-Pin MSOP

Figure 15. 10-pin MSOP Package Drawing

Table 14. 10-MSOP Package Dimensions

Dimension Min Nom Max

A——1.10

A1 0.00 — 0.15

A2 0.75 0.85 0.95

b 0.17 — 0.33

c 0.08 — 0.23

D 3.00 BSC

E 4.90 BSC

E1 3.00 BSC

e 0.50 BSC

L 0.400.600.80

L2 0.25 BSC

q0—8

aaa — — 0.20

bbb — — 0.25

ccc — — 0.10

ddd — — 0.08

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to the JEDEC Solid State Outline MO-137, Variation C

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body

Components.



m —IUU

Si5350C-B

22 Rev. 1.1

8. Land Pattern: 20-Pin QFN

Figure 16 shows the recommended land pattern details for the Si5350 in a 20-Pin QFN package. Table 15 lists the

values for the dimensions shown in the illustration.

Figure 16. 20-Pin QFN Land Pattern

, . SILIEDN LABS

Si5350C-B

Rev. 1.1 23

Table 15. PCB Land Pattern Dimensions

Symbol Millimeters

C1 4.0

C2 4.0

E 0.50 BSC

X1 0.30

X2 2.70

Y1 0.80

Y2 2.70

Notes:

General

1. All dimensions shown are in millimeters

(mm) unless otherwise noted.

2. This land pattern design is based on IPC-

7351 guidelines.

Solder Mask Design

3. All metal pads are to be non-solder mask

defined (NSMD). Clearance between the

solder mask and the metal pad is to be

60 µm minimum, all the way around the pad.

Stencil Design

4. A stainless steel, laser-cut and electro-

polished stencil with trapezoidal walls should

be used to assure good solder paste release.

5. The stencil thickness should be 0.125 mm

(5 mils).

6. The ratio of stencil aperture to land pad size

should be 1:1 for all perimeter pads.

7. A 2x2 array of 1.10 x 1.10 mm openings on

1.30 mm pitch should be used for the center

ground pad.

Card Assembly

8. A No-Clean, Type-3 solder paste is

recommended.

9. The recommended card reflow profile is per

the JEDEC/IPC J-STD-020 specification for

Small Body components.

ID .—m—. Ev 5 WW E] 7 iii , [[1 i 77777777 [Ii 7, 1 WET I w ﬁgﬂgiw Ill-IEIII \EE \ET’IL 7 ($9 SILICON LABS

Si5350C-B

24 Rev. 1.1

9. 10-pin MSOP Package Outline

Figure 17 illustrates the package details for the Si5350C-B in a 10-pin MSOP package. Table 16 lists the values for

the dimensions shown in the illustration.

Figure 17. 10-pin MSOP Package Drawing



, . SILIEDN LABS

Si5350C-B

Rev. 1.1 25

Table 16. 10-MSOP Package Dimensions

Dimension Min Nom Max

A——1.10

A1 0.00 — 0.15

A2 0.75 0.85 0.95

b 0.17 — 0.33

c 0.08 — 0.23

D 3.00 BSC

E 4.90 BSC

E1 3.00 BSC

e 0.50 BSC

L 0.400.600.80

L2 0.25 BSC

q0—8

aaa — — 0.20

bbb — — 0.25

ccc — — 0.10

ddd — — 0.08

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to the JEDEC Solid State Outline MO-137, Variation C

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body

Components.

SSSSSSSSSSS

Si5350C-B

26 Rev. 1.1

10. Land Pattern: 10-Pin MSOP

Figure 18 shows the recommended land pattern details for the Si5350C-B in a 10-Pin MSOP package. Table 17

lists the values for the dimensions shown in the illustration.

Figure 18. 10-Pin MSOP Land Pattern



, . SILIEDN LABS

Si5350C-B

Rev. 1.1 27

Table 17. PCB Land Pattern Dimensions

Symbol Millimeters

Min Max

C1 4.40 REF

E 0.50 BSC

G1 3.00 —

X1 — 0.30

Y1 1.40 REF

Z1 — 5.80

Notes:

General

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ASME Y14.5M-1994.

3. This Land Pattern Design is based on the IPC-7351 guidelines.

4. All dimensions shown are at Maximum Material Condition (MMC). Least

Material Condition (LMC) is calculated based on a Fabrication

Allowance of 0.05mm.

Solder Mask Design

5. All metal pads are to be non-solder mask defined (NSMD). Clearance

between the solder mask and the metal pad is to be 60 µm minimum, all

the way around the pad.

Stencil Design

6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal

walls should be used to assure good solder paste release.

7. The stencil thickness should be 0.125 mm (5 mils).

8. The ratio of stencil aperture to land pad size should be 1:1.

Card Assembly

9. A No-Clean, Type-3 solder paste is recommended.

10. The recommended card reflow profile is per the JEDEC/IPC J-STD-

020C specification for Small Body components.

i TTTTTT O SSSSSSSSSSS

Si5350C-B

28 Rev. 1.1

11. Top Marking

11.1. 20-Pin QFN Top Marking

Figure 19. 20-Pin QFN Top Marking

11.2. Top Marking Explanation

Mark Method: Laser

Pin 1 Mark: Filled Circle = 0.50 mm Diameter

(Bottom-Left Corner)

Font Size: 0.60 mm (24 mils)

Line 1 Mark Format Device Part Number Si5350

Line 2 Mark Format: TTTTTT = Mfg Code* Manufacturing Code from the Assembly Purchase

Order Form.

Line 3 Mark Format: YY = Year

WW = Work Week Assigned by the Assembly House. Corresponds to

the year and work week of the assembly date.

*Note: The code shown in the “TTTTTT” line does not correspond to the orderable part number or frequency plan. It is used

for package assembly quality tracking purposes only.

TTTT

Si5350C-B

Rev. 1.1 29

11.3. 10-Pin MSOP Top Marking

Figure 20. 10-Pin MSOP Top Marking

11.4. Top Marking Explanation

Mark Method: Laser

Pin 1 Mark: Mold Dimple (Bottom-Left Corner)

Font Size: 0.60 mm (24 mils)

Line 1 Mark Format Device Part Number Si5350

Line 2 Mark Format: TTTT = Mfg Code* Line 2 from the “Markings” section of the Assembly

Purchase Order form.

Line 3 Mark Format: YWW = Date Code Assigned by the Assembly House.

Y = Last Digit of Current Year (Ex: 2013 = 3)

WW = Work Week of Assembly Date.

*Note: The code shown in the “TTTT” line does not correspond to the orderable part number or frequency plan. It is used for

package assembly quality tracking purposes only.

($9 SILIEEIN LABS

Si5350C-B

30 Rev. 1.1

DOCUMENT CHANGE LIST

Revision 0.75 to Revision 0.76

Updated Table 4 on page 5.

Updated spread-spectrum frequency deviation

parameter test condition and minimum spec value.

Updated “6. Ordering Information” .

Updated Figure 13, “Custom Clock Part Numbers,” on

page 18.

Revision 0.76 to Revision 1.0

Extended frequency range from 8 MHz-160 MHz to

2.5 kHz-200 MHz.

Added 1.8V VDD support.

Updated block diagrams for clarity.

Added complete Si5350/51 family table, Table 1.

Added top mark information.

Added landing pattern drawings.

Added PowerUp Time, PLL Bypass, Table 4.

Clarified Down Spread step sizes in Table 4.

Updated max jitter specs (typ unchanged) in Table 6.

Clarified power supply sequencing requirement,

Section 4.5.2.

Updated 4.4.5 Loss of Lock (LOLB) section.

Revision 1.0 to Revision 1.1

Updated "6. Ordering Information" on page 18.

Changed “Blank = Bulk” to “Blank = Coil Tape” in

Figure 13.

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