PL123S-05/09 Datasheet by Microchip Technology

EnlcﬂEL PL123S-05l-09 E j E j CLKA1 E j CLKAZ E j CLKAS CLKA4 5 E j . , . , .,2 E j ' ' E 3 >3 CLKB1 E 3 >14 CLKBZ E j E 3 >14 CLKBS . E 3 >14 CLKB4 g K j www mmrel com

PL123S-05/-09

Spread-Compatible Low Skew Zero Delay Buffer

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 94 4 -0800 • fax +1 (408) 474- 1000 • www.micrel.com Rev 12/14/11 Page 1

FEATURES

 Frequency Range 10MHz to 134 MHz

 Output Options:

o 5 outputs PL123S-05

o 9 outputs PL123S-09

 Zero input - output delay

 Optional Drive Strength:

Standard (8mA) PL123S-05/-09

High (12mA) PL123S-05H/-09H

 3.3V, ±10% operation

 Available in Commercial and Industrial temperature

ranges

 Available in 16-Pin SOP or TSSOP (PL123S-09),

and 8-Pin SOP (PL123S-05) packages

 Spread-compatible with spread-spectrum modula-

tion clock inputs

DESCRIPTION

The PL123S-05/-09 (-05H/-09H for High Drive) are high

performance, low skew, low jitter zero delay buffers

designed to distribute high speed clocks. They have

one (PL123S-05) or two (PL123S-09) low-skew output

banks, of 4 outputs each, that are synchronized with

the input. The PL123S-09 allows control of the banks

of outputs by using the S1 and S2 inputs as shown in

the Selector Definition table on page 2.

The synchronization is established via CLKOUT feed

back to the input of the PLL. Since the skew between

the input and output is less than 100ps, the device

acts as a zero delay buffer. The input output propaga-

tion delay can be advanced or delayed by adjusting the

load on the CLKOUT pin.

These parts are not intended for 5V input-tolerant ap-

plications.

BLOCK DIAGRAM

PLL

REF CLKOUT

CLKA1

CLKA2

CLKA3

CLKA4

Mux

CLKB1

CLKB2

CLKB3

CLKB4

S1

S2

1REF

CLKA1

CLKA2

VDD

CLKOUT

CLKA4

CLKA3

VDD

PL123S-09

GND

CLKB4

CLKB3

S1

10

11

12

13

14

15

16

98

7

6

5

4

3

2

S2

CLKB2

CLKB1

GND

Bank B Bank A

Selector

Inputs

(PL123S-09 Only)

1

2

3

4

REF

5

6

7

8

CLKA2

CLKA1

GND

CLKOUT

CLKA4

VDD

CLKA3

PL123S-05

Enllil L PL123S-05l-09 Buffered clock output. Internal feedback www mmre‘ com

PL123S-05/-09

Spread-Compatible Low Skew Zero Delay Buffer

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 94 4 -0800 • fax +1 (408) 474-1000 • www.micrel .com Rev 12/14/11 Page 2

PIN DESCRIPTIONS

Name

PL123S-09

PL123S-05

Type

Description

TSSOP-16L, SOP-16L

SOP-8L

REF[1 ]

1

I

Input reference frequency

CLKA1[2 ]

2

3

O

Buffered clock output, Bank A

CLKA2[2 ]

3

2

O

Buffered clock output, Bank A

VDD

4,13

6

P

VDD connection

GND

5,12

4

P

GND connection

CLKB1[2 ]

6

-

O

Buffered clock output, Bank B

CLKB2[2 ]

7

-

O

Buffered clock output, Bank B

S2[3 ]

8

-

I

Selector input

S1[3 ]

9

-

I

Selector input

CLKB3[2 ]

10

-

O

Buffered clock output, Bank B

CLKB4[2 ]

11

-

O

Buffered clock output, Bank B

CLKA3[2 ]

14

5

O

Buffered clock output, Bank A

CLKA4[2 ]

15

7

O

Buffered clock output, Bank A

CLKOUT[2 ]

16

8

O

Buffered clock output. Internal feedback

on this pin.

Notes: 1: Weak pull-down. 2: Weak pull-down on all outputs. 3: Weak Pull-Up on S1 and S2

SELECTOR DEFINITION FOR PL123S-09

S2

S1

CLOCK A1–A4

(Bank A)

CLOCK B1–B4

(Bank B)

CLKOUT

Output Source

PLL Shutdown

0

Three-state

Driven

PLL

N

0

1

Driven

Three-state

Driven

PLL

N

1

0

Driven

Reference

Y

1

Driven

PLL

N

INPUT / OUTPUT SKEW CONTROL

The PL123S-05/-09 will achieve Zero Delay from input to output when all the outputs are loaded equally . Adjust-

ments to the input/output delay can be made by adding additional loading to the CLKOUT pin.

Please contact Micrel for more information.

EHIEREL PL1238-05/-09 wwwwwwwwwwww

PL123S-05/-09

Spread-Compatible Low Skew Zero Delay Buffer

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 94 4 -0800 • fax +1 (408) 474-1000 • www.micrel .com Rev 12/14/11 Page 3

SPREAD COMPATIBLE

Many products today utilize spread-spectrum modulation clocking to reduce electromagnetic interference (EMI)

and pass FCC regulations. This product was designed to pass spread -spectrum input clock modulation frequen-

cies to the output. When a buffer is not designed to pass spread spectrum, there will exist significant tracking ji t-

ter between input and output clocks, which may result in problems with system timing and synchronization.

LAYOUT RECOMMENDATIONS

The following guidelines are to assist you with a performance optimized PCB design:

Signal Integrity and Termination

Considerations

- Keep traces short!

- Trace = Inductor. With a capacitive load this equals

ringing!

- Long trace = Transmission Line. Without proper termi-

nation this will cause reflections ( looks like ringing ).

- Design long traces as “striplines” or “microstrips” with

defined impedance.

- Match trace at one side to avoid reflections bounc ing

back and forth.

Decoupling and Power Supply

Considerations

- Place decoupling capacitors as close as possible

to the VDD pin(s) to limit noise from the power

supply

- Addition of a ferrite bead in series with VDD can

help prevent noise from other board sources

- Value of decoupling capacitor is frequency de-

pendant. Typical values to use are 0.1F for de-

signs using frequencies < 50MHz and 0.01F for

designs using frequencies > 50MHz.

Typical CMOS termination

Place Series Resistor as close as possible to CMOS output

CMOS Output Buffer

( Typical buffer impedance 20  To CMOS Input

50 line

Connect a 33 series

resistor at each of the output

clocks to enhance the

stability of the output signal

Enllil L PL123S-05l-09 Test Conditions Min. Max. Unit Io =8 mA IOL =12 mA IoH = —8 mA IOL = —12 mA 66.67MH2 thh un‘oaded outputs www mmre‘ com

PL123S-05/-09

Spread-Compatible Low Skew Zero Delay Buffer

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 94 4 -0800 • fax +1 (408) 474-1000 • www.micrel .com Rev 12/14/11 Page 4

ABSOLUTE MAXIMUM CONDITIONS

Supply Voltage to Ground Potential ...... –0.5V to 4.6V

DC Input Voltage ............................ VSS – 0.5V to 4.6V

Storage Temperature ..........................–65°C to 150°C

Junction Temperature………………………….. 150°C

Static Discharge Voltage

(per MIL-STD-883, Method 3015)…………..> 2000V

OPERATING CONDITIONS

Parameter

Description

Min.

Max.

Unit

VDD

Supply Voltage

3.0

3.6

V

TA

Commercial Operating Temperature (ambient temperature)

0

70

C

Industrial Operating Temperature (ambient te mperature)

-40

85

C

CL

Load Capacitance, below 100 MHz

―

30

pF

Load Capacitance, above 100 MHz

―

10

pF

CIN

Input Capacitance

―

7

pF

tPU

Power-up time for all VDDs to reach minimum specified voltage

(power ramps must be monotonic)

0.05

250

ms

ELECTRICAL CHARACTERISTICS

Parameter

Description

Test Conditions

Min.

Max.

Unit

VIL

Input LOW Voltage

–

0.8

V

VIH

Input HIGH Voltage

2.5

–

V

IIL

Input LOW Current

VIN = 0V

–

50

µA

IIH

Input HIGH Current

VIN = VDD

–

100

µA

VOL

Output LOW Voltage[4]

IOL = 8 mA

IOL = 12 mA

–

0.4

V

VOH

Output HIGH Voltage[4]

IOH = –8 mA

IOL = –12 mA

2.4

–

V

IDD

Supply Current

(Unloaded Outputs)

66.67MHz with unloaded outputs

Commercial Temp.

–

32

mA

66.67MHz with unloaded outputs

Industrial Temp.

–

45

mA

Notes: 4. Parameter is guaranteed by design and characterization. Not 100% tested in production .

EnlcﬂEL PL123S-05l-09 wwwwwwwwwwww

PL123S-05/-09

Spread-Compatible Low Skew Zero Delay Buffer

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 94 4 -0800 • fax +1 (408) 474-1000 • www.micrel .com Rev 12/14/11 Page 5

SWITCHING CHARACTERISTICS [5 ]

Parameter

Name

Test Conditions

Min.

Typ.

Max.

Unit

t1

Output Frequency

30-pF load

10

–

100

MHz

10-pF load

10

–

134

MHz

Duty Cycle [4] = t2 ÷ t1

Measured at 1.4V, FOUT = 66.67MHz

40

50

60

%

Duty Cycle [4] = t2 ÷ t1

Measured at 1.4V, FOUT <50MHz

45

50

55

%

t3

Rise Time [4]

Measured between 0.8V and 2.0V

–

2.5

–

ns

Rise Time [4] (High Drive)

Measured between 0.8V and 2.0V

–

1.5

–

ns

t4

Fall Time [4]

Measured between 0.8V and 2.0V

–

2.5

–

ns

Fall Time [4] (High Drive)

Measured between 0.8V and 2.0V

–

1.5

–

ns

t5

Output to Output Skew

All outputs equally loaded

–

250

ps

t6A

Delay, REF Rising Edge to

CLKOUT Rising Edge [4]

Measured at VDD/2

–

0

±350

ps

t6B

Delay, REF Rising Edge to

CLKOUT Rising Edge [4]

Measured at VDD/2. Measured in PLL bypass

mode, PL123S-09 only.

1

5

8.5

ns

t7

Device to Device Skew [4]

Measured at VDD/2 on the CLKOUT pin

–

0

700

ps

t8

Output Slew Rate [4]

Measured between 0.8V and 2.0V using Test

Circuit #2

1

–

V/ns

tJ

Cycle to Cycle Jitter [4]

Measured at 66.67 MHz, loaded outputs

–

75

200

ps

tLOCK

PLL Lock Time [4]

Stable power supply, valid clock presented on

REF pin

–

1.0

ms

Notes:

4. Parameter is guaranteed by design and characterization. Not 100% tested in production .

5. All parameters are specified with loaded outputs.

ERIEEIELE Duty Cycle Timing All Outputs Rise/Fall Time PL123S-05l-09 — 2.0V 3.3V OUTPUT Z'OV 0.8V 0.8V 0V 1 —> —> t Output-Output Skew OUTPUT 1_4V 7W OUTPUT ,W t Input-Output Propagation Delay iNPUT mm W OUTPUT Device-Device Skew CLKOUT, Device i CLKOUT, Device 2 www micrel com

PL123S-05/-09

Spread-Compatible Low Skew Zero Delay Buffer

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 94 4 -0800 • fax +1 (408) 474-1000 • www.micrel .com Rev 12/14/11 Page 6

SWITCHING WAVEFORMS

1.4V

t2

t1

VDD/2

INPUT

t6

OUTPUT

VDD/2

1.4V

OUTPUT

t5

OUTPUT

1.4V

Duty Cycle Timing

All Outputs Rise/Fall Time

Output-Output Skew

Input-Output Propagation Delay

t3

t4

OUTPUT

0.8V

2.0V

0V

3.3V

V

0.8V

2.0V

VDD/2

CLKOUT, Device 1

t7

CLKOUT, Device 2

VDD/2

Device-Device Skew

EnllilELE PL123S-05l-09 Tesi Circuit #1 Test Circuit #2 VDD VDD 1K0 p :: CLK u :: : OUTPUTS : OUTPUTS — :: C _ 1K0 :: 10 pF VDD VDD ,. :: G GND W H :: ND 11 ? www mmrel com

PL123S-05/-09

Spread-Compatible Low Skew Zero Delay Buffer

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 94 4 -0800 • fax +1 (408) 474-1000 • www.micrel .com Rev 12/14/11 Page 7

TEST CIRCUITS

VDD

GND

OUTPUTS

CL O AD

CLK

0.1 F

Test Circuit #1

VDD

GND

OUTPUTS

0.1 F

Test Circuit #2

10 pF

1KΩ

EnlcﬂEL PL123S-05l-09 A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 c 0.19 0.25 D 0.00 10.00 7 E 3.00 4.00 I H 5.00 6.20 0.40 050 :11 11 11 11 L 0.40 1.27 1 T H H 11: i , 6 127350 +1 1++ T +11+ H H H H T 1 I; ,1 H H H H 7 img L7 \7 T 1 ‘1 1- 1 #1 1k www m1cre1 com

PL123S-05/-09

Spread-Compatible Low Skew Zero Delay Buffer

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 94 4 -0800 • fax +1 (408) 474-1000 • www.micrel .com Rev 12/14/11 Page 8

PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)

SOP 8L

Symbol

Dimension in mm

Min.

Max.

A

1.35

1.75

A1

0.10

0.25

A2

1.25

1.50

B

0.33

0.53

C

0.19

0.27

D

4.80

5.00

E

3.80

4.00

H

5.80

6.20

L

0.40

0.89

e

1.27 BSC

C

L

A

SOP-16L, TSSOP-16L ( mm )

SOP

Symbol Min. Max.

A 1.35 1.75 -

A1 0.10 0.25

B 0.33 0.51

C 0.19 0.25

D 9.80 10.00

E 3.80 4.00

H 5.80 6.20 6.40 BSC

L 0.40 1.27

e1.27 BSC

EH

D

A1

eB

TSSOP

Min. Max.

1.20

0.05 0.15

0.19 0.3

0.09 0.20

4.90 5.10

4.30 4.50

0.45 0.75

0.65 BSC

C

L

A2

EH

D

A1

eb

A

EBIEEIELE PL123S-05l-09 PL123S-0xﬂ) XX X Pan/Order Number Marking Package Option P123805 PL1238-05HSC P123805H 8»Pm SOP Tube PL1238-0900 P123809 16-Pin TSSOP Tube PL1238-09HOC P123809H 16-Pin TSSOP Tube PL1238-098C P123809 16-Pin 80P Tube PL1238-09HSC P123809H 16-Pin 80P Tube www mmre1com

PL123S-05/-09

Spread-Compatible Low Skew Zero Delay Buffer

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 94 4 -0800 • fax +1 (408) 474-1000 • www.micrel .com Rev 12/14/11 Page 9

ORDERING INFORM ATION

Micrel Inc., reserves the right to make changes in its products or specifications, or both at any ti m e without notice. The information furnis hed by Micrel

is beli eved to be accur ate and reliable. However, Micrel makes no guara ntee or warranty concerning the accuracy of s aid informat ion and shall no t be

respon sible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.

LIFE SUPPORT POLICY: Micrel’s pr oducts are not au thorized for use as critical compo nents in life sup port device s or systems without the express

written approval of the President of Mic rel Inc.

For part ordering, please contact our Sales Department:

2180 Fortune Drive, San Jose, CA 95131, USA

Tel: (408) 944-0800 Fax: (408) 474-1000

PART NUMBER

The order number for this device is a combination of the following:

Part number, Package type and Operating temperature range

PL123S-0x(H) X X - X

Part Number

H=High Drive

None = Standard Drive

Package Type

O=TSSOP

S=SOP

None=Tubes

R=Tape & Reel

Temperature Range

C=Commercial (0°C to 70°C)

I=Industrial (-40°C to 85°C)

Part/Order Number

Marking

Package Option

PL123S-05SC

P123S05

SC

LLLLL

8-Pin SOP Tube

PL123S-05SC-R

8-Pin SOP (Tape and Reel)

PL123S-05HSC

P123S05H

SC

LLLLL

8-Pin SOP Tube

PL123S-05HSC-R

8-Pin SOP (Tape and Reel)

PL123S-09OC

P123S09

OC

LLLLL

16-Pin TSSOP Tube

PL123S-09OC-R

16-Pin TSSOP (Tape and Reel)

PL123S-09HOC

P123S09H

OC

LLLLL

16-Pin TSSOP Tube

PL123S-09HOC-R

16-Pin TSSOP (Tape and Reel)

PL123S-09SC

P123S09

SC

LLLLL

16-Pin SOP Tube

PL123S-09SC-R

16-Pin SOP (Tape and Reel)

PL123S-09HSC

P123S09H

SC

LLLLL

16-Pin SOP Tube

PL123S-09HSC-R

16-Pin SOP (Tape and Reel)

PL123S-05/09 Datasheet by Microchip Technology

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