LV8111V Datasheet by ON Semiconductor

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LV8111V Bi-CMOS IC For Polygon Mirror Motor 3-phase Brushless Motor Driver Overview The LV8111V i. .1 37pm brusltle. 0N Semioonductor‘“ nttp//oriserni.corn motor driver tor polygon mirror motor driving of LBP. A circuit needed to drive of polygon mirror motor can be composed of a singleechip. Also the output transistor is made DMOS by using BiDC proc l. (l-leut gener on) it achieved. Features . 3rphuse pipolur drive v and by adopting the synchronous rect‘ 0 Direct PWM drive + synchronous rectification . 10 max] 25A . 10 max] = 30A (t : 0.1ms) - Output current control circuit 0 PLL speed control circuit I Fh' 0 Compatible with Hall FG o Provides a 5V regulator output e lock detection output (with m' k function) a Forward / Rever ution method, the lower power consumption . Full complement of onrchip protection circuits, including lock protection, current limiter, underevoltage protection, and thermal s utdown protection circuits a Circuit to switch slowing down method while stopped (Free run or Shonecircuit broke) a Constraint protection detection s na1 switching circuit (PG or LD) witching circuit 0 Hull bias pin (Bius current cut in a stopped state) c SDCC (Speed Detection Current Control) function Speclflcalions Absolute Maximum Ratings at Tu = 25°C Parameter Symbol conditions Rallngs unit Supply voltage VCC max VCC pin 37 V VG max VG pm A2 V Ouipulcurrenl lo maxi ‘1 2.5 A lo max2 l:0,ims ‘i 3.0 A Allowable Power dlSSlpalInn Pd max Mounled on a specmed beam ‘2 i 7 W Operation temperature Tool 725 to +50 “to Storage temperature Tslg ,55 to +150 “'0 .tunction temperature T) max 150 “to .t T) max = 1501) must not be exceeded, .2 Specmed poaro H4 3mm x 76 trnm x i am, glass epoxy board caution t) Absolute maximum ratings represent tne value whlcl'l cannot be exceeded lor any lengtn ol time caution 2) Even wnen tne device is used Witnin tne range at absolute maxlmum ratings, as a result at continuous usage under nign temperature, nigh current, nign voltage. or orastic temperature cnange, tne reilablilly ol tne lC may be degraded Please contact us lpr the tunner delalls Semiconductor Components luduuries. LLC. 2m 3 May, 2013 3l4l2 SY 20120224750000} / 0l409 SY loom) MS / 22509 MS Nu,Al4lfirl/13
31412 SY 20120224-S00003 / O1409 SY / 60309 MS / 22509 MS No.A1416-1/13
http://onsemi.com
Semiconductor Components Industries, LLC, 2013
May, 2013
LV8111V
Overview
The LV8111V is a 3-phase brushless motor driver for polygon mirror motor driving of LBP.
A circuit needed to drive of polygon mirror motor can be composed of a single-chip. Also, the output transistor is made
DMOS by using BiDC process, and by adopting the synchronous rectification method, the lower power consumption
(Heat generation) is achieved.
Features
• 3-phase bipolar drive
• Direct PWM drive + synchronous rectification
• IO max1 = 2.5A
• Full complement of on-chip protection circuits, including lock
protection, current limiter, under-voltage protection, and thermal
shutdown protection circuits
• IO max1 = 3.0A (t ≤ 0.1ms)
• Output current control circuit • Circuit to switch slowing down method while stopped
(Free run or Short-circuit brake)
• PLL speed control circuit • Constraint protection detection signal switching circuit (FG or LD)
• Phase lock detection output (with mask function) • Forward / Reverse switching circuit
• Compatible with Hall FG • Hall bias pin (Bias current cut in a stopped state)
• Provides a 5V regulator output • SDCC (Speed Detection Current Control) function
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter Symbol Conditions Ratings Unit
VCC max VCC pin 37 V Supply voltage
VG max VG pin 42 V
IO max1 *1 2.5 A Output current
IO max2 t ≤ 0.1ms *1 3.0 A
Allowable Power dissipation Pd max Mounted on a specified board *2 1.7 W
Operation temperature Topr -25 to +80 °C
Storage temperature Tstg -55 to +150 °C
Junction temperature Tj max 150 °C
*1. Tj max = 150°C must not be exceeded.
*2. Specified board: 114.3mm × 76.1mm × 1.6mm, glass epoxy board.
Caution 1) Absolute maximum ratings represent the value which cannot be exceeded for any length of time.
Caution 2) Even when the device is used within the range of absolute maximum ratings, as a result of continuous usage under high temperature, high current,
high voltage, or drastic temperature change, the reliability of the IC may be degraded. Please contact us for the further details.
Bi-CMOS IC
For Polygon Mirror Motor
3-phase Brushless Motor Driver
Orderin
g
numbe
r
: ENA1416C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
LV8111V
No.A1416-2/13
Allowable Operating Ranges at Ta = 25°C
Parameter Symbol Conditions Ratings Unit
Supply voltage range VCC 10 to 35 V
5V constant voltage output current IREG 0 to -30 mA
LD pin applied voltage VLD 0 to 5 V
LD pin output current ILD 0 to 15 mA
FG pin applied voltage VFG 0 to 5 V
FG pin output current IFG 0 to 15 mA
HB pin output current IHB 0 to -30 mA
Electrical Characteristics at Ta = 25°C, VCC = 24V
Ratings
Parameter Symbol Conditions min typ max
Unit
ICC1 5.5 6.5 mA Current drain
ICC2 In a stop state 1.0 1.5 mA
5V Constant Voltage Output
Output voltage VREG 4.65 5.0 5.35 V
Line regulation ΔVREG1 VCC = 10 to 35V 20 100 mV
Load regulation ΔVREG2 IO = -5 to -20mA 25 60 mV
Temperature coefficient ΔVREG3 Design target value * 0 mV/°C
Output Block
Output ON resistance RON I
O = 1A , Sum of the lower and upper side
outputs
1.5 1.9 Ω
Output leakage current IOleak Design target value * 10 μA
Lower side Diode forward voltage VD1 ID = -1A 1.0 1.35 V
Upper side Diode forward voltage VD2 ID = 1A 1.0 1.35 V
Charge Pump Output (VG pin)
Output voltage VGOUT V
CC+4.9 V
CP1 pin
Output ON resistance (High level) VOH(CP1) ICP1 = -2mA 500 700 Ω
Output ON resistance (Low level) VOL(CP1) ICP1 = 2mA 300 400 Ω
Hall Amplifier Block
Input bias current IHB(HA) -2 -0.5 μA
Common mode input voltage range VICM 0.5 VREG-2.0 V
Hall input sensitivity 80 mVp-p
Hysteresis ΔVIN(HA) 15 24 42 mV
Input voltage L → H VSLH 12 mV
Input voltage H → L VSHL -12 mV
Hall Bias (HB pin) P-channel Output
Output voltage ON resistance VOL(HB) IHB = -20mA 20 30 Ω
Output leakage current IL(HB) VO = 0V 10 μA
FG Amplifier Schmitt Block (IN1)
Input amplifier gain GFG Design target value * 5 times
Input hysteresis (H → L) VSHL(FGS) Input referred, Design target value * 0 mV
Input hysteresis (L → H) VSLH(FGS) Input referred, Design target value * 10 mV
hysteresis VFGL Input referred, Design target value * 10 mV
* Design target value, Do not measurement.
Continued on next page.
LV8111V
No.A1416-3/13
Continued from preceding page.
Ratings
Parameter Symbol Conditions min typ max
Unit
FGFIL pin
High level output voltage VOH(FGFIL) 2.7 3.0 3.3 V
Low level output voltage VOL(FGFIL) 0.75 0.85 0.95 V
External capacitor charge current ICHG1 VCHG1 = 1.5V -5 -4 -3 μA
External capacitor discharge current ICHG2 VCHG2 = 1.5V 3 4 5 μA
Amplitude V(FGFIL) 1.95 2.15 2.35 Vp-p
FG Output
Output ON resistance VOL(FG) IFG = 7mA 20 30 Ω
Output leakage current IL(FG) VO = 5V 10 μA
PWM Oscillator
High level output voltage VOH(PWM) 2.95 3.2 3.45 V
Low level output voltage VOL(PWM) 1.3 1.5 1.7 V
External capacitor charge current ICHG(PWM) VPWM = 2V -90 -70 -50 μA
Oscillation frequency f(PWM) C = 150pF 180 225 270 kHz
Amplitude V(PWM) 1.5 1.7 1.9 Vp-p
Recommended operation frequency
range
fOPR 15 300 kHz
CSD Oscillation Circuit
High level output voltage VOH(CSD) 2.7 3.0 3.3 V
Low level output voltage VOL(CSD) 0.8 1.0 1.2 V
Amplitude V(CSD) 1.75 2.0 2.25 Vp-p
External capacitor charge current ICHG1(CSD) VCHG1 = 2.0V -14 -10 -6 μA
External Capacitor Discharge Current ICHG2(CSD) VCHG2 = 2.0V 8 11 14 μA
Oscillation frequency f(CSD) C = 0.068μF, Design target value * 30 40 50 Hz
Phase comparing output
Output ON resistance (high level) VPDH I
OH = -100μA 500 700 Ω
Output ON resistance (low level) VPDL I
OL = 100μA 500 700 Ω
Phase Lock Detection Output
Output ON resistance VOL(LD) ILD = 10mA 20 30 Ω
Output leakage current IL(LD) VO = 5V 10 μA
Error Amplifier Block
Input offset voltage VIO(ER) Design target value * -10 +10 mV
Input bias current IB(ER) -1 +1 μA
High level output voltage VOH(ER) IOH = -100μA EI+0.7 EI+0.85 EI+1.0 V
Low level output voltage VOL(ER) IOL = 100μA EI-1.75 EI-1.6 EI-1.45 V
DC bias level VB(ER) -5% VREG/2 5% V
Current Control Circuit
Drive gain GDF While phase locked 0.5 0.55 0.6 times
Current Limiter Circuit (pins RF and RFS)
Limiter voltage VRF 0.465 0.515 0.565 V
Under-voltage Protection
Operation voltage VSD 8.3 8.7 9.1 V
Hyteresis ΔVSD 0.2 0.35 0.5 V
CLD Circuit
External capacitor charge current ICLD V
CLD = 0V -4.5 -3.0 -1.5 μA
Operation voltage VH(CLD) 3.25 3.5 3.75 V
Thermal Shutdown Operation
Thermal shutdown operation
temperature
TSD Design target value (Junction temperature) 150 175 °C.
Hysteresis ΔTSD Design target value (Junction temperature) 30 °C
* Design target value, Do not measurement.
Continued on next page.
LV8111V
No.A1416-4/13
Continued from preceding page.
Ratings
Parameter Symbol Conditions min typ max
Unit
CLK pin
External input frequency fI(CLK) 0.1 10 kHz
High level input voltage VIH(CLK) 2.0 VREG V
Low level input voltage VIL(CLK) 0 1.0 V
Input open voltage VIO(CLK) VREG-0.5 VREG V
Hysteresis VIS(CLK) 0.2 0.3 0.4 V
High level input current IIH(CLK) VCLK = VREG -10 0 +10 μA
Low level input current IIL(CLK) VCLK = 0V -110 -85 -60 μA
CSDSEL pin
High level input voltage VIH(CSD) 2.0 VREG V
Low level input voltage VIL(CSD) 0 1.0 V
Input open voltage VIO(CSD) VREG-0.5 VREG V
High level input current IIH(CSD) VCSD = VREG -10 0 +10 μA
Low level input current IIL(CSD) VCSD = 0V -110 -85 -60 μA
S/S pin
High level input voltage VIH(SS) 2.0 VREG V
Low level input voltage VIL(SS) 0 1.0 V
Input open voltage VIO(SS) VREG-0.5 VREG V
Hysteresis VIS(SS) 0.2 0.3 0.4 V
High level input current IIH(SS) VS/S = VREG -10 0 +10 μA
Low level input current IIL(SS) VS/S =0V -110 -85 -60 μA
BRSEL pin
High level input voltage VIH(BRSEL) 2.0 VREG V
Low level input voltge VIL(BRSEL) 0 1.0 V
Input open voltage VIO(BRSEL) VREG-0.5 VREG V
High level input current IIH(BRSEL) VBRSEL = VREG -10 0 +10 μA
Low level input current IIL(BRSEL) VBRSEL = 0V -110 -85 -60 μA
F/R pin
High level input voltage VIH(FR) 2.0 VREG V
Low level input voltage VIL(FR) 0 1.0 V
Input open voltage VIO(FR) VREG-0.5 VREG V
High level input current IIH(FR) VF/R = VREG -10 0 +10 μA
Low level input current IIL(FR) VF/R = 0V -110 -85 -60 μA
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LV8111V
No.A1416-5/13
Package Dimensions
unit : mm (typ)
3333
-20 0 20 40 60 80 100
0
2.0
1.5
1.0
0.5
Pd max -- Ta
1.7
0.95
Ambient temperature, Ta -- °C
Allowable power dissipation, Pd max -- W
Specified board: 114.3×76.1×1.6mm3
glass epoxy board.
Pin Assignment
44 43 42 41 40 39 38 37 29
3031
323334
35
36 23
2425
262728
1
CLK
2
LD
3
S/S
4
VREG
5
BRSEL
6
CSDSEL
7
F/R
8
CLD
161514
131211
10
922
2120
191817
CSD
FG
PWM
FC
FGFIL
PH
PD
EI
EO
TOC
GND
HB
CP2
CP1
VG
VCC1
VCC2
RFS
RF
OUT1
OUT2
OUT3
GND2
SUB
IN3−
IN3+
IN2−
IN2+
IN1−
IN1+
LV8111V
Top view
SANYO : SSOP44K(275mil)
15.0
7.6
(3.5)
(4.7)
5.6
0.5
0.22 0.2
0.65
(0.68)
0.1 (1.5)
1.7MAX
TOP VIEW SIDE VIEW
SIDE VIEW
BOTTOM VIEW
122
2344
LV8111V
No.A1416-6/13
Block Diagram and Application Circuit Example
CSDSEL
CSD
OSC
BRSEL
S/S
F/R
COUNT
LOGIC
LD
LD
MASK
CLK
PLL
FG
FILTER
HALL HYS AMP HB CURR
LIM
CNTROL
CIRCUIT
LOGIC PWM
OSC
COMP CONT
AMP
PEAK
HOLD
VREG
LVDS
DRIVER
CHARGE
PUMP
VREG
PD
EI
EO
TOC
FC
PH
VREG
VCC1
VCC2
VG
CP1
CP2
VCC
OUT1
OUT2
OUT3
GND2
SUB
GNDRFRFSHBIN1+IN2+IN3+
IN1−IN2−IN3−
FGFIL
FG
CLK
CLD
LD
F/R
S/S
BRSEL
CSD
CSDSEL
PWM
LD output
CLK input
FG output
TSD
fl 5%
LV8111V
No.A1416-7/13
Pin Function
Pin No. Pin name Function Equivalent circuit
1 CLK Clock input pin (10kHz maximum)
1
5kΩ10kΩ
55kΩ
VREG
2 LD Phase lock detection output pin.
Goes ON during PLL-phase lock.
Open drain output.
2
VREG
3 S/S Start/Stop input pin.
START with a low-level input.
STOP with a high-level input or open input
3
5kΩ10kΩ
55kΩ
VREG
4 VREG 5V regulator output pin.
(the control circuit power supply)
Connect a capacitor between this pin and GND for
stabilization.
4
VCC
50Ω
5 BRSEL Brake selection pin.
By low level, short-circuit braking when the S/S pin is in a
stopped state.
(Brake for the inspection process)
5
5kΩ
55kΩ
VREG
6 CSDSEL Motor constraint protection detection signal selection pin.
Select FG with low,
and LD with high or in an open state.
6
5kΩ
55kΩ
VREG
Continued on next page.
fl
LV8111V
No.A1416-8/13
Continued from preceding page.
Pin No. Pin name Function Equivalent circuit
7 F/R Pin to select Forward / Reverse.
7
5kΩ
55kΩ
VREG
8 CLD Pin to set phase lock signal mask time.
Connect a capacitor between this pin and GND.
If there is no need for masking, this pin must be left open.
8
500Ω
VREG
2kΩ
9 CSD Pin for both the constraint protection circuit operation time
and the initial reset pulse setting.
Connect a capacitor between this pin and GND.
If the motor constraint protection circuit is not used,
a capacitor and a resistor must be connected in parallel
between the CSD pin and GND.
9
500Ω
VREG
10 FG FG Schmitt output pin.
Open drain output.
10
VREG
12 PWM Pin to set the oscillation frequency of PWM.
Connect a capacitor between this pin and GND.
12
VREG
200Ω
2kΩ
14 FC Frequency characteristics correction pin of the current
limiter circuit.
Connect a capacitor between this pin and GND.
14
VREG
500Ω
110kΩ
Continued on next page.
LV8111V
No.A1416-9/13
Continued from preceding page.
Pin No. Pin name Function Equivalent circuit
15 FGFIL FG filter pin.
When the noise of the FG signal is a problem, connect a
capacitor between this pin and GND for stabilization.
15
500Ω
VREG
15kΩ
16 PH Pin to stabilize the RF waveform.
Connect a capacitor between this pin and GND.
16
VREG
500Ω
10kΩ
17 PD Phase comparison output pin.
The phase error is output by the duty changing of the pulse.
17
VREG
500Ω
18 EI Error amplifier input pin.
18
VREG
500Ω
19 EO Error amplifier output pin.
VREG
100kΩ
19
20 TOC Torque command voltage input pin.
Normally, this pin must be connected with the EO pin.
20
VREG
21 GND Ground pin of the control circuit block.
Continued on next page.
LV8111V
No.A1416-10/13
Continued from preceding page.
Pin No. Pin name Function Equivalent circuit
22 HB Hall element bias current pin.
Goes ON when the S/S pin is in a start state.
Goes OFF when the S/S pin is in an stopped state.
22
VREG
23
24
25
26
27
28
IN1+
IN1−
IN2+
IN2−
IN3+
IN3−
Hall amplifier input pin.
A high level state of logic is recognized when IN+ > IN−.
In reverse case is a low-level state.
The input amplitude of 100mVp-p or more (differential) is
desirable in the Hall sensor inputs.
If noise on the Hall inputs is a problem, that noise must be
excluded by inserting capacitors across the inputs.
25
VREG
500Ω500Ω
26
24 28 2723
29 SUB Frame ground pin. This pin is connected with the GND2 pin.
30 GND2 Ground pin of the output circuit block.
32
34
36
OUT3
OUT2
OUT1
Output pin.
As for PWM, Duty control is executed on the upper- side
FET.
38 RF Source pin of output MOSFET (lower-side).
Connect a low resistance (Rf) between this pin and GND.
32
VCC
34 36
38
39 RFS Output current detection pin.
Connect to RF pin.
39
5kΩ
VREG
40 VCC2 Power supply pin.
Connect a capacitor between this pin and GND for
stabilization.
41 VCC1 Power supply pin for control.
42 VG Charge pump output pin (Power supply for the upper side
FET gate).
Connect a capacitor between this pin and VCC.
43
44
CP1
CP2
Pin to connect a capacitor for charge pump.
Connect a capacitor between CP1 and CP2.
VCC
44
500Ω
42
43
100Ω
LV8111V
No.A1416-11/13
3-phase Logic Truth Table (IN = “H” indicates the state where in IN+ > IN−)
F/R = H F/R = L Output
IN1 IN2 IN3 IN1 IN2 IN3 OUT1 OUT2 OUT3
H L H L H L L H M
H L L L H H L M H
H H L L L H M L H
L H L H L H H L M
L H H H L L H M L
L L H H H L M H L
S/S Pin BRSEL Pin
Input state Mode Input state While stopped
High or Open Stop High or Open Free run
Low Start
Low Short-circuit brake
CSDSEL Pin
Input state Mode
High or Open LD standard
Low FG standard
LV8111V Description
1. Speed Control Circuit
This IC can realize a high efficiency, low-jitter, a stable rotation by adopting the PLL speed control method.
This the PLL circuit compares the phase difference of the edge between the CLK signal and the FG signal and controls
by using the output of error. The FG servo frequency under control becomes congruent with the CLK frequency.
fFG (Servo) = fCLK
2. Output Drive Circuit
This IC adopts the direct PWM drive method to reduce power loss in the output. Adjusts the driving force of the motor
by changing on-duty of output transistor. The PWM switching of the output is performed by the upper-side output
transistor.
Also, this IC has a parasitic diode of the output DMOS as a regeneration route when the PWM switching is off.
But, this IC is cut down the fever than the diode regeneration by performing synchronous rectification.
3. Current Limiter Circuit
This IC limits the (peak) current at the value
I = VRF / Rf (VRF = 0.515V (typical), Rf : current detection resister)).
The current limitation operation consists of reducing the PWM output on duty to suppress the current.
To prevent malfunction of the current limitation operation when the reverse recovery current of diode is detected, the
operation has a delay (approximately 300ns). In case of a coil resistance of motor is small or small inductance, since
the current change at start-up is fast, there is a possibility that the current more than specified current is flowed by this
delay.
It is necessary to set the current increases by the delay.
4. Power Saving Circuit
This IC becomes the power saving state of decreasing the consumption current in the stop state. The bias current of the
majority circuits is cut in the power saving state. Also, 5V regulator output is output in the power saving state.
5. Reference Clock
Note that externally-applied clock signal has no noise of chattering. The input circuit has a hysteresis.
But, if noise is a problem, that noise must be excluded by inserting capacitors across the inputs.
If clock input goes to the no input state when the IC is in the start state, the drive is turned off after a few rotation of
motor if the motor constrained protection circuit does operate. (Clock disconnection protection)
LV8111V
No.A1416-12/13
6. PWM Frequency
The PWM frequency is determined by using a capacitor C (F) connected to the PWM pin.
fPWM ≈ 1 / (29500 × C ) … 150pF or more
fPWM ≈ 1 / (32000 × C ) … 100pF or more, less than 150pF
The frequency is oscillated at about 225kHz when a capacitor of 150pF is connected.
The GND of a capacitor must be placed as close to the control block GND (GND pin ) of the IC as possible to reduce
influence of the output.
7. Hall Effect Sensor Input Signals
The signal input of the amplitude of hysteresis of 42mV max or more is required in the Hall effect sensor inputs.
Also, an input amplitude of over 100mVp-p is desirable in the Hall effect sensor inputs in view of influence of noise.
If the output waveform (when the phase changes ) is distorted by noise, that noise must be excluded by inputting
capacitors across the inputs.
8. FG Signals
The Hall signal of IN1 is used as the FG signal in the IC. If noise is a problem, the noise of the FG signal can be
excluded by inserting a capacitor between the FGFIL pin and GND.
Note that normal operation becomes impossible if the value of the capacitor is overlarge. Also, note that the trouble of
noise occurs easily when the position of GND of a capacitor is incorrect.
9. Constraint Protection Circuit
This IC has an on-chip constraint protection circuit to protect the IC and the motor in motor constraint mode. when the
CSDSEL pin is set to the high level or open input, if the LD output remains high (unlocked statement) for a fixed
period in the start state, this circuit operates. In the low level setting case, if the FG signal is not switched for a fixed
period in the start state, this circuit is operates. Also, the upper-side output transistor is turned off while the constraint
protection circuit is operating. This time is set by the capacitance of the capacitor attached to the CSD pin.
The set time (in seconds) is 102 × C (μF)
When a capacitor of 0.068μF is attached, the protection time becomes about 7.0 seconds.
The set time must be set well in advance for the motor start-up time. When the motor is decelerated by switching the
clock frequency, this protection circuit is not operated. To clear the motor constrained state, the S/S pin is switched
into a stop state or the power must be turned off and reapplied. Since the CSD pin also functions as the power-on reset
pin, if the CSD pin were connected directly to ground, the logic circuit goes to the reset state and the speed cannot be
controlled.
Therefore, if the motor constraint protection circuit is not used, a resistor of about 220kΩ and a capacitor of about
4700pF must be connected in parallel between the CSD pin and GND.
10. Phase Lock Signals
(1) Phase lock range
This IC has no the speed system counter. The speed error range in the phase lock state is indeterminable only by the
characteristics of the IC. ( because the accelerations of the change in FG frequency influences.)
When it is necessary to specify for the speed error as a motor, the value obtained while the motor is actually operating
must be measured. Since the speed error occurs easily when the accelerations of FG is large, the speed error will be
the largest when the IC goes into the lock state during start-up or the unlocked state by switching the clock.
(2) Phase lock signal mask functions
When the IC goes into the lock state during start-up or the unlocked state by switching the clock, the low signal for a
short-time by using the hunting when the IC goes into the locked state is masked. Therefore, the lock signal is output
in stable state. But, the mask time duration causes the delay of the lock signal output. The mask time is set by the
capacitance of the capacitor attached between the CLD pin and GND.
The mask time (seconds) is 1.8 × C (μF)
When a capacitor of 0.1μF is attached, the mask time becomes about 180ms.
If the signals should be masked completely, the mask time must be set well in advance.
When there is no need for masking, the CLD pin must be left open.
PS NoAMlsM
LV8111V
PS No.A1416-13/13
11. Power Supply Stabilization
Since this IC is used in applications that draw large output currents and adopts the drive method by switching, the
power-Supply line is subject to fluctuations. Therefore, capacitors with capacitances adequate to stabilize the
power-supply voltage must be connected between the VCC pin and GND. The ground-side a capacitor must be
connected as close to the GND2 pin of power GND as possible. If it is impossible to connect a capacitor (electrolytic
capacitor) near the pin, the ceramic capacitor of about 0.1μF must be connected as close to the pin as possible.
If diodes are inserted in the power-supply line to prevent IC destruction due to reverse power supply connection,
Since this makes the power-supply voltage even more subject to fluctuations, even larger capacitors will be required.
12. VREG Stabilization
To stabilize the VREG voltage that is the power supply of the control circuit, connect a capacitor of 0.1μF or more.
GND of the capacitor must be attached as close to the control block GND (GND1 pin) of the IC as possible.
13. Error Amplifier
External components of the error amplifier block must be placed as close to the IC as possible to reduce influence of
noise.
Also, these components must be placed as separate from the motor as possible.
14. IC Reverse Metal
To improve heat radiation, the metal part on the reverse of IC is stuck fast to the substrate by using highly-conduction
solder.
15. SDCC (Speed Detection Current Control) function
The SDCC circuit controls the speed detection current. It limits the current to 87.5% of the specified current to reduce
acceleration of the motor when the rotation of the motor exceeds 95% of its target speed. This enables stabilized phase
lock pull-in and minimizes the variation in startup time.
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