SILIEIJN LABS
Low Jitter and Power Clock Generator with SSCG
Rev 2.2, August 1, 2010 Page 1 of 10
400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com
SL16020DC
Key Features
Low power dissipation
- 14.5mA-typ CL=15pF
- 20.0mA-max CL=15pF
3.3V +/-10% power supply range
27.000MHz crystal or clock input
27.000MHz REFCLK
100MHz SSCLK with SSEL0/1 spread options
Low CCJ Jitter
Low LT Jitter
Internal Voltage Regulators
45% to 55% Output Duty Cycle
On-chip Crystal Oscillator
-10 to +85 Temperature Range
10-pin 3x3x0.75 mm TDFN package
Application
Video Cards
NB and DT PCs
HDTV and DVD-R/W
Routers, Switches and Servers
Data Communications
Embeded Digital Applications
Description
The SL16020DC is a low power dissipation spread
spectrum clock generator using SLI proprietary low jitter
PLL. The SL16020DC provides two output clocks.
REFCLK (Pin-9) which is a buffered output of the
27.000MHz input crystal and SSCLK (Pin-5) which is
synthesized as 100.000MHz nominal by an internal PLL
using the 27.00MHz external input crystal or clock.
In addition, SSEL0 (Pin-7) and SSEL1 (Pin-3) spread
percent selection control inputs enable users to select
from 0.0% (no spread) to –1.5% down spread at
100.000MHz SSCLK output to reduce and optimize
system EMI levels.
The SL16020DC operates in an extended temperature
range of -10 to +85°C.
Contact SLI for other programmable frequencies, Spread
Spectrum Clock (SSC) options, as well as 2.5V+/-10 and
1.8V+/-5% power supply options.
Benefits
EMI Reduction
Improved Jitter
Low Power Dissipation
Eleminates external Xtals or XOs
Block Diagram
1Low Jitter PLL
With
Modulation Control
5
Input Decoder
4 6
10
7 3
300K
SSCLK
100.000MHz
With Spread Options
XIN/CLKIN
XOUT
VDD1 VSS1 SSEL0 SSEL1
9REFCLK
27.000MHz
8 2
VSS2VDD2
Figure 1. Block Diagram
Low Jitter and Power Clock Generator with SSCG
7 w
SILICEIN LABS
SL16020DC
Rev 2.2, August 1, 2010 Page 2 of 10
SL16020DC
Pin Configuration
10
9
8
7
1
2
3
4
XOUT
REFCLK
VDD2
SSEL0
XIN/CLKIN
VSS2
SSEL1
VDD1
SSCLK 56VSS1
Figure 2. 10-Pin TDFN (3x3x0.75 mm)
Table 1. Pin Description
Pin
Number
Pin Name
Pin Type
Pin Description
1
XIN
Input
External crystal or clock input. Capacitance at this pin is 4 pF-typ.
2
VSS2
Power
Power supply ground for 27.000MHz REFCLK output.
3
SSEL1
Input
SSEL1 spread percent selection pin. Refer to Table 5 for available
spread options using SSEL1 pin. This pin has 150kΩ pull down resistor
to VSS.
4
VDD1
Power
Positive power supply for 100.000MHz SSCLK output. 3.3V +/-10%.
5
SSCLK
Output
SSCLK clock output. 100.000MHz nominal. Refer to Table 5 for available
spread % options by using SSEL0 and SSEL1 control pins.
6
VSS1
Power
Power supply ground for 100.000MHz SSCLK output.
7
SSEL0
Input
SSEL spread percent selection pin. Refer to Table 5 for available
spread options using SSEL0 pin. This pin has 150kΩ pull down resistor
to VSS.
8
VDD2
Power
Positive power supply for 27.000MHz REFCLK output. 3.3V +/-10%.
9
REFCLK
Output
REFCLK clock output. 27.000MHz nominal.
10
XOUT
Output
Crystal output. Capacitance at this pin 4 pF-typ. If clock input is used,
leave this pin unconnected (N/C).
6’ SL16020DC
SILICON LABS
Rev 2.2, August 1, 2010 Page 3 of 10
SL16020DC
Table 2. Absolute Maximum Ratings
Description
Condition
Min
Max
Unit
Supply voltage, VDD
-0.5
4.2
V
All Inputs and Outputs
-0.5
VDD+0.5
V
Ambient Operating Temperature
In operation, extended C grade
-10
85
°C
Storage Temperature
No power is applied
-65
150
°C
Junction Temperature
In operation, power is applied
-
125
°C
Soldering Temperature
-
260
°C
ESD Rating (Human Body Model)
JEDEC22-A114D
-4,000
4,000
V
ESD Rating (Charge Device Model)
JEDEC22-C101C
-1,500
1,500
V
ESD Rating (Machine Model)
JEDEC22-A115D
-200
200
V
Table 3. DC Electrical Characteristics (C-Grade)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range -10 to +85Deg C
Description
Symbol
Condition
Min
Typ
Max
Unit
Operating Voltage
VDD1/2
VDD1=VDD2=3.3V +/-10%
2.97
3.3
3.63
V
Input Low Voltage
VINL
SSEL0 and SSEL1
0
-
0.2
V
Input Middle Voltage
VINM
SSEL0 and SSEL1
0.4VDD
-
0.6VDD
Input High Voltage
VINH
SSEL0 and SSEL1
0.9VDD
-
VDD
V
Output Low Voltage
VOL
IOL=15mA, Pins 5 and 9
-
-
0.4
V
Output High Voltage
VOH
IOH=-15mA , Pins 5 and 9
VDD-0.4
-
-
V
Power Supply Current
IDD
SSEL=1, M or 0, CL=15pF,
VDD=3.63V and T=85°C
-
14.5
20.0
mA
Input Capacitance
CIN1
XIN and XOUT, Pins 1 and 10
-
4
-
pF
Input Capacitance
CIN2
SSEL0/1, Pins 7 and 3
-
3
5
pF
Load Capacitance
CL
SSCLK and REFCLK,
Pins 5 and 9
-
-
15
pF
Pull Down Resistor
RPD
Pins 3 and 7
100
150
250
kΩ
$3 SL16020DC
SILICON LABS
Rev 2.2, August 1, 2010 Page 4 of 10
SL16020DC
Table 4. AC Electrical Characteristics (C-Grade)
Unless otherwise stated VDD= 3.3V+/-10%, CL=15pF and Ambient Temperature range -10 to +85 Deg C
Parameter
Symbol
Condition
Min
Typ
Max
Unit
Frequency Range
FR-1
Input crystal or clock range, +/-10 ppm
accuracy if a crystal is used
-
27.000
-
MHz
Frequency Range
FR-2
REFCLK, Pin 9
-
27.000
-
MHz
Frequency Range
FR-3
SSCLK, Pin 5
-
100.000
-
MHz
Frequency Accuracy
FACC1
REFCLK, Pin 9
-
+/-0
-
ppm
Frequency Accuracy
FACC2
SSCLK, Pin 5, SSEL0/1=0
-
+/-0
-
ppm
Rise and Fall Time
TR/F-1
REFCLK, Pin 9, CL=5pF, measured
from 20% to 80% of VDD
-
1.0
1.5
ns
Rise and Fall Time
TR/F-2
REFCLK, Pin 9, CL=15pF, measured
from 20% to 80% of VDD
-
1.5
2.0
ns
Rise and Fall Time
TR/F-3
SSCLK, Pin 5, CL=5pF, measured
from 20% to 80% of VDD
-
0.75
1.0
ns
Rise and Fall Time
TR/F-4
SSCLK, Pin 5, CL=15pF, measured
from 20% to 80% of VDD
-
1.5
1.75
ns
Output Duty Cycle
DC
SSCLK and REFCLK , Pins 5 and 9
measured at VDD/2, CL=15pF
45
50
55
%
Cycle-to-Cycle Jitter
CCJ1
SSCLK, Pin 5, all S0/1 states
-100
+/-50
100
ps
Cycle-to-Cycle Jitter
CCJ2
REFCLK, Pins 9, all S0/1 states
-150
+/-100
150
ps
Long Term Jitter
LTJ
REFCLK, Pins 9, 10,000 cycles, all
S0/1 states
-
150
250
ps
Power-up Time
(VDD)
tPU1
Time from 0.9VDD to valid frequency
at output Pins 5 and 9
-
2.0
5.0
ms
Spread Percent
Change Settling Time
tSS%
Time from SSEL0/1 change to stable
SSCLK with spread %
-
-
1.0
ms
Modulation Frequency
MF
SSCLK, 100MHz nominal, Pin 5
31
32
33
kHz
Modulation Type and
Slew Rate
FMTSR
SSCLK, Pin 5, Triangular Modulation
Profile
-
-
0.125
%/μs
$3 SL16020DC
SILICON LABS
Rev 2.2, August 1, 2010 Page 5 of 10
SL16020DC
Table 5. SSEL1 and SSEL0 versus Spread % Selection at SSCLK
SSEL1 (Pin 3)
SSEL0 (Pin 7)
Spread Percent (%)
SSCLK (Pin 5)
Low (VSS)
Low (VSS)
Spread Off (No Spread)
Low (VSS)
Middle (VDD/2)
-0.50%
Low (VSS)
High (VDD)
-0.375%
Middle (VDD/2)
Low (VSS)
-0.25%
Middle (VDD/2)
Middle (VDD/2)
-0.75%
Middle (VDD/2)
High (VDD)
-1.00%
High (VDD)
Low (VSS)
-1.50%
High (VDD)
Middle (VDD/2)
Spread Off (No Spread)-Test
High (VDD)
High (VDD)
Spread Off (No Spread)-Test
Table 6. Recommended Crystal Specifications
Description
Min
Typ
Max
Unit
Nominal Frequency (Fundamental Crystal)
-
27.000
-
MHz
Crystal Accuracy
-
+/-10
-
ppm
Load Capacitance
6
12
18
pF
Shunt Capacitance
-
-
7.0
pF
Equivalent Series Resistance (ESR)
-
-
30
Ω
Drive Level
-
-
1.0
mW
6’ SL16020DC
SILIEEIN LABS
iris
Use 5kQ/5kn external resistor dividers
Rev 2.2, August 1, 2010 Page 6 of 10
SL16020DC
External Resistor Dividers for 3-Level Logic Implementation
3-Level Logic
HIGH=VDD
VDD
5KΩ
SSEL0
or
SSEL1
INPUT
7/3
3-Level Logic
LOW=VSS
VSS
5KΩ
SSEL0
or
SSEL1
INPUT
7/3
HIGH (H) = VDD
MIDDLE (M) = VDD/2
LOW (L) = VSS
3-Level Logic
Middle=VDD/2
VSS
VDD
5KΩ
5KΩ
SSEL0
or
SSEL1
INPUT
7/3
Figure 3. FSEL0 and FSEL1 Spread % Selection Logic
Note: SSEL0 and SSEL1 pins use 3-Level L(LOW) = VSS, M(MIDDLE)=VDD/2 and H(HIGH) = VDD
3-Level logic to provide 9 spread % values at SSCLK (pin 5) as given in Table 5.
Use 5kΩ/5kΩ external resistor dividers at SSEL0 and SSEL1 pins from VDD to VSS to obtain VDD/2
for M=VDD/2 Logic level as shown above in Figure 3.
6’ SL16020DC
SILIEEIN LABS
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Rev 2.2, August 1, 2010 Page 7 of 10
SL16020DC
External Components and Design Considerations
Typical Application Circuit
SL16020DC
XIN(1)
VDD2(8)
XOUT(10)
SSCLK(5)
SSEL1(3)
SSEL0(7)
100MHz
27MHz
CL1
CL2
0.1μF
VSS2(2)
REFCLK(9) 27MHz
VSS1(6)
VDD1(4)
10μF
External crystal and crystal
load capacitors required if
crystal is used.
If external clock (XO) is used
leave Pin-10 XOUT
unconnected (N/C) and drive
Pin 1 XIN/CLKIN with clock
VDD
VDD
0.1μF
5K
5K
This example is configured
for -0.5% Spread
SSEL0=M (VDD/2) and
SSEL1=LOW (VSS)
5K
Figure 4. Typical Application Schematic
Comments and Recommendations
Crystal and Crystal Load: Only use a parallel resonant fundamental AT cut crystal. DO NOT USE higher overtone
crystals. To meet the crystal initial accuracy specification (in ppm) make sure that external crystal load capacitor is
matched to crystal load specification. To determine the value of CL1 and CL2, use the following formula;
C1 = C2 = 2CL – (Cpin + Cp)
Where: CL is load capacitance stated by crystal manufacturer
Cpin is the SL16010 pin capacitance (4pF)
Cp is the parasitic capacitance of the PCB traces.
EXAMPLE; if a crystal with CL=12pF specification is used and Cp=1pF (parasitic PCB capacitance on PCB), 19 or
20pF external capacitors from pins XIN (pin-1) and XOUT (Pin-10) to VSS are required since CXIN=CXOUT=4pF for
the SL1610DC product. Users must verify Cp value.
Decoupling Capacitor: A decoupling capacitor of 0.1μF must be used between VDD1/2 pins and VSS1/2 pin. Place
the capacitor on the component side of the PCB as close to the VDD1/2 pins as possible. The PCB trace to the
VDD1/2 pins and to the VSS via should be kept as short as possible Do not use vias between the decoupling
capacitor and the VDD1/2 pins. In addition, a 10uf capacitor should be placed between VDD and VSS.
Series Termination Resistor: A series termination resistor is recommended if the distance between the outputs
(REFCLK and SSCLK) and the load if PCB trace is over 1 ½ inch. The nominal impedance of the outputs is about 24
(:59 SL16020DC
SILIEEIN LABS
we
Rev 2.2, August 1, 2010 Page 8 of 10
SL16020DC
Ω. Use 22 Ω resistors in series with the outputs to terminate 50Ω trace impedance and place 22 Ω resistors as close
to the clock outputs as possible.
Package Outline and Package Dimensions
10-Pin TDFN Package (3x3x0.75 mm)
3.00+/-0.10
0.20+/-0.025
C: 0.25X45°C
Pin #1 ID
Top View Bottom View
Side View
Side View
0.00-0.05
0.50
3.00+/-0.10
0.75+/-0.05
0°
0.25+/-0.05
2.00+/-0.10
0.30+/-0.05
1.50+/-0.10
Dimentions are in mm
15
610
Table 7. Thermal Characteristics
Parameter
Symbol
Condition
Min
Typ
Max
Unit
Thermal Resistance
Junction to Ambient
θJA1
Still air
-
75
-
°C/W
θJA2
1m/s air flow
-
70
-
°C/W
θJA3
3m/s air flow
-
55
-
°C/W
Thermal Resistance
Junction to Case
θJC
Independent of air flow
-
25
-
°C/W
a, SL16020DC
SILICEIN LABS
Rev 2.2, August 1, 2010 Page 9 of 10
SL16020DC
Table 8. Ordering Information
Note:
1. SL16020DC is RoHS compliant and Halogen Free.
Product Revisions History
Revision
Date
Originator
Description
Rev 1.0
11/12/2009
C. Ozdalga
Original
Rev 1.1
11/12/2009
C. Ozdalga
Change spread % from -1.50% to -0.375% for S1=0 (VSS) and
S0=1(VDD) state on Table 5.
Rev 1.2
11/23/2009
C. Ozdalga
Add 150kΩ weak pull down resistors at S0 and S1 pins to VSS.
Rev2.0
4/19/2010
C. Ozdalga
Final datasheet after product qualification. CCJ1 SSCLK
decreased to +/-50-ps-typ and +/-100ps-max and CCJ2
REFCLK decreased to +/-100ps-typ and +/-150ps-max and LTJ
decreased to +/-250ps-max. IDD change to 20mA-max (AMD
spec 50mA-max).
Rev 2.1
6/14/2010
C. Ozdalga
Add clock input function (in addition to crystal). SL16020DC
works with both external crystal and clock (XO).
Rev 2.2
8/1/2010
C. Ozdalga
Add “Halogen Free”, page 8.
Ordering Number
Marking
Shipping Package
Package
Temperature
SL16020DC
SL16020DC
Tube
10-pin TDFN
-10 to 85°C
SL16020DCT
SL16020DC
Tape and Reel
10-pin TDFN
-10 to 85°C
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