L6910(A) Datasheet by STMicroelectronics

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May 2005
1/29
L6910
L6910A
May 2005
1 FEATURES
■OPERATING SUPPLY VOLTAGE FROM 5V
TO 12V BUSES
■UP TO 1.3A GATE CURRENT CAPABILITY
■ADJUSTABLE OUTPUT VOLTAGE
■N-INVERTING E/A INPUT AVAILABLE
■0.9V ±1.5% VOLTAGE REFERENCE
■VOLTAGE MODE PWM CONTROL
■VERY FAST LOAD TRANSIENT RESPONSE
■0% TO 100% DUTY CYCLE
■POWER GOOD OUTPUT
■OVERVOLTAGE PROTECTION
■HICCUP OVERCURRENT PROTECTION
■200kHz INTERNAL OSCILLATOR
■OSCILLATOR EXTERNALLY ADJUSTABLE
FROM 50kHz TO 1MHz
■SOFT START AND INHIBIT
■PACKAGES: SO-16 & HTSSOP16
2 APPLICATIONS
■SUPPLY FOR MEMORIES AND TERMI-
NATIONS
■COMPUTER ADD-ON CARDS
■LOW VOLTAGE DISTRIBUTED DC-DC
■MAG-AMP REPLACEMENT
3 DESCRIPTION
The device is a pwm controller for high performance
dc-dc conversion from 3.3V, 5V and 12V buses.
The output voltage is adjustable down to 0.9V;
higher voltages can be obtained with an external
voltage divider.
High peak current gate drivers provide for fast switch-
ing to the external power section, and the output
current can be in excess of 20A.
The device assures protections against load overcur-
rent and overvoltage. An internal crowbar is also pro-
vided turning on the low side mosfet as long as the
over-voltage is detected. In case of over-current de-
tection, the soft start capacitor is discharged and the
system works in HICCUP mode.
ADJUSTABLE STEP DOWN CONTROLLER
WITH SYNCHRONOUS RECTIFICATION
Figure 2. Block Diagram
MONITOR
PROTECTION
& REF
OSC
E/A PWM
UGATE
BOOT
BOOT
LGATE
PGND
GND
VFB
SS
OSC
EAREF
RT
VREF
PGOOD
VCC OCSET
COMP
300K
+
-
-
+
VO
Vin 5V to 12V
D03IN1509
Rev. 9
Fi
gure 1.
P
ac
k
ages
Table 1. Order Codes
Part Number Package
L6910 SO-16
L6910TR SO-16 in Tape & Reel
L6910A HTSSOP16
L6910ATR HTSSOP16 in Tape & Reel
SO-16 (Narrow) HTSSOP16 (Exposed Pad)
£7
L6910 - L6910A
2/29
Table 2. Absolute Maximum Ratings
Table 3. Thermal Data
(*) Device soldered on 1 S2P PC board
Figure 3. Pins Connection (Top view)
Symbol Parameter Value Unit
Vcc Vcc to GND, PGND 15 V
VBOOT
-
VPHASE
Boot Voltage 15 V
VHGATE-
VPHASE
15 V
OCSET, LGATE, PHASE -0.3 to Vcc+0.3 V
SS, FB, PGOOD, VREF, EAREF, RT 7 V
COMP 6.5 V
TjJunction Temperature Range -40 to 150 °C
Tstg Storage temperature range -40 to 150 °C
Ptot Maximum power dissipation at Tamb = 25°C1W
Symbol Parameter SO-16 HTSSOP16 HTSSOP16 (*) Unit
Rth j-amb Thermal Resistance Junction to Ambient 120 110 50 °C/W
VREF
OSC
OCSET
SS/INH
COMP
GND
FB
EAREF PGOOD
PHASE
BOOT
HGATE
PGND
LGATE
VCC
N.C.1
3
2
4
5
6
7
8
14
13
12
11
10
9
15
16
D03IN1510
VREF
OSC
OCSET
SS/INH
N.C.
FB
COMP
GND EAREF
PGOOD
HGATE
PHASE
BOOT
PGND
LGATE
VCC
D03IN1511
1
3
2
4
5
6
7
8
14
13
12
11
10
9
15
16
3/29
L6910 - L6910A
Table 4. Pins Function
SO HTSSOP Name Description
1 1 VREF Internal 0.9V ±1.5% reference is available for external regulators or for the internal error
amplifier (connecting this pin to EAREF) if external reference is not available.
A minimum 1nF capacitor is required.
If the pin is forced to a voltage lower than 70%, the device enters the hiccup mode.
2 2 OSC Oscillator switching frequency pin. Connecting an external resistor (RT) from this pin to
GND, the external frequency is increased according to the equation:
Connecting a resistor (R
T
) from this pin to Vcc (12V), the switching frequency is reduced
according to the equation:
If the pin is not connected, the switching frequency is 200KHz.
The voltage at this pin is fixed at 1.23V. Forcing a 50µA current into this pin, the built in
oscillator stops to switch.
In Over Voltage condition this pin goes over 3V until that conditon is removed.
3 3 OCSET A resistor connected from this pin and the upper Mos Drain sets the current limit
protection.
The internal 200µA current generator sinks a constant current through the external
resistor. The Over-Current threshold is due to the following equation:
4 4 SS/INH The soft start time is programmed connecting an external capacitor from this pin and
GND. The internal current generator forces through the capacitor 10µA.
This pin can be used to disable the device forcing a voltage lower than 0.4V
5 6 COMP This pin is connected to the error amplifier output and is used to compensate the voltage
control feedback loop.
6 7 FB This pin is connected to the error amplifier inverting input and is used to compensate the
voltage control feedback loop.
Connected to the output resistor divider, if used, or directly to Vout, it manages also over-
voltage conditions and the PGOOD signal
7 8 GND All the internal references are referred to this pin. Connect it to the PCB signal ground.
8 9 EAREF Error amplifier non-inverting input. Connect to this pin an external reference (from 0.9V to
3V) for the PWM regulation or short it to VREF pin to use the internal reference.
If this pin goes under 650mV (typ), the device shuts down.
910
PGOOD
This pin is an open collector output and it is pulled low if the output voltage is not within the
above specified thresholds. If not used it may be left floating.
10 11 PHASE
This pin is connected to the source of the upper mosfet and provides the return path for the
high side driver. This pin monitors the drop across the upper mosfet for the current limit
together with OCSET.
11 12 HGATE High side gate driver output.
12 13 BOOT Bootstrap capacitor pin. Through this pin is supplied the high side driver and the upper
mosfet. Connect through a capacitor to the PHASE pin and through a diode to Vcc
(cathode vs. boot).
13 14 PGND Power ground pin. This pin has to be connected closely to the low side mosfet source in
order to reduce the noise injection into the device
14 5 LGATE This pin is the lower mosfet gate driver output
15 16 VCC Device supply voltage. The operative supply voltage ranges is from 5V to 12V.
DO NOT CONNECT VIN TO A VOLTAGE GREATER THAN VCC.
16 5 N.C. This pin is not internally bonded. It may be left floating or connected to GND.
fOSC,RT 200KHz 4.94 106
⋅
RTKΩ()
-------------------------+=
fOSC,RT 200KHz 4.306 107
⋅
RTKΩ()
-----------------------------–=
IP
IOCSET ROCSET
⋅
RDSon
----------------------------------------------=
L6910 - L6910A
4/29
Table 5. Electrical Characteristics (Vcc = 12V, TJ =25°C unless otherwise specified)
Symbol Parameter Test Condition Min Typ Max Unit
Vcc SUPPLY CURRENT
Icc Vcc Supply current OSC = open; SS to GND 4 7 9 mA
POWER-ON
Turn-On Vcc threshold VOCSET = 4V 4.0 4.3 4.6 V
Turn-Off Vcc threshold VOCSET = 4V 3.8 4.1 4.4 V
Rising VOCSET threshold 1.24 1.4 V
Turn On EAREF threshold VOCSET = 4V 650 750 mV
SOFT START AND INHIBIT
Iss Soft start Current
S.S. current in INH condition
SS = 2V
SS = 0 to 0.4V
610
35
14
60
µA
µA
OSCILLATOR
fOSC Initial Accuracy OSC = OPEN
OSC = OPEN; Tj = 0° to 125°
180
170
200 220
230
KHz
kHz
fOSC,RT Total Accuracy 16 KΩ < RT to GND < 200 KΩ-15 15 %
∆Vosc Ramp amplitude 1.9 V
REFERENCE
VOUT Output Voltage Accuracy VOUT = VFB; VEAREF = VREF 0.886 0.900 0.913 V
VREF Reference Voltage CREF = 1nF; IREF = 0 to 100µA 0.886 0.900 0.913 V
VREF Reference Voltage CREF = 1nF; TJ = 0 to 125°C-2 +2%
ERROR AMPLIFIER
IEAREF N.I. bias current VEAREF = 3V 10 µA
EAREF Input Resistance Vs. GND 300 kΩ
IFB I.I. bias current VFB = 0V to 3V 0.01 0.5 µA
VCM Common Mode Voltage 0.8 3 V
VCOMP Output Voltage 0.5 4 V
GVOpen Loop Voltage Gain 70 85 dB
GBWP Gain-Bandwidth Product 10 MHz
SR Slew-Rate COMP = 10pF 10 V/µs
GATE DRIVERS
IHGATE High Side
Source Current
VBOOT - VPHASE = 12V
VHGATE - VPHASE = 6V
11.3 A
RHGATE High Side
Sink Resistance
VBOOT - VPHASE = 12V 2 4 Ω
ILGATE Low Side Source Current Vcc = 12V; VLGATE = 6V 0.9 1.1 A
RLGATE Low Side Sink Resistance Vcc = 12V 1.5 3 Ω
Output Driver Dead Time PHASE connected to GND 90 210 ns
PROTECTIONS
IOCSET OCSET Current Source VOCSET = 4V 170 200 230 µA
Over Voltage Trip (VFB / VEAREF)V
FB Rising 117 120 %
IOSC OSC Sourcing Current VFB > OVP Trip 15 30 mA
POWER GOOD
Upper Threshold (VFB / VEAREF)V
FB Rising 108 110 112 %
Lower Threshold (VFB / VEAREF)V
FB Falling 88 90 92 %
Hysteresis (VFB / VEAREF) Upper and Lower threshold 2 %
VPGOOD PGOOD Voltage Low IPGOOD = -4mA 0.4 V
IPGOOD Output Leakage Current VPGOOD = 6V 0.2 1 µA
5/29
L6910 - L6910A
4 DEVICE DESCRIPTION
The device is an integrated circuit realized in BCD technology. The controller provides complete con-
trol logic and protection for a high performance step-down DC-DC converter. It is designed to drive N
Channel Mosfets in a synchronous-rectified buck topology. The output voltage of the converter can be
precisely regulated down to 900mV with a maximum tolerance of ±1.5% when the internal reference is
used (simply connecting together EAREF and VREF pins). The device allows also using an external
reference (0.9V to 3V) for the regulation. The device provides voltage-mode control with fast transient
response. It includes a 200kHz free-running oscillator that is adjustable from 50kHz to 1MHz. The er-
ror amplifier features a 10MHz gain-bandwidth product and 10V
/
µ
s
slew rate that permits to realize
high converter bandwidth for fast transient performance. The PWM duty cycle can range from 0% to
100%. The device protects against over-current conditions entering in HICCUP mode. The device
monitors the current by using the
r
DS(ON)
of the upper MOSFET(s) that eliminates the need for a cur-
rent sensing resistor. The device is available in SO16 narrow package.
4.1 Oscillator
The switching frequency is internally fixed to 200kHz. The internal oscillator generates the triangular waveform
for the PWM charging and discharging with a constant current an internal capacitor. The current delivered to the
oscillator is typically 50
µ
A (F
sw
= 200KHz) and may be varied using an external resistor (R
T
) connected between
OSC pin and GND or V
CC
. Since the OSC pin is maintained at fixed voltage (typ. 1.235V), the frequency is var-
ied proportionally to the current sunk (forced) from (into) the pin.
In particular connecting R
T
vs. GND the frequency is increased (current is sunk from the pin), according to the
following relationship:
Connecting R
T
to V
CC
= 12V or to V
CC
= 5V the frequency is reduced (current is forced into the pin), according
to the following relationships:
V
CC
= 12V
V
CC
= 5V
Switching frequency variation vs. RT are repeated in Fig. 4.
Note that forcing a 50
µ
A current into this pin, the device stops switching because no current is delivered to the
oscillator.
Figure 4.
fOSC,RT 200KHz 4.94 106
⋅
RTKΩ()
-------------------------+=
fOSC,RT 200KHz 4.306 107
⋅
RTKΩ()
-----------------------------–=
fOSC,RT 200KHz 15 106
⋅
RTKΩ()
---------------------–=
10 100 1000
Frequency [kHz]
10
100
1000
10000
Resistance [kOhm]
RT to GND
RT to VCC=12V
RT to VCC=5V
Tek so flkS/s I Acqs [ r ch; 2nnv u.- zonv-u
L6910 - L6910A
6/29
4.2 Reference
A precise ±1.5% 0.9V reference is available. This reference must be filtered with 1nF ceramic capacitor to avoid
instability in the internal linear regulator. It is able to deliver up to 100
µ
A and may be used as reference for the
device regulation and also for other devices. If forced under 70% of its nominal value, the device enters in Hic-
cup mode until this condition is removed.
Through the EAREF pin the reference for the regulation is taken. This pin directly connects the non-inverting
input of the error amplifier. An external reference (or the internal 0.9V ±1.5%) may be used. The input for this
pin can range from 0.9V to 3V. It has an internal pull-down (300k
Ω
resistor) that forces the device shutdown if
no reference is connected (pin floating). However the device is shut down if the voltage on the EAREF pin is
lower than 650mV (typ).
4.3 Soft Start
At start-up a ramp is generated charging the external capacitor C
SS
with an internal current generator. The initial
value for this current is of 35
µ
A and speeds-up the charge of the capacitor up to 0.5V. After that it becames
10
µ
A until the final charge value of approximatively 4V.
When the voltage across the soft start capacitor (V
SS
) reaches 0.5V the lower power MOS is turned on to dis-
charge the output capacitor. As V
SS
reaches 1.1V (i.e. the oscillator triangular wave inferior limit) also the upper
MOS begins to switch and the output voltage starts to increase.
No switching activity is observable if SS is kept lower than 0.5V and both mosfets are off.
If VCC and OCSET pins are not above their own turn-on thresholds and V
EAREF
is not above 650mV, the Soft-
Start will not take place, and the relative pin is internally shorted to GND. During normal operation, if any under-
voltage is detected on one of the two supplies, the SS pin is internally shorted to GND and so the SS capacitor
is rapidly discharged.
Figure 5. Soft Start (with Reference Present)
4.4 Driver Section
The driver capability on the high and low side drivers allows using different types of power MOS (also multiple
MOS to reduce the R
DSON
), maintaining fast switching transition.
The low-side mos driver is supplied directly by Vcc while the high-side driver is supplied by the BOOT pin.
Adaptative dead time control is implemented to prevent cross-conduction and allow to use several kinds of mos-
fets. The upper mos turn-on is avoided if the lower gate is over about 200mV while the lower mos turn-on is
Timing Diagram
Vcc Turn-on threshold
Vin Turn-on threshold
0.5V
1V
Vcc
Vin
Vss
LGATE
Vout
to GND
Acquisition: CH1 = PHASE; CH2 = Vout;
CH3 = PGOOD; CH4 = Vss
m m... zSnMS/s m m an no m mm mm]; m m 5007M M on"; cm so". an mo M on"; Ch LODA r-K m. stsls mus m m 250ml: mm? man 2; lees
7/29
L6910 - L6910A
avoided if the PHASE pin is over about 500mV. The lower mos is in any case turned-on after 200ns from the
high side turn-off.
The peak current is shown for both the upper (fig. 6) and the lower (fig. 7) driver at 5V and 12V. A 3.3nF capac-
itive load has been used in these measurements.
For the lower driver, the source peak current is 1.1A @ V
CC
= 12V and 500mA @ V
CC
= 5V, and the sink peak
current is 1.3A @ V
CC
= 12V and 500mA @ V
CC
= 5V.
Similarly, for the upper driver, the source peak current is 1.3A @ Vboot-Vphase = 12V and 600mA @ Vboot-
Vphase = 5V, and the sink peak current is 1.3A @ Vboot-Vphase =12V and 550mA @ Vboot-Vphase = 5V.
Figure 6. High Side Driver Peak Current. Vboot-Vphase = 12V (right) Vboot-Vphase = 5V (left)
Figure 7. Low Side Driver Peak Current. VCC = 12V (right) VCC = 5V (left)
4.5 Monitoring and Protections
The output voltage is monitored by means of pin FB. If it is not within ±10% (typ.) of the programmed value, the
powergood output is forced low.
The device provides overvoltage protection, when the voltage sensed on pin FB reaches a value 17% (typ.)
greater than the reference the OSC pin is forced high (3V typ.) and the lower driver is turned on as long as the
over-voltage is detected.
CH1 = High Side Gate CH4 = Gate Current
CH1 = Low Side Gate CH4 = Gate Current
m WW 5 nnksls Szmwe cm 100A M mums cm I {no
L6910 - L6910A
8/29
Overcurrent protection is performed by the device comparing the drop across the high side MOS, due to the
R
DSON
, with the voltage across the external resistor (R
OCS
) connected between the OCSET pin and drain of the
upper MOS. Thus the overcurrent threshold (I
P
) can be calculated with the following relationship:
Where the typical value of I
OCS
is 200
µ
A. To calculate the R
OCS
value it must be considered the maximum
R
dsON
(also the variation with temperature) and the minimum value of I
OCS
. To avoid undesirable trigger of
overcurrent protection this relationship must be satisfied:
Where
∆
I is the inductance ripple current and I
OUTMAX
is the maximum output current.
In case of over current detectionthe soft start capacitor is discharged with constant current (10
µ
A typ.) and when
the SS pin reaches 0.5V the soft start phase is restarted. During the soft start the over-current protection is al-
ways active and if such kind of event occurs, the device turns off both mosfets, and the SS capacitor is dis-
charged again (after reaching the upper threshold of about 4V). The system is now working in HICCUP mode,
as shown in figure 8. After removing the cause of the over-current, the device restart working normally without
power supplies turn off and on.
IP
ROCS IOCS
⋅
RdsON
---------------------------------=
IPIOUTMAX I∆
2
-----+≥IPEAK
=
Figure 8. Hiccup Mode Figure 9. Inductor Ripple Current vs. Vout
CH1 = SS; CH4 = Inductor current
0
1
2
3
4
5
6
7
8
9
0.5 1.5 2.5 3.5
Output Voltage [V]
Inductor Ripple [A]
L=3µH,
Vin=12V
L=2µH,
Vin=12V
L=1.5
µ
H
,
Vin=12V
L=2µH,
Vin=5V
L=1.5µH,
Vin=5V
L=3
µ
H
,
Vin=5V
4.6 Inductor Design
The inductance value is defined by a compromise between the transient response time, the efficiency, the cost
and the size. The inductor has to be calculated to sustain the output and the input voltage variation to maintain
the ripple current
∆
I
L
between 20% and 30% of the maximum output current. The inductance value can be cal-
culated with this relationship:
Where f
SW
is the switching frequency, V
IN
is the input voltage and V
OUT
is the output voltage. Figure 9 shows
the ripple current vs. the output voltage for different values of the inductor, with V
IN
= 5V and V
IN
= 12V.
Increasing the value of the inductance reduces the ripple current but, at the same time, reduces the converter
response time to a load transient. If the compensation network is well designed, the device is able to open or
close the duty cycle up to 100% or down to 0%. The response time is now the time required by the inductor to
change its current from initial to final value. Since the inductor has not finished its charging time, the output cur-
rent is supplied by the output capacitors. Minimizing the response time can minimize the output capacitance
required.
LVIN VOUT
–
fsw IL
∆⋅
------------------------------ VOUT
VIN
---------------
⋅=
(
9/29
L6910 - L6910A
The response time to a load transient is different for the application or the removal of the load: if during the ap-
plication of the load the inductor is charged by a voltage equal to the difference between the input and the output
voltage, during the removal it is discharged only by the output voltage. The following expressions give approx-
imate response time for
∆
I load transient in case of enough fast compensation network response:
The worst condition depends on the input voltage available and the output voltage selected. Anyway the worst
case is the response time after removal of the load with the minimum output voltage programmed and the max-
imum input voltage available.
4.7 Output Capacitor
The output capacitor is a basic component for the fast response of the power supply. In fact, during load tran-
sient, for first few microseconds they supply the current to the load. The controller recognizes immediately the
load transient and sets the duty cycle at 100%, but the current slope is limited by the inductor value. The output
voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the ESL):
A minimum capacitor value is required to sustain the current during the load transient without discharge it. The
voltage drop due to the output capacitor discharge is given by the following equation:
Where D
MAX
is the maximum duty cycle value that is 100%. The lower is the ESR, the lower is the output drop
during load transient and the lower is the output voltage static ripple.
4.8 Input Capacitor
The input capacitor has to sustain the ripple current produced during the on time of the upper MOS, so it must
have a low ESR to minimize the losses. The rms value of this ripple is:
Where D is the duty cycle. The equation reaches its maximum value with D = 0.5. The losses in worst case are:
4.9 Compensation Network Design
The control loop is a voltage mode (figure 10). The output voltage is regulated to the input Reference voltage
level (EAREF). The error amplifier output V
COMP
is then compared with the oscillator triangular wave to provide
a pulse-width modulated (PWM) wave with an amplitude of V
IN
at the PHASE node. This wave is filtered by the
output filter. The modulator transfer function is the small-signal transfer function of V
OUT
/V
COMP
. This function
has a double pole at frequency F
LC
depending on the L-C
out
resonance and a zero at F
ESR
depending on the
output capacitor ESR. The DC Gain of the modulator is simply the input voltage V
IN
divided by the peak-to-peak
oscillator voltage
∆
V
OSC
.
tapplication LI∆⋅
VIN VOUT
–
------------------------------ tremoval LI∆⋅
VOUT
---------------==
VOUT
∆IOUT
∆ESR⋅=
VOUT
∆IOUT
2
∆L⋅
2C
OUT VINMIN DMAX VOUT
–⋅()⋅⋅
---------------------------------------------------------------------------------------------=
Irms IOUT D1D–()⋅=
P ESR Irms
2
⋅=
E l E >—|:|—“—< l—="" .="" e="" i="" the="" compensation="" network="" consists="" in="" the="" internal="" error="" amplifier="" and="" the="" c20)="" and="" zfb="" (r5,="" 018="" and="" 019).="" the="" compensation="" network="" has="" to="" prov="" the="" highest="" 0gb="" crossmg="" trequency="" to="" have="" last="" response="" (but="" always="" lo="" in="" dc="" conditions="" to="" minimize="" the="" load="" regulation.="" a="" stable="" control="" loop="" has="" a="" gain="" crossing="" with="" rzodb/decade="" slope="" and="" a="" worstrcase="" component="" variations="" when="" determining="" phase="" margin.="" to="" locate="" poles="" and="" zeroes="" ol="" the="" compensation="" networks,="" the="" tollowtng="" modulator="" singularity="" lrequencies:="" compensation="" network="" singularity="" frequency:="" ,="" put="" the="" gain="" r5/fl3="" in="" order="" to="" obtain="" the="" desired="" converter="" ban="" ,="" place="" (1)21="" before="" the="" output="" filter="" resonance="" mm;="" ,="" place="" mm="" at="" the="" output="" filter="" resonance="" mm;="" ,="" place="" mp1="" at="" the="" output="" capacitor="" esr="" zero="" (desr;="" ,="" place="" mp2="" at="" one="" half="" of="" the="" switching="" lrequency;="" ,="" check="" the="" loop="" gain="" considering="" the="" error="" amplifier="" open="" loop="" g="" 10/29="">
L6910 - L6910A
10/29
Figure 10. Compensation Network
The compensation network consists in the internal error amplifier and the impedance networks Z
IN
(R3, R4 and
C20) and Z
FB
(R5, C18 and C19). The compensation network has to provide a closed loop transfer function with
the highest 0dB crossing frequency to have fast response (but always lower than fsw/10) and the highest gain
in DC conditions to minimize the load regulation.
A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45°. Include
worst-case component variations when determining phase margin.
To locate poles and zeroes of the compensation networks, the following suggestions may be used:
Modulator singularity frequencies:
Compensation network singularity frequency:
– Put the gain R5/R3 in order to obtain the desired converter bandwidth;
–Place ωZ1 before the output filter resonance ωLC;
–Place ωZ2 at the output filter resonance ωLC;
–Place ωP1 at the output capacitor ESR zero ωESR;
–Place ωP2 at one half of the switching frequency;
– Check the loop gain considering the error amplifier open loop gain.
+
-
L
PWM
COMPARATOR
ESR
C
OUT
V
OUT
V
COMP
EAREF
∆V
OSC
V
IN
R3
C19
R5
C18
C20 R4
D03IN1512
ωLC 1
LC
OUT
⋅
--------------------------- ωESR 1
ESR COUT
⋅
---------------------------------==
ωP1 1
R5 C18 C19⋅
C18 C19+
-----------------------------
⎝⎠
⎛⎞
⋅
----------------------------------------------- ωP2 1
R4 C20⋅
------------------------==
ωZ1 1
R5 C19⋅
------------------------ ωZ2 1
R3 R4+()C20⋅
-------------------------------------------==
dB Amplifier cloud Loop min DESCRIPTION n ol lhe device in a general purpose application. 0 5V through the switches 3265 according to the closed). Outpul ourrenl in excess 0120A can be 08 moslet may be used for both High side and Lo lation simply leavrng open G1 and the switches 82 V99 input rail supplies lhe device while lhe pow able to operale with a single supply vollage; in this can be directly conneoled to lhe VIN inpul. The no minimize conduction losses considering the h l is used as a logic level and Ms been pulled up 1 n the demo board. In case of input voltage high 9) 3 5V reference is required. Figure 12 shows the demo ematic swam rill-0 .llH My mum
11/29
L6910 - L6910A
Figure 11. Asymptotic Bode Plot of Converter's Gain
5 15A DEMO BOARD DESCRIPTION
The demo board shows the operation of the device in a general purpose application. This evaluation board al-
lows voltage adjustability from 0.9V to 5V through the switches S2-S5 according to the reported table when the
internal 0.9V reference is used (G1 closed). Output current in excess of 20A can be reached dependently on
the kind of mosfet used: up to three SO8 mosfet may be used for both High side and Low side switches. External
reference may be used for the regulation simply leaving open G1 and the switches S2-S5. The device may also
be disabled with the switch S1. The V
CC
input rail supplies the device while the power conversion starts from
the V
IN
input rail. The device is also able to operate with a single supply voltage; in this case the jumper G2 has
to be closed and a 5V to 12V input can be directly connected to the V
IN
input. The four layers demo board's
copper thickness is of 70
µ
m in order to minimize conduction losses considering the high current that the circuit
is able to deliver.The PGOOD signal is used as a logic level and it's been pulled up to V
IN
because there's no
other appropriate voltage available on the demo board.
In case of input voltage higher than 7V (PGOOD Pin
Maximum Absolute Rating) a 5V reference is required.
Figure 12 shows the demo board's schematic circuit
Figure 12. 15A Demo Board Schematic
Error Am
p
lifier
ωΖ1
Ζ2
ωP1
P2
ωESR
R5/R3
Modulator Gain
Compensation Network Gain
Error Amplifier Closed Loop Gain
LC
ω
dB
UGATE
PHASE
LGATE
PGND
PGOOD
VFB
SS
OSC
EAREF
VREF
R1
GND
VCC
BOOT
C17
C16
C21
C15
VIN
GNDIN
VCC
GNDCC
REFIN
GNDREFIN
+VREF
GNDREF
R7
R6
C13
Q1-3
Q4-6
D2
C14
G2
OCSET
COMP
5
12
15
7
8
1
4
2
13
14
10
11
9
3
6
S2
S1
S4
S5
S3
R10
SR12
SR13
R11
VOUT
PWRGD
GNDOUT
L2
L1
D1
C1-C3
C4-
11
D03IN1513
G1
F1
C19
C18
R5 R3
R8
R2
R9
R4 C20
C22
C12
VOUT S2
Open Open Open Open
ON Open Open Open
ONOpen Open Open
ON ON Open Open
Open Open ON Open
Open Open Open ON
Open Open ON ON
S3 S4 S5
0.9
1.2
1.5
1.8
2.5
3.3
5.0
L6910 - L6910A
12/29
Table 6. Part List
Table 7. Other Inductor Manufacturer
Reference Description Manufacturer
R1 N.C NEOHM
R2 10K 5% 125mW NEOHM SMD 0805
R3 4.7K 5% 125mW NEOHM SMD 0805
R4 1KOhm 5% 125mW NEOHM SMD 0805
R5 2.7K 5% 125mW NEOHM SMD 0805
R6 10Ohm 5% 125mW NEOHM SMD 0805
R7 510Ohm 5% 125mW NEOHM SMD 0805
R8 N.C
R9 0 Ohm SMD 0805
R10 14K 5% 125mW NEOHM SMD 0805
R11 6.98K 5% 125mW NEOHM SMD 0805
R12 2.61K 5% 125mW NEOHM SMD 0805
R13 1.74K 5 5% 125mW NEOHM SMD 0805
C1, C3 100µF - 20V OSCON 20SA100M RADIAL 10X10.5
C9, C10 330µF - 6.3V POSCAP 6TPB330M SMD7343
C12, C13,
C15, C21
100nF KEMET SMD0805
C14 1nF KEMET SMD0805
C16 100nF KEMET
C17 4.7µF - 16V AUX SMA6032
C18 1.5nF KEMET SMD0805
C19 15nF KEMET SMD0805
C20 47nF KEMET SMD0805
C22 N.C
L1 Short
L2 3µH (T50-52B Core, 7T AWG15) MICROMETALS
Q2,Q3,Q4,Q6 STS11NF30L ST SO8
D1 1N4148 SOT23
D2 STPS2L25U ST SMB
U1 Device L6910 ST SO16Narrow
F1 Short
SWITCH DIP SWITCH 6 POS.
Manufacturer Series Inductor Value (µH) Saturation Current (A)
WÜRTH ELEKTRONIK 744318 1.8 to 2.7 16 to 20
PANASONIC ETQP6F1R8FA 1.8 20
SUMIDA CDEP134-2R7MC-H 2.7 15
:Nr ‘ J m
13/29
L6910 - L6910A
Figure 13. PCB and Components Layouts
Figure 14. PCB and Components Layouts
Figure 15. Efficiency vs Output Current
Component Side Internal Signal GND Layer
Internal Power GND Layer Solder Side
75
80
85
90
95
100
1357911131517
Vo=1.2V
Vo=1.5V
Vo=1.8V
Vo=2.5V
Vin=Vcc=5V
Fsw=200KHz
Vo=3.3V
Vo=0.9V
Efficiency (%)
75
80
85
90
95
100
1357911131517
Vo=1.2V
Vo=1.5V
Vo=1.8V
Vo=2.5V
Vin=Vcc=5V
Fsw=200KHz
Vo=3.3V
Vo=0.9V
Efficiency (%)
Output Current (A)
3: Sign £7
L6910 - L6910A
14/29
Figure 16. Efficiency vs Output Current
6 COMPONENTS SELECTION
6.1 Inductor Selection
To select the right inductor value, the application conditions must be fixed. For example we can consider:
Vin=12V Vout =3.3V Iout=15A
Considering a ripple of approximately 25% to 30% of Iout, the inductor value will be L=3
µ
H.
An iron powder core (TO50-52B) with 7 windings has been chosen.
6.2 Output Capacitors
2 POSCAP capacitors, model 6TPB330M, have been chosen, with a maximum ERS equal to 40m
Ω
each.
Therefore, the resultant ESR is of 20m
Ω
. Considering a current ripple of 4A, the output voltage ripple is:
∆
Vout = 4 · 0.02 = 80mV
6.3 Input Capacitors
For I
OUT
= 15A and D = 0.5 (worst case for input current ripple), the RMS current of the input capacitor is equal
to 7.5A.
Two OSCON electrolytic capacitors 6SP680M, with a maximum ESR equal to 13m
Ω
, have been chosen to sus-
tain the ripple. Therefore, the resultant ESR is equal to 13m
Ω
/2 = 6.5m
Ω
. The losses, in worst case, are:
P = ESR · I
2
rms = 366mW
6.4 Over-Current Protection
The current limit can be set to approximately 20A. Substituting the demo board parameters in the relation-
ship reported in the relative section, (IOSCMIN =170µA; IP = 20A; RDSONMAX = 9mΩ / 2=4.5mΩ) it results
that ROCS = 510Ω
Output Current (A)
Efficiency (%)
50
55
60
65
70
75
80
85
90
95
100
1357911131517
Vin=Vcc=12V
Fsw.=200KHZ
Vo=1.2V
Vo=1.8V
Vo=3.3V
Vo=5V
Vo=0.9V
Vin=Vcc=12V
Fsw.=200KHZ
Vo=1.2V
Vo=1.8V
Vo=3.3V
Vo=5V
Vo=0.9V
Vo=1.5V
Vo=2.5V
Vo=1.5V
Vo=2.5V
Output Current (A)
A compacl demo board has been realized to manage currems in The range ol SAVGA . The exlernal power moslels are included in a single SOS package lo save space and more Two separale rails are provided, for VCC and VW. They can be connecled logelner by shor The PGOOD signal is used as a logic level and i1‘s been pulled up lo VIN because there's n vollage available on The demo board. In case of input vollage higher ihan 7V (PGOOD solute Rating) a 5V reference is required. Figure 17. 6A Demo Board Schemaiic vw 5mm 01 vac mantel
15/29
L6910 - L6910A
6.5 APPLICATION SUGGESTIONS FOR HIGHER CURRENTS
For higher output currents, up to 20A, the following configuration can be used (with reference to the demo board
schematic):
Q1,Q2,Q3: STS11NF30L
Q4,Q5,Q6: STS17NF3LL
L: 2.5
µ
H Magnetic 77121A7 Core 7T 2x AWG16
In these conditions, the following performance have been achieved:
Table 8.
For currents higher than 20A, bigger mosfets should be selected (e.g. STS25NH3LL) both for the high side and
low side (depending on the duty cycle and input voltage).
7 6A DEMO BOARD DESCRIPTION
A compact demo board has been realized to manage currents in the range of 5A-6A .
The external power mosfets are included in a single SO8 package to save space and increase power density.
Two separate rails are provided, for V
CC
and V
IN
. They can be connected together by shorting the jumper J1.
The PGOOD signal is used as a logic level and it's been pulled up to V
IN
because there's no other appropriate
voltage available on the demo board.
In case of input voltage higher than 7V (PGOOD Pin Maximum Ab-
solute Rating) a 5V reference is required.
Figure 17. 6A Demo Board Schematic
VIN (V) VOUT (V) IOUT (A) η (%) VIN (V) VOUT (V) IOUT (A) η (%)
5 1.2 20 81 12 1.2 20 80
5 1.5 20 83 12 1.5 20 83
5 1.8 20 85 12 1.8 20 85
5 2.5 20 89 12 2.5 20 88
5 3.3 20 91 12 3.3 20 91
12 5 20 93
L1
R7
C1- C2
C7
C3-4
Q1/Q1
D2
13
14
10
11
3
1
U1
L6910
VIN
VOUT
PWRGD
6
12
5
4
2
15
7
9
VCC
GND
VREF
SS
OSC
OCSET
UGATE
PHASE
LGATE
PGND
PGOOD
VFB
COMP
C19
R10
C9
C6
D1
GNDOUT
GNDIN
R2
C8
C5
R6
C18
8
GNDCC
VCC
R5
J1
R3
R4 C20
EAREF
BOOT
R1
C10
R11
Q2/Q1
R8
R9
L1
R7
C1- C2
C7
C3-4
Q1/Q1
D2
13
14
10
11
3
1
U1
L6910
VIN
VOUT
PWRGD
6
12
5
4
2
15
7
9
VCC
GND
VREF
SS
OSC
OCSET
UGATE
PHASE
LGATE
PGND
PGOOD
VFB
COMP
C19
R10
C9C9
C6
D1
GNDOUT
GNDINGNDIN
R2
C8
C5
R6
C18
8
GNDCC
VCC
R5
J1
R3
R4R4 C20C20
EAREF
BOOT
R1
C10
R11
Q2/Q1
R8
R9
L6910 - L6910A
16/29
Table 9. Part List
Table 10. Other inductor manufacturer
Reference Description Manufacturer
Resistor
R1 2K7 Ohm 0805 5% 125mW NEOHM (Vout = 2.5V)
1K8 Ohm 0805 5% 125mW NEOHM (Vout = 3.3V)
1K Ohm 0805 5% 125mW NEOHM (Vout = 5V)
R2 10K 5% 125mW NEOHM SMD 0805
R3 4K7 5% 125mW NEOHM SMD 0805
R4 4K7 5% 125mW NEOHM SMD 0805
R5 2K7 5% 125mW NEOHM SMD 0805
R6 10 Ohm 5% 125mW NEOHM SMD 0805
R7 680 Ohm 5% 125mW NEOHM SMD 0805
R8 R9 2.2 Ohm 5% 125mW NEOHM SMD 0805
R10 N.C
R11 N.C
Capacitors
C1,C2 10µF 25V TOKIN C34Y5U1E106ZTE12
C3,C4 100µF - 6.3V POSCAP 6TPB100M SMD7343
C5,C6,C9 100nF KEMET SMD0805
C7,C8 1nF KEMET SMD0805
C10 N.C
C18 1.5nF KEMET SMD0805
C19 15nF KEMET SMD0805
C20 47nF KEMET SMD0805
Magnetics
L1 7µH (T50-52B Core, 12T AWG 21) MICROMETALS
Transistor
Q1 STS8DNF3LL ST
Diodes
D1 1N4148 SOT23
D2 STPS2L25U ST SMB
Device
U1 Device L6910 ST SO16Narrow
Manufacturer Series Inductor Value (µH) Saturation Current (A)
WÜRTH ELEKTRONIK 744 382 4.8 to 5.8 7.5 to 8
PANASONIC ETQP6F 4.6 to 6.4 9.3 to 7.9
SUMIDA CDEP134-H 6 to 8 7.2 to 9.6
COILCRAFT DO3316P-472HC 4.7 5.4
DO3340P 10 to 22 8 to 5.5
COILTRONICS DR125-8R2 8.2 7.8
EIEI El vcc cccnm vm :4 c3 5“ so as an 75 7a i vln=vm=5v wa=2nnkxx 1 2 a 4 5 5 Figure 20. Efficiency vs. Outpui Current A R
17/29
L6910 - L6910A
Figure 18. PCB and Components Layouts
7.1 Compact Demo Board Performances
Figures 19, 20 show the measured efficiency versus load current for different values of output voltage. The mea-
sure has been done at 5V and 12V input. Output voltage has been changed modifying the value of R1 in the
demo board as reported in the part list.
Figure 19. Efficiency vs. Output Current
Figure 20. Efficiency vs. Output Current
Component Side Solder Side
70
75
80
85
90
95
100
12345678
Vin=Vcc=5V
Fsw=200KHz Vo=1.2V
Vo=1.5V
Vo=1.8V
Vo=3.3V
Vo=2.5V
Output Current (A)
Efficiency (%)
70
75
80
85
90
95
100
12345678
Vin=Vcc=5V
Fsw=200KHz Vo=1.2V
Vo=1.5V
Vo=1.8V
Vo=3.3V
Vo=2.5V
Output Current (A)
Efficiency (%)
70
75
80
85
90
95
12345678
70
75
80
85
90
95
12345678
Vo=1.2V
Vo=1.5V
Vo=1.8V
Vo=2.5V
Vo=3.3V
Vo=5V
Efficiency (%)
Output Current (A)
Vin=Vcc=12V
Fsw=200KHz Vo=1.2V
Vo=1.5V
Vo=1.8V
Vo=2.5V
Vo=3.3V
Vo=5V
Efficiency (%)
Output Current (A)
Vin=Vcc=12V
Fsw=200KHz
vuw emur mm ,Vve o”; m 3mm ow» m mm W m Wm WM 0N W mm W W WM ON ON mm “a MT R2 fir a; HF 52 SS 54 55 Table 11. Pan List Helelence Description Manufacturer R1 N.C R2 ‘OK 5% ‘25mW NEOHM SMD 0505 R3 4.7K 5% 125mW NEOHM SMD 0505 R4 1K Ohm 5%125mw NEOHM SMD 0505 R5 2.7K 5% ‘25mW NEOHM SMD 05 R6 ‘0 Ohm 5%‘25mW NEOHM SMD 05 R7 560 Ohm 5% ‘25mW NEOHM SMD R8 N.C R9 0 Ohm NEOHM SM m0 14K 5% 125mW NEOHM SM m 1 6.98K 5% 125mW NEOHM SMD m2 2.6m 5% 125mW NEOHM SMD m 3 ‘.74K 5% ‘25mW NEOHM SMD m4 0 Ohm NEOHM m5 0 Ohm NEOHM m6 N.C CLCS 100uF 20v OSCON 205A100M 09,010 330% - 6.3V POSCAP 6TPEBBOM ‘8/29
L6910 - L6910A
18/29
8 15A HTSSOP16 DEMO BOARD DESCRIPTION
A specific Demo Board has been realized for the HTSSOP16 package. The features are the same of the 15A
Demo Board previously described but thermal performance are improved. The PGOOD signal is used as a logic
level and it's been pulled up to V
IN
because there's no other appropriate voltage available on the demo board.
In case of input voltage higher than 7V (PGOOD Pin Maximum Absolute Rating) a 5V reference is re-
quired
.
Figure 21. 15A HTSSOP16 Demo Board Schematic
Table 11. Part List
Reference Description Manufacturer
R1 N.C
R2 10K 5% 125mW NEOHM SMD 0805
R3 4.7K 5% 125mW NEOHM SMD 0805
R4 1K Ohm 5% 125mW NEOHM SMD 0805
R5 2.7K 5% 125mW NEOHM SMD 0805
R6 10 Ohm 5% 125mW NEOHM SMD 0805
R7 560 Ohm 5% 125mW NEOHM SMD 0805
R8 N.C
R9 0 Ohm NEOHM SMD 0805
R10 14K 5% 125mW NEOHM SMD 0805
R11 6.98K 5% 125mW NEOHM SMD 0805
R12 2.61K 5% 125mW NEOHM SMD 0805
R13 1.74K 5% 125mW NEOHM SMD 0805
R14 0 Ohm NEOHM SMD 0805
R15 0 Ohm NEOHM SMD 0805
R16 N.C
C1,C3 100uF 20V OSCON
20SA100M
RADIAL 10X10.5
C9,C10 330uF - 6.3V POSCAP
6TPB330M
SMD7343
L2
R7
C1-C3
C14
C4Q4-6
Q1-3
D2
C17
F1
14
15
11
12
3
1
U1
L6910A
VIN
VOUT
PWRGD
7
13
6
4
2
16
8
10
VCC
GND
VREF
SS
OSC
OCSET
UGATE
PHASE
LGATE
PGND
PGOOD
VFB
COMP
C19
R1
C21
C13
D1
-11
GNDIN
GNDOUT
R2
GNDref
+Vref
C12
GNDRef
Ref IN
C16
C15
R6
C18
9
L1
GNDCC
VCC
R5
G2
R8
R3
R4
R9
C22
C20
S1
S2
S3
S4
S5
R10
R11
R12
R13
EAREF
BOOT
Vout S2 S3 S4 S5
0.9
1.2
1.5
1.8
2.5
3.3
5.0
Open Open
ON
Open Open
Open Open
Open Open
Open Open
Open Open
Open Open
Open Open
ON
ONON
Open
Open
ON
ON
ONON
Open
Open
R14
R15 R16
C23
u u m: um
19/29
L6910 - L6910A
Table 12. Other inductor manufacturer
Figure 22. PCB and Components Layout
Reference Description Manufacturer
C12,C13,
C15,C21,C16
100nF KEMET SMD0805
C14 1nF KEMET SMD0805
C17 4.7uF - 16V AVX SMA6032
C18 1.5nF KEMET SMD0805
C19 15nF KEMET SMD0805
C20 47nF KEMET SMD0805
C22 N.C
C23 N.C
L1 Short
L2 3uH T50-52B Core, 7T AWG15 MICROMETALS
Q2,Q3,Q4,Q6 STS11NF30L ST SO8
D1 1N4148 SOT23
D2 STPS340U ST SMB
U1 Device L6910 ST HTSSOP16
F1 Short
SWITCH DIP SWITCH
Manufacturer Series Inductor Value (µH) Saturation Current (A)
WÜRTH ELEKTRONIK 744318 1.8 to 2.7 16 to 20
PANASONIC ETQP6F1R8FA 1.8 20
SUMIDA CDEP134-2R7MC-H 2.7 15
Table 11. Part List (continued)
Component Side Internal Power GND Layer
Internal Signal GND Layer Solder Side
DDR was MEMORY mm mm \J E a ml UT fl % Tc; i“ 1;: q = “1 B "M '—\ r‘ v" _ m- J T jm . =- _:Pwmn 1 1 .'"' 1 The current required by the memory and the termination supply, depends on the memory type and size. The ligure 24, 25 shows the ellicrency ol the L6910 lor the termination section ol the application shown in fig. 23, in sink and source mode. The ligures show the eflioiency values also when the input voltage is coming die rec1ly lrom the 12V rail. 20/29 £7
L6910 - L6910A
20/29
9 APPLICATION IDEA 1: DDR MEMORY AND TERMINATION SUPPLY
Double Data Rate (DDR) Memories require a particular Power Management Architecture. This is due to the fact
that the trace between the driving chipset and the memory input must be terminated with resistors.
Since the Chipset driving the Memory has a push pull output buffer, the Termination voltage must be capable
of sourcing and sinking current.
Moreover, the Termination voltage must be equal to one half of the memory supply (the input of the memory is
a differential stage requiring a reference bias midpoint) and in tracking with it. For DDRI the Memory Supply is
2.5V and the Termination voltage is 1.25V while, for DDRII, the Memory Supply is 1.8V and the Termination
voltage is 0.9V. Fig. 23 shows a complete DDRI Memory and Termination Power Supply realized by using 2 x
L6910. The 2.5V section is powering the memory while the 1.25V section is providing the termination voltage.
The tracking between the two sections is realized by providing the EAREF voltage of the 1.25V section through
a resistor divider connected to the 2.5V.
Figure 23. Application idea : DDR Memory Supply
The current required by the memory and the termination supply, depends on the memory type and size.
The figure 24, 25 shows the efficiency of the L6910 for the termination section of the application shown in fig.
23, in sink and source mode. The figures show the efficiency values also when the input voltage is coming di-
rectly from the 12V rail.
VREF
13
14
10
11
3
1
6
12
5
4
2
15
7
9
VCC
GND
VREF
SS
OSC
OCSET
UGATE
PHASE
LGATE
PGND
PGOOD
VFB
COMP
VIN
12V
8
EAREF
BOOT
13
14
10
11
3
1
PWRGD
6
12
5
4
2
15
7
9
VCC
GND
VREF
SS
OSC
OCSET
UGATE
PHASE
LGATE
PGND
PGOOD
VFB
COMP
8
EAREF
BOOT STS8DNF3LL
STS11NF3LL
R
+
-
VDDQ
2.5V@15A
VTT
1.25V@ - 5A
VIN
12V
U1
L6910
U2
L6910
PWRGD
R
TERMINATION
NETWORK
BUS
STS11NF3LL
DDR
MEMORY
CHIPSET
+
VREF
13
14
10
11
3
1
6
12
5
4
2
15
7
9
VCC
GND
VREF
SS
OSC
OCSET
UGATE
PHASE
LGATE
PGND
PGOOD
VFB
COMP
VIN
12V
8
EAREF
BOOT
13
14
10
11
3
1
PWRGD
6
12
5
4
2
15
7
9
VCC
GND
VREF
SS
OSC
OCSET
UGATE
PHASE
LGATE
PGND
PGOOD
VFB
COMP
8
EAREF
BOOT STS8DNF3LL
STS11NF3LL
R
+
-
VDDQ
2.5V@15A
VTT
1.25V@ - 5A
VIN
12V
U1
L6910
U2
L6910
PWRGD
R
TERMINATION
NETWORK
BUS
STS11NF3LL
DDR
MEMORY
CHIPSET
+
VREF
13
14
10
11
3
1
6
12
5
4
2
15
7
9
VCC
GND
VREF
SS
OSC
OCSET
UGATE
PHASE
LGATE
PGND
PGOOD
VFB
COMP
VIN
12V
8
EAREF
BOOT
13
14
10
11
3
1
PWRGD
6
12
5
4
2
15
7
9
VCC
GND
VREF
SS
OSC
OCSET
UGATE
PHASE
LGATE
PGND
PGOOD
VFB
COMP
8
EAREF
BOOT STS8DNF3LL
STS11NF3LL
R
+
-
VDDQ
2.5V@15A
VTT
1.25V@ - 5A
VIN
12V
U1
L6910
U2
L6910
PWRGD
R
TERMINATION
NETWORK
BUS
STS11NF3LL
DDR
MEMORY
CHIPSET
+
§ 88288 // Fn‘ 7o 55 7 so i i i i r r r r , r 1 2 a 4 5 a 7 5 Onlplli Cum-m mm Figure 25- Efficiency VS UMP“l CUTTEM Sink Figure 28. Efficiency vs Output Current Source Mode Mode For very big systems (e.g. servers), the DDR memory termination can require much higher currents, in the @199 01 10/“ 5A and more. _ _ Figure 29. Efficiency vs Output Current Source Figures 26, 27 and 28, 29 show the effrcrency oi the Made L6910 in sink and source mode, up to 17A both ior DDHI and DDRII memoriesThe measurements have been re alized with the 15A demo board. (See pag.11 ) Figure 26. Efficiency vs Output Current Sink Mode fi 21/29
21/29
L6910 - L6910A
Figure 24. Efficiency vs Output Current Source
Mode
Figure 25. Efficiency vs Output Current Sink
Mode
For very big systems (e.g. servers), the DDR memory
termination can require much higher currents, in the
range of 10A-15A and more.
Figures 26, 27 and 28, 29 show the efficiency of the
L6910 in sink and source mode, up to 17A both for DDRI
and DDRII memories.The measurements have been re-
alized with the 15A demo board. (See pag.11 )
Figure 26. Efficiency vs Output Current Sink
Mode
Figure 27. Efficiency vs Output Current Sink
Mode
Figure 28. Efficiency vs Output Current Source
Mode
Figure 29. Efficiency vs Output Current Source
Mode
8
60
65
70
75
80
85
90
95
1234567
Efficiency (%)
Output Current (A)
Vin=12V
Vin=2.5V
Vcc=12V
Vout=1.25V
Fsw=200KHz
8
60
65
70
75
80
85
90
95
1234567 8
60
65
70
75
80
85
90
95
1234567
Efficiency (%)
Output Current (A)
Vin=12V
Vin=2.5V
Vcc=12V
Vout=1.25V
Fsw=200KHz
60
65
70
75
80
85
90
95
12345678
Vin=12V
Vin=2.5V
Vcc=12V
Vout=1.25V
Fsw=200KHz
Output Current (A)
Efficiency (%)
60
65
70
75
80
85
90
95
12345678
Vin=12V
Vin=2.5V
Vcc=12V
Vout=1.25V
Fsw=200KHz
Output Current (A)
Efficiency (%)
Vin=12V
Vin=2.5V
Vcc=12V
Vout=1.25V
Fsw=200KHz
Output Current (A)
Efficiency (%)
Vin=12V
50
60
70
80
90
100
1357911131517
Vin=2.5V
Vin=12V
Vcc=12V
Vout=1.25V
Fsw=200KHz
Efficiency (%)
Output Current (A)
Vin=12V
50
60
70
80
90
100
1357911131517
Vin=2.5V
Vin=12V
Vcc=12V
Vout=1.25V
Fsw=200KHz
Efficiency (%)
Output Current (A)
50
60
70
80
90
100
1357911131517
Vin=2.5V
Vin=12V
Vcc=12V
Vout=1.25V
Fsw=200KHz
Efficiency (%)
Output Current (A)
Vin=2.5V
Vin=12V
Vcc=12V
Vout=1.25V
Fsw=200KHz
Efficiency (%)
Output Current (A)
40
50
60
70
80
90
100
1 3 5 7 9 11 13 15 17
Vin=12V
Vin=1.8V
Vcc=12V
Vout=0.9V
Fsw=200KHz
Output Current (A)
Efficiency (%)
40
50
60
70
80
90
100
1 3 5 7 9 11 13 15 17
Vin=12V
Vin=1.8V
Vcc=12V
Vout=0.9V
Fsw=200KHz
40
50
60
70
80
90
100
1 3 5 7 9 11 13 15 17
40
50
60
70
80
90
100
1 3 5 7 9 11 13 15 17
Vin=12V
Vin=1.8V
Vcc=12V
Vout=0.9V
Fsw=200KHz
Output Current (A)
Efficiency (%)
50
60
70
80
90
100
1357911131517
Vout=12V
Vcc=12V
Vout=1.25V
Fsw=200KHz
Vout=2.5V
Efficiency (%)
Output Current (A)
50
60
70
80
90
100
1357911131517
Vout=12V
Vcc=12V
Vout=1.25V
Fsw=200KHz
Vout=2.5V
Efficiency (%)
Output Current (A)
50
60
70
80
90
100
1357911131517
Vin=12V
Vout=0.9V
Fsw=200KHz
Vin=12V
Vin=1.8V
Efficiency (%)
Output Current (A)
50
60
70
80
90
100
1357911131517
Vin=12V
Vout=0.9V
Fsw=200KHz
Vin=12V
Vin=1.8V
50
60
70
80
90
100
1357911131517
Vin=12V
Vout=0.9V
Fsw=200KHz
Vin=12V
Vin=1.8V
Efficiency (%)
Output Current (A)
vw \nv 5v 12v W5; Guam vcc MN m 01- i emf 2229 ‘7]
L6910 - L6910A
22/29
10 APPLICATION IDEA 2: POSITIVE BUCK-BOOST REGULATOR 3V TO 13.2V
INPUT / 5V 2.5A OUTPUT
In some applications the input voltage changes in a very wide range while the output must be regulated to a
fixed value. In this case a Buck-Boost topology can be required in order to keep the output voltage in regulation.
The schematic below shows how to implement a Buck-Boost regulating 5V at the output from both 3.3V and 5V
and 12V input buses.
In a Buck-Boost topology the current is delivered to the output during the OFF phase only. So, for a given current
limit, the maximum output current depends strongly on the duty cycle. Assuming a 100% efficiency and neglect-
ing the current ripple across the inductor, the relationship betweent the current limit and the maximum output
current is the following:
Where I
LIM
is the current limit and D is the duty cycle of the application.
The worst case is with D
MAX
. Since, in a Buck-Boost application, D is given by the following formula:
The worst case is with V
INMIN
.
Obviously, since the efficiency is lower than 100% and the ripple is usually not negligible, the maximum output
current is always lower than the value calculated in the above formula
Figure 30. Positive buck-boost regulator 3V to 13.2V input / 5V 2.5A Output Circuit
IOMAX ILIM 1D–()⋅=
DVO
VIN VO
+
-----------------------=
L1
R1
C1- C2
C3
Q2Q2
Q1
D2
C6
13
14
10
11
3
1
U1
L6910/A
VIN (3.3V-5V-12V BUSES)
VOUT ( 5V 2.5A )
6
12
5
4
2
15
7
9
VCC
GND
VREF
SS
OSC
OCSET
UGATE
PHASE
LGATE
PGND
PGOOD
VFB
COMP
C9
C8
C4
D1
-14
C13-14
C13
GNDOUT
R2
C12
C7C7
C5
R7
C10
8
GNDINGNDIN
VCC (12V BUS)
R5
G1
R6
EAREF
BOOT
Q3
Q4
R3
R4 C11
GNDCCGNDCC
man (no Enicioncy (%) on O 75 VDc:5V 7o Vomzfiv st:ZODKHz 65 1 1 .5 2 2.5 3 cunpm Curran: (A)
23/29
L6910 - L6910A
Table 13. Part List
Figure 31. Efficiency vs. Output Current
Reference Description Manufacturer
R1 910 Ohm 5% 125mW NEOHM SMD 0805
R2 10K 5% 125mW NEOHM SMD 0805
R3 4.7K 5% 125mW NEOHM SMD 0805
R4 1K 5% 125mW NEOHM SMD 0805
R5 2.7K 5% 125mW NEOHM SMD 0805
R6 1K1 NEOHM SMD 0805
R7 10 Ohm 125mW NEOHM SMD 0805
C1,C2 100µF - 20V OSCON 20SA100M RADIAL 10X10.5
C13,C14 330µF - 6.3V POSCAP 6TPB330M SMD7343
C12,C5,C8 100nF KEMET SMD0805
C3 1nF KEMET SMD0805
C4 470nF KEMET SMD0805
C6 4.7µF - 16V AUX SMA6032
C7 100nF KEMET
C9 15nF KEMET SMD0805
C10 1.5nF KEMET SMD0805
C11 47nF KEMET SMD0805
G1 Open Jumper
L1 2.5µH
(77121A7 Core, Double winding 7 AWG16)
MAGNETICS
Q1,Q2,Q3 STS11NF30L ST SO8
Q4 STS5P30L ST SO8
D1 1N4148 SOT23
D2 STPS3L25U (STPS340U) ST SMB (D0144)
U1 Device L6910 ST SO16 Narrow
65
70
75
80
85
90
1 1.5 2 2.5 3 3.5
Output Current (A)
Efficiency (%)
Vcc=5V
Vout=5V
Fsw=200KHz
Vin=12V
Vin=5V
Vin=3.3V
65
70
75
80
85
90
1 1.5 2 2.5 3 3.5
Output Current (A)
Efficiency (%)
Vcc=5V
Vout=5V
Fsw=200KHz
Vin=12V
Vin=5V
Vin=3.3V
vm (3v «5 my m GMDIM=ENDO|N o vcusv) of N La“. '1' vmmevaA! fl Table 14. Part List Reference Description Manufacturer R1 910 0m 5% 125mw NEOHM SMD 0505 R2 10K 5% 125mW NEOHM SMD 0505 R3 4.7K 5% 125mw NEOHM SMD 0505 R4 1K Ohm 5% 125mw NEOHM SMD 0505 R5 2.7K 5% 125mw NEOHM SMD 0505 R6 m 5% ‘25mW NEOHM SMD 0505 R7 10 Ohm 5% 125mW NEOHM SMD 0505 c‘ ,02 wow - 20v OSCON ZOSA‘OOM HAmAL mm 0 0 mm 330W - 5.5V POSCAP 6TPBBBOM SMD7045 0‘2,C4,C5‘08 100nF KEMET SMD0805 03 1nF KEMET SMD0805 Ce 4,7uF - ‘ev AUX SMA6032 c7 100nF KEMET 24/29 E
L6910 - L6910A
24/29
11 APPLICATION IDEA 3: BUCK-BOOST REGULATOR 3V TO 5.5V INPUT/-5V
3A OUTPUT
In applications where a negative output voltage is required, a standard Buck-Boost topology can be implement-
ed. The considerations related to the maximum output current are the same of the "Positive Buck-Boost" (Ap-
plication Idea 2).
A particularity of this topology is that the device undergoes a voltage that is the sum of V
IN
and V
OUT
. So, con-
verting 5V to -5V, the device undergoes 10V voltage. It must be checked that the sum of the input and output
voltage is lower than the maximum operating input voltage of the device.
Figure 32. buck-boost regulator 3V to 5.5V input / -5V 3A Output Circuit
Table 14. Part List
Reference Description Manufacturer
R1 910 Ohm 5% 125mW NEOHM SMD 0805
R2 10K 5% 125mW NEOHM SMD 0805
R3 4.7K 5% 125mW NEOHM SMD 0805
R4 1K Ohm 5% 125mW NEOHM SMD 0805
R5 2.7K 5% 125mW NEOHM SMD 0805
R6 1K 5% 125mW NEOHM SMD 0805
R7 10 Ohm 5% 125mW NEOHM SMD 0805
C1,C2 100µF - 20V OSCON 20SA100M RADIAL 10X10.5
C13,C14 330µF - 6.3V POSCAP 6TPB330M SMD7343
C12,C4,C5,C8 100nF KEMET SMD0805
C3 1nF KEMET SMD0805
C6 4.7µF - 16V AUX SMA6032
C7 100nF KEMET
L1
R1
C1- C2
C3
C13
-
14
Q2
Q1
D2
C6
13
14
10
11
3
1
U1
L6910/A
VIN (3V to 5.5V )
VOUT (-5V 3A)
6
12
5
4
2
15
7
9
VCC
GND
VREF
SS
OSC
OCSET
UGATE
PHASE
LGATE
PGND
PGOOD
VFB
COMP
C9
C8
C4
D1
GNDOUT
C7
C5
R7
C10
C12
8
GNDIN=GNDOUT
R5
R3
R4 C11
R6
EAREF
BOOT
G1
VCC (5V)
GNDCC
L1
R1
C1- C2
C3
C13
-
14
Q2
Q1
D2
C6
13
14
10
11
3
1
U1
L6910/A
VIN (3V to 5.5V )
VOUT (-5V 3A)
6
12
5
4
2
15
7
9
VCC
GND
VREF
SS
OSC
OCSET
UGATE
PHASE
LGATE
PGND
PGOOD
VFB
COMP
C9
C8
C4
D1
GNDOUT
C7
C5
R7
C10
C12
8
GNDIN=GNDOUT
R5
R3
R4 C11
R6
EAREF
BOOT
G1
VCC (5V)
GNDCC
L1
R1
C1- C2C1- C2
C3
C13
-
14
Q2
Q1
D2
C6
13
14
10
11
3
1
U1
L6910/A
VIN (3V to 5.5V )
VOUT (-5V 3A)
6
12
5
4
2
15
7
9
VCC
GND
VREF
SS
OSC
OCSET
UGATE
PHASE
LGATE
PGND
PGOOD
VFB
COMP
C9
C8C8
C4
D1
GNDOUTGNDOUT
C7C7
C5
R7
C10
C12C12
8
GNDIN=GNDOUT
R5
R3
R4 C11
R6
EAREF
BOOT
G1
VCC (5V)
GNDCC
‘21A7 Core, Double wmdmg 7 AWG‘ 5) MAGNETICS STS‘ 1 NFBOL ST 808 1N4‘48 SOTZB STPSBLZSU (STPSB4OU) ST SMB (D0144) Dewce L69‘O ST SO‘6 Narrow vs. Output Currem Efllclency (m Vcc=5v Vnul: -5v st=2n0KHz I 1 5 2 2.5 ompm Current (A)
25/29
L6910 - L6910A
Figure 33. Efficiency vs. Output Current
C9 15nF KEMET SMD0805
C10 1.5nF KEMET SMD0805
Reference Description Manufacturer
C11 47nF KEMET SMD0805
G1 Open Jumper
L1 2.5µH (77121A7 Core, Double winding 7 AWG16) MAGNETICS
Q1,Q2 STS11NF30L ST SO8
D1 1N4148 SOT23
D2 STPS3L25U ( STPS340U) ST SMB (D0144)
U1 Device L6910 ST SO16 Narrow
Table 14. Part List (continued)
82
84
86
88
90
92
94
11.522.53
Output Current (A)
Efficiency (%)
Vcc=5V
Vout= -5V
Fsw=200KHz
Vin=5V
Vin=3.3V
82
84
86
88
90
92
94
11.522.53
Output Current (A)
Efficiency (%)
Vcc=5V
Vout= -5V
Fsw=200KHz
Vin=5V
Vin=3.3V
D1 SEAT‘NG PLANE TE 0,25 mm GAUGE PLANE _\ g1 NOUVUHUNEW L Md E1 0m-
L6910 - L6910A
26/29
Figure 34. HTSSOP16 (Exposed pad) Mechanical Data & Package Dimensions
OUTLINE AND
MECHANICAL DATA
DIM.
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A1.20.047
A1 0.15 0.006
A2 0.8 1.0 1.05 0.031 0.039 0.041
b 0.19 0.3 0.007 0.012
c 0.09 0.2 0.003 0.008
D (*) 4.9 5.0 5.1 0.192 0.197 0.200
D1 1.7 0.067
E 6.2 6.4 6.6 0.244 0.252 0.260
E1 (*) 4.3 4.4 4.5 0.169 0.173 0.177
E2 1.5 0.059
e 0.65 0.026
L 0.45 0.6 0.75 0.018 0.024 0.029
L1 1.0 0.039
k 0˚ (min), 8˚ (max)
aaa 0.10 0.004
(*)
Dimensions D and E1 does not include mold flash or
protusions. Mold flash or protusions shall not exeed
0.15mm per side.
HTSSOP16
7419276
(Exposed Pad)
LHe
27/29
L6910 - L6910A
Figure 35. SO-16 (Narrow) Mechanical Data & Package Dimensions
OUTLINE AND
MECHANICAL DATA
DIM.
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 1.75 0.069
a1 0.1 0.25 0.004 0.009
a2 1.6 0.063
b 0.35 0.46 0.014 0.018
b1 0.19 0.25 0.007 0.010
C 0.5 0.020
c1 45°(typ.)
D(1) 9.8 10 0.386 0.394
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 8.89 0.350
F(1) 3.8 4.0 0.150 0.157
G 4.60 5.30 0.181 0.208
L 0.4 1.27 0.150 0.050
M 0.62 0.024
S8° (max.)
(1) "D" and "F" do not include mold flash or protrusions - Mold
flash or protrusions shall not exceed 0.15mm (.006inc.)
SO16 (Narrow)
0016020 D
L6910 - L6910A
28/29
Table 1. Revision History
Date Revision Description of Changes
January 2004 7 Migration from ST-Press to EDOCS dms.
August 2004 8 Changed any figures and textes; add. the section “15A HTSSOP16
Demo Board Description”.
Changed the style-look following the new “Corporate Technical
Pubblications Design Guide” rules; and figs 23, 30, 32
May 2005 9 Changed the figure 30.
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2005 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
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Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
29/29
L6910 - L6910A

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