LPC1110-15 Datasheet by NXP USA Inc.

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Section 16 “References"
1. General description
The LPC1110/11/12/13/14/15 are an ARM Cortex-M0 based, low-cost 32-bit MCU family,
designed for 8/16-bit microcontroller applications, offering performance, low power, simple
instruction set and memory addressing together with reduced code size compared to
existing 8/16-bit architectures.
The LPC1110/11/12/13/14/15 operate at CPU frequencies of up to 50 MHz.
The peripheral complement of the LPC1110/11/12/13/14/15 includes up to 64 kB of flash
memory, up to 8 kB of data memory, one Fast-mode Plus I2C-bus interface, one
RS-485/EIA-485 UART, up to two SPI interfaces with SSP features, four general purpose
counter/timers, a 10-bit ADC, and up to 42 general purpose I/O pins.
Remark: The LPC111x series consists of the LPC1100 series (parts
LPC111x/101/201/301), LPC1100L series (parts LPC111x/002/102/202/302), and the
LPC1100XL series (parts LPC111x/103/203/303/323/333). The LPC1100L and
LPC1100XL series include the power profiles, a windowed watchdog timer, and a
configurable open-drain mode.
For related documentation, see Section 16 “References”.
2. Features and benefits
System:
ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.
ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).
Non-Maskable Interrupt (NMI) input selectable from several input sources
(LPC1100XL series only).
Serial Wire Debug.
System tick timer.
Memory:
64 kB (LPC1115), 56 kB (LPC1114/333), 48 kB (LPC1114/323), 32 kB
(LPC1114/102/201/202/203/301/302/303), 24 kB (LPC1113), 16 kB (LPC1112),
8 kB (LPC1111), or 4 kB (LPC1110) on-chip flash programming memory.
256 byte page erase function (LPC1100XL series only)
8 kB, 4 kB, 2 kB, or 1 kB SRAM.
In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
bootloader software.
LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller; up to 64 kB flash and
8 kB SRAM
Rev. 9.2 — 26 March 2014 Product data sheet
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 2 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Digital peripherals:
Up to 42 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down
resistors. In addition, a configurable open-drain mode is supported on the
LPC1100L and LPC1100XL series.
GPIO pins can be used as edge and level sensitive interrupt sources.
High-current output driver (20 mA) on one pin.
High-current sink drivers (20 mA) on two I2C-bus pins in Fast-mode Plus (not on
LPC1112FDH20/102).
Four general purpose counter/timers with up to eight capture inputs and up to 13
match outputs.
Programmable WatchDog Timer (WDT) the LPC1100 series only.
Programmable windowed WDT on the LPC1100L and LPC1100XL series only.
Analog peripherals:
10-bit ADC with input multiplexing among 5, 6, or 8 pins depending on package
size.
Serial interfaces:
UART with fractional baud rate generation, internal FIFO, and RS-485 support.
Two SPI controllers with SSP features and with FIFO and multi-protocol
capabilities (second SPI on LPC1100 and LPC1100L series LQFP48 package
only).
I2C-bus interface supporting full I2C-bus specification and Fast-mode Plus with a
data rate of 1 Mbit/s with multiple address recognition and monitor mode (not on
LPC1112FDH20/102).
Clock generation:
12 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used
as a system clock.
Crystal oscillator with an operating range of 1 MHz to 25 MHz.
Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz.
PLL allows CPU operation up to the maximum CPU rate without the need for a
high-frequency crystal. May be run from the system oscillator or the internal RC
oscillator.
Clock output function with divider that can reflect the system oscillator clock, IRC
clock, CPU clock, and the Watchdog clock.
Power control:
Integrated PMU (Power Management Unit) to minimize power consumption during
Sleep, Deep-sleep, and Deep power-down modes.
Power profiles residing in boot ROM allowing to optimize performance and
minimize power consumption for any given application through one simple function
call. (LPC1100L and LPC1100XL series only.)
Three reduced power modes: Sleep, Deep-sleep, and Deep power-down.
Processor wake-up from Deep-sleep mode via a dedicated start logic using up to
13 of the functional pins.
Power-On Reset (POR).
Brownout detect with up to four separate thresholds for interrupt and forced reset.
Unique device serial number for identification.
Single power supply (1.8 V to 3.6 V).
Available as LQFP48 package, HVQFN33 package, and TFBGA48 package.
Table 2
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 3 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
LPC1100L series available as TSSOP28 package, DIP28 package, TSSOP20
package, and SO20 package.
Extended temperature (40 C to +105 C) for selected parts (see Table 2).
3. Applications
4. Ordering information
eMetering Lighting
Alarm systems White goods
Table 1. Ordering information
Type number Package
Name Description Version
SO20, TSSOP20, TSSOP28, and DIP28 packages
LPC1110FD20 SO20 SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
LPC1111FDH20/002 TSSOP20 TSSOP20: plastic thin shrink small outline package; 20 leads; body
width 4.4 mm SOT360-1
LPC1112FD20/102 SO20 SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
LPC1112FDH20/102 TSSOP20 TSSOP20: plastic thin shrink small outline package; 20 leads; body
width 4.4 mm SOT360-1
LPC1112FDH28/102 TSSOP28 TSSOP28: plastic thin shrink small outline package; 28 leads; body
width 4.4 mm SOT361-1
LPC1114FDH28/102 TSSOP28 TSSOP28: plastic thin shrink small outline package; 28 leads; body
width 4.4 mm SOT361-1
LPC1114FN28/102 DIP28 DIP28: plastic dual in-line package; 28 leads (600 mil) SOT117-1
HVQFN24/33, LQFP48, and TFBGA48 packages
LPC1111FHN33/101 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC1111FHN33/102 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC1111FHN33/201 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC1111FHN33/202 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC1111FHN33/103 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC1111JHN33/103 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC1111FHN33/203 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC1111JHN33/203 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC1112FHN33/101 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC1112FHN33/102 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 4 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
LPC1112FHN33/201 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC1112FHN33/202 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC1112FHN24/202 HVQFN24 HVQFN24: plastic thermal enhanced very thin quad flat package; no
leads; 24 terminals; body 4 x 4 x 0.85 mm SOT616-3
LPC1112FHI33/102 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 5 5 0.85 mm n/a
LPC1112FHI33/202 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 5 5 0.85 mm n/a
LPC1112FHI33/203 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 5 5 0.85 mm n/a
LPC1112JHI33/203 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 5 5 0.85 mm n/a
LPC1112FHN33/103 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC1112JHN33/103 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC1112JHN33/203 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC1112FHN33/203 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC1113FHN33/201 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC1113FHN33/202 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC1113FHN33/203 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC1113JHN33/203 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC1113FHN33/301 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC1113FHN33/302 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC1113FHN33/303 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC1113JHN33/303 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC1114FHN33/201 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC1114FHN33/202 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC1114FHN33/301 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC1114FHN33/302 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
Table 1. Ordering information …continued
Type number Package
Name Description Version
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 5 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
LPC1114FHI33/302 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 5 5 0.85 mm n/a
LPC1114FHI33/303 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 5 5 0.85 mm n/a
LPC1114JHI33/303 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 5 5 0.85 mm n/a
LPC1114FHN33/203 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC1114JHN33/203 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC1114FHN33/303 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC1114JHN33/303 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC1114FHN33/333 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC1114JHN33/333 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 7 7 0.85 mm n/a
LPC1113FBD48/301 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 7
1.4 mm SOT313-2
LPC1113FBD48/302 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 7
1.4 mm SOT313-2
LPC1113FBD48/303 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 7
1.4 mm SOT313-2
LPC1113JBD48/303 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 7
1.4 mm SOT313-2
LPC1114FBD48/301 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 7
1.4 mm SOT313-2
LPC1114FBD48/302 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 7
1.4 mm SOT313-2
LPC1114FBD48/303 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 7
1.4 mm SOT313-2
LPC1114JBD48/303 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 7
1.4 mm SOT313-2
LPC1114FBD48/323 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 7
1.4 mm SOT313-2
LPC1114JBD48/323 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 7
1.4 mm SOT313-2
LPC1114FBD48/333 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 7
1.4 mm SOT313-2
LPC1114JBD48/333 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 7
1.4 mm SOT313-2
LPC1115FBD48/303 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 7
1.4 mm SOT313-2
Table 1. Ordering information …continued
Type number Package
Name Description Version
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 6 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
4.1 Ordering options
LPC1115JBD48/303 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 7
1.4 mm SOT313-2
LPC1115FET48/303 TFBGA48 plastic thin fine-pitch ball grid array package; 48 balls; body 4.5 4.5
0.7 mm SOT1155-2
LPC1115JET48/303 TFBGA48 plastic thin fine-pitch ball grid array package; 48 balls; body 4.5 4.5
0.7 mm SOT1155-2
Table 1. Ordering information …continued
Type number Package
Name Description Version
Table 2. Ordering options
Type number Series Flash Total
SRAM Power
profiles UART I2C/
Fast+ SPI ADC
channel GPIO Package Temp[1]
LPC1110
LPC1110FD20 LPC1100L 4 kB 1 kB yes 1 1 1 5 16 SO20 F
LPC1111
LPC1111FDH20/002 LPC1100L 8 kB 2 kB yes 1 1 1 5 16 TSSOP20 F
LPC1111FHN33/101 LPC1100 8 kB 2 kB no 1 1 1 8 28 HVQFN33 F
LPC1111FHN33/102 LPC1100L 8 kB 2 kB yes 1 1 1 8 28 HVQFN33 F
LPC1111FHN33/103 LPC1100XL 8 kB 2 kB yes 1 1 2 8 28 HVQFN33 F
LPC1111JHN33/103 LPC1100XL 8 kB 2 kB yes 1 1 2 8 28 HVQFN33 J
LPC1111FHN33/201 LPC1100 8 kB 4 kB no 1 1 1 8 28 HVQFN33 F
LPC1111FHN33/202 LPC1100L 8 kB 4 kB yes 1 1 1 8 28 HVQFN33 F
LPC1111FHN33/203 LPC1100XL 8 kB 4 kB yes 1 1 2 8 28 HVQFN33 F
LPC1111JHN33/203 LPC1100XL 8 kB 4 kB yes 1 1 2 8 28 HVQFN33 J
LPC1112
LPC1112FD20/102 LPC1100L 16 kB 4 kB yes 1 1 1 5 16 SO20 F
LPC1112FDH20/102 LPC1100L 16 kB 4 kB yes 1 - 1 5 14 TSSOP20 F
LPC1112FDH28/102 LPC1100L 16 kB 4 kB yes 1 1 1 6 22 TSSOP28 F
LPC1112FHN24/202 LPC1100L 16 kB 4 kB yes 1 1 1 6 19 HVQFN24 F
LPC1112FHN33/101 LPC1100 16 kB 2 kB no 1 1 1 8 28 HVQFN33 F
LPC1112FHN33/102 LPC1100L 16 kB 2 kB yes 1 1 1 8 28 HVQFN33 F
LPC1112FHN33/103 LPC1100XL 16 kB 2 kB yes 1 1 2 8 28 HVQFN33 F
LPC1112JHN33/103 LPC1100XL 16 kB 2 kB yes 1 1 2 8 28 HVQFN33 J
LPC1112FHN33/201 LPC1100 16 kB 4 kB no 1 1 1 8 28 HVQFN33 F
LPC1112FHN33/202 LPC1100L 16 kB 4 kB yes 1 1 1 8 28 HVQFN33 F
LPC1112FHN33/203 LPC1100XL 16 kB 4 kB yes 1 1 2 8 28 HVQFN33 F
LPC1112JHN33/203 LPC1100XL 16 kB 4 kB yes 1 1 2 8 28 HVQFN33 J
LPC1112FHI33/102 LPC1100L 16 kB 2 kB yes 1 1 1 8 28 HVQFN33 F
LPC1112FHI33/202 LPC1100L 16 kB 4 kB yes 1 1 1 8 28 HVQFN33 F
LPC1112FHI33/203 LPC1100XL 16 kB 4 kB yes 1 1 2 8 28 HVQFN33 F
LPC1112JHI33/203 LPC1100XL 16 kB 4 kB yes 1 1 2 8 28 HVQFN33 J
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 7 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
LPC1113
LPC1113FHN33/201 LPC1100 24 kB 4 kB no 1 1 1 8 28 HVQFN33 F
LPC1113FHN33/202 LPC1100L 24 kB 4 kB yes 1 1 1 8 28 HVQFN33 F
LPC1113FHN33/203 LPC1100XL 24 kB 4 kB yes 1 1 2 8 28 HVQFN33 F
LPC1113JHN33/203 LPC1100XL 24 kB 4 kB yes 1 1 2 8 28 HVQFN33 J
LPC1113FHN33/301 LPC1100 24 kB 8 kB no 1 1 1 8 28 HVQFN33 F
LPC1113FHN33/302 LPC1100L 24 kB 8 kB yes 1 1 1 8 28 HVQFN33 F
LPC1113FHN33/303 LPC1100XL 24 kB 8 kB yes 1 1 2 8 28 HVQFN33 F
LPC1113JHN33/303 LPC1100XL 24 kB 8 kB yes 1 1 2 8 28 HVQFN33 J
LPC1113FBD48/301 LPC1100 24 kB 8 kB no 1 1 2 8 42 LQFP48 F
LPC1113FBD48/302 LPC1100L 24 kB 8 kB yes 1 1 2 8 42 LQFP48 F
LPC1113FBD48/303 LPC1100XL 24 kB 8 kB yes 1 1 2 8 42 LQFP48 F
LPC1113JBD48/303 LPC1100XL 24 kB 8 kB yes 1 1 2 8 42 LQFP48 J
LPC1114
LPC1114FDH28/102 LPC1100L 32 kB 4 kB yes 1 1 1 6 22 TSSOP28 F
LPC1114FN28/102 LPC1100L 32 kB 4 kB yes 1 1 1 6 22 DIP28 F
LPC1114FHN33/201 LPC1100 32 kB 4 kB no 1 1 1 8 28 HVQFN33 F
LPC1114FHN33/202 LPC1100L 32 kB 4 kB yes 1 1 1 8 28 HVQFN33 F
LPC1114FHN33/203 LPC1100XL 32 kB 4 kB yes 1 1 2 8 28 HVQFN33 F
LPC1114JHN33/203 LPC1100XL 32 kB 4 kB yes 1 1 2 8 28 HVQFN33 J
LPC1114FHN33/301 LPC1100 32 kB 8 kB no 1 1 1 8 28 HVQFN33 F
LPC1114FHN33/302 LPC1100L 32 kB 8 kB yes 1 1 1 8 28 HVQFN33 F
LPC1114FHN33/303 LPC1100XL 32 kB 8 kB yes 1 1 2 8 28 HVQFN33 F
LPC1114JHN33/303 LPC1100XL 32 kB 8 kB yes 1 1 2 8 28 HVQFN33 J
LPC1114FHN33/333 LPC1100XL 56 kB 8 kB yes 1 1 2 8 28 HVQFN33 F
LPC1114JHN33/333 LPC1100XL 56 kB 8 kB yes 1 1 2 8 28 HVQFN33 J
LPC1114FHI33/302 LPC1100L 32 kB 8 kB yes 1 1 1 8 28 HVQFN33 F
LPC1114FHI33/303 LPC1100XL 32 kB 8 kB yes 1 1 2 8 28 HVQFN33 F
LPC1114JHI33/303 LPC1100XL 32 kB 8 kB yes 1 1 2 8 28 HVQFN33 J
LPC1114FBD48/301 LPC1100 32 kB 8 kB no 1 1 2 8 42 LQFP48 F
LPC1114FBD48/302 LPC1100L 32 kB 8 kB yes 1 1 2 8 42 LQFP48 F
LPC1114FBD48/303 LPC1100XL 32 kB 8 kB yes 1 1 2 8 42 LQFP48 F
LPC1114JBD48/303 LPC1100XL 32 kB 8 kB yes 1 1 2 8 42 LQFP48 J
LPC1114FBD48/323 LPC1100XL 48 kB 8 kB yes 1 1 2 8 42 LQFP48 F
LPC1114JBD48/323 LPC1100XL 48 kB 8 kB yes 1 1 2 8 42 LQFP48 J
LPC1114FBD48/333 LPC1100XL 56 kB 8 kB yes 1 1 2 8 42 LQFP48 F
LPC1114JBD48/333 LPC1100XL 56 kB 8 kB yes 1 1 2 8 42 LQFP48 J
LPC1115
LPC1115FBD48/303 LPC1100XL 64 kB 8 kB yes 1 1 2 8 42 LQFP48 F
Table 2. Ordering options …continued
Type number Series Flash Total
SRAM Power
profiles UART I2C/
Fast+ SPI ADC
channel GPIO Package Temp[1]
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 8 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
[1] F = 40 C to +85 C, J = 40 C to +105 C.
LPC1115JBD48/303 LPC1100XL 64 kB 8 kB yes 1 1 2 8 42 LQFP48 J
LPC1115FET48/303 LPC1100XL 64 kB 8 kB yes 1 1 2 8 42 TFBGA48 F
LPC1115JET48/303 LPC1100XL 64 kB 8 kB yes 1 1 2 8 42 TFBGA48 J
Table 2. Ordering options …continued
Type number Series Flash Total
SRAM Power
profiles UART I2C/
Fast+ SPI ADC
channel GPIO Package Temp[1]
\f‘f‘r‘f
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 9 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
5. Block diagram
(1) LQFP48 packages only.
(2) Not on LPC1112FDH20/102.
(3) All pins available on LQFP48 and HVQFN33 packages. CT16B1_MAT1 not available on TSSOP28/DIP28 packages.
CT32B1_MAT3, CT16B1_CAP0, CT16B1_MAT[1:0], CT32B0_CAP0 not available on TSSOP20/SO20 packages.
CT16B1_MAT[1:0], CT32B0_CAP0 not available on the HVQFN24 package. XTALOUT not available on LPC1112FHN24.
(4) AD[7:0] available on LQFP48 and HVQFN33 packages. AD[5:0] available on TSSOP28/DIP28 packages. AD[4:0] available on
TSSOP20/SO20 packages.
(5) All pins available on LQFP48 packages. RXD, TXD, DTR, CTS, RTS available on HVQFN 33 packages. RXD, TXD, CTS, RTS
available on TSSOP28/DIP28 packages. RXD, TXD, CTS available on HVQFN24 packages. RXD, TXD available on
TSSOP20/SO20 packages.
Fig 1. LPC1100/LPC1100L series block diagram
SRAM
1/2/4/8 kB
ARM
CORTEX-M0
TEST/DEBUG
INTERFACE
FLASH
4/8/16/24/32 kB
HIGH-SPEED
GPIO
AHB TO APB
BRIDGE
CLOCK
GENERATION,
POWER CONTROL,
SYSTEM
FUNCTIONS
XTALIN
XTALOUT(3) RESET
clocks and
controls
SWD
LPC1110/11/12/13/14
002aae696
slave
slave
slave slave
ROM
slave
AHB-LITE BUS
GPIO ports
PIO0/1/2/3
CLKOUT
IRC
POR
SPI0
10-bit ADC
UART
32-bit COUNTER/TIMER 0
I2C-BUS(2)
WDT
IOCONFIG
CT32B0_MAT[3:0](3)
AD[7:0](4)
CT32B0_CAP0(3)
SDA
SCL
RXD
TXD
DTR, DSR, CTS(5),
DCD, RI, RTS(5)
SYSTEM CONTROL
PMU
32-bit COUNTER/TIMER 1
CT32B1_MAT[3:0](3)
CT32B1_CAP0(3)
16-bit COUNTER/TIMER 1
CT16B1_MAT[1:0](3)
CT16B1_CAP0(3)
16-bit COUNTER/TIMER 0
CT16B0_MAT[2:0](3)
CT16B0_CAP0(3)
SCK0, SSEL0
MISO0, MOSI0
SCK1, SSEL1
MISO1, MOSI1
SPI1(1)
system bus
U U
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 10 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
(1) LQFP48 and TFBGA48 only.
Fig 2. LPC1100XL series block diagram
SRAM
2/4/8 kB
ARM
CORTEX-M0
TEST/DEBUG
INTERFACE
FLASH
8/16/24/32/
48/56/64 kB
HIGH-SPEED
GPIO
AHB TO APB
BRIDGE
CLOCK
GENERATION,
POWER CONTROL,
SYSTEM
FUNCTIONS
XTALIN
XTALOUT
RESET
clocks and
controls
SWD
LPC1111/12/13/14/15XL
002aag780
slave
slave
slave slave
ROM
slave
AHB-LITE BUS
GPIO ports
PIO0/1/2/3
CLKOUT
IRC
POR
SPI0
10-bit ADC
UART
32-bit COUNTER/TIMER 0
I2C-BUS
WWDT
IOCONFIG
CT32B0_MAT[3:0]
AD[7:0]
CT32B0_CAP[1:0]
SDA
SCL
RXD
TXD
DTR, DSR(1), CTS,
DCD(1), RI(1), RTS
SYSTEM CONTROL
PMU
32-bit COUNTER/TIMER 1
CT32B1_MAT[3:0]
CT32B1_CAP[1:0]
16-bit COUNTER/TIMER 1
CT16B1_MAT[1:0]
CT16B1_CAP[1:0]
16-bit COUNTER/TIMER 0
CT16B0_MAT[2:0]
CT16B0_CAP[1:0]
SCK0, SSEL0
MISO0, MOSI0
SCK1, SSEL1
MISO1, MOSI1
SPI1
system bus
Table 4 Figure 9 W Figure 9 W Figure 10 W Figure 9 w Figure 11 W Figure 12 W Figure 13 W Figure 13 M Figure 6 M Figure 6 Table 11 Figure 7 Table 11 Figure 7 M Figure 6 M Figure 6 Table 11 Figure 7 Table 11 Figure 7 Table 9 Figure 6 Table 9 Figure 6 Table 11 Figure 7 Table 11 Figure 7 Table 9 Figure 6 Table 9 ' ure 6 Table 11 Figure 7 Table 11 Figure 7 Table 9 Figure 6 Table 11 Figure 7 Table 11 Figure 7 Table 9 Figure 6 Table 9 Figure 6 Table 11 Figure 7 Table 11 Figure 7 Table 9 Figure 6 Table 9 Figure 6 Table 11 Figure 7 Table 11 Figure 7 Table 9 Figure 6 Table 9 Figure 6
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 11 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
6. Pinning information
6.1 Pinning
Table 3. Pin description overview
Part Pin description table Pinning diagram
LPC1110FD20 Table 4 Figure 8
LPC1111FDH20/002 Table 4 Figure 9
LPC1112FD20/102 Table 4 Figure 10
LPC1112FDH20/102 Table 5 Figure 9
LPC1112FHN24/202 Table 6 Figure 11
LPC1112FDH28/102 Table 7 Figure 12
LPC1114FDH28/102 Table 7 Figure 13
LPC1114FN28/102 Table 7 Figure 13
LPC1111FHN33/101 Table 9 Figure 6
LPC1111FHN33/102 Table 9 Figure 6
LPC1111JHN33/103 Table 11 Figure 7
LPC1111FHN33/103 Table 11 Figure 7
LPC1111FHN33/201 Table 9 Figure 6
LPC1111FHN33/202 Table 9 Figure 6
LPC1111FHN33/203 Table 11 Figure 7
LPC1111JHN33/203 Table 11 Figure 7
LPC1112FHN33/101 Table 9 Figure 6
LPC1112FHN33/102 Table 9 Figure 6
LPC1112FHN33/103 Table 11 Figure 7
LPC1112JHN33/103 Table 11 Figure 7
LPC1112FHN33/201 Table 9 Figure 6
LPC1112FHN33/202 Table 9 Figure 6
LPC1112FHN33/203 Table 11 Figure 7
LPC1112JHN33/203 Table 11 Figure 7
LPC1112FHI33/202 Table 9 Figure 6
LPC1112FHI33/203 Table 11 Figure 7
LPC1112JHI33/203 Table 11 Figure 7
LPC1113FHN33/201 Table 9 Figure 6
LPC1113FHN33/202 Table 9 Figure 6
LPC1113FHN33/203 Table 11 Figure 7
LPC1113JHN33/203 Table 11 Figure 7
LPC1113FHN33/301 Table 9 Figure 6
LPC1113FHN33/302 Table 9 Figure 6
LPC1113FHN33/303 Table 11 Figure 7
LPC1113JHN33/303 Table 11 Figure 7
LPC1114FHN33/201 Table 9 Figure 6
LPC1114FHN33/202 Table 9 Figure 6
Table 11 Figure 7 Table 11 Figure 7 Table 9 Figure 6 Table 9 Figure 6 Table 11 Figure 7 Table 11 Figure 7 Table 11 Figure 7 Table 11 Figure 7 Table 9 Figure 6 Table 11 ' ure 7 Table 11 Figure 7 Table 9 Figure 3 Table 9 Figure 3 Table 10 Figure 4 Table 10 Figure 4 Table 9 Figure 3 Table 9 Figure 3 Table 10 Figure 4 Table 10 Figure 4 Table 10 Figure 4 Table 10 Figure 4 Table 10 Figure 4 Table 10 Figure 4 Table 10 Figure 4 Table 10 Figure 4 Table 10 Figure 5 Table 10 Figure 5
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 12 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
LPC1114FHN33/203 Table 11 Figure 7
LPC1114JHN33/203 Table 11 Figure 7
LPC1114FHN33/301 Table 9 Figure 6
LPC1114FHN33/302 Table 9 Figure 6
LPC1114JHN33/303 Table 11 Figure 7
LPC1114FHN33/303 Table 11 Figure 7
LPC1114FHN33/333 Table 11 Figure 7
LPC1114JHN33/333 Table 11 Figure 7
LPC1114FHI33/302 Table 9 Figure 6
LPC1114FHI33/303 Table 11 Figure 7
LPC1114JHI33/303 Table 11 Figure 7
LPC1113FBD48/301 Table 8 Figure 3
LPC1113FBD48/302 Table 8 Figure 3
LPC1113FBD48/303 Table 10 Figure 4
LPC1113JBD48/303 Table 10 Figure 4
LPC1114FBD48/301 Table 8 Figure 3
LPC1114FBD48/302 Table 8 Figure 3
LPC1114FBD48/303 Table 10 Figure 4
LPC1114JBD48/303 Table 10 Figure 4
LPC1114FBD48/323 Table 10 Figure 4
LPC1114JBD48/323 Table 10 Figure 4
LPC1114FBD48/333 Table 10 Figure 4
LPC1114JBD48/333 Table 10 Figure 4
LPC1115FBD48/303 Table 10 Figure 4
LPC1115JBD48/303 Table 10 Figure 4
LPC1115FET48/303 Table 10 Figure 5
LPC1115JET48/303 Table 10 Figure 5
Table 3. Pin description overview
Part Pin description table Pinning diagram
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 13 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Fig 3. LPC1100 and LPC1100L series pin configuration LQFP48 package
LPC1113FBD48/301
LPC1113FBD48/302
LPC1114FBD48/301
LPC1114FBD48/302
PIO2_6 PIO3_0/DTR
PIO2_0/DTR/SSEL1 R/PIO1_2/AD3/CT32B1_MAT1
RESET/PIO0_0 R/PIO1_1/AD2/CT32B1_MAT0
PIO0_1/CLKOUT/CT32B0_MAT2 R/PIO1_0/AD1/CT32B1_CAP0
V
SS
R/PIO0_11/AD0/CT32B0_MAT3
XTALIN PIO2_11/SCK0
XTALOUT PIO1_10/AD6/CT16B1_MAT1
V
DD
SWCLK/PIO0_10/SCK0/CT16B0_MAT2
PIO1_8/CT16B1_CAP0 PIO0_9/MOSI0/CT16B0_MAT1
PIO0_2/SSEL0/CT16B0_CAP0 PIO0_8/MISO0/CT16B0_MAT0
PIO2_7 PIO2_2/DCD/MISO1
PIO2_8 PIO2_10
PIO2_1/DSR/SCK1 PIO3_3/RI
PIO0_3 PIO1_7/TXD/CT32B0_MAT1
PIO0_4/SCL PIO1_6/RXD/CT32B0_MAT0
PIO0_5/SDA PIO1_5/RTS/CT32B0_CAP0
PIO1_9/CT16B1_MAT0 V
DD
PIO3_4 PIO3_2/DCD
PIO2_4 PIO1_11/AD7
PIO2_5 V
SS
PIO3_5 PIO1_4/AD5/CT32B1_MAT3/WAKEUP
PIO0_6/SCK0 SWDIO/PIO1_3/AD4/CT32B1_MAT2
PIO0_7/CTS
PIO2_9
PIO2_3/RI/MOSI1
PIO3_1/DSR
002aae697
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
13
14
15
16
17
18
19
20
21
22
23
48
47
46
45
44
43
42
41
40
39
38
37
24
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 14 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Fig 4. LPC1100XL series pin configuration LQFP48 package
LPC1113, LPC1114, LPC1115
PIO2_6/CT32B0_MAT1 PIO3_0/DTR/CT16B0_MAT0/TXD
PIO2_0/DTR/SSEL1 R/PIO1_2/AD3/CT32B1_MAT1
RESET/PIO0_0 R/PIO1_1/AD2/CT32B1_MAT0
PIO0_1/CLKOUT/CT32B0_MAT2 R/PIO1_0/AD1/CT32B1_CAP0
VSS R/PIO0_11/AD0/CT32B0_MAT3
XTALIN PIO2_11/SCK0/CT32B0_CAP1
XTALOUT PIO1_10/AD6/CT16B1_MAT1/MISO1
VDD SWCLK/PIO0_10/SCK0/CT16B0_MAT2
PIO1_8/CT16B1_CAP0 PIO0_9/MOSI0/CT16B0_MAT1
PIO0_2/SSEL0/CT16B0_CAP0 PIO0_8/MISO0/CT16B0_MAT0
PIO2_7/CT32B0_MAT2/RXD PIO2_2/DCD/MISO1
PIO2_8/CT32B0_MAT3/TXD PIO2_10
PIO2_1/DSR/SCK1 PIO3_3/RI/CT16B0_CAP0
PIO0_3 PIO1_7/TXD/CT32B0_MAT1
PIO0_4/SCL PIO1_6/RXD/CT32B0_MAT0
PIO0_5/SDA PIO1_5/RTS/CT32B0_CAP0
PIO1_9/CT16B1_MAT0/MOSI1 VDD
PIO3_4/CT16B0_CAP1/RXD PIO3_2/DCD/CT16B0_MAT2/SCK1
PIO2_4/CT16B1_MAT1/SSEL1 PIO1_11/AD7/CT32B1_CAP1
PIO2_5/CT32B0_MAT0 VSS
PIO3_5/CT16B1_CAP1/TXD PIO1_4/AD5/CT32B1_MAT3/WAKEUP
PIO0_6/SCK0 SWDIO/PIO1_3/AD4/CT32B1_MAT2
PIO0_7/CTS
PIO2_9/CT32B0_CAP0
PIO2_3/RI/MOSI1
PIO3_1/DSR/CT16B0_MAT1/RXD
002aag781
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
13
14
15
16
17
18
19
20
21
22
23
48
47
46
45
44
43
42
41
40
39
38
37
24
OO 00 OO 00 OO 00 OO 00 a aaaaeaa HHHQQQQQ Dfiflfiflfififi DDDDDDD
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 15 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Fig 5. LPC1100XL series pin configuration TFBGA48 package
aaa-008364
LPC1115
Transparent top view
H
G
F
D
B
E
C
A
24681357
ball A1
index area
Fig 6. LPC1100 and LPC1100L series pin configuration HVQFN33 7x7 and 5x5 packages
002aae698
Transparent top view
PIO0_8/MISO0/CT16B0_MAT0
PIO1_8/CT16B1_CAP0
PIO0_2/SSEL0/CT16B0_CAP0
PIO0_9/MOSI0/CT16B0_MAT1
VDD SWCLK/PIO0_10/SCK0/CT16B0_MAT2
XTALOUT PIO1_10/AD6/CT16B1_MAT1
XTALIN R/PIO0_11/AD0/CT32B0_MAT3
PIO0_1/CLKOUT/CT32B0_MAT2 R/PIO1_0/AD1/CT32B1_CAP0
RESET/PIO0_0 R/PIO1_1/AD2/CT32B1_MAT0
PIO2_0/DTR R/PIO1_2/AD3/CT32B1_MAT1
PIO0_3
PIO0_4/SCL
PIO0_5/SDA
PIO1_9/CT16B1_MAT0
PIO3_4
PIO3_5
PIO0_6/SCK0
PIO0_7/CTS
PIO1_7/TXD/CT32B0_MAT1
PIO1_6/RXD/CT32B0_MAT0
PIO1_5/RTS/CT32B0_CAP0
VDD
PIO3_2
PIO1_11/AD7
PIO1_4/AD5/CT32B1_MAT3/WAKEUP
SWDIO/PIO1_3/AD4/CT32B1_MAT2
8 17
7 18
6 19
5 20
4 21
3 22
2 23
1 24
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
terminal 1
index area
33 VSS
aaaaauuu ! E mm a @ D DDDDDDD jjjjjjjjjj EEEEEEEEEE
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 16 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Fig 7. LPC1100XL series pin configuration HVQFN33
002aag782
Transparent top view
PIO0_8/MISO0/CT16B0_MAT0
PIO1_8/CT16B1_CAP0
PIO0_2/SSEL0/CT16B0_CAP0
PIO0_9/MOSI0/CT16B0_MAT1
V
DD
SWCLK/PIO0_10/SCK0/CT16B0_MAT2
XTALOUT PIO1_10/AD6/CT16B1_MAT1/MISO1
XTALIN R/PIO0_11/AD0/CT32B0_MAT3
PIO0_1/CLKOUT/CT32B0_MAT2 R/PIO1_0/AD1/CT32B1_CAP0
RESET/PIO0_0 R/PIO1_1/AD2/CT32B1_MAT0
PIO2_0/DTR/SSEL1 R/PIO1_2/AD3/CT32B1_MAT1
PIO0_3
PIO0_4/SCL
PIO0_5/SDA
PIO1_9/CT16B1_MAT0/MOSI1
PIO3_4/CT16B0_CAP1/RXD
PIO3_5/CT16B1_CAP1/TXD
PIO0_6/SCK0
PIO0_7/CTS
PIO1_7/TXD/CT32B0_MAT1
PIO1_6/RXD/CT32B0_MAT0
PIO1_5/RTS/CT32B0_CAP0
V
DD
PIO3_2/CT16B0_MAT2/SCK1
PIO1_11/AD7/CT32B1_CAP1
PIO1_4/AD5/CT32B1_MAT3/WAKEUP
SWDIO/PIO1_3/AD4/CT32B1_MAT2
817
718
619
520
421
322
223
124
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
terminal 1
index area
33 V
SS
Fig 8. LPC1100L series pin configuration SO20 package
LPC1110FD20
LPC1112FD20/
102
PIO0_8/MISO0/CT16B0_MAT0 PIO0_4/SCL
PIO0_9/MOSI0/CT16B0_MAT1 PIO0_2/SSEL0/CT16B0_CAP0
SWCLK/PIO0_10/SCK0/CT16B0_MAT2 PIO0_1/CLKOUT/CT32B0_MAT2
R/PIO0_11/AD0/CT32B0_MAT3 RESET/PIO0_0
PIO0_5/SDA VSS
PIO0_6/SCK0 VDD
R/PIO1_0/AD1/CT32B1_CAP0 XTALIN
R/PIO1_1/AD2/CT32B1_MAT0 XTALOUT
R/PIO1_2/AD3/CT32B1_MAT1 PIO1_7/TXD/CT32B0_MAT1
SWDIO/PIO1_3/AD4/CT32B1_MAT2 PIO1_6/RXD/CT32B0_MAT0
002aag595
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
jjjjjjjjjj 0 333333333: EEEEEEEEEE O EEEEEEEEEE 666666 CCCCCC 333333 flflflflflfl
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 17 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Fig 9. LPC1100L series pin configuration TSSOP20 package with I2C-bus pins
LPC1111FDH20/002
PIO0_8/MISO0/CT16B0_MAT0 PIO0_4/SCL
PIO0_9/MOSI0/CT16B0_MAT1 PIO0_2/SSEL0/CT16B0_CAP0
SWCLK/PIO0_10/SCK0/CT16B0_MAT2 PIO0_1/CLKOUT/CT32B0_MAT2
R/PIO0_11/AD0/CT32B0_MAT3 RESET/PIO0_0
PIO0_5/SDA VSS
PIO0_6/SCK0 VDD
R/PIO1_0/AD1/CT32B1_CAP0 XTALIN
R/PIO1_1/AD2/CT32B1_MAT0 XTALOUT
R/PIO1_2/AD3/CT32B1_MAT1 PIO1_7/TXD/CT32B0_MAT1
SWDIO/PIO1_3/AD4/CT32B1_MAT2 PIO1_6/RXD/CT32B0_MAT0
002aag596
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
Fig 10. LPC1100L series pin configuration TSSOP20 package with VDDA and VSSA pins
LPC1112FDH20/102
PIO0_8/MISO0/CT16B0_MAT0 PIO0_3
PIO0_9/MOSI0/CT16B0_MAT1 PIO0_2/SSEL0/CT16B0_CAP0
SWCLK/PIO0_10/SCK0/CT16B0_MAT2 PIO0_1/CLKOUT/CT32B0_MAT2
R/PIO0_11/AD0/CT32B0_MAT3 RESET/PIO0_0
VDDA VSS
VSSA VDD
R/PIO1_0/AD1/CT32B1_CAP0 XTALIN
R/PIO1_1/AD2/CT32B1_MAT0 XTALOUT
R/PIO1_2/AD3/CT32B1_MAT1 PIO1_7/TXD/CT32B0_MAT1
SWDIO/PIO1_3/AD4/CT32B1_MAT2 PIO1_6/RXD/CT32B0_MAT0
002aag597
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
Fig 11. LPC1100L series pin configuration HVQFN24 package
002aah173
LPC1112FHN24
Transparent top view
PIO0_9
V
DD
PIO1_8
PIO0_10
XTALIN PIO0_11
V
SS
PIO1_0
PIO0_1 PIO1_1
RESET/PIO0_0 PIO1_2
PIO0_2
PIO0_4
PIO0_5
PIO0_6
PIO0_7
PIO0_8
PIO1_7
PIO1_6
V
DD
V
SS
PIO1_4
PIO1_3
terminal 1
index area
613
514
415
316
217
118
7
8
9
10
11
12
24
23
22
21
20
19
33333333333333 0 33333333333333 U EEEEEEEEEEEEEE EEEEEEEEEEEEEE
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 18 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Fig 12. LPC1100L pin configuration TSSOP28 package
LPC1112FDH28/102
LPC1114FDH28/102
PIO0_8/MISO0/CT16B0_MAT0 PIO0_7/CTS
PIO0_9/MOSI0/CT16B0_MAT1 PIO0_4/SCL
SWCLK/PIO0_10/SCK0/CT16B0_MAT2 PIO0_3
R/PIO0_11/AD0/CT32B0_MAT3 PIO0_2/SSEL0/CT16B0_CAP0
PIO0_5/SDA PIO0_1/CLKOUT/CT32B0_MAT2
PIO0_6/SCK0 RESET/PIO0_0
VDDA VSS
VSSA VDD
R/PIO1_0/AD1/CT32B1_CAP0 XTALIN
R/PIO1_1/AD2/CT32B1_MAT0 XTALOUT
R/PIO1_2/AD3/CT32B1_MAT1 PIO1_9/CT16B1_MAT0
SWDIO/PIO1_3/AD4/CT32B1_MAT2 PIO1_8/CT16B1_CAP0
PIO1_4/AD5/CT32B1_MAT3/WAKEUP PIO1_7/TXD/CT32B0_MAT1
PIO1_5/RTS/CT32B0_CAP0 PIO1_6/RXD/CT32B0_MAT0
002aag598
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
18
17
20
19
22
21
24
23
26
25
28
27
Fig 13. LPC1100L series pin configuration DIP28 package
LPC1114FN28/
102
PIO0_8/MISO0/CT16B0_MAT0 PIO0_7/CTS
PIO0_9/MOSI0/CT16B0_MAT1 PIO0_4/SCL
SWCLK/PIO0_10/SCK0/CT16B0_MAT2 PIO0_3
R/PIO0_11/AD0/CT32B0_MAT3 PIO0_2/SSEL0/CT16B0_CAP0
PIO0_5/SDA PIO0_1/CLKOUT/CT32B0_MAT2
PIO0_6/SCK0 RESET/PIO0_0
V
DDA
V
SS
V
SSA
V
DD
R/PIO1_0/AD1/CT32B1_CAP0 XTALIN
R/PIO1_1/AD2/CT32B1_MAT0 XTALOUT
R/PIO1_2/AD3/CT32B1_MAT1 PIO1_9/CT16B1_MAT0
SWDIO/PIO1_3/AD4/CT32B1_MAT2 PIO1_8/CT16B1_CAP0
PIO1_4/AD5/CT32B1_MAT3/WAKEUP PIO1_7/TXD/CT32B0_MAT1
PIO1_5/RTS/CT32B0_CAP0 PIO1_6/RXD/CT32B0_MAT0
002aag599
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
18
17
20
19
22
21
24
23
26
25
28
27
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 19 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
6.2 Pin description
Table 4. LPC1100L series: LPC1110/11/12 pin description table (SO20 and TSSOP20 package with
I2C-bus pins)
Symbol
Pin SO20/
TSSOP20
Start
logic
input
Type Reset
state
[1]
Description
PIO0_0 to PIO0_11 I/O Port 0 — Port 0 is a 12-bit I/O port with individual direction and
function controls for each bit. The operation of port 0 pins depends
on the function selected through the IOCONFIG register block.
RESET/PIO0_0 17 [2] yes I I; PU RESET — External reset input with 20 ns glitch filter. A LOW-going
pulse as short as 50 ns on this pin resets the device, causing I/O
ports and peripherals to take on their default states, and processor
execution to begin at address 0.
In deep power-down mode, this pin must be pulled HIGH externally.
The RESET pin can be left unconnected or be used as a GPIO pin
if an external RESET function is not needed and Deep power-down
mode is not used.
I/O - PIO0_0 — General purpose digital input/output pin with 10 ns glitch
filter.
PIO0_1/CLKOUT/
CT32B0_MAT2 18 [3] yes I/O I; PU PIO0_1 — General purpose digital input/output pin. A LOW level on
this pin during reset starts the ISP command handler.
O- CLKOUT — Clockout pin.
O- CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
PIO0_2/SSEL0/
CT16B0_CAP0 19 [3] yes I/O I; PU PIO0_2 — General purpose digital input/output pin.
I/O - SSEL0 — Slave Select for SPI0.
I- CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
PIO0_4/SCL 20 [4] yes I/O I; IA PIO0_4 — General purpose digital input/output pin (open-drain).
I/O - SCL — I2C-bus, open-drain clock input/output. High-current sink
only if I2C Fast-mode Plus is selected in the I/O configuration
register.
PIO0_5/SDA 5 [4] yes I/O I; IA PIO0_5 — General purpose digital input/output pin (open-drain).
I/O - SDA — I2C-bus, open-drain data input/output. High-current sink
only if I2C Fast-mode Plus is selected in the I/O configuration
register.
PIO0_6/SCK0 6 [3] yes I/O I; PU PIO0_6 — General purpose digital input/output pin.
I/O - SCK0 — Serial clock for SPI0.
PIO0_8/MISO0/
CT16B0_MAT0 1[3] yes I/O I; PU PIO0_8 — General purpose digital input/output pin.
I/O - MISO0 — Master In Slave Out for SPI0.
O- CT16B0_MAT0 — Match output 0 for 16-bit timer 0.
PIO0_9/MOSI0/
CT16B0_MAT1 2[3] yes I/O I; PU PIO0_9 — General purpose digital input/output pin.
I/O - MOSI0 — Master Out Slave In for SPI0.
O- CT16B0_MAT1 — Match output 1 for 16-bit timer 0.
SWCLK/PIO0_10/
SCK0/
CT16B0_MAT2
3[3] yes I I; PU SWCLK — Serial wire clock.
I/O - PIO0_10 — General purpose digital input/output pin.
I/O - SCK0 — Serial clock for SPI0.
O- CT16B0_MAT2 — Match output 2 for 16-bit timer 0.
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Product data sheet Rev. 9.2 — 26 March 2014 20 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
R/PIO0_11/
AD0/CT32B0_MAT3 4[5] yes I I; PU R — Reserved. Configure for an alternate function in the
IOCONFIG block.
I/O - PIO0_11 — General purpose digital input/output pin.
I- AD0 — A/D converter, input 0.
O- CT32B0_MAT3 — Match output 3 for 32-bit timer 0.
PIO1_0 to PIO1_7 I/O Port 1 — Port 1 is a 12-bit I/O port with individual direction and
function controls for each bit. The operation of port 1 pins depends
on the function selected through the IOCONFIG register block.
R/PIO1_0/
AD1/CT32B1_CAP0 7[5] yes I I; PU R — Reserved. Configure for an alternate function in the
IOCONFIG block.
I/O - PIO1_0 — General purpose digital input/output pin.
I- AD1 — A/D converter, input 1.
I- CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.
R/PIO1_1/
AD2/CT32B1_MAT0 8[5] no O I; PU R — Reserved. Configure for an alternate function in the
IOCONFIG block.
I/O - PIO1_1 — General purpose digital input/output pin.
I- AD2 — A/D converter, input 2.
O- CT32B1_MAT0 — Match output 0 for 32-bit timer 1.
R/PIO1_2/
AD3/CT32B1_MAT1 9[5] no I I; PU R — Reserved. Configure for an alternate function in the
IOCONFIG block.
I/O - PIO1_2 — General purpose digital input/output pin.
I- AD3 — A/D converter, input 3.
O- CT32B1_MAT1 — Match output 1 for 32-bit timer 1.
SWDIO/PIO1_3/
AD4/CT32B1_MAT2 10 [5] no I/O I; PU SWDIO — Serial wire debug input/output.
I/O - PIO1_3 — General purpose digital input/output pin.
I- AD4 — A/D converter, input 4.
O- CT32B1_MAT2 — Match output 2 for 32-bit timer 1.
PIO1_6/RXD/
CT32B0_MAT0 11 [3] no I/O I; PU PIO1_6 — General purpose digital input/output pin.
I- RXD — Receiver input for UART.
O- CT32B0_MAT0 — Match output 0 for 32-bit timer 0.
PIO1_7/TXD/
CT32B0_MAT1 12 [3] no I/O I; PU PIO1_7 — General purpose digital input/output pin.
O- TXD — Transmitter output for UART.
O- CT32B0_MAT1 — Match output 1 for 32-bit timer 0.
VDD 15 - - 3.3 V supply voltage to the internal regulator, the external rail, and
the ADC. Also used as the ADC reference voltage.
XTALIN 14 [6] - I - Input to the oscillator circuit and internal clock generator circuits.
Input voltage must not exceed 1.8 V.
XTALOUT 13 [6] - O - Output from the oscillator amplifier.
VSS 16 - - Ground.
Table 4. LPC1100L series: LPC1110/11/12 pin description table (SO20 and TSSOP20 package with
I2C-bus pins) …continued
Symbol
Pin SO20/
TSSOP20
Start
logic
input
Type Reset
state
[1]
Description
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 21 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full VDD level ); IA = inactive,
no pull-up/down enabled.
[2] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode.
[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 51).
[4] I2C-bus pin compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus. The pin requires an external pull-up
to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain
configuration applies to all functions on this pin.
[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 51).
[6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
Table 5. LPC1100L series: LPC1112 pin description table (TSSOP20 with VDDA and VSSA pins)
Symbol
Pin TSSOP20
Start
logic
input
Type Reset
state
[1]
Description
PIO0_0 to PIO0_11 I/O Port 0 — Port 0 is a 12-bit I/O port with individual direction
and function controls for each bit. The operation of port 0 pins
depends on the function selected through the IOCONFIG
register block.
RESET/PIO0_0 17 [2] yes I I; PU RESET — External reset input with 20 ns glitch filter. A
LOW-going pulse as short as 50 ns on this pin resets the
device, causing I/O ports and peripherals to take on their
default states, and processor execution to begin at address 0.
In deep power-down mode, this pin must be pulled HIGH
externally. The RESET pin can be left unconnected or be
used as a GPIO pin if an external RESET function is not
needed and Deep power-down mode is not used.
I/O - PIO0_0 — General purpose digital input/output pin with 10 ns
glitch filter.
PIO0_1/CLKOUT/
CT32B0_MAT2 18 [3] yes I/O I; PU PIO0_1 — General purpose digital input/output pin. A LOW
level on this pin during reset starts the ISP command handler.
O-CLKOUT — Clockout pin.
O-CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
PIO0_2/SSEL0/
CT16B0_CAP0 19 [3] yes I/O I; PU PIO0_2 — General purpose digital input/output pin.
I/O - SSEL0 — Slave Select for SPI0.
I-CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
PIO0_3 20 [3] yes I/O I; PU PIO0_3 — General purpose digital input/output pin.
PIO0_8/MISO0/
CT16B0_MAT0 1[3] yes I/O I; PU PIO0_8 — General purpose digital input/output pin.
I/O - MISO0 — Master In Slave Out for SPI0.
O-CT16B0_MAT0 — Match output 0 for 16-bit timer 0.
PIO0_9/MOSI0/
CT16B0_MAT1 2[3] yes I/O I; PU PIO0_9 — General purpose digital input/output pin.
I/O - MOSI0 — Master Out Slave In for SPI0.
O-CT16B0_MAT1 — Match output 1 for 16-bit timer 0.
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Product data sheet Rev. 9.2 — 26 March 2014 22 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
SWCLK/PIO0_10/
SCK0/
CT16B0_MAT2
3[3] yes I I; PU SWCLK — Serial wire clock.
I/O - PIO0_10 — General purpose digital input/output pin.
I/O - SCK0 — Serial clock for SPI0.
O-CT16B0_MAT2 — Match output 2 for 16-bit timer 0.
R/PIO0_11/
AD0/CT32B0_MAT3 4[4] yes I I; PU R — Reserved. Configure for an alternate function in the
IOCONFIG block.
I/O - PIO0_11 — General purpose digital input/output pin.
I-AD0 — A/D converter, input 0.
O-CT32B0_MAT3 — Match output 3 for 32-bit timer 0.
PIO1_0 to PIO1_7 I/O Port 1 — Port 1 is a 12-bit I/O port with individual direction
and function controls for each bit. The operation of port 1 pins
depends on the function selected through the IOCONFIG
register block.
R/PIO1_0/
AD1/CT32B1_CAP0 7[4] yes I I; PU R — Reserved. Configure for an alternate function in the
IOCONFIG block.
I/O - PIO1_0 — General purpose digital input/output pin.
I-AD1 — A/D converter, input 1.
I-CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.
R/PIO1_1/
AD2/CT32B1_MAT0 8[4] no O I; PU R — Reserved. Configure for an alternate function in the
IOCONFIG block.
I/O - PIO1_1 — General purpose digital input/output pin.
I-AD2 — A/D converter, input 2.
O-CT32B1_MAT0 — Match output 0 for 32-bit timer 1.
R/PIO1_2/
AD3/CT32B1_MAT1 9[4] no I I; PU R — Reserved. Configure for an alternate function in the
IOCONFIG block.
I/O - PIO1_2 — General purpose digital input/output pin.
I-AD3 — A/D converter, input 3.
O-CT32B1_MAT1 — Match output 1 for 32-bit timer 1.
SWDIO/PIO1_3/
AD4/CT32B1_MAT2 10 [4] no I/O I; PU SWDIO — Serial wire debug input/output.
I/O - PIO1_3 — General purpose digital input/output pin.
I-AD4 — A/D converter, input 4.
O-CT32B1_MAT2 — Match output 2 for 32-bit timer 1.
PIO1_6/RXD/
CT32B0_MAT0 11 [3] no I/O I; PU PIO1_6 — General purpose digital input/output pin.
I-RXD — Receiver input for UART.
O-CT32B0_MAT0 — Match output 0 for 32-bit timer 0.
PIO1_7/TXD/
CT32B0_MAT1 12 [3] no I/O I; PU PIO1_7 — General purpose digital input/output pin.
O-TXD — Transmitter output for UART.
O-CT32B0_MAT1 — Match output 1 for 32-bit timer 0.
VDD 15 - I - 3.3 V supply voltage to the internal regulator and the external
rail.
Table 5. LPC1100L series: LPC1112 pin description table (TSSOP20 with VDDA and VSSA pins) …continued
Symbol
Pin TSSOP20
Start
logic
input
Type Reset
state
[1]
Description
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 23 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full VDD level ); IA = inactive,
no pull-up/down enabled.
[2] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode.
[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 51).
[4] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 51).
[5] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
VDDA 5 - I - 3.3 V supply voltage to the ADC. Also used as the ADC
reference voltage.
XTALIN 14 [5] - I - Input to the oscillator circuit and internal clock generator
circuits. Input voltage must not exceed 1.8 V.
XTALOUT 13 [5] - O - Output from the oscillator amplifier.
VSS 16 - I - Ground.
VSSA 6 - I - Analog ground.
Table 5. LPC1100L series: LPC1112 pin description table (TSSOP20 with VDDA and VSSA pins) …continued
Symbol
Pin TSSOP20
Start
logic
input
Type Reset
state
[1]
Description
Table 6. LPC1100L series: LPC1112 (HVQFN24 package)
Symbol HVQFN
pin Start
logic
input
Type Reset
state
[1]
Description
RESET/PIO0_0 1[2] yes I I; PU RESET — External reset input with 20 ns glitch filter. A
LOW-going pulse as short as 50 ns on this pin resets the
device, causing I/O ports and peripherals to take on their
default states, and processor execution to begin at address 0.
In deep power-down mode, this pin must be pulled HIGH
externally. The RESET pin can be left unconnected or be used
as a GPIO pin if an external RESET function is not needed and
Deep power-down mode is not used.
I/O - PIO0_0 — General purpose digital input/output pin with 10 ns
glitch filter.
PIO0_1/CLKOUT/
CT32B0_MAT2 2[3] yes I/O I; PU PIO0_1 — General purpose digital input/output pin. A LOW
level on this pin during reset starts the ISP command handler.
O-CLKOUT — Clockout pin.
O-CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
PIO0_2/SSEL0/
CT16B0_CAP0 7[3] yes I/O I; PU PIO0_2 — General purpose digital input/output pin.
I/O - SSEL0 — Slave Select for SPI0.
I-CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
PIO0_4/SCL 8[4] yes I/O I; IA PIO0_4 — General purpose digital input/output pin
(open-drain).
I/O - SCL — I2C-bus, open-drain clock input/output. High-current
sink only if I2C Fast-mode Plus is selected in the I/O
configuration register.
10, 11, 12, 13, 14, 16, 17, 1a,
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Product data sheet Rev. 9.2 — 26 March 2014 24 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
PIO0_5/SDA 9[4] yes I/O I; IA PIO0_5 — General purpose digital input/output pin
(open-drain).
I/O - SDA — I2C-bus, open-drain data input/output. High-current
sink only if I2C Fast-mode Plus is selected in the I/O
configuration register.
PIO0_6/SCK0 10[3] yes I/O I; PU PIO0_6 — General purpose digital input/output pin.
I/O - SCK0 — Serial clock for SPI0.
PIO0_7/CTS 11[3] yes I/O I; PU PIO0_7 — General purpose digital input/output pin
(high-current output driver).
I-CTS — Clear To Send input for UART.
PIO0_8/MISO0/
CT16B0_MAT0 12[3] yes I/O I; PU PIO0_8 — General purpose digital input/output pin.
I/O - MISO0 — Master In Slave Out for SPI0.
O-CT16B0_MAT0 — Match output 0 for 16-bit timer 0.
PIO0_9/MOSI0/
CT16B0_MAT1 13[3] yes I/O I; PU PIO0_9 — General purpose digital input/output pin.
I/O - MOSI0 — Master Out Slave In for SPI0.
O-CT16B0_MAT1 — Match output 1 for 16-bit timer 0.
SWCLK/PIO0_10/
SCK0/
CT16B0_MAT2
14[3] yes I I; PU SWCLK — Serial wire clock.
I/O - PIO0_10 — General purpose digital input/output pin.
I/O - SCK0 — Serial clock for SPI0.
O-CT16B0_MAT2 — Match output 2 for 16-bit timer 0.
R/PIO0_11/
AD0/CT32B0_MAT3 15[5] yes I I; PU R — Reserved. Configure for an alternate function in the
IOCONFIG block.
I/O - PIO0_11 — General purpose digital input/output pin.
I-AD0 — A/D converter, input 0.
O-CT32B0_MAT3 — Match output 3 for 32-bit timer 0.
R/PIO1_0/
AD1/CT32B1_CAP0 16[5] yes I I; PU R — Reserved. Configure for an alternate function in the
IOCONFIG block.
I/O - PIO1_0 — General purpose digital input/output pin.
I-AD1 — A/D converter, input 1.
I-CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.
R/PIO1_1/
AD2/CT32B1_MAT0 17[5] no O I; PU R — Reserved. Configure for an alternate function in the
IOCONFIG block.
I/O - PIO1_1 — General purpose digital input/output pin.
I-AD2 — A/D converter, input 2.
O-CT32B1_MAT0 — Match output 0 for 32-bit timer 1.
R/PIO1_2/
AD3/CT32B1_MAT1 18[5] no I I; PU R — Reserved. Configure for an alternate function in the
IOCONFIG block.
I/O - PIO1_2 — General purpose digital input/output pin.
I-AD3 — A/D converter, input 3.
O-CT32B1_MAT1 — Match output 1 for 32-bit timer 1.
Table 6. LPC1100L series: LPC1112 (HVQFN24 package) …continued
Symbol HVQFN
pin Start
logic
input
Type Reset
state
[1]
Description
19, 20, 23, 24,
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 25 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full VDD level); IA = inactive,
no pull-up/down enabled.
[2] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up
from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. See Figure 52 for the
reset pad configuration.
[3] Pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 51).
[4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus. The pin requires an external
pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain
configuration applies to all functions on this pin.
[5] Pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When
configured as a ADC input, digital section of the pad is disabled (see Figure 51).
[6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
SWDIO/PIO1_3/
AD4/CT32B1_MAT2 19[5] no I/O I; PU SWDIO — Serial wire debug input/output.
I/O - PIO1_3 — General purpose digital input/output pin.
I-AD4 — A/D converter, input 4.
O-CT32B1_MAT2 — Match output 2 for 32-bit timer 1.
PIO1_4/AD5/
CT32B1_MAT3/
WAKEUP
20[5] no I/O I; PU PIO1_4 — General purpose digital input/output pin with 10 ns
glitch filter. In Deep power-down mode, this pin serves as the
Deep power-down mode wake-up pin with 20 ns glitch filter.
Pull this pin HIGH externally before entering Deep power-down
mode. Pull this pin LOW to exit Deep power-down mode. A
LOW-going pulse as short as 50 ns wakes up the part.
I-AD5 — A/D converter, input 5.
O-CT32B1_MAT3 — Match output 3 for 32-bit timer 1.
PIO1_6/RXD/
CT32B0_MAT0 23[3] no I/O I; PU PIO1_6 — General purpose digital input/output pin.
I-RXD — Receiver input for UART.
O-CT32B0_MAT0 — Match output 0 for 32-bit timer 0.
PIO1_7/TXD/
CT32B0_MAT1 24[3] no I/O I; PU PIO1_7 — General purpose digital input/output pin.
O-TXD — Transmitter output for UART.
O-CT32B0_MAT1 — Match output 1 for 32-bit timer 0.
PIO1_8/
CT16B1_CAP0 6[3] no I/O I; PU PIO1_8 — General purpose digital input/output pin.
I-CT16B1_CAP0 — Capture input 0 for 16-bit timer 1.
XTALIN 4[6] - I - Input to the oscillator circuit and internal clock generator
circuits. Input voltage must not exceed 1.8 V.
VDD 5; 22 - I - 1.8 V supply voltage to the internal regulator, the external rail,
and the ADC. Also used as the ADC reference voltage.
VSS 3; 21 - I - Ground.
Table 6. LPC1100L series: LPC1112 (HVQFN24 package) …continued
Symbol HVQFN
pin Start
logic
input
Type Reset
state
[1]
Description
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 26 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Table 7. LPC1100L series: LPC1112/14 pin description table (TSSOP28 and DIP28 packages)
Symbol
Pin TSSOP28/
DIP28
Start
logic
input
Type Reset
state
[1]
Description
PIO0_0 to PIO0_11 I/O Port 0 — Port 0 is a 12-bit I/O port with individual direction and
function controls for each bit. The operation of port 0 pins depends
on the function selected through the IOCONFIG register block.
RESET/PIO0_0 23 [2] yes I I; PU RESET — External reset input with 20 ns glitch filter. A LOW-going
pulse as short as 50 ns on this pin resets the device, causing I/O
ports and peripherals to take on their default states, and processor
execution to begin at address 0.
In deep power-down mode, this pin must be pulled HIGH
externally. The RESET pin can be left unconnected or be used as a
GPIO pin if an external RESET function is not needed and Deep
power-down mode is not used.
I/O - PIO0_0 — General purpose digital input/output pin with 10 ns
glitch filter.
PIO0_1/CLKOUT/
CT32B0_MAT2 24 [3] yes I/O I; PU PIO0_1 — General purpose digital input/output pin. A LOW level
on this pin during reset starts the ISP command handler.
O- CLKOUT — Clockout pin.
O- CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
PIO0_2/SSEL0/
CT16B0_CAP0 25 [3] yes I/O I; PU PIO0_2 — General purpose digital input/output pin.
I/O - SSEL0 — Slave Select for SPI0.
I- CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
PIO0_3 26 [3] yes I/O I; PU PIO0_3 — General purpose digital input/output pin.
PIO0_4/SCL 27 [4] yes I/O I; IA PIO0_4 — General purpose digital input/output pin (open-drain).
I/O - SCL — I2C-bus, open-drain clock input/output. High-current sink
only if I2C Fast-mode Plus is selected in the I/O configuration
register.
PIO0_5/SDA 5 [4] yes I/O I; IA PIO0_5 — General purpose digital input/output pin (open-drain).
I/O - SDA — I2C-bus, open-drain data input/output. High-current sink
only if I2C Fast-mode Plus is selected in the I/O configuration
register.
PIO0_6/SCK0 6 [3] yes I/O I; PU PIO0_6 — General purpose digital input/output pin.
I/O - SCK0 — Serial clock for SPI0.
PIO0_7/CTS 28 [3] yes I/O I; PU PIO0_7 — General purpose digital input/output pin (high-current
output driver).
I- CTS — Clear To Send input for UART.
PIO0_8/MISO0/
CT16B0_MAT0 1[3] yes I/O I; PU PIO0_8 — General purpose digital input/output pin.
I/O - MISO0 — Master In Slave Out for SPI0.
O- CT16B0_MAT0 — Match output 0 for 16-bit timer 0.
PIO0_9/MOSI0/
CT16B0_MAT1 2[3] yes I/O I; PU PIO0_9 — General purpose digital input/output pin.
I/O - MOSI0 — Master Out Slave In for SPI0.
O- CT16B0_MAT1 — Match output 1 for 16-bit timer 0.
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 27 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
SWCLK/PIO0_10/
SCK0/
CT16B0_MAT2
3[3] yes I I; PU SWCLK — Serial wire clock.
I/O - PIO0_10 — General purpose digital input/output pin.
I/O - SCK0 — Serial clock for SPI0.
O- CT16B0_MAT2 — Match output 2 for 16-bit timer 0.
R/PIO0_11/
AD0/CT32B0_MAT3 4[5] yes I I; PU R — Reserved. Configure for an alternate function in the
IOCONFIG block.
I/O - PIO0_11 — General purpose digital input/output pin.
I- AD0 — A/D converter, input 0.
O- CT32B0_MAT3 — Match output 3 for 32-bit timer 0.
PIO1_0 to PIO1_9 I/O Port 1 — Port 1 is a 12-bit I/O port with individual direction and
function controls for each bit. The operation of port 1 pins depends
on the function selected through the IOCONFIG register block.
R/PIO1_0/
AD1/CT32B1_CAP0 9[5] yes I I; PU R — Reserved. Configure for an alternate function in the
IOCONFIG block.
I/O - PIO1_0 — General purpose digital input/output pin.
I- AD1 — A/D converter, input 1.
I- CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.
R/PIO1_1/
AD2/CT32B1_MAT0 10 [5] no O I; PU R — Reserved. Configure for an alternate function in the
IOCONFIG block.
I/O - PIO1_1 — General purpose digital input/output pin.
I- AD2 — A/D converter, input 2.
O- CT32B1_MAT0 — Match output 0 for 32-bit timer 1.
R/PIO1_2/
AD3/CT32B1_MAT1 11 [5] no I I; PU R — Reserved. Configure for an alternate function in the
IOCONFIG block.
I/O - PIO1_2 — General purpose digital input/output pin.
I- AD3 — A/D converter, input 3.
O- CT32B1_MAT1 — Match output 1 for 32-bit timer 1.
SWDIO/PIO1_3/
AD4/CT32B1_MAT2 12 [5] no I/O I; PU SWDIO — Serial wire debug input/output.
I/O - PIO1_3 — General purpose digital input/output pin.
I- AD4 — A/D converter, input 4.
O- CT32B1_MAT2 — Match output 2 for 32-bit timer 1.
PIO1_4/AD5/
CT32B1_MAT3/
WAKEUP
13 [5] no I/O I; PU PIO1_4 — General purpose digital input/output pin with 10 ns
glitch filter. In Deep power-down mode, this pin serves as the Deep
power-down mode wake-up pin with 20 ns glitch filter. Pull this pin
HIGH externally before entering Deep power-down mode. Pull this
pin LOW to exit Deep power-down mode. A LOW-going pulse as
short as 50 ns wakes up the part.
I- AD5 — A/D converter, input 5.
O- CT32B1_MAT3 — Match output 3 for 32-bit timer 1.
Table 7. LPC1100L series: LPC1112/14 pin description table (TSSOP28 and DIP28 packages) …continued
Symbol
Pin TSSOP28/
DIP28
Start
logic
input
Type Reset
state
[1]
Description
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 28 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full VDD level ); IA = inactive,
no pull-up/down enabled.
[2] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up
from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. See Figure 52 for the
reset pad configuration.
[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 51).
[4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus. The pin requires an external
pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain
configuration applies to all functions on this pin.
[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 51).
[6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
PIO1_5/RTS/
CT32B0_CAP0 14 [3] no I/O I; PU PIO1_5 — General purpose digital input/output pin.
O- RTS — Request To Send output for UART.
I- CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.
PIO1_6/RXD/
CT32B0_MAT0 15 [3] no I/O I; PU PIO1_6 — General purpose digital input/output pin.
I- RXD — Receiver input for UART.
O- CT32B0_MAT0 — Match output 0 for 32-bit timer 0.
PIO1_7/TXD/
CT32B0_MAT1 16 [3] no I/O I; PU PIO1_7 — General purpose digital input/output pin.
O- TXD — Transmitter output for UART.
O- CT32B0_MAT1 — Match output 1 for 32-bit timer 0.
PIO1_8/
CT16B1_CAP0 17 [3] no I/O I; PU PIO1_8 — General purpose digital input/output pin.
I- CT16B1_CAP0 — Capture input 0 for 16-bit timer 1.
PIO1_9/
CT16B1_MAT0 18 [3] no I/O I; PU PIO1_9 — General purpose digital input/output pin.
O- CT16B1_MAT0 — Match output 0 for 16-bit timer 1.
VDD 21 - - 3.3 V supply voltage to the internal regulator and the external rail.
VDDA 7 - - - 3.3 V supply voltage to the ADC. Also used as the ADC reference
voltage.
XTALIN 20 [6] - I - Input to the oscillator circuit and internal clock generator circuits.
Input voltage must not exceed 1.8 V.
XTALOUT 19 [6] - O - Output from the oscillator amplifier.
VSS 22 - - Ground.
VSSA 8 - - - Analog ground.
Table 7. LPC1100L series: LPC1112/14 pin description table (TSSOP28 and DIP28 packages) …continued
Symbol
Pin TSSOP28/
DIP28
Start
logic
input
Type Reset
state
[1]
Description
10, 15, 16, 22, 23, 27, 28,
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 29 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Table 8. LPC1100 and LPC1100L series: LPC1113/14 pin description table (LQFP48 package)
Symbol Pin Start
logic
input
Type Reset
state
[1]
Description
PIO0_0 to PIO0_11 I/O Port 0 — Port 0 is a 12-bit I/O port with individual direction and
function controls for each bit. The operation of port 0 pins
depends on the function selected through the IOCONFIG
register block.
RESET/PIO0_0 3[2] yes I I; PU RESET — External reset input with 20 ns glitch filter. A
LOW-going pulse as short as 50 ns on this pin resets the
device, causing I/O ports and peripherals to take on their default
states, and processor execution to begin at address 0.
In deep power-down mode, this pin must be pulled HIGH
externally. The RESET pin can be left unconnected or be used
as a GPIO pin if an external RESET function is not needed and
Deep power-down mode is not used.
I/O - PIO0_0 — General purpose digital input/output pin with 10 ns
glitch filter.
PIO0_1/CLKOUT/
CT32B0_MAT2 4[3] yes I/O I; PU PIO0_1 — General purpose digital input/output pin. A LOW
level on this pin during reset starts the ISP command handler.
O-CLKOUT — Clockout pin.
O-CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
PIO0_2/SSEL0/
CT16B0_CAP0 10[3] yes I/O I; PU PIO0_2 — General purpose digital input/output pin.
I/O - SSEL0 — Slave Select for SPI0.
I-CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
PIO0_3 14[3] yes I/O I; PU PIO0_3 — General purpose digital input/output pin.
PIO0_4/SCL 15[4] yes I/O I; IA PIO0_4 — General purpose digital input/output pin
(open-drain).
I/O - SCL — I2C-bus, open-drain clock input/output. High-current
sink only if I2C Fast-mode Plus is selected in the I/O
configuration register.
PIO0_5/SDA 16[4] yes I/O I; IA PIO0_5 — General purpose digital input/output pin
(open-drain).
I/O - SDA — I2C-bus, open-drain data input/output. High-current sink
only if I2C Fast-mode Plus is selected in the I/O configuration
register.
PIO0_6/SCK0 22[3] yes I/O I; PU PIO0_6 — General purpose digital input/output pin.
I/O - SCK0 — Serial clock for SPI0.
PIO0_7/CTS 23[3] yes I/O I; PU PIO0_7 — General purpose digital input/output pin
(high-current output driver).
I-CTS — Clear To Send input for UART.
PIO0_8/MISO0/
CT16B0_MAT0 27[3] yes I/O I; PU PIO0_8 — General purpose digital input/output pin.
I/O - MISO0 — Master In Slave Out for SPI0.
O-CT16B0_MAT0 — Match output 0 for 16-bit timer 0.
PIO0_9/MOSI0/
CT16B0_MAT1 28[3] yes I/O I; PU PIO0_9 — General purpose digital input/output pin.
I/O - MOSI0 — Master Out Slave In for SPI0.
O-CT16B0_MAT1 — Match output 1 for 16-bit timer 0.
29, 32, 33, 34, 35, 39, 40, 45,
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Product data sheet Rev. 9.2 — 26 March 2014 30 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
SWCLK/PIO0_10/
SCK0/
CT16B0_MAT2
29[3] yes I I; PU SWCLK — Serial wire clock.
I/O - PIO0_10 — General purpose digital input/output pin.
I/O - SCK0 — Serial clock for SPI0.
O-CT16B0_MAT2 — Match output 2 for 16-bit timer 0.
R/PIO0_11/
AD0/CT32B0_MAT3 32[5] yes I I; PU R — Reserved. Configure for an alternate function in the
IOCONFIG block.
I/O - PIO0_11 — General purpose digital input/output pin.
I-AD0 — A/D converter, input 0.
O-CT32B0_MAT3 — Match output 3 for 32-bit timer 0.
PIO1_0 to PIO1_11 I/O Port 1 — Port 1 is a 12-bit I/O port with individual direction and
function controls for each bit. The operation of port 1 pins
depends on the function selected through the IOCONFIG
register block.
R/PIO1_0/
AD1/CT32B1_CAP0 33[5] yes I I; PU R — Reserved. Configure for an alternate function in the
IOCONFIG block.
I/O - PIO1_0 — General purpose digital input/output pin.
I-AD1 — A/D converter, input 1.
I-CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.
R/PIO1_1/
AD2/CT32B1_MAT0 34[5] no O I; PU R — Reserved. Configure for an alternate function in the
IOCONFIG block.
I/O - PIO1_1 — General purpose digital input/output pin.
I-AD2 — A/D converter, input 2.
O-CT32B1_MAT0 — Match output 0 for 32-bit timer 1.
R/PIO1_2/
AD3/CT32B1_MAT1 35[5] no I I; PU R — Reserved. Configure for an alternate function in the
IOCONFIG block.
I/O - PIO1_2 — General purpose digital input/output pin.
I-AD3 — A/D converter, input 3.
O-CT32B1_MAT1 — Match output 1 for 32-bit timer 1.
SWDIO/PIO1_3/
AD4/CT32B1_MAT2 39[5] no I/O I; PU SWDIO — Serial wire debug input/output.
I/O - PIO1_3 — General purpose digital input/output pin.
I-AD4 — A/D converter, input 4.
O-CT32B1_MAT2 — Match output 2 for 32-bit timer 1.
PIO1_4/AD5/
CT32B1_MAT3/
WAKEUP
40[5] no I/O I; PU PIO1_4 — General purpose digital input/output pin with 10 ns
glitch filter. In Deep power-down mode, this pin serves as the
Deep power-down mode wake-up pin with 20 ns glitch filter. Pull
this pin HIGH externally before entering Deep power-down
mode. Pull this pin LOW to exit Deep power-down mode. A
LOW-going pulse as short as 50 ns wakes up the part.
I-AD5 — A/D converter, input 5.
O-CT32B1_MAT3 — Match output 3 for 32-bit timer 1.
PIO1_5/RTS/
CT32B0_CAP0 45[3] no I/O I; PU PIO1_5 — General purpose digital input/output pin.
O-RTS — Request To Send output for UART.
I-CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.
Table 8. LPC1100 and LPC1100L series: LPC1113/14 pin description table (LQFP48 package) …continued
Symbol Pin Start
logic
input
Type Reset
state
[1]
Description
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 31 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
PIO1_6/RXD/
CT32B0_MAT0 46[3] no I/O I; PU PIO1_6 — General purpose digital input/output pin.
I-RXD — Receiver input for UART.
O-CT32B0_MAT0 — Match output 0 for 32-bit timer 0.
PIO1_7/TXD/
CT32B0_MAT1 47[3] no I/O I; PU PIO1_7 — General purpose digital input/output pin.
O-TXD — Transmitter output for UART.
O-CT32B0_MAT1 — Match output 1 for 32-bit timer 0.
PIO1_8/
CT16B1_CAP0 9[3] no I/O I; PU PIO1_8 — General purpose digital input/output pin.
I-CT16B1_CAP0 — Capture input 0 for 16-bit timer 1.
PIO1_9/
CT16B1_MAT0 17[3] no I/O I; PU PIO1_9 — General purpose digital input/output pin.
O-CT16B1_MAT0 — Match output 0 for 16-bit timer 1.
PIO1_10/AD6/
CT16B1_MAT1 30[5] no I/O I; PU PIO1_10 — General purpose digital input/output pin.
I-AD6 — A/D converter, input 6.
O-CT16B1_MAT1 — Match output 1 for 16-bit timer 1.
PIO1_11/AD7 42[5] no I/O I; PU PIO1_11 — General purpose digital input/output pin.
I-AD7 — A/D converter, input 7.
PIO2_0 to PIO2_11 I/O Port 2 — Port 2 is a 12-bit I/O port with individual direction and
function controls for each bit. The operation of port 2 pins
depends on the function selected through the IOCONFIG
register block.
PIO2_0/DTR/SSEL1 2[3] no I/O I; PU PIO2_0 — General purpose digital input/output pin.
O-DTR — Data Terminal Ready output for UART.
I/O - SSEL1 — Slave Select for SPI1.
PIO2_1/DSR/SCK1 13[3] no I/O I; PU PIO2_1 — General purpose digital input/output pin.
I-DSR — Data Set Ready input for UART.
I/O - SCK1 — Serial clock for SPI1.
PIO2_2/DCD/MISO1 26[3] no I/O I; PU PIO2_2 — General purpose digital input/output pin.
I-DCD — Data Carrier Detect input for UART.
I/O - MISO1 — Master In Slave Out for SPI1.
PIO2_3/RI/MOSI1 38[3] no I/O I; PU PIO2_3 — General purpose digital input/output pin.
I-RI — Ring Indicator input for UART.
I/O - MOSI1 — Master Out Slave In for SPI1.
PIO2_4 19[3] no I/O I; PU PIO2_4 — General purpose digital input/output pin.
PIO2_5 20[3] no I/O I; PU PIO2_5 — General purpose digital input/output pin.
PIO2_6 1[3] no I/O I; PU PIO2_6 — General purpose digital input/output pin.
PIO2_7 11[3] no I/O I; PU PIO2_7 — General purpose digital input/output pin.
PIO2_8 12[3] no I/O I; PU PIO2_8 — General purpose digital input/output pin.
PIO2_9 24[3] no I/O I; PU PIO2_9 — General purpose digital input/output pin.
PIO2_10 25[3] no I/O I; PU PIO2_10 — General purpose digital input/output pin.
PIO2_11/SCK0 31[3] no I/O I; PU PIO2_11 — General purpose digital input/output pin.
I/O - SCK0 — Serial clock for SPI0.
Table 8. LPC1100 and LPC1100L series: LPC1113/14 pin description table (LQFP48 package) …continued
Symbol Pin Start
logic
input
Type Reset
state
[1]
Description
36, 37, 43, 48,
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 32 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to 2.6 V for
LPC111x/101/201/301, pins pulled up to full VDD level on LPC111x/002/102/202/302 (VDD = 3.3 V)); IA = inactive, no pull-up/down
enabled.
[2] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up
from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. See Figure 52 for the
reset pad configuration.
[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 51).
[4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus. The pin requires an external
pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain
configuration applies to all functions on this pin.
[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 51).
[6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
PIO3_0 to PIO3_5 I/O Port 3 — Port 3 is a 12-bit I/O port with individual direction and
function controls for each bit. The operation of port 3 pins
depends on the function selected through the IOCONFIG
register block. Pins PIO3_6 to PIO3_11 are not available.
PIO3_0/DTR 36[3] no I/O I; PU PIO3_0 — General purpose digital input/output pin.
O-DTR — Data Terminal Ready output for UART.
PIO3_1/DSR 37[3] no I/O I; PU PIO3_1 — General purpose digital input/output pin.
I-DSR — Data Set Ready input for UART.
PIO3_2/DCD 43[3] no I/O I; PU PIO3_2 — General purpose digital input/output pin.
I-DCD — Data Carrier Detect input for UART.
PIO3_3/RI 48[3] no I/O I; PU PIO3_3 — General purpose digital input/output pin.
I-RI — Ring Indicator input for UART.
PIO3_4 18[3] no I/O I; PU PIO3_4 — General purpose digital input/output pin.
PIO3_5 21[3] no I/O I; PU PIO3_5 — General purpose digital input/output pin.
VDD 8; 44 - I - 3.3 V supply voltage to the internal regulator, the external rail,
and the ADC. Also used as the ADC reference voltage.
XTALIN 6[6] - I - Input to the oscillator circuit and internal clock generator circuits.
Input voltage must not exceed 1.8 V.
XTALOUT 7[6] - O - Output from the oscillator amplifier.
VSS 5; 41 - I - Ground.
Table 8. LPC1100 and LPC1100L series: LPC1113/14 pin description table (LQFP48 package) …continued
Symbol Pin Start
logic
input
Type Reset
state
[1]
Description
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 33 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Table 9. LPC1100 and LPC1100L series: LPC1111/12/13/14 pin description table (HVQFN33 package)
Symbol Pin Start
logic
input
Type Reset
state
[1]
Description
PIO0_0 to PIO0_11 Port 0 — Port 0 is a 12-bit I/O port with individual direction and
function controls for each bit. The operation of port 0 pins depends on
the function selected through the IOCONFIG register block.
RESET/PIO0_0 2[2] yes I I;PU RESET — External reset input with 20 ns glitch filter. A LOW-going
pulse as short as 50 ns on this pin resets the device, causing I/O ports
and peripherals to take on their default states and processor execution
to begin at address 0.
In deep power-down mode, this pin must be pulled HIGH externally.
The RESET pin can be left unconnected or be used as a GPIO pin if
an external RESET function is not needed and Deep power-down
mode is not used.
I/O - PIO0_0 — General purpose digital input/output pin with 10 ns glitch
filter.
PIO0_1/CLKOUT/
CT32B0_MAT2 3[3] yes I/O I;PU PIO0_1 — General purpose digital input/output pin. A LOW level on
this pin during reset starts the ISP command handler.
O- CLKOUT — Clock out pin.
O- CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
PIO0_2/SSEL0/
CT16B0_CAP0 8[3] yes I/O I;PU PIO0_2 — General purpose digital input/output pin.
I/O - SSEL0 — Slave select for SPI0.
I- CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
PIO0_3 9[3] yes I/O I;PU PIO0_3 — General purpose digital input/output pin.
PIO0_4/SCL 10[4] yes I/O I;IA PIO0_4 — General purpose digital input/output pin (open-drain).
I/O - SCL — I2C-bus, open-drain clock input/output. High-current sink only
if I2C Fast-mode Plus is selected in the I/O configuration register.
PIO0_5/SDA 11[4] yes I/O I;IA PIO0_5 — General purpose digital input/output pin (open-drain).
I/O - SDA — I2C-bus, open-drain data input/output. High-current sink only if
I2C Fast-mode Plus is selected in the I/O configuration register.
PIO0_6/SCK0 15[3] yes I/O I;PU PIO0_6 — General purpose digital input/output pin.
I/O - SCK0 — Serial clock for SPI0.
PIO0_7/CTS 16[3] yes I/O I;PU PIO0_7 — General purpose digital input/output pin (high-current
output driver).
I- CTS — Clear To Send input for UART.
PIO0_8/MISO0/
CT16B0_MAT0 17[3] yes I/O I;PU PIO0_8 — General purpose digital input/output pin.
I/O - MISO0 — Master In Slave Out for SPI0.
O- CT16B0_MAT0 — Match output 0 for 16-bit timer 0.
PIO0_9/MOSI0/
CT16B0_MAT1 18[3] yes I/O I;PU PIO0_9 — General purpose digital input/output pin.
I/O - MOSI0 — Master Out Slave In for SPI0.
O- CT16B0_MAT1 — Match output 1 for 16-bit timer 0.
SWCLK/PIO0_10/
SCK0/
CT16B0_MAT2
19[3] yes I I;PU SWCLK — Serial wire clock.
I/O - PIO0_10 — General purpose digital input/output pin.
I/O - SCK0 — Serial clock for SPI0.
O- CT16B0_MAT2 — Match output 2 for 16-bit timer 0.
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 34 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
R/PIO0_11/AD0/
CT32B0_MAT3 21[5] yes - I;PU R — Reserved. Configure for an alternate function in the IOCONFIG
block.
I/O - PIO0_11 — General purpose digital input/output pin.
I- AD0 — A/D converter, input 0.
O- CT32B0_MAT3 — Match output 3 for 32-bit timer 0.
PIO1_0 to PIO1_11 Port 1 — Port 1 is a 12-bit I/O port with individual direction and
function controls for each bit. The operation of port 1 pins depends on
the function selected through the IOCONFIG register block.
R/PIO1_0/AD1/
CT32B1_CAP0 22[5] yes - I;PU R — Reserved. Configure for an alternate function in the IOCONFIG
block.
I/O - PIO1_0 — General purpose digital input/output pin.
I- AD1 — A/D converter, input 1.
I- CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.
R/PIO1_1/AD2/
CT32B1_MAT0 23[5] no - I;PU R — Reserved. Configure for an alternate function in the IOCONFIG
block.
I/O - PIO1_1 — General purpose digital input/output pin.
I- AD2 — A/D converter, input 2.
O- CT32B1_MAT0 — Match output 0 for 32-bit timer 1.
R/PIO1_2/AD3/
CT32B1_MAT1 24[5] no - I;PU R — Reserved. Configure for an alternate function in the IOCONFIG
block.
I/O - PIO1_2 — General purpose digital input/output pin.
I- AD3 — A/D converter, input 3.
O- CT32B1_MAT1 — Match output 1 for 32-bit timer 1.
SWDIO/PIO1_3/
AD4/CT32B1_MAT2 25[5] no I/O I;PU SWDIO — Serial wire debug input/output.
I/O - PIO1_3 — General purpose digital input/output pin.
I- AD4 — A/D converter, input 4.
O- CT32B1_MAT2 — Match output 2 for 32-bit timer 1.
PIO1_4/AD5/
CT32B1_MAT3/
WAKEUP
26[5] no I/O I;PU PIO1_4 — General purpose digital input/output pin with 10 ns glitch
filter. In Deep power-down mode, this pin serves as the Deep
power-down mode wake-up pin with 20 ns glitch filter. Pull this pin
HIGH externally before entering Deep power-down mode. Pull this pin
LOW to exit Deep power-down mode. A LOW-going pulse as short as
50 ns wakes up the part.
I- AD5 — A/D converter, input 5.
O- CT32B1_MAT3 — Match output 3 for 32-bit timer 1.
PIO1_5/RTS/
CT32B0_CAP0 30[3] no I/O I;PU PIO1_5 — General purpose digital input/output pin.
O- RTS — Request To Send output for UART.
I- CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.
PIO1_6/RXD/
CT32B0_MAT0 31[3] no I/O I;PU PIO1_6 — General purpose digital input/output pin.
I- RXD — Receiver input for UART.
O- CT32B0_MAT0 — Match output 0 for 32-bit timer 0.
Table 9. LPC1100 and LPC1100L series: LPC1111/12/13/14 pin description table (HVQFN33 package) …continued
Symbol Pin Start
logic
input
Type Reset
state
[1]
Description
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Product data sheet Rev. 9.2 — 26 March 2014 35 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to 2.6 V for
LPC111x/101/201/301, pins pulled up to full VDD level on LPC111x/002/102/202/302 (VDD = 3.3 V)); IA = inactive, no pull-up/down
enabled.
[2] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up
from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. See Figure 52 for the
reset pad configuration.
[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 51).
[4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus. The pin requires an external
pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain
configuration applies to all functions on this pin.
[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
When configured as a ADC input, digital section of the pad is disabled, and the pin is not 5 V tolerant (see Figure 51).
PIO1_7/TXD/
CT32B0_MAT1 32[3] no I/O I;PU PIO1_7 — General purpose digital input/output pin.
O- TXD — Transmitter output for UART.
O- CT32B0_MAT1 — Match output 1 for 32-bit timer 0.
PIO1_8/
CT16B1_CAP0 7[3] no I/O I;PU PIO1_8 — General purpose digital input/output pin.
I- CT16B1_CAP0 — Capture input 0 for 16-bit timer 1.
PIO1_9/
CT16B1_MAT0 12[3] no I/O I;PU PIO1_9 — General purpose digital input/output pin.
O- CT16B1_MAT0 — Match output 0 for 16-bit timer 1.
PIO1_10/AD6/
CT16B1_MAT1 20[5] no I/O I;PU PIO1_10 — General purpose digital input/output pin.
I- AD6 — A/D converter, input 6.
O- CT16B1_MAT1 — Match output 1 for 16-bit timer 1.
PIO1_11/AD7 27[5] no I/O I;PU PIO1_11 — General purpose digital input/output pin.
I- AD7 — A/D converter, input 7.
PIO2_0 Port 2 — Port 2 is a 12-bit I/O port with individual direction and
function controls for each bit. The operation of port 2 pins depends on
the function selected through the IOCONFIG register block. Pins
PIO2_1 to PIO2_11 are not available.
PIO2_0/DTR 1[3] no I/O I;PU PIO2_0 — General purpose digital input/output pin.
O- DTR — Data Terminal Ready output for UART.
PIO3_0 to PIO3_5 Port 3 — Port 3 is a 12-bit I/O port with individual direction and
function controls for each bit. The operation of port 3 pins depends on
the function selected through the IOCONFIG register block. Pins
PIO3_0, PIO3_1, PIO3_3 and PIO3_6 to PIO3_11 are not available.
PIO3_2 28[3] no I/O I;PU PIO3_2 — General purpose digital input/output pin.
PIO3_4 13[3] no I/O I;PU PIO3_4 — General purpose digital input/output pin.
PIO3_5 14[3] no I/O I;PU PIO3_5 — General purpose digital input/output pin.
VDD 6; 29 - I - 3.3 V supply voltage to the internal regulator, the external rail, and the
ADC. Also used as the ADC reference voltage.
XTALIN 4[6] - I - Input to the oscillator circuit and internal clock generator circuits. Input
voltage must not exceed 1.8 V.
XTALOUT 5[6] - O - Output from the oscillator amplifier.
VSS 33 - - - Thermal pad. Connect to ground.
Table 9. LPC1100 and LPC1100L series: LPC1111/12/13/14 pin description table (HVQFN33 package) …continued
Symbol Pin Start
logic
input
Type Reset
state
[1]
Description
01, 02, H2, 3, H3, H6,
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Product data sheet Rev. 9.2 — 26 March 2014 36 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
[6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
Table 10. LPC1100XL series: LPC1113/14/15 pin description table (LQFP48 and TFBGA48 package)
Symbol
LQFP48
TFBGA48
Start
logic
input
Type Reset
state
[1]
Description
PIO0_0 to PIO0_11 I/O Port 0 — Port 0 is a 12-bit I/O port with individual
direction and function controls for each bit. The
operation of port 0 pins depends on the function
selected through the IOCONFIG register block.
RESET/PIO0_0 3[2] C1[2] yes I I; PU RESET — External reset input with 20 ns glitch filter. A
LOW-going pulse as short as 50 ns on this pin resets
the device, causing I/O ports and peripherals to take on
their default states, and processor execution to begin at
address 0.
In deep power-down mode, this pin must be pulled
HIGH externally. The RESET pin can be left
unconnected or be used as a GPIO pin if an external
RESET function is not needed and Deep power-down
mode is not used.
I/O - PIO0_0 — General purpose digital input/output pin with
10 ns glitch filter.
PIO0_1/CLKOUT/
CT32B0_MAT2 4[3] C2[3] yes I/O I; PU PIO0_1 — General purpose digital input/output pin. A
LOW level on this pin during reset starts the ISP
command handler.
O-CLKOUT — Clockout pin.
O-CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
PIO0_2/SSEL0/
CT16B0_CAP0 10[3] F1[3] yes I/O I; PU PIO0_2 — General purpose digital input/output pin.
I/O - SSEL0 — Slave Select for SPI0.
I-CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
PIO0_3 14[3] H2[3] yes I/O I; PU PIO0_3 — General purpose digital input/output pin.
PIO0_4/SCL 15[4] G3[4] yes I/O I; IA PIO0_4 — General purpose digital input/output pin
(open-drain).
I/O - SCL — I2C-bus, open-drain clock input/output.
High-current sink only if I2C Fast-mode Plus is selected
in the I/O configuration register.
PIO0_5/SDA 16[4] H3[4] yes I/O I; IA PIO0_5 — General purpose digital input/output pin
(open-drain).
I/O - SDA — I2C-bus, open-drain data input/output.
High-current sink only if I2C Fast-mode Plus is selected
in the I/O configuration register.
PIO0_6/SCK0 22[3] H6[3] yes I/O I; PU PIO0_6 — General purpose digital input/output pin.
I/O - SCK0 — Serial clock for SPI0.
PIO0_7/CTS 23[3] G7[3] yes I/O I; PU PIO0_7 — General purpose digital input/output pin
(high-current output driver).
I-CTS — Clear To Send input for UART.
E7, D8, C7, 08, E7, ES,
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Product data sheet Rev. 9.2 — 26 March 2014 37 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
PIO0_8/MISO0/
CT16B0_MAT0 27[3] F8[3] yes I/O I; PU PIO0_8 — General purpose digital input/output pin.
I/O - MISO0 — Master In Slave Out for SPI0.
O-CT16B0_MAT0 — Match output 0 for 16-bit timer 0.
PIO0_9/MOSI0/
CT16B0_MAT1 28[3] F7[3] yes I/O I; PU PIO0_9 — General purpose digital input/output pin.
I/O - MOSI0 — Master Out Slave In for SPI0.
O-CT16B0_MAT1 — Match output 1 for 16-bit timer 0.
SWCLK/PIO0_10/
SCK0/
CT16B0_MAT2
29[3] E7[3] yes I I; PU SWCLK — Serial wire clock.
I/O - PIO0_10 — General purpose digital input/output pin.
I/O - SCK0 — Serial clock for SPI0.
O-CT16B0_MAT2 — Match output 2 for 16-bit timer 0.
R/PIO0_11/
AD0/CT32B0_MAT3 32[5] D8[5] yes I I; PU R — Reserved. Configure for an alternate function in
the IOCONFIG block.
I/O - PIO0_11 — General purpose digital input/output pin.
I-AD0 — A/D converter, input 0.
O-CT32B0_MAT3 — Match output 3 for 32-bit timer 0.
PIO1_0 to PIO1_11 I/O Port 1 — Port 1 is a 12-bit I/O port with individual
direction and function controls for each bit. The
operation of port 1 pins depends on the function
selected through the IOCONFIG register block.
R/PIO1_0/
AD1/CT32B1_CAP0 33[5] C7[5] yes I I; PU R — Reserved. Configure for an alternate function in
the IOCONFIG block.
I/O - PIO1_0 — General purpose digital input/output pin.
I-AD1 — A/D converter, input 1.
I-CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.
R/PIO1_1/
AD2/CT32B1_MAT0 34[5] C8[5] no O I; PU R — Reserved. Configure for an alternate function in
the IOCONFIG block.
I/O - PIO1_1 — General purpose digital input/output pin.
I-AD2 — A/D converter, input 2.
O-CT32B1_MAT0 — Match output 0 for 32-bit timer 1.
R/PIO1_2/
AD3/CT32B1_MAT1 35[5] B7[5] no I I; PU R — Reserved. Configure for an alternate function in
the IOCONFIG block.
I/O - PIO1_2 — General purpose digital input/output pin.
I-AD3 — A/D converter, input 3.
O-CT32B1_MAT1 — Match output 1 for 32-bit timer 1.
SWDIO/PIO1_3/
AD4/CT32B1_MAT2 39[5] B6[5] no I/O I; PU SWDIO — Serial wire debug input/output.
I/O - PIO1_3 — General purpose digital input/output pin.
I-AD4 — A/D converter, input 4.
O-CT32B1_MAT2 — Match output 2 for 32-bit timer 1.
Table 10. LPC1100XL series: LPC1113/14/15 pin description table (LQFP48 and TFBGA48 package) …continued
Symbol
LQFP48
TFBGA48
Start
logic
input
Type Reset
state
[1]
Description
A6, A3, BS, 32, E8, A5, BI, H1,
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NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
PIO1_4/AD5/
CT32B1_MAT3/
WAKEUP
40[5] A6[5] no I/O I; PU PIO1_4 — General purpose digital input/output pin with
10 ns glitch filter. In Deep power-down mode, this pin
serves as the Deep power-down mode wake-up pin
with 20 ns glitch filter. Pull this pin HIGH externally
before entering Deep power-down mode. Pull this pin
LOW to exit Deep power-down mode. A LOW-going
pulse as short as 50 ns wakes up the part.
I-AD5 — A/D converter, input 5.
O-CT32B1_MAT3 — Match output 3 for 32-bit timer 1.
PIO1_5/RTS/
CT32B0_CAP0 45[3] A3[3] no I/O I; PU PIO1_5 — General purpose digital input/output pin.
O-RTS — Request To Send output for UART.
I-CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.
PIO1_6/RXD/
CT32B0_MAT0 46[3] B3[3] no I/O I; PU PIO1_6 — General purpose digital input/output pin.
I-RXD — Receiver input for UART.
O-CT32B0_MAT0 — Match output 0 for 32-bit timer 0.
PIO1_7/TXD/
CT32B0_MAT1 47[3] B2[3] no I/O I; PU PIO1_7 — General purpose digital input/output pin.
O-TXD — Transmitter output for UART.
O-CT32B0_MAT1 — Match output 1 for 32-bit timer 0.
PIO1_8/
CT16B1_CAP0 9[3] F2[3] no I/O I; PU PIO1_8 — General purpose digital input/output pin.
I-CT16B1_CAP0 — Capture input 0 for 16-bit timer 1.
PIO1_9/
CT16B1_MAT0/
MOSI1
17[3] G4[3] no I/O I; PU PIO1_9 — General purpose digital input/output pin.
O-CT16B1_MAT0 — Match output 0 for 16-bit timer 1.
I/O - MOSI1 — Master Out Slave In for SPI1.
PIO1_10/AD6/
CT16B1_MAT1/
MISO1
30[5] E8[5] no I/O I; PU PIO1_10 — General purpose digital input/output pin.
I-AD6 — A/D converter, input 6.
O-CT16B1_MAT1 — Match output 1 for 16-bit timer 1.
I/O - MISO1 — Master In Slave Out for SPI1.
PIO1_11/AD7/
CT32B1_CAP1 42[5] A5[5] no I/O I; PU PIO1_11 — General purpose digital input/output pin.
I-AD7 — A/D converter, input 7.
I-CT32B1_CAP1 — Capture input 1 for 32-bit timer 1.
PIO2_0 to PIO2_11 I/O Port 2 — Port 2 is a 12-bit I/O port with individual
direction and function controls for each bit. The
operation of port 2 pins depends on the function
selected through the IOCONFIG register block.
PIO2_0/DTR/SSEL1 2[3] B1[3] no I/O I; PU PIO2_0 — General purpose digital input/output pin.
O-DTR — Data Terminal Ready output for UART.
I/O - SSEL1 — Slave Select for SPI1.
PIO2_1/DSR/SCK1 13[3] H1[3] no I/O I; PU PIO2_1 — General purpose digital input/output pin.
I-DSR — Data Set Ready input for UART.
I/O - SCK1 — Serial clock for SPI1.
Table 10. LPC1100XL series: LPC1113/14/15 pin description table (LQFP48 and TFBGA48 package) …continued
Symbol
LQFP48
TFBGA48
Start
logic
input
Type Reset
state
[1]
Description
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Product data sheet Rev. 9.2 — 26 March 2014 39 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
PIO2_2/DCD/MISO1 26[3] G8[3] no I/O I; PU PIO2_2 — General purpose digital input/output pin.
I-DCD — Data Carrier Detect input for UART.
I/O - MISO1 — Master In Slave Out for SPI1.
PIO2_3/RI/MOSI1 38[3] A7[3] no I/O I; PU PIO2_3 — General purpose digital input/output pin.
I-RI — Ring Indicator input for UART.
I/O - MOSI1 — Master Out Slave In for SPI1.
PIO2_4/
CT16B1_MAT1/
SSEL1
19[3] G5[3] no I/O I; PU PIO2_4 — General purpose digital input/output pin.
O-CT16B1_MAT1 — Match output 1 for 16-bit timer 1.
O-SSEL1 — Slave Select for SPI1.
PIO2_5/
CT32B0_MAT0 20[3] H5[3] no I/O I; PU PIO2_5 — General purpose digital input/output pin.
O-CT32B0_MAT0 — Match output 0 for 32-bit timer 0.
PIO2_6/
CT32B0_MAT1 1[3] A1[3] no I/O I; PU PIO2_6 — General purpose digital input/output pin.
O-CT32B0_MAT1 — Match output 1 for 32-bit timer 0.
PIO2_7/
CT32B0_MAT2/RXD 11[3] G2[3] no I/O I; PU PIO2_7 — General purpose digital input/output pin.
O-CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
I-RXD — Receiver input for UART.
PIO2_8/
CT32B0_MAT3/TXD 12[3] G1[3] no I/O I; PU PIO2_8 — General purpose digital input/output pin.
O-CT32B0_MAT3 — Match output 3 for 32-bit timer 0.
O-TXD — Transmitter output for UART.
PIO2_9/
CT32B0_CAP0 24[3] H7[3] no I/O I; PU PIO2_9 — General purpose digital input/output pin.
I-CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.
PIO2_10 25[3] H8[3] no I/O I; PU PIO2_10 — General purpose digital input/output pin.
PIO2_11/SCK0/
CT32B0_CAP1 31[3] D7[3] no I/O I; PU PIO2_11 — General purpose digital input/output pin.
I/O - SCK0 — Serial clock for SPI0.
I-CT32B0_CAP1 — Capture input for 32-bit timer 0.
PIO3_0 to PIO3_5 I/O Port 3 — Port 3 is a 12-bit I/O port with individual
direction and function controls for each bit. The
operation of port 3 pins depends on the function
selected through the IOCONFIG register block. Pins
PIO3_6 to PIO3_11 are not available.
PIO3_0/DTR/
CT16B0_MAT0/TXD 36[3] B8[3] no I/O I; PU PIO3_0 — General purpose digital input/output pin.
O-DTR — Data Terminal Ready output for UART.
O-CT16B0_MAT0 — Match output 0 for 16-bit timer 0.
O-TXD — Transmitter Output for UART.
PIO3_1/DSR/
CT16B0_MAT1/RXD 37[3] A8[3] no I/O I; PU PIO3_1 — General purpose digital input/output pin.
I-DSR — Data Set Ready input for UART.
O-CT16B0_MAT1 — Match output 1 for 16-bit timer 0.
I-RXD — Receiver input for UART.
Table 10. LPC1100XL series: LPC1113/14/15 pin description table (LQFP48 and TFBGA48 package) …continued
Symbol
LQFP48
TFBGA48
Start
logic
input
Type Reset
state
[1]
Description
A4, H4, D1, E1,
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Product data sheet Rev. 9.2 — 26 March 2014 40 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full VDD level (VDD = 3.3 V));
IA = inactive, no pull-up/down enabled.
[2] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up
from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. See Figure 52 for the
reset pad configuration.
[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 51).
[4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus. The pin requires an external
pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain
configuration applies to all functions on this pin.
[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 51).
[6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
PIO3_2/DCD/
CT16B0_MAT2/
SCK1
43[3] A4[3] no I/O I; PU PIO3_2 — General purpose digital input/output pin.
I-DCD — Data Carrier Detect input for UART.
O-CT16B0_MAT2 — Match output 2 for 16-bit timer 0.
I/O - SCK1 — Serial clock for SPI1.
PIO3_3/RI/
CT16B0_CAP0 48[3] A2[3] no I/O I; PU PIO3_3 — General purpose digital input/output pin.
I-RI — Ring Indicator input for UART.
I-CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
PIO3_4/
CT16B0_CAP1/RXD 18[3] H4[3] no I/O I; PU PIO3_4 — General purpose digital input/output pin.
I-CT16B0_CAP1 — Capture input 1 for 16-bit timer 0.
I-RXD — Receiver input for UART
PIO3_5/
CT16B1_CAP1/TXD 21[3] G6[3] no I/O I; PU PIO3_5 — General purpose digital input/output pin.
I-CT16B1_CAP1 — Capture input 1 for 16-bit timer 1.
O-TXD — Transmitter output for UART
VDD 8; 44 E2;
B4 - I - 3.3 V supply voltage to the internal regulator, the
external rail, and the ADC. Also used as the ADC
reference voltage.
XTALIN 6[6] D1[6] - I - Input to the oscillator circuit and internal clock generator
circuits. Input voltage must not exceed 1.8 V.
XTALOUT 7[6] E1[6] - O - Output from the oscillator amplifier.
VSS 5; 41 D2;
B5 - I - Ground.
Table 10. LPC1100XL series: LPC1113/14/15 pin description table (LQFP48 and TFBGA48 package) …continued
Symbol
LQFP48
TFBGA48
Start
logic
input
Type Reset
state
[1]
Description
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 41 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Table 11. LPC1100XL series: LPC1111/12/13/14 pin description table (HVQFN33 package)
Symbol Pin Start
logic
input
Type Reset
state
[1]
Description
PIO0_0 to PIO0_11 Port 0 — Port 0 is a 12-bit I/O port with individual direction and
function controls for each bit. The operation of port 0 pins depends on
the function selected through the IOCONFIG register block.
RESET/PIO0_0 2[2] yes I I;PU RESET — External reset input with 20 ns glitch filter. A LOW-going
pulse as short as 50 ns on this pin resets the device, causing I/O ports
and peripherals to take on their default states and processor execution
to begin at address 0.
In deep power-down mode, this pin must be pulled HIGH externally.
The RESET pin can be left unconnected or be used as a GPIO pin if
an external RESET function is not needed and Deep power-down
mode is not used.
I/O - PIO0_0 — General purpose digital input/output pin with 10 ns glitch
filter.
PIO0_1/CLKOUT/
CT32B0_MAT2 3[3] yes I/O I;PU PIO0_1 — General purpose digital input/output pin. A LOW level on
this pin during reset starts the ISP command handler.
O- CLKOUT — Clock out pin.
O- CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
PIO0_2/SSEL0/
CT16B0_CAP0 8[3] yes I/O I;PU PIO0_2 — General purpose digital input/output pin.
I/O - SSEL0 — Slave select for SPI0.
I- CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
PIO0_3 9[3] yes I/O I;PU PIO0_3 — General purpose digital input/output pin.
PIO0_4/SCL 10[4] yes I/O I;IA PIO0_4 — General purpose digital input/output pin (open-drain).
I/O - SCL — I2C-bus, open-drain clock input/output. High-current sink only
if I2C Fast-mode Plus is selected in the I/O configuration register.
PIO0_5/SDA 11[4] yes I/O I;IA PIO0_5 — General purpose digital input/output pin (open-drain).
I/O - SDA — I2C-bus, open-drain data input/output. High-current sink only if
I2C Fast-mode Plus is selected in the I/O configuration register.
PIO0_6/SCK0 15[3] yes I/O I;PU PIO0_6 — General purpose digital input/output pin.
I/O - SCK0 — Serial clock for SPI0.
PIO0_7/CTS 16[3] yes I/O I;PU PIO0_7 — General purpose digital input/output pin (high-current
output driver).
I- CTS — Clear To Send input for UART.
PIO0_8/MISO0/
CT16B0_MAT0 17[3] yes I/O I;PU PIO0_8 — General purpose digital input/output pin.
I/O - MISO0 — Master In Slave Out for SPI0.
O- CT16B0_MAT0 — Match output 0 for 16-bit timer 0.
PIO0_9/MOSI0/
CT16B0_MAT1 18[3] yes I/O I;PU PIO0_9 — General purpose digital input/output pin.
I/O - MOSI0 — Master Out Slave In for SPI0.
O- CT16B0_MAT1 — Match output 1 for 16-bit timer 0.
SWCLK/PIO0_10/
SCK0/
CT16B0_MAT2
19[3] yes I I;PU SWCLK — Serial wire clock.
I/O - PIO0_10 — General purpose digital input/output pin.
I/O - SCK0 — Serial clock for SPI0.
O- CT16B0_MAT2 — Match output 2 for 16-bit timer 0.
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Product data sheet Rev. 9.2 — 26 March 2014 42 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
R/PIO0_11/AD0/
CT32B0_MAT3 21[5] yes - I;PU R — Reserved. Configure for an alternate function in the IOCONFIG
block.
I/O - PIO0_11 — General purpose digital input/output pin.
I- AD0 — A/D converter, input 0.
O- CT32B0_MAT3 — Match output 3 for 32-bit timer 0.
PIO1_0 to PIO1_11 Port 1 — Port 1 is a 12-bit I/O port with individual direction and
function controls for each bit. The operation of port 1 pins depends on
the function selected through the IOCONFIG register block.
R/PIO1_0/AD1/
CT32B1_CAP0 22[5] yes - I;PU R — Reserved. Configure for an alternate function in the IOCONFIG
block.
I/O - PIO1_0 — General purpose digital input/output pin.
I- AD1 — A/D converter, input 1.
I- CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.
R/PIO1_1/AD2/
CT32B1_MAT0 23[5] no - I;PU R — Reserved. Configure for an alternate function in the IOCONFIG
block.
I/O - PIO1_1 — General purpose digital input/output pin.
I- AD2 — A/D converter, input 2.
O- CT32B1_MAT0 — Match output 0 for 32-bit timer 1.
R/PIO1_2/AD3/
CT32B1_MAT1 24[5] no - I;PU R — Reserved. Configure for an alternate function in the IOCONFIG
block.
I/O - PIO1_2 — General purpose digital input/output pin.
I- AD3 — A/D converter, input 3.
O- CT32B1_MAT1 — Match output 1 for 32-bit timer 1.
SWDIO/PIO1_3/
AD4/CT32B1_MAT2 25[5] no I/O I;PU SWDIO — Serial wire debug input/output.
I/O - PIO1_3 — General purpose digital input/output pin.
I- AD4 — A/D converter, input 4.
O- CT32B1_MAT2 — Match output 2 for 32-bit timer 1.
PIO1_4/AD5/
CT32B1_MAT3/
WAKEUP
26[5] no I/O I;PU PIO1_4 — General purpose digital input/output pin with 10 ns glitch
filter. In Deep power-down mode, this pin serves as the Deep
power-down mode wake-up pin with 20 ns glitch filter. Pull this pin
HIGH externally before entering Deep power-down mode. Pull this pin
LOW to exit Deep power-down mode. A LOW-going pulse as short as
50 ns wakes up the part.
I- AD5 — A/D converter, input 5.
O- CT32B1_MAT3 — Match output 3 for 32-bit timer 1.
PIO1_5/RTS/
CT32B0_CAP0 30[3] no I/O I;PU PIO1_5 — General purpose digital input/output pin.
O- RTS — Request To Send output for UART.
I- CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.
PIO1_6/RXD/
CT32B0_MAT0 31[3] no I/O I;PU PIO1_6 — General purpose digital input/output pin.
I- RXD — Receiver input for UART.
O- CT32B0_MAT0 — Match output 0 for 32-bit timer 0.
Table 11. LPC1100XL series: LPC1111/12/13/14 pin description table (HVQFN33 package) …continued
Symbol Pin Start
logic
input
Type Reset
state
[1]
Description
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NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
PIO1_7/TXD/
CT32B0_MAT1 32[3] no I/O I;PU PIO1_7 — General purpose digital input/output pin.
O- TXD — Transmitter output for UART.
O- CT32B0_MAT1 — Match output 1 for 32-bit timer 0.
PIO1_8/
CT16B1_CAP0 7[3] no I/O I;PU PIO1_8 — General purpose digital input/output pin.
I- CT16B1_CAP0 — Capture input 0 for 16-bit timer 1.
PIO1_9/
CT16B1_MAT0/
MOSI1
12[3] no I/O I;PU PIO1_9 — General purpose digital input/output pin.
O- CT16B1_MAT0 — Match output 0 for 16-bit timer 1.
I/O - MOSI1 — Master Out Slave In for SPI1
PIO1_10/AD6/
CT16B1_MAT1/
MISO1
20[5] no I/O I;PU PIO1_10 — General purpose digital input/output pin.
I- AD6 — A/D converter, input 6.
O- CT16B1_MAT1 — Match output 1 for 16-bit timer 1.
I/O - MISO1 — Master In Slave Out for SPI1
PIO1_11/AD7/
CT32B1_CAP1 27[5] no I/O I;PU PIO1_11 — General purpose digital input/output pin.
I- AD7 — A/D converter, input 7.
I- CT32B1_CAP1 — Capture input 1 for 32-bit timer 1.
PIO2_0 Port 2 — Port 2 is a 12-bit I/O port with individual direction and
function controls for each bit. The operation of port 2 pins depends on
the function selected through the IOCONFIG register block. Pins
PIO2_1 to PIO2_11 are not available.
PIO2_0/DTR/SSEL1 1[3] no I/O I;PU PIO2_0 — General purpose digital input/output pin.
O- DTR — Data Terminal Ready output for UART.
I/O - SSEL1 — Slave Select for SPI1.
PIO3_0 to PIO3_5 Port 3 — Port 3 is a 12-bit I/O port with individual direction and
function controls for each bit. The operation of port 3 pins depends on
the function selected through the IOCONFIG register block. Pins
PIO3_0, PIO3_1, PIO3_3 and PIO3_6 to PIO3_11 are not available.
PIO3_2/
CT16B0_MAT2/
SCK1
28[3] no I/O I;PU PIO3_2 — General purpose digital input/output pin.
O- CT16B0_MAT2 — Match output 2 for 16-bit timer 0.
I/O - SCK1 — Serial clock for SPI1.
PIO3_4/
CT16B0_CAP1/RXD 13[3] no I/O I;PU PIO3_4 — General purpose digital input/output pin.
I- CT16B0_CAP1 — Capture input 1 for 16-bit timer 0.
I- RXD — Receiver input for UART.
PIO3_5/
CT16B1_CAP1/TXD 14[3] no I/O I;PU PIO3_5 — General purpose digital input/output pin.
I- CT16B1_CAP1 — Capture input 1 for 16-bit timer 1.
O- TXD — Transmitter output for UART.
Table 11. LPC1100XL series: LPC1111/12/13/14 pin description table (HVQFN33 package) …continued
Symbol Pin Start
logic
input
Type Reset
state
[1]
Description
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Product data sheet Rev. 9.2 — 26 March 2014 44 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full VDD level (VDD = 3.3 V));
IA = inactive, no pull-up/down enabled.
[2] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up
from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. See Figure 52 for the
reset pad configuration.
[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 51).
[4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus. The pin requires an external
pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain
configuration applies to all functions on this pin.
[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
When configured as a ADC input, digital section of the pad is disabled, and the pin is not 5 V tolerant (see Figure 51).
[6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
VDD 6; 29 - I - 3.3 V supply voltage to the internal regulator, the external rail, and the
ADC. Also used as the ADC reference voltage.
XTALIN 4[6] - I - Input to the oscillator circuit and internal clock generator circuits. Input
voltage must not exceed 1.8 V.
XTALOUT 5[6] - O - Output from the oscillator amplifier.
VSS 33 - - - Thermal pad. Connect to ground.
Table 11. LPC1100XL series: LPC1111/12/13/14 pin description table (HVQFN33 package) …continued
Symbol Pin Start
logic
input
Type Reset
state
[1]
Description
Figure 14
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Product data sheet Rev. 9.2 — 26 March 2014 45 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
7. Functional description
7.1 ARM Cortex-M0 processor
The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high
performance and very low power consumption.
7.2 On-chip flash program memory
The LPC1110/11/12/13/14/15 contain 64 kB (LPC1115), 56 kB (LPC1114/333), 48 kB
(LPC1114/323), 32 kB (LPC1114), 24 kB (LPC1113), 16 kB (LPC1112), 8 kB (LPC1111) or
4 kB (LPC1110) of on-chip flash memory.
7.3 On-chip SRAM
The LPC1110/11/12/13/14/15 contain a total of 8 kB, 4 kB, 2 kB, or 1 kB on-chip static
RAM memory.
7.4 Memory map
The LPC1110/11/12/13/14/15 incorporate several distinct memory regions, shown in the
following figures. Figure 14 shows the overall map of the entire address space from the
user program viewpoint following reset. The interrupt vector area supports address
remapping.
The AHB peripheral area is 2 MB in size, and is divided to allow for up to 128 peripherals.
The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals.
Each peripheral of either type is allocated 16 kB of space. This allows simplifying the
address decoding for each peripheral.
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Product data sheet Rev. 9.2 — 26 March 2014 46 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
(1) LQFP48 package only.
(1) Not on part LPC1112FDH20/102.
Fig 14. LPC1100 and LPC1100L series memory map
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Product data sheet Rev. 9.2 — 26 March 2014 47 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
7.5 Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The
tight coupling to the CPU allows for low interrupt latency and efficient processing of late
arriving interrupts.
7.5.1 Features
•Controls system exceptions and peripheral interrupts.
Fig 15. LPC1100XL series memory map
0x5000 0000
0x5001 0000
0x5002 0000
0x5020 0000
AHB peripherals
127-16 reserved
GPIO PIO1
4-7
0x5003 0000
0x5004 0000
GPIO PIO2
GPIO PIO3
8-11
12-15
GPIO PIO0
0-3
APB peripherals
0x4000 4000
0x4000 8000
0x4000 C000
0x4001 0000
0x4001 8000
0x4002 0000
0x4002 8000
0x4003 8000
0x4003 C000
0x4004 0000
0x4004 4000
0x4004 8000
0x4004 C000
0x4005 8000
0x4005 C000
0x4008 0000
0x4002 4000
0x4001 C000
0x4001 4000
0x4000 0000
WWDT
32-bit counter/timer 0
32-bit counter/timer 1
ADC
UART
PMU
I2C-bus
13-10 reserved
reserved
reserved
21-19 reserved
31-23 reserved
0
1
2
3
4
5
6
7
8
9
16
15
14
17
18
reserved
reserved
reserved
0x0000 0000
0 GB
0.5 GB
4 GB
1 GB
0x0000 2000
0x1000 2000
0x1000 1000
0x1000 0800
0x1FFF 0000
0x1FFF 4000
0x2000 0000
0x4000 0000
0x4008 0000
0x5000 0000
0x5020 0000
0xFFFF FFFF
reserved
reserved
reserved
APB peripherals
AHB peripherals
8 kB SRAM (LPC1113/14/15/303/323/333)
4 kB SRAM (LPC1111/12/13/14/203)
2 kB SRAM (LPC1111/12/103)
0x1000 0000
LPC1111/12/13/14/15XL
8 kB on-chip flash (LPC1111)
0x0000 4000
0x0000 6000
16 kB on-chip flash (LPC1112)
0x0000 8000
32 kB on-chip flash (LPC1114)
24 kB on-chip flash (LPC1113)
0x0000 C000
0x0000 E000
48 kB on-chip flash (LPC1114/323)
0x0001 0000
64 kB on-chip flash (LPC1115)
56 kB on-chip flash (LPC1114/333)
16 kB boot ROM
0x0000 0000
0x0000 00C0
active interrupt vectors 002aag788
reserved
SPI0
16-bit counter/timer 1
16-bit counter/timer 0
IOCONFIG
system control
22 SPI1
flash controller
0xE000 0000
0xE010 0000
private peripheral bus
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Product data sheet Rev. 9.2 — 26 March 2014 48 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
•In the LPC1110/11/12/13/14/15, the NVIC supports 32 vectored interrupts including up
to 13 inputs to the start logic from individual GPIO pins.
•Four programmable interrupt priority levels with hardware priority level masking.
•Software interrupt generation.
7.5.2 Interrupt sources
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags. Individual interrupt flags may also represent more than one interrupt
source.
Any GPIO pin (total of up to 42 pins) regardless of the selected function, can be
programmed to generate an interrupt on a level, or rising edge or falling edge, or both.
7.6 IOCONFIG block
The IOCONFIG block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on-chip peripherals.
Peripherals should be connected to the appropriate pins prior to being activated and prior
to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is
not mapped to a related pin should be considered undefined.
7.7 Fast general purpose parallel I/O
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs
can be set or cleared in one write operation.
LPC1110/11/12/13/14/15 use accelerated GPIO functions:
•GPIO registers are a dedicated AHB peripheral so that the fastest possible I/O timing
can be achieved.
•Entire port value can be written in one instruction.
Additionally, any GPIO pin (total of up to 42 pins) providing a digital function can be
programmed to generate an interrupt on a level, a rising or falling edge, or both.
7.7.1 Features
•Bit level port registers allow a single instruction to set or clear any number of bits in
one write operation.
•Direction control of individual bits.
•All I/O default to inputs with pull-ups enabled after reset with the exception of the
I2C-bus pins PIO0_4 and PIO0_5.
•Pull-up/pull-down resistor configuration can be programmed through the IOCONFIG
block for each GPIO pin (except for pins PIO0_4 and PIO0_5).
•On the LPC1100, all GPIO pins (except PIO0_4 and PIO0_5) are pulled up to 2.6 V
(VDD = 3.3 V) if their pull-up resistor is enabled in the IOCONFIG block.
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32-bit ARM Cortex-M0 microcontroller
•On the LPC1100L and LPC1100XL series, all GPIO pins (except PIO0_4 and PIO0_5)
are pulled up to 3.3 V (VDD = 3.3 V) if their pull-up resistor is enabled in the
IOCONFIG block.
•Programmable open-drain mode for series LPC1100L and LPC1100XL.
7.8 UART
The LPC1110/11/12/13/14/15 contain one UART.
Support for RS-485/9-bit mode allows both software address detection and automatic
address detection using 9-bit mode.
The UART includes a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
7.8.1 Features
•Maximum UART data bit rate of 3.125 MBit/s.
•16 Byte Receive and Transmit FIFOs.
•Register locations conform to 16C550 industry standard.
•Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
•Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
•FIFO control mechanism that enables software flow control implementation.
•Support for RS-485/9-bit mode.
•Support for modem control.
7.9 SPI serial I/O controller
The LPC1100 and LPC1100L series contain two SPI controllers on the LQFP48 package
and one SPI controller on the HVQFN33/TSSOP28/DIP28/TSSOP20/SO20 packages
(SPI0).
The LPC1100XL series contain two SPI controllers.
Both SPI controllers support SSP features.
The SPI controller is capable of operation on a SSP, 4-wire SSI, or Microwire bus. It can
interact with multiple masters and slaves on the bus. Only a single master and a single
slave can communicate on the bus during a given data transfer. The SPI supports full
duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the
slave and from the slave to the master. In practice, often only one of these data flows
carries meaningful data.
7.9.1 Features
•Maximum SPI speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode)
•Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
•Synchronous serial communication
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32-bit ARM Cortex-M0 microcontroller
•Master or slave operation
•8-frame FIFOs for both transmit and receive
•4-bit to 16-bit frame
7.10 I2C-bus serial I/O controller
The LPC1110/11/12/13/14/15 contain one I2C-bus controller.
Remark: Part LPC1112FDH20/102 does not contain the I2C-bus controller.
The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line
(SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be
controlled by more than one bus master connected to it.
7.10.1 Features
•The I2C-interface is a standard I2C-bus compliant interface with open-drain pins. The
I2C-bus interface also supports Fast-mode Plus with bit rates up to 1 Mbit/s.
•Easy to configure as master, slave, or master/slave.
•Programmable clocks allow versatile rate control.
•Bidirectional data transfer between masters and slaves.
•Multi-master bus (no central master).
•Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
•Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
•Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
•The I2C-bus can be used for test and diagnostic purposes.
•The I2C-bus controller supports multiple address recognition and a bus monitor mode.
7.11 10-bit ADC
The LPC1110/11/12/13/14/15 contain one ADC. It is a single 10-bit successive
approximation ADC with eight channels.
7.11.1 Features
•10-bit successive approximation ADC.
•Input multiplexing among 8 pins.
•Power-down mode.
•Measurement range 0 V to VDD.
•10-bit conversion time 2.44 s (up to 400 kSamples/s).
•Burst conversion mode for single or multiple inputs.
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32-bit ARM Cortex-M0 microcontroller
•Optional conversion on transition of input pin or timer match signal.
•Individual result registers for each ADC channel to reduce interrupt overhead.
7.12 General purpose external event counter/timers
The LPC1110/11/12/13/14/15 include two 32-bit counter/timers and two 16-bit
counter/timers. The counter/timer is designed to count cycles of the system derived clock.
It can optionally generate interrupts or perform other actions at specified timer values,
based on four match registers. Each counter/timer also includes up to two capture inputs
to trap the timer value when an input signal transitions, optionally generating an interrupt.
7.12.1 Features
•A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.
•Counter or timer operation.
•Up to two capture channels per timer, that can take a snapshot of the timer value
when an input signal transitions. A capture event may also generate an interrupt.
•The timer and prescaler may be configured to be cleared on a designated capture
event. This feature permits easy pulse width measurement by clearing the timer on
the leading edge of an input pulse and capturing the timer value on the trailing edge.
•Four match registers per timer that allow:
–Continuous operation with optional interrupt generation on match.
–Stop timer on match with optional interrupt generation.
–Reset timer on match with optional interrupt generation.
•Up to four external outputs corresponding to match registers, with the following
capabilities:
–Set LOW on match.
–Set HIGH on match.
–Toggle on match.
–Do nothing on match.
7.13 System tick timer
The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a fixed time interval (typically 10 ms).
7.14 Watchdog timer (LPC1100 series, LPC111x/101/201/301)
Remark: The watchdog timer without windowed features is available on parts
LPC111x/101/201/301.
The purpose of the watchdog is to reset the microcontroller within a selectable time
period.
7.14.1 Features
•Internally resets chip if not periodically reloaded.
•Debug mode.
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Product data sheet Rev. 9.2 — 26 March 2014 52 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
•Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
•Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
•Flag to indicate watchdog reset.
•Programmable 24-bit timer with internal prescaler.
•Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 224 4) in
multiples of Tcy(WDCLK) 4.
•The Watchdog Clock (WDCLK) source can be selected from the Internal RC oscillator
(IRC), the Watchdog oscillator, or the main clock. This gives a wide range of potential
timing choices of Watchdog operation under different power reduction conditions. It
also provides the ability to run the WDT from an entirely internal source that is not
dependent on an external crystal and its associated components and wiring for
increased reliability.
7.15 Windowed WatchDog Timer (LPC1100L and LPC1100XL series)
Remark: The windowed watchdog timer is available on the LPC1100L and LPC1100XL
series only.
The purpose of the watchdog is to reset the controller if software fails to periodically
service it within a programmable time window.
7.15.1 Features
•Internally resets chip if not periodically reloaded during the programmable time-out
period.
•Optional windowed operation requires reload to occur between a minimum and
maximum time period, both programmable.
•Optional warning interrupt can be generated at a programmable time prior to
watchdog time-out.
•Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
•Incorrect feed sequence causes reset or interrupt if enabled.
•Flag to indicate watchdog reset.
•Programmable 24-bit timer with internal prescaler.
•Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 224 4) in
multiples of Tcy(WDCLK) 4.
•The Watchdog Clock (WDCLK) source can be selected from the IRC or the dedicated
watchdog oscillator (WDO). This gives a wide range of potential timing choices of
watchdog operation under different power conditions.
7.16 Clocking and power control
7.16.1 Crystal oscillators
The LPC1110/11/12/13/14/15 include three independent oscillators. These are the system
oscillator, the Internal RC oscillator (IRC), and the Watchdog oscillator. Each oscillator can
be used for more than one purpose as required in a particular application.
L] /
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Following reset, the LPC1110/11/12/13/14/15 will operate from the Internal RC oscillator
until switched by software. This allows systems to operate without any external crystal and
the bootloader code to operate at a known frequency.
See Figure 16 for an overview of the LPC1110/11/12/13/14/15 clock generation.
7.16.1.1 Internal RC oscillator
The IRC may be used as the clock source for the WDT, and/or as the clock that drives the
PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is
trimmed to 1 % accuracy over the entire voltage and temperature range.
Upon power-up or any chip reset, the LPC1110/11/12/13/14/15 use the IRC as the clock
source. Software may later switch to one of the other available clock sources.
7.16.1.2 System oscillator
The system oscillator can be used as the clock source for the CPU, with or without using
the PLL.
Fig 16. LPC1110/11/12/13/14/15 clock generation block diagram
SYSTEM PLL
IRC oscillator
system oscillator
watchdog oscillator
IRC oscillator
watchdog oscillator
MAINCLKSEL
(main clock select)
SYSPLLCLKSEL
(system PLL clock select)
SYSTEM CLOCK
DIVIDER
AHB clock 0
(system)
SYSAHBCLKCTRL[1:18]
(AHB clock enable)
AHB clocks 1 to 18
(memories
and peripherals)
SPI0 PERIPHERAL
CLOCK DIVIDER SPI0
SPI1 PERIPHERAL
CLOCK DIVIDER SPI1
UART PERIPHERAL
CLOCK DIVIDER UART
WDT CLOCK
DIVIDER WDT
WDTUEN
(WDT clock update enable)
watchdog oscillator
IRC oscillator
system oscillator CLKOUT PIN CLOCK
DIVIDER CLKOUT pin
CLKOUTUEN
(CLKOUT update enable) 002aae514
main clock
system clock
IRC oscillator
18
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32-bit ARM Cortex-M0 microcontroller
The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be
boosted to a higher frequency, up to the maximum CPU operating frequency, by the
system PLL.
7.16.1.3 Watchdog oscillator
The watchdog oscillator can be used as a clock source that directly drives the CPU, the
watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is
programmable between 9.4 kHz and 2.3 MHz. The frequency spread over processing and
temperature is 40 %.
7.16.2 System PLL
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).
The multiplier can be an integer value from 1 to 32. The CCO operates in the range of
156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within
its frequency range while the PLL is providing the desired output frequency. The PLL
output frequency must be lower than 100 MHz. The output divider may be set to divide by
2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is
insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed
following a chip reset and may be enabled by software. The program must configure and
activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source.
The PLL settling time is 100 s.
7.16.3 Clock output
The LPC1110/11/12/13/14/15 features a clock output function that routes the IRC
oscillator, the system oscillator, the watchdog oscillator, or the main clock to an output pin.
7.16.4 Wake-up process
The LPC1110/11/12/13/14/15 begin operation at power-up and when awakened from
Deep power-down mode by using the 12 MHz IRC oscillator as the clock source. This
allows chip operation to resume quickly. If the system oscillator or the PLL is needed by
the application, software will need to enable these features and wait for them to stabilize
before they are used as a clock source.
7.16.5 Power control
The LPC1110/11/12/13/14/15 support a variety of power control features. There are three
special modes of processor power reduction: Sleep mode, Deep-sleep mode, and Deep
power-down mode. The CPU clock rate may also be controlled as needed by changing
clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This
allows a trade-off of power versus processing speed based on application requirements.
In addition, a register is provided for shutting down the clocks to individual on-chip
peripherals, allowing fine tuning of power consumption by eliminating all dynamic power
use in any peripherals that are not required for the application. Selected peripherals have
their own clock divider which provides even better power control.
7.16.5.1 Power profiles (LPC1100L and LPC1100XL series only)
The power consumption in Active and Sleep modes can be optimized for the application
through simple calls to the power profile. The power configuration routine configures the
LPC1110/11/12/13/14/15 for one of the following power modes:
Table 8 Table 9
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•Default mode corresponding to power configuration after reset.
•CPU performance mode corresponding to optimized processing capability.
•Efficiency mode corresponding to optimized balance of current consumption and CPU
performance.
•Low-current mode corresponding to lowest power consumption.
In addition, the power profile includes routines to select the optimal PLL settings for a
given system clock and PLL input clock.
7.16.5.2 Sleep mode
When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep
mode does not need any special sequence but re-enabling the clock to the ARM core.
In Sleep mode, execution of instructions is suspended until either a reset or interrupt
occurs. Peripheral functions continue operation during Sleep mode and may generate
interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses.
7.16.5.3 Deep-sleep mode
In Deep-sleep mode, the chip is in Sleep mode, and in addition all analog blocks are shut
down. As an exception, the user has the option to keep the watchdog oscillator and the
BOD circuit running for self-timed wake-up and BOD protection. Deep-sleep mode allows
for additional power savings.
Up to 13 pins total serve as external wake-up pins to the start logic to wake up the chip
from Deep-sleep mode.
Unless the watchdog oscillator is selected to run in Deep-sleep mode, the clock source
should be switched to IRC before entering Deep-sleep mode, because the IRC can be
switched on and off glitch-free.
7.16.5.4 Deep power-down mode
In Deep power-down mode, power is shut off to the entire chip with the exception of the
WAKEUP pin. The LPC1110/11/12/13/14/15 can wake up from Deep power-down mode
via the WAKEUP pin.
A LOW-going pulse as short as 50 ns wakes up the part from Deep power-down mode.
When entering Deep power-down mode, an external pull-up resistor is required on the
WAKEUP pin to hold it HIGH. The RESET pin must also be held HIGH to prevent it from
floating while in Deep power-down mode.
7.17 System control
7.17.1 Start logic
The start logic connects external pins to corresponding interrupts in the NVIC. Each pin
shown in Table 8 to Table 9 as input to the start logic has an individual interrupt in the
NVIC interrupt vector table. The start logic pins can serve as external interrupt pins when
the chip is running. In addition, an input signal on the start logic pins can wake up the chip
from Deep-sleep mode when all clocks are shut down.
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32-bit ARM Cortex-M0 microcontroller
The start logic must be configured in the system configuration block and in the NVIC
before being used.
7.17.2 Reset
Reset has four sources on the LPC1110/11/12/13/14/15: the RESET pin, the Watchdog
reset, Power-On Reset (POR), and the BrownOut Detection (BOD) circuit. The RESET
pin is a Schmitt trigger input pin. Assertion of chip reset by any source, once the operating
voltage attains a usable level, starts the IRC and initializes the flash controller.
A LOW-going pulse as short as 50 ns resets the part.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the boot block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
An external pull-up resistor is required on the RESET pin if Deep power-down mode is
used.
7.17.3 Brownout detection
The LPC1110/11/12/13/14/15 includes up to four levels for monitoring the voltage on the
VDD pin. If this voltage falls below one of the selected levels, the BOD asserts an interrupt
signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable
Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the
signal by reading a dedicated status register. Four threshold levels can be selected to
cause a forced reset of the chip.
7.17.4 Code security (Code Read Protection - CRP)
This feature of the LPC1110/11/12/13/14/15 allows user to enable different levels of
security in the system so that access to the on-chip flash and use of the Serial Wire
Debugger (SWD) and In-System Programming (ISP) can be restricted. When needed,
CRP is invoked by programming a specific pattern into a dedicated flash location. IAP
commands are not affected by the CRP.
In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For
details see the LPC111x user manual.
There are three levels of Code Read Protection:
1. CRP1 disables access to the chip via the SWD and allows partial flash update
(excluding flash sector 0) using a limited set of the ISP commands. This mode is
useful when CRP is required and flash field updates are needed but all sectors can
not be erased.
2. CRP2 disables access to the chip via the SWD and only allows full flash erase and
update using a reduced set of the ISP commands.
3. Running an application with level CRP3 selected fully disables any access to the chip
via the SWD pins and the ISP. This mode effectively disables ISP override using
PIO0_1 pin, too. It is up to the user’s application to provide (if needed) flash update
mechanism using IAP calls or call reinvoke ISP command to enable flash update via
the UART.
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32-bit ARM Cortex-M0 microcontroller
In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be
disabled. For details see the LPC111x user manual.
7.17.5 APB interface
The APB peripherals are located on one APB bus.
7.17.6 AHBLite
The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main
static RAM, and the Boot ROM.
7.17.7 External interrupt inputs
All GPIO pins can be level or edge sensitive interrupt inputs. In addition, start logic inputs
serve as external interrupts (see Section 7.17.1).
7.18 Emulation and debugging
Debug functions are integrated into the ARM Cortex-M0. Serial wire debug with four
breakpoints and two watchpoints is supported.
CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
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32-bit ARM Cortex-M0 microcontroller
8. Limiting values
[1] The following applies to the limiting values:
a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated
maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
c) The limiting values are stress ratings only. Operating the part at these values is not recommended, and proper operation is not
guaranteed. The conditions for functional operation are specified in Table 16.
[2] Maximum/minimum voltage above the maximum operating voltage (see Table 16) and below ground that can be applied for a short time
(< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device.
[3] Including voltage on outputs in 3-state mode.
[4] VDD present or not present. Compliant with the I2C-bus standard. 5.5 V can be applied to this pin when VDD is powered down.
[5] See Table 18 for maximum operating voltage.
[6] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined
based on required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details.
[7] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
Table 12. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol Parameter Conditions Min Max Unit
VDD supply voltage (core and external rail) [2] 0.5 +4.6 V
VIinput voltage 5 V tolerant I/O
pins; only valid
when the VDD
supply voltage is
present
[2][3] 0.5 +5.5 V
5 V tolerant
open-drain pins
PIO0_4 and
PIO0_5
[2][4] 0.5 +5.5 V
VIA analog input voltage pin configured as
analog input
[2][5] 0.5 4.6 V
IDD supply current per supply pin - 100 mA
ISS ground current per ground pin - 100 mA
Ilatch I/O latch-up current (0.5VDD) < VI <
(1.5VDD);
Tj < 125 C
- 100 mA
Tstg storage temperature non-operating [6] 65 +150 C
Tj(max) maximum junction temperature - 150 C
Ptot(pack) total power dissipation (per package) based on package
heat transfer, not
device power
consumption
-1.5W
VESD electrostatic discharge voltage human body
model; all pins
[7] - +6500 V
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Product data sheet Rev. 9.2 — 26 March 2014 59 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
9. Thermal characteristics
The average chip junction temperature, Tj (C), can be calculated using the following
equation:
(1)
•Tamb = ambient temperature (C),
•Rth(j-a) = the package junction-to-ambient thermal resistance (C/W)
•PD = sum of internal and I/O power dissipation
The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of
the I/O pins is often small and many times can be negligible. However it can be significant
in some applications.
TjTamb PDRth j a–
+=
Table 13. Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
Tj(max) maximum junction
temperature --125 C
Table 14. LPC111x/x01 Thermal resistance value (C/W): ±15 %
HVQFN33 LQFP48
ja ja
JEDEC (4.5 in 4 in) JEDEC (4.5 in 4 in)
0 m/s 40.4 0 m/s 82.1
1 m/s 32.7 1 m/s 73.7
2.5 m/s 28.3 2.5 m/s 68.2
Single-layer (4.5 in 3 in) 8-layer (4.5 in 3 in)
0 m/s 84.8 0 m/s 115.2
1 m/s 61.6 1 m/s 94.7
2.5 m/s 53.1 2.5 m/s 86.3
jc 20.3 jc 29.6
jb 1.1 jb 34.2
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Product data sheet Rev. 9.2 — 26 March 2014 60 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Table 15. LPC111x/x02 Thermal resistance value (C/W): ±15 %
HVQFN33 LQFP48
ja ja
JEDEC (4.5 in 4 in) JEDEC (4.5 in 4 in)
0 m/s 40.8 0 m/s 83.3
1 m/s 33.1 1 m/s 74.9
2.5 m/s 28.7 2.5 m/s 69.4
Single-layer (4.5 in 3 in) 8-layer (4.5 in 3 in)
0 m/s 85.2 0 m/s 116.3
1 m/s 62 1 m/s 96
2.5 m/s 53.5 2.5 m/s 87.5
jc 17.9 jc 28.3
jb 1.5 jb 35.5
Typ,
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32-bit ARM Cortex-M0 microcontroller
10. Static characteristics
10.1 LPC1100, LPC1100L series
Table 16. Static characteristics (LPC1100, LPC1100L series)
Tamb =
40
C to +85
C, unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max Unit
VDD supply voltage (core
and external rail) 1.8 3.3 3.6 V
LPC1100 series (LPC111x/101/201/301) power consumption
IDD supply current Active mode; code
while(1){}
executed from flash
system clock = 12 MHz
VDD = 3.3 V
[2][3][4]
[5][6] -3-mA
system clock = 50 MHz
VDD = 3.3 V
[2][3][5]
[6][7] -9-mA
Sleep mode;
system clock = 12 MHz
VDD = 3.3 V
[2][3][4]
[5][6] -2-mA
Deep-sleep mode;
VDD = 3.3 V
[2][3][8] -6-A
Deep power-down mode;
VDD = 3.3 V
[2][9] -220-nA
LPC1100L series (LPC111x/002/102/202/302) power consumption in low-current mode[11]
IDD supply current Active mode; code
while(1){}
executed from flash
system clock = 1 MHz
VDD = 3.3 V
[2][3][5]
[6][10] -840-A
system clock = 6 MHz
VDD = 3.3 V
[2][3][5]
[6][10] -1-mA
system clock = 12 MHz
VDD = 3.3 V
[2][3][4]
[5][6] -2-mA
system clock = 50 MHz
VDD = 3.3 V
[2][3][5]
[6][7] -7-mA
Sleep mode;
system clock = 12 MHz
VDD = 3.3 V
[2][3][4]
[5][6] -1-mA
system clock = 50 MHz
VDD = 3.3 V
[2][3][4]
[5][6] -5-mA
Deep-sleep mode;
VDD = 3.3 V
[2][3][8] -2-A
Deep power-down mode;
VDD = 3.3 V
[2][9] -220-nA
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32-bit ARM Cortex-M0 microcontroller
Standard port pins, RESET
IIL LOW-level input current VI= 0 V; on-chip pull-up
resistor disabled - 0.5 10 nA
IIH HIGH-level input
current VI=V
DD; on-chip
pull-down resistor
disabled
- 0.5 10 nA
IOZ OFF-state output
current VO=0V; V
O=V
DD;
on-chip pull-up/down
resistors disabled
- 0.5 10 nA
VIinput voltage pin configured to provide
a digital function
[12][13]
[14] 0- 5.0V
VOoutput voltage output active 0 - VDD V
VIH HIGH-level input
voltage 0.7VDD --V
VIL LOW-level input voltage - - 0.3VDD V
Vhys hysteresis voltage - 0.4 - V
VOH HIGH-level output
voltage 2.5 V VDD 3.6 V;
IOH =4 mA VDD 0.4--V
1.8 V VDD < 2.5 V;
IOH =3 mA VDD 0.4--V
VOL LOW-level output
voltage 2.5 V VDD 3.6 V;
IOL =4 mA --0.4V
1.8 V VDD < 2.5 V;
IOL =3 mA --0.4V
IOH HIGH-level output
current VOH =V
DD 0.4 V;
2.5 V VDD 3.6 V
4--mA
1.8 V VDD < 2.5 V 3--mA
IOL LOW-level output
current VOL =0.4V
2.5 V VDD 3.6 V
4--mA
1.8 V VDD < 2.5 V 3--mA
IOHS HIGH-level short-circuit
output current VOH =0V [15] --45 mA
IOLS LOW-level short-circuit
output current VOL =V
DD [15] --50mA
Ipd pull-down current VI=5V 10 50 150 A
Ipu pull-up current VI=0V;
2.0 V VDD 3.6 V
15 50 85 A
1.8 V VDD < 2.0 V 10 50 85 A
VDD <V
I<5V 000A
High-drive output pin (PIO0_7)
IIL LOW-level input current VI= 0 V; on-chip pull-up
resistor disabled - 0.5 10 nA
IIH HIGH-level input
current VI=V
DD; on-chip
pull-down resistor
disabled
- 0.5 10 nA
Table 16. Static characteristics (LPC1100, LPC1100L series) …continued
Tamb =
40
C to +85
C, unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max Unit
Typ,
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32-bit ARM Cortex-M0 microcontroller
IOZ OFF-state output
current VO=0V; V
O=V
DD;
on-chip pull-up/down
resistors disabled
- 0.5 10 nA
VIinput voltage pin configured to provide
a digital function
[12][13]
[14] 0- 5.0V
VOoutput voltage output active 0 - VDD V
VIH HIGH-level input
voltage 0.7VDD --V
VIL LOW-level input voltage - - 0.3VDD V
Vhys hysteresis voltage 0.4 - - V
VOH HIGH-level output
voltage 2.5 V VDD 3.6 V;
IOH =20 mA VDD 0.4--V
1.8 V VDD < 2.5 V;
IOH =12 mA VDD 0.4--V
VOL LOW-level output
voltage 2.5 V VDD 3.6 V;
IOL =4 mA --0.4V
1.8 V VDD < 2.5 V;
IOL =3 mA --0.4V
IOH HIGH-level output
current VOH =V
DD 0.4 V;
2.5 V VDD 3.6 V 20--mA
1.8 V VDD < 2.5 V 12--mA
IOL LOW-level output
current VOL =0.4V
2.5 V VDD 3.6 V
4--mA
1.8 V VDD < 2.5 V 3--mA
IOLS LOW-level short-circuit
output current VOL =V
DD [15] --50mA
Ipd pull-down current VI=5V 10 50 150 A
Ipu pull-up current VI=0V
2.0 V VDD 3.6 V
15 50 85 A
1.8 V VDD < 2.0 V 10 50 85 A
VDD <V
I<5V 000A
I2C-bus pins (PIO0_4 and PIO0_5)
VIH HIGH-level input
voltage 0.7VDD --V
VIL LOW-level input voltage - - 0.3VDD V
Vhys hysteresis voltage - 0.05VDD -V
IOL LOW-level output
current VOL =0.4V; I
2C-bus pins
configured as standard
mode pins
2.5 V VDD 3.6 V
3.5--mA
1.8 V VDD < 2.5 V 3 - -
Table 16. Static characteristics (LPC1100, LPC1100L series) …continued
Tamb =
40
C to +85
C, unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max Unit
Typ,
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32-bit ARM Cortex-M0 microcontroller
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
[2] Tamb =25C.
[3] IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.
[4] IRC enabled; system oscillator disabled; system PLL disabled.
[5] BOD disabled.
[6] All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks to UART and SPI0/1 disabled in system configuration
block.
[7] IRC disabled; system oscillator enabled; system PLL enabled.
[8] All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0x0000 18FF.
[9] WAKEUP pin and RESET pin are pulled HIGH externally.
[10] System oscillator enabled; IRC disabled; system PLL disabled.
[11] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles.
[12] Including voltage on outputs in 3-state mode.
[13] VDD supply voltage must be present.
[14] 3-state outputs go into 3-state mode in Deep power-down mode.
[15] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[16] To VSS.
IOL LOW-level output
current VOL =0.4V; I
2C-bus pins
configured as Fast-mode
Plus pins
2.5 V VDD 3.6 V
20--mA
1.8 V VDD < 2.5 V 16 - -
ILI input leakage current VI=V
DD [16] -24A
VI=5V - 10 22 A
Oscillator pins
Vi(xtal) crystal input voltage 0.5 1.8 1.95 V
Vo(xtal) crystal output voltage 0.5 1.8 1.95 V
Pin capacitance
Cio input/output
capacitance pins configured for analog
function --7.1pF
I2C-bus pins (PIO0_4 and
PIO0_5) --2.5 pF
pins configured as GPIO - - 2.8 pF
Table 16. Static characteristics (LPC1100, LPC1100L series) …continued
Tamb =
40
C to +85
C, unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max Unit
Typ, Ge,
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Product data sheet Rev. 9.2 — 26 March 2014 65 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
10.2 LPC1100XL series
Table 17. Static characteristics (LPC1100XL series)
Tamb =
40
C to +105
C, unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max Unit
VDD supply voltage (core
and external rail) 1.8 3.3 3.6 V
LPC1100XL series (LPC111x/103/203/303/323/333) power consumption in low-current mode[2]
IDD supply current Active mode; code
while(1){}
executed from flash
system clock = 3 MHz
VDD = 3.3 V
[3][4][5]
[6][7] -600-A
system clock = 6 MHz
VDD = 3.3 V
[3][4][5]
[6][7] -850-A
system clock = 12 MHz
VDD = 3.3 V
[3][4][6]
[7][8] -1.4-mA
system clock = 50 MHz
VDD = 3.3 V
[3][4][6]
[7][9] -5.8-mA
Sleep mode;
system clock = 12 MHz
VDD = 3.3 V
[3][4][6]
[7][8] -700-A
system clock = 50 MHz
VDD = 3.3 V
[3][4][6]
[7][8] -2.2-mA
Deep-sleep mode;
VDD = 3.3 V; 25 C
[3][4]
[10] -1.815A
Deep-sleep mode;
VDD = 3.3 V; 105 C
[4][10]
[11] --50A
Deep power-down mode;
VDD = 3.3 V; 25 C
[3][12] - 220 1000 nA
Deep power-down mode;
VDD = 3.3 V; 105 C
[11][12] --3A
Standard port pins, RESET
IIL LOW-level input current VI= 0 V; on-chip pull-up
resistor disabled - 0.5 10 nA
IIH HIGH-level input
current VI=V
DD; on-chip
pull-down resistor
disabled
- 0.5 10 nA
IOZ OFF-state output
current VO=0V; V
O=V
DD;
on-chip pull-up/down
resistors disabled
- 0.5 10 nA
VIinput voltage pin configured to provide
a digital function
[13][14]
[15] 0- 5.0V
VOoutput voltage output active 0 - VDD V
VIH HIGH-level input
voltage 0.7VDD --V
Typ,
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32-bit ARM Cortex-M0 microcontroller
VIL LOW-level input voltage - - 0.3VDD V
Vhys hysteresis voltage - 0.4 - V
VOH HIGH-level output
voltage 2.5 V VDD 3.6 V;
IOH =4 mA VDD 0.4--V
1.8 V VDD < 2.5 V;
IOH =3 mA VDD 0.4--V
VOL LOW-level output
voltage 2.5 V VDD 3.6 V;
IOL =4 mA --0.4V
1.8 V VDD < 2.5 V;
IOL =3 mA --0.4V
IOH HIGH-level output
current VOH =V
DD 0.4 V;
2.5 V VDD 3.6 V
4--mA
1.8 V VDD < 2.5 V 3--mA
IOL LOW-level output
current VOL =0.4V
2.5 V VDD 3.6 V
4--mA
1.8 V VDD < 2.5 V 3--mA
IOHS HIGH-level short-circuit
output current VOH =0V [16] --45 mA
IOLS LOW-level short-circuit
output current VOL =V
DD [16] --50mA
Ipd pull-down current VI=5V 10 50 150 A
Ipu pull-up current VI=0V;
2.0 V VDD 3.6 V
15 50 85 A
1.8 V VDD < 2.0 V 10 50 85 A
VDD <V
I<5V 000A
High-drive output pin (PIO0_7)
IIL LOW-level input current VI= 0 V; on-chip pull-up
resistor disabled - 0.5 10 nA
IIH HIGH-level input
current VI=V
DD; on-chip
pull-down resistor
disabled
- 0.5 10 nA
IOZ OFF-state output
current VO=0V; V
O=V
DD;
on-chip pull-up/down
resistors disabled
- 0.5 10 nA
VIinput voltage pin configured to provide
a digital function
[13][14]
[15] 0- 5.0V
VOoutput voltage output active 0 - VDD V
VIH HIGH-level input
voltage 0.7VDD --V
VIL LOW-level input voltage - - 0.3VDD V
Vhys hysteresis voltage 0.4 - - V
Table 17. Static characteristics (LPC1100XL series) …continued
Tamb =
40
C to +105
C, unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max Unit
Typ,
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Product data sheet Rev. 9.2 — 26 March 2014 67 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
VOH HIGH-level output
voltage 2.5 V VDD 3.6 V;
IOH =20 mA VDD 0.4--V
1.8 V VDD < 2.5 V;
IOH =12 mA VDD 0.4--V
VOL LOW-level output
voltage 2.5 V VDD 3.6 V;
IOL =4 mA --0.4V
1.8 V VDD < 2.5 V;
IOL =3 mA --0.4V
IOH HIGH-level output
current VOH =V
DD 0.4 V;
2.5 V VDD 3.6 V 20--mA
1.8 V VDD < 2.5 V 12--mA
IOL LOW-level output
current VOL =0.4V
2.5 V VDD 3.6 V
4--mA
1.8 V VDD < 2.5 V 3--mA
IOLS LOW-level short-circuit
output current VOL =V
DD [16] --50mA
Ipd pull-down current VI=5V 10 50 150 A
Ipu pull-up current VI=0V
2.0 V VDD 3.6 V
15 50 85 A
1.8 V VDD < 2.0 V 10 50 85 A
VDD <V
I<5V 000A
I2C-bus pins (PIO0_4 and PIO0_5)
VIH HIGH-level input
voltage 0.7VDD --V
VIL LOW-level input voltage - - 0.3VDD V
Vhys hysteresis voltage - 0.05VDD -V
IOL LOW-level output
current VOL =0.4V; I
2C-bus pins
configured as standard
mode pins
2.5 V VDD 3.6 V
3.5--mA
1.8 V VDD < 2.5 V 3 - -
IOL LOW-level output
current VOL =0.4V; I
2C-bus pins
configured as Fast-mode
Plus pins
2.5 V VDD 3.6 V
20--mA
1.8 V VDD < 2.5 V 16 - -
ILI input leakage current VI=V
DD [17] -24A
VI=5V - 10 22 A
Table 17. Static characteristics (LPC1100XL series) …continued
Tamb =
40
C to +105
C, unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max Unit
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Product data sheet Rev. 9.2 — 26 March 2014 68 of 127
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32-bit ARM Cortex-M0 microcontroller
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
[2] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles.
[3] Tamb =25C.
[4] IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.
[5] System oscillator enabled; IRC disabled; system PLL disabled.
[6] BOD disabled.
[7] All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks to UART and SPI0/1 disabled in system configuration
block.
[8] IRC enabled; system oscillator disabled; system PLL disabled.
[9] IRC disabled; system oscillator enabled; system PLL enabled.
[10] All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0x0000 18FF.
[11] 105 C spec applies only to parts with the J designator (e.g. LPC1115JET48).
[12] WAKEUP pin and RESET pin are pulled HIGH externally.
[13] Including voltage on outputs in 3-state mode.
[14] VDD supply voltage must be present.
[15] 3-state outputs go into 3-state mode in Deep power-down mode.
[16] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[17] To VSS.
Oscillator pins
Vi(xtal) crystal input voltage 0.5 1.8 1.95 V
Vo(xtal) crystal output voltage 0.5 1.8 1.95 V
Pin capacitance
Cio input/output
capacitance pins configured for analog
function --7.1pF
I2C-bus pins (PIO0_4 and
PIO0_5) --2.5 pF
pins configured as GPIO - - 2.8 pF
Table 17. Static characteristics (LPC1100XL series) …continued
Tamb =
40
C to +105
C, unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max Unit
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Product data sheet Rev. 9.2 — 26 March 2014 69 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
10.3 ADC static characteristics
[1] The ADC is monotonic, there are no missing codes.
[2] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 17.
[3] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 17.
[4] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
ideal curve. See Figure 17.
[5] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
error, and the straight line which fits the ideal transfer curve. See Figure 17.
[6] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
ADC and the ideal transfer curve. See Figure 17.
[7] Tamb = 25 C; maximum sampling frequency fs = 400 kSamples/s and analog input capacitance Cia = 1 pF.
[8] Input resistance Ri depends on the sampling frequency fs: Ri = 1 / (fs Cia).
Table 18. ADC static characteristics
Tamb =
40
C to +105
C unless otherwise specified; ADC frequency 4.5 MHz, VDD = 2.5 V to 3.6 V.
Symbol Parameter Conditions Min Typ Max Unit
VIA analog input voltage 0 - VDD V
Cia analog input capacitance - - 1 pF
EDdifferential linearity error [1][2] -- 1LSB
EL(adj) integral non-linearity [3] -- 1.5 LSB
EOoffset error [4] -- 3.5 LSB
EGgain error [5] --0.6%
ETabsolute error [6] -- 4LSB
Rvsi voltage source interface
resistance --40k
Riinput resistance [7][8] --2.5M
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Product data sheet Rev. 9.2 — 26 March 2014 70 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential linearity error (ED).
(4) Integral non-linearity (EL(adj)).
(5) Center of a step of the actual transfer curve.
Fig 17. ADC characteristics
002aaf426
1023
1022
1021
1020
1019
(2)
(1)
10241018 1019 1020 1021 1022 1023
7123456
7
6
5
4
3
2
1
0
1018
(5)
(4)
(3)
1 LSB
(ideal)
code
out
VDD − VSS
1024
offset
error
EO
gain
error
EG
offset error
EO
VIA (LSBideal)
1 LSB =
clerislics,
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Product data sheet Rev. 9.2 — 26 March 2014 71 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
10.4 BOD static characteristics
[1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC111x
user manual.
Table 19. BOD static characteristics[1]
Tamb =25
C.
Symbol Parameter Conditions Min Typ Max Unit
Vth threshold voltage interrupt level 1
assertion - 2.22 - V
de-assertion - 2.35 - V
interrupt level 2
assertion - 2.52 - V
de-assertion - 2.66 - V
interrupt level 3
assertion - 2.80 - V
de-assertion - 2.90 - V
reset level 0
assertion - 1.46 - V
de-assertion - 1.63 - V
reset level 1
assertion - 2.06 - V
de-assertion - 2.15 - V
reset level 2
assertion - 2.35 - V
de-assertion - 2.43 - V
reset level 3
assertion - 2.63 - V
de-assertion - 2.71 - V
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Product data sheet Rev. 9.2 — 26 March 2014 72 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
10.5 Power consumption LPC1100 series (LPC111x/101/201/301)
Power measurements in Active, Sleep, and Deep-sleep modes were performed under the
following conditions (see LPC111x user manual):
•Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block.
•Configure GPIO pins as outputs using the GPIOnDIR registers.
•Write 0 to all GPIOnDATA registers to drive the outputs LOW.
Conditions: Tamb = 25 C; active mode entered executing code
while(1){}
from flash; all
peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral
clocks disabled; internal pull-up resistors disabled; BOD disabled.
(1) System oscillator and system PLL disabled; IRC enabled.
(2) System oscillator and system PLL enabled; IRC disabled.
Fig 18. Active mode: Typical supply current IDD versus supply voltage VDD for different
system clock frequencies (for LPC111x/101/201/301)
VDD (V)
1.8 3.63.02.4
002aaf390
4
8
12
IDD
(mA)
0
12 MHz(1)
24 MHz(2)
36 MHz(2)
48 MHz(2)
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Product data sheet Rev. 9.2 — 26 March 2014 73 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Conditions: VDD = 3.3 V; active mode entered executing code
while(1){}
from flash; all
peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral
clocks disabled; internal pull-up resistors disabled; BOD disabled.
(1) System oscillator and system PLL disabled; IRC enabled.
(2) System oscillator and system PLL enabled; IRC disabled.
Fig 19. Active mode: Typical supply current IDD versus temperature for different system
clock frequencies (for LPC111x/101/201/301)
Conditions: VDD = 3.3 V; sleep mode entered from flash; all peripherals disabled in the
SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal
pull-up resistors disabled; BOD disabled.
(1) System oscillator and system PLL disabled; IRC enabled.
(2) System oscillator and system PLL enabled; IRC disabled.
Fig 20. Sleep mode: Typical supply current IDD versus temperature for different system
clock frequencies (for LPC111x/101/201/301)
temperature (°C)
−40 853510 60−15
002aaf391
4
8
12
IDD
(mA)
0
12 MHz(1)
24 MHz(2)
36 MHz(2)
48 MHz(2)
002aaf392
temperature (°C)
−40 853510 60−15
2
6
4
8
IDD
(mA)
0
12 MHz(1)
36 MHz(2)
48 MHz(2)
24 MHz(2)
< \\="">
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Product data sheet Rev. 9.2 — 26 March 2014 74 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register
(PDSLEEPCFG = 0x0000 18FF).
Fig 21. Deep-sleep mode: Typical supply current IDD versus temperature for different
supply voltages VDD (for LPC111x/101/201/301)
Fig 22. Deep power-down mode: Typical supply current IDD versus temperature for
different supply voltages VDD (for LPC111x/101/201/301)
002aaf394
temperature (°C)
−40 853510 60−15
10
30
20
40
IDD
(μA)
0
3.6 V
3.3 V
2.0 V
1.8 V
002aaf457
0.2
0.6
0.4
0.8
IDD
(μA)
0
temperature (°C)
−40 853510 60−15
VDD = 3.6 V
3.3 V
2.0 V
1.8 V
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Product data sheet Rev. 9.2 — 26 March 2014 75 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
10.6 Power consumption LPC1100L series (LPC111x/002/102/202/302)
Power measurements in Active, Sleep, and Deep-sleep modes were performed under the
following conditions (see LPC111x user manual):
•Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block.
•Configure GPIO pins as outputs using the GPIOnDIR registers.
•Write 0 to all GPIOnDATA registers to drive the outputs LOW.
Conditions: Tamb = 25 C; active mode entered executing code
while(1){}
from flash; all
peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral
clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode.
(1) System oscillator and system PLL disabled; IRC enabled.
(2) System oscillator and system PLL enabled; IRC disabled.
Fig 23. Active mode: Typical supply current IDD versus supply voltage VDD for different
system clock frequencies (for LPC111x/002/102/202/302)
VDD (V)
1.8 3.63.02.4
002aaf980
4
6
2
8
10
IDD
(mA)
0
12 MHz(1)
24 MHz(2)
36 MHz(2)
48 MHz(2)
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Product data sheet Rev. 9.2 — 26 March 2014 76 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Conditions: VDD = 3.3 V; active mode entered executing code
while(1){}
from flash; all
peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral
clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode.
(1) System oscillator and system PLL disabled; IRC enabled.
(2) System oscillator and system PLL enabled; IRC disabled.
Fig 24. Active mode: Typical supply current IDD versus temperature for different system
clock frequencies (for LPC111x/002/102/202/302)
Conditions: VDD = 3.3 V; sleep mode entered from flash; all peripherals disabled in the
SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal
pull-up resistors disabled; BOD disabled; low-current mode.
(1) System oscillator and system PLL disabled; IRC enabled.
(2) System oscillator and system PLL enabled; IRC disabled.
Fig 25. Sleep mode: Typical supply current IDD versus temperature for different system
clock frequencies (for LPC111x/002/102/202/302)
002aaf981
temperature (°C)
−40 853510 60−15
2
8
6
4
10
IDD
(mA)
0
12 MHz(1)
24 MHz(2)
36 MHz(2)
48 MHz(2)
temperature (°C)
−40 853510 60−15
002aaf982
2
4
6
IDD
(mA)
0
12 MHz(1)
24 MHz(2)
36 MHz(2)
48 MHz(2)
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Product data sheet Rev. 9.2 — 26 March 2014 77 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register
(PDSLEEPCFG = 0x0000 18FF).
Fig 26. Deep-sleep mode: Typical supply current IDD versus temperature for different
supply voltages VDD (for LPC111x/002/102/202/302)
Fig 27. Deep power-down mode: Typical supply current IDD versus temperature for
different supply voltages VDD (for LPC111x/002/102/202/302)
002aaf977
temperature (°C)
−40 853510 60−15
2.5
4.5
3.5
5.5
IDD
(μA)
1.5
VDD = 3.3 V, 3.6 V
1.8 V
002aaf978
0.2
0.6
0.4
0.8
IDD
(μA)
0
temperature (°C)
−40 853510 60−15
VDD = 3.6 V
3.3 V
1.8 V
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Product data sheet Rev. 9.2 — 26 March 2014 78 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
10.7 Power consumption LPC1100XL series
(LPC111x/103/203/303/323/333)
[1] WDT OSC enabled, VDD = 3.3 V, Temp = 25 C.
Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles.
IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled,
IRC disabled, System Oscillator disabled, System PLL disabled, BOD disabled.
All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks to UART and SPI0/1 disabled in system configuration
block.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
Table 20. Power consumption at very low frequencies using the watchdog oscillator
Symbol Parameter Conditions[1] Min Typ[2] Max Unit
IDD supply current Active mode; code
while(1){}
executed from flash
system clock = 8.8 kHz - 275 - A
system clock = 257 kHz - 305 - A
system clock = 515 kHz - 335 - A
system clock = 784 kHz - 368 - A
system clock = 1028 kHz - 396 - A
system clock = 2230 kHz - 538 - A
Sleep mode;
system clock = 8.8 kHz - 274 - A
system clock = 257 kHz - 285 - A
system clock = 515 kHz - 295 - A
system clock = 784 kHz - 309 - A
system clock = 1028 kHz - 317 - A
system clock = 2230 kHz - 368 - A
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Product data sheet Rev. 9.2 — 26 March 2014 79 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Power measurements in Active, Sleep, and Deep-sleep modes were performed under the
following conditions (see LPC111x user manual):
•Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block.
•Configure GPIO pins as outputs using the GPIOnDIR registers.
•Write 0 to all GPIOnDATA registers to drive the outputs LOW.
Conditions: Tamb = 25 C; active mode entered executing code
while(1){}
from flash; all
peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral
clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode.
1 MHz to 6 MHz: system oscillator enabled; PLL, IRC disabled.
12 MHz: IRC enabled; system oscillator, PLL disabled.
24 MHz to 48 MHz: IRC disabled; system oscillator, PLL enabled.
Fig 28. Active mode: Typical supply current IDD versus supply voltage VDD for different
system clock frequencies (for LPC111xXL)
DDD
  
9''9
,'','',''
P$P$P$
0+]0+]0+]
0+]0+]0+]
0+]0+]0+]
0+]0+]0+]
0+]0+]0+]
0+]0+]0+]
0+]0+]0+]
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0+]0+]0+]
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 80 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Conditions: VDD = 3.3 V; active mode entered executing code
while(1){}
from flash; all
peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral
clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode.
1 MHz to 6 MHz: system oscillator enabled; PLL, IRC disabled.
12 MHz: IRC enabled; system oscillator, PLL disabled.
24 MHz to 48 MHz: IRC disabled; system oscillator, PLL enabled.
Fig 29. Active mode: Typical supply current IDD versus temperature for different system
clock frequencies (for LPC111xXL)
Conditions: VDD = 3.3 V; sleep mode entered from flash; all peripherals disabled in the
SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal
pull-up resistors disabled; BOD disabled; low-current mode.
1 MHz to 6 MHz: system oscillator enabled; PLL, IRC disabled.
12 MHz: IRC enabled; system oscillator, PLL disabled.
24 MHz to 48 MHz: IRC disabled; system oscillator, PLL enabled.
Fig 30. Sleep mode: Typical supply current IDD versus temperature for different system
clock frequencies (for LPC111xXL)
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LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 81 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register
(PDSLEEPCFG = 0x0000 18FF).
Fig 31. Deep-sleep mode: Typical supply current IDD versus temperature for different
supply voltages VDD (for LPC111xXL)
Fig 32. Deep power-down mode: Typical supply current IDD versus temperature for
different supply voltages VDD (for LPC111xXL)
002aah553
-40 -10 20 50 80 110
0
5
10
15
20
temperature (°C)
IDD
(μA)
1.8 V
VDD = 3.6 V
3.3 V
002aah554
-40 -10 20 50 80 110
0
0.5
1
1.5
2
temperature (°C)
IDD
(μA)
3.3 V
1.8 V
VDD = 3.6 V
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 82 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
10.8 CoreMark data
Remark: All CoreMark data were taken with the Keil uVision v. 4.6 tool.
VDD = 3.3 V; T = 25 °C; active mode; typical samples.
Fig 33. CoreMark score for different Power API modes
VDD = 3.3 V; T = 25 °C; active mode; typical samples. System oscillator enabled; main clock
derived from external clock signal; PLL and SYSAHBCLKDIV enabled for frequencies > 20 MHz.
Fig 34. CoreMark current consumption for different power modes using external clock
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LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 83 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
VDD = 3.3 V; T = 25 °C; active mode; typical samples. IRC enabled; main clock derived from IRC;
PLL and SYSAHBCLKDIV enabled as needed.
Fig 35. CoreMark current consumption for different power modes using IRC
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LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 84 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
10.9 Peripheral power consumption
The supply current per peripheral is measured as the difference in supply current between
the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG
and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both
registers and no code is executed. Measured on a typical sample at Tamb =25 C. Unless
noted otherwise, the system oscillator and PLL are running in both measurements.
The supply currents are shown for system clock frequencies of 12 MHz and 48 MHz.
Table 21. Power consumption for individual analog and digital blocks
Peripheral
Typical supply current in
mA Notes
n/a 12 MHz 48 MHz
IRC 0.27 - - System oscillator running; PLL off; independent
of main clock frequency.
System oscillator
at 12 MHz 0.22 - - IRC running; PLL off; independent of main clock
frequency.
Watchdog
oscillator at
500 kHz/2
0.004 - - System oscillator running; PLL off; independent
of main clock frequency.
BOD 0.051 - - Independent of main clock frequency.
Main PLL - 0.21 -
ADC - 0.08 0.29
CLKOUT - 0.12 0.47 Main clock divided by 4 in the CLKOUTDIV
register.
CT16B0 - 0.02 0.06
CT16B1 - 0.02 0.06
CT32B0 - 0.02 0.07
CT32B1 - 0.02 0.06
GPIO - 0.23 0.88 GPIO pins configured as outputs and set to
LOW. Direction and pin state are maintained if
the GPIO is disabled in the SYSAHBCLKCFG
register.
IOCONFIG - 0.03 0.10
I2C - 0.04 0.13
ROM - 0.04 0.15
SPI0 - 0.12 0.45
SPI1 - 0.12 0.45
UART - 0.22 0.82
WDT/WWDT - 0.02 0.06 Main clock selected as clock source for the
WDT.
//A \\\\ \\ \
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Product data sheet Rev. 9.2 — 26 March 2014 85 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
10.10 Electrical pin characteristics
Conditions: VDD = 3.3 V; on pin PIO0_7.
Fig 36. High-drive output: Typical HIGH-level output voltage VOH versus HIGH-level
output current IOH.
Conditions: VDD = 3.3 V; on pins PIO0_4 and PIO0_5.
Fig 37. I2C-bus pins (high current sink): Typical LOW-level output current IOL versus
LOW-level output voltage VOL
IOH (mA)
060402010 5030
002aah548
2.8
2.4
3.2
3.6
VOH
(V)
2
T = 105°C
85 °C
25 °C
-40 °C
VOL (V)
0 0.60.40.2
002aah549
20
40
60
IOL
(mA)
0
T = 105°C
85 °C
25 °C
-40 °C
\\ \ \\\
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 86 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Conditions: VDD = 3.3 V; standard port pins and PIO0_7.
Fig 38. Typical LOW-level output current IOL versus LOW-level output voltage VOL
Conditions: VDD = 3.3 V; standard port pins.
Fig 39. Typical HIGH-level output voltage VOH versus HIGH-level output source current
IOH
VOL (V)
0
0.60.40.2
002aah550
5
10
15
IOL
(mA)
0
T = 105°C
85 °C
25 °C
-40 °C
IOH (mA)
024168
002aah551
2.8
2.4
3.2
3.6
VOH
(V)
2
T = 105 °C
85 °C
25 °C
-40 °C
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Product data sheet Rev. 9.2 — 26 March 2014 87 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Conditions: VDD = 3.3 V; standard port pins.
Fig 40. Typical pull-up current Ipu versus input voltage VI
Conditions: VDD = 3.3 V; standard port pins.
Fig 41. Typical pull-down current Ipd versus input voltage VI
VI (V)
0 54231
002aah552
-30
-50
-10
10
Ipu
(μA)
-70
T = 105 °C
85 °C
25 °C
-40 °C
VI (V)
0 54231
002aah547
40
20
60
80
Ipd
(μA)
0
T = 105 °C
85 °C
25 °C
-40 °C
cleristics,
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Product data sheet Rev. 9.2 — 26 March 2014 88 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
11. Dynamic characteristics
11.1 Power-up ramp conditions
[1] Does not apply to the LPC1100XL series (LPC111x/103/203/303/323/333).
[2] See Figure 42.
[3] The wait time specifies the time the power supply must be at levels below 400 mV before ramping up.
11.2 Flash memory
[1] Number of program/erase cycles.
[2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash
in blocks of 256 bytes. Flash programming operation temperature must not exceed Tamb = 85 C.
Table 22. Power-up characteristics[1]
Tamb =
40
C to +85
C.
Symbol Parameter Conditions Min Typ Max Unit
trrise time at t = t1: 0 < VI 400 mV [2] 0- 500 ms
twait wait time [2][3] 12 - - s
VIinput voltage at t = t1 on pin VDD 0 - 400 mV
Condition: 0 < VI 400 mV at start of power-up (t = t1)
Fig 42. Power-up ramp
V
DD
0
400 mV
t
r
t
wait
t = t
1002aag001
Table 23. Flash characteristics
Tamb =
40
C to +105
C, unless otherwise specified. Tamb =85
C for flash programming.
Symbol Parameter Conditions Min Typ Max Unit
Nendu endurance [1] 10000 100000 - cycles
tret retention time powered 10 - - years
unpowered 20 - - years
ter erase time sector or multiple
consecutive sectors 95 100 105 ms
tprog programming time [2] 0.95 1 1.05 ms
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Product data sheet Rev. 9.2 — 26 March 2014 89 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
11.3 External clock
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
Table 24. Dynamic characteristic: external clock
Tamb =
40
C to +105
C; VDD over specified ranges.[1]
Symbol Parameter Conditions Min Typ[2] Max Unit
fosc oscillator frequency 1 - 25 MHz
Tcy(clk) clock cycle time 40 - 1000 ns
tCHCX clock HIGH time Tcy(clk) 0.4 - - ns
tCLCX clock LOW time Tcy(clk) 0.4 - - ns
tCLCH clock rise time - - 5 ns
tCHCL clock fall time - - 5 ns
Fig 43. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)
tCHCL tCLCX
tCHCX
Tcy(clk)
tCLCH
002aaa907
Typ, k\
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Product data sheet Rev. 9.2 — 26 March 2014 90 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
11.4 Internal oscillators
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
Table 25. Dynamic characteristic: internal oscillators
Tamb =
40
C to +105
C; 2.7 V
VDD
3.6 V.[1]
Symbol Parameter Conditions Min Typ[2] Max Unit
fosc(RC) internal RC oscillator frequency - 11.88 12 12.12 MHz
Conditions: Frequency values are typical values. 12 MHz 1 % accuracy is guaranteed for
2.7 V VDD 3.6 V and Tamb =40 C to +85 C. Variations between parts may cause the IRC to
fall outside the 12 MHz 1 % accuracy specification for voltages below 2.7 V.
Fig 44. Internal RC oscillator frequency versus temperature (F parts)
002aaf403
11.95
12.05
12.15
f
(MHz)
11.85
temperature (°C)
−40 853510 60−15
VDD = 3.6 V
3.3 V
3.0 V
2.7 V
2.4 V
2.0 V
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Product data sheet Rev. 9.2 — 26 March 2014 91 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Conditions: Frequency values are typical values. 12 MHz 1 % accuracy is guaranteed for
2.7 V VDD 3.6 V and Tamb =40 C to +105 C. Variations between parts may cause the IRC to
fall outside the 12 MHz 1 % accuracy specification for voltages below 2.7 V.
Fig 45. Internal RC oscillator frequency versus temperature (J parts)
002aah597
-50 -10 30 70 110
11.85
11.9
11.95
12
12.05
12.1
12.15
temperature (°C)
fosc(RC)
(MHz)
3.6 V
3.3 V
3.0 V
2.7 V
2.4 V
2.0 V
Typ,
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Product data sheet Rev. 9.2 — 26 March 2014 92 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
[2] The typical frequency spread over processing and temperature (Tamb = 40 C to +105 C) is 40 %.
[3] See the LPC111x user manual.
11.5 I/O pins
[1] Applies to standard port pins and RESET pin.
Table 26. Dynamic characteristics: Watchdog oscillator
Symbol Parameter Conditions Min Typ[1] Max Unit
fosc(int) internal oscillator
frequency DIVSEL = 0x1F, FREQSEL = 0x1
in the WDTOSCCTRL register;
[2][3] -9.4 - kHz
DIVSEL = 0x00, FREQSEL = 0xF
in the WDTOSCCTRL register
[2][3] - 2300 - kHz
Table 27. Dynamic characteristic: I/O pins[1]
Tamb =
40
C to +105
C; 3.0 V
VDD
3.6 V.
Symbol Parameter Conditions Min Typ Max Unit
trrise time pin
configured as
output
3.0 - 5.0 ns
tffall time pin
configured as
output
2.5 - 5.0 ns
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Product data sheet Rev. 9.2 — 26 March 2014 93 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
11.6 I2C-bus
[1] See the I2C-bus specification UM10204 for details.
[2] Parameters are valid over operating temperature range unless otherwise specified.
[3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission
and the acknowledge.
[4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the
VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.
[5] Cb = total capacitance of one bus line in pF.
[6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA
output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the
SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf.
[7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors
are used, designers should allow for this when considering bus timing.
[8] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than
the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if
the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the
data must be valid by the set-up time before it releases the clock.
[9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in
transmission and the acknowledge.
[10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement
tSU;DAT = 250 ns must then be met. This will automatically be the case if the device does not stretch the
LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the
Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must
meet this set-up time.
Table 28. Dynamic characteristic: I2C-bus pins[1]
Tamb =
40
C to +105
C.[2]
Symbol Parameter Conditions Min Max Unit
fSCL SCL clock
frequency Standard-mode 0 100 kHz
Fast-mode 0 400 kHz
Fast-mode Plus 0 1 MHz
tffall time [4][5][6][7] of both SDA and
SCL signals
Standard-mode
- 300 ns
Fast-mode 20 + 0.1 Cb300 ns
Fast-mode Plus - 120 ns
tLOW LOW period of
the SCL clock Standard-mode 4.7 - s
Fast-mode 1.3 - s
Fast-mode Plus 0.5 - s
tHIGH HIGH period of
the SCL clock Standard-mode 4.0 - s
Fast-mode 0.6 - s
Fast-mode Plus 0.26 - s
tHD;DAT data hold time [3][4][8] Standard-mode 0 - s
Fast-mode 0 - s
Fast-mode Plus 0 - s
tSU;DAT data set-up
time
[9][10] Standard-mode 250 - ns
Fast-mode 100 - ns
Fast-mode Plus 50 - ns
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Product data sheet Rev. 9.2 — 26 March 2014 94 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
11.7 SPI interfaces
[1] Tcy(clk) = (SSPCLKDIV (1 + SCR) CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the
main clock frequency fmain, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register),
and the SPI CPSDVSR parameter (specified in the SPI clock prescale register).
[2] Tamb = 40 C to 105 C.
[3] Tcy(clk) = 12 Tcy(PCLK).
[4] Tamb = 25 C; for normal voltage supply range: VDD = 3.3 V.
Fig 46. I2C-bus pins clock timing
002aaf425
tf
70 %
30 %
SDA
tf
70 %
30 %
S
70 %
30 %
70 %
30 %
tHD;DAT
SCL
1 / fSCL
70 %
30 %
70 %
30 %
tVD;DAT
tHIGH
tLOW
tSU;DAT
Table 29. Dynamic characteristics of SPI pins in SPI mode
Symbol Parameter Conditions Min Typ Max Unit
SPI master (in SPI mode)
Tcy(clk) clock cycle time full-duplex mode [1] 50 - - ns
when only transmitting [1] 40 ns
tDS data set-up time in SPI mode
2.4 V VDD 3.6 V
[2] 15 - - ns
2.0 V VDD < 2.4 V [2] 20 ns
1.8 V VDD < 2.0 V [2] 24 - - ns
tDH data hold time in SPI mode [2] 0-- ns
tv(Q) data output valid time in SPI mode [2] --10 ns
th(Q) data output hold time in SPI mode [2] 0-- ns
SPI slave (in SPI mode)
Tcy(PCLK) PCLK cycle time 20 - - ns
tDS data set-up time in SPI mode [3][4] 0-- ns
tDH data hold time in SPI mode [3][4] 3 Tcy(PCLK) + 4 - - ns
tv(Q) data output valid time in SPI mode [3][4] --3 Tcy(PCLK) + 11 ns
th(Q) data output hold time in SPI mode [3][4] --2 Tcy(PCLK) + 5 ns
’Tfl I
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Product data sheet Rev. 9.2 — 26 March 2014 95 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1.
Fig 47. SPI master timing in SPI mode
SCK (CPOL = 0)
MOSI
MISO
Tcy(clk)
tDS tDH
tv(Q)
DATA VALID DATA VALID
th(Q)
SCK (CPOL = 1)
DATA VALID DATA VALID
MOSI
MISO
tDS tDH
DATA VALID DATA VALID
th(Q)
DATA VALID DATA VALID
tv(Q)
CPHA = 1
CPHA = 0
002aae829
——— \— _\____
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Product data sheet Rev. 9.2 — 26 March 2014 96 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1.
Fig 48. SPI slave timing in SPI mode
SCK (CPOL = 0)
MOSI
MISO
Tcy(clk)
tDS tDH
tv(Q)
DATA VALID DATA VALID
th(Q)
SCK (CPOL = 1)
DATA VALID DATA VALID
MOSI
MISO
tDS tDH
tv(Q)
DATA VALID DATA VALID
th(Q)
DATA VALID DATA VALID
CPHA = 1
CPHA = 0
002aae830
Table 18 @I H (Figure 49 Figure 50 Table 30 Table 31
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Product data sheet Rev. 9.2 — 26 March 2014 97 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
12. Application information
12.1 ADC usage notes
The following guidelines show how to increase the performance of the ADC in a noisy
environment beyond the ADC specifications listed in Table 18:
•The ADC input trace must be short and as close as possible to the
LPC1110/11/12/13/14/15 chip.
•The ADC input traces must be shielded from fast switching digital signals and noisy
power supply lines.
•Because the ADC and the digital core share the same power supply, the power supply
line must be adequately filtered.
•To improve the ADC performance in a very noisy environment, put the device in Sleep
mode during the ADC conversion.
12.2 Use of ADC input trigger signals
For applications that use trigger signals to start conversions and require a precise sample
frequency, ensure that the period of the trigger signal is an integral multiple of the period
of the ADC clock.
12.3 XTAL input
The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a
clock in slave mode, it is recommended that the input be coupled through a capacitor with
Ci = 100 pF. To limit the input voltage to the specified range, choose an additional
capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave
mode, a minimum of 200 mV (RMS) is needed.
In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF
(Figure 49), with an amplitude between 200 mV (RMS) and 1000 mV (RMS). This
corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.
The XTALOUT pin in this configuration can be left unconnected.
External components and models used in oscillation mode are shown in Figure 50 and in
Table 30 and Table 31. Since the feedback resistance is integrated on chip, only a crystal
and the capacitances CX1 and CX2 need to be connected externally in case of
Fig 49. Slave mode operation of the on-chip oscillator
LPC1xxx
XTALIN
Ci
100 pF Cg
002aae788
Figure 50 4T: AER TL ‘w—I: HI
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Product data sheet Rev. 9.2 — 26 March 2014 98 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
fundamental mode oscillation (the fundamental frequency is represented by L, CL and
RS). Capacitance CP in Figure 50 represents the parallel package capacitance and should
not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal
manufacturer (see Table 30).
Fig 50. Oscillator modes and models: oscillation mode of operation and external crystal
model used for CX1/CX2 evaluation
Table 30. Recommended values for CX1/CX2 in oscillation mode (crystal and external
components parameters) low frequency mode
Fundamental oscillation
frequency FOSC
Crystal load
capacitance CL
Maximum crystal
series resistance RS
External load
capacitors CX1, CX2
1 MHz to 5 MHz 10 pF < 300 18 pF, 18 pF
20 pF < 300 39 pF, 39 pF
30 pF < 300 57 pF, 57 pF
5 MHz to 10 MHz 10 pF < 300 18 pF, 18 pF
20 pF < 200 39 pF, 39 pF
30 pF < 100 57 pF, 57 pF
10 MHz to 15 MHz 10 pF < 160 18 pF, 18 pF
20 pF < 60 39 pF, 39 pF
15 MHz to 20 MHz 10 pF < 80 18 pF, 18 pF
Table 31. Recommended values for CX1/CX2 in oscillation mode (crystal and external
components parameters) high frequency mode
Fundamental oscillation
frequency FOSC
Crystal load
capacitance CL
Maximum crystal
series resistance RS
External load
capacitors CX1, CX2
15 MHz to 20 MHz 10 pF < 180 18 pF, 18 pF
20 pF < 100 39 pF, 39 pF
20 MHz to 25 MHz 10 pF < 160 18 pF, 18 pF
20 pF < 80 39 pF, 39 pF
002aaf424
LPC1xxx
XTALIN XTALOUT
CX2
CX1
XTAL
=CLCP
RS
L
Figure 51
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Product data sheet Rev. 9.2 — 26 March 2014 99 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
12.4 XTAL Printed Circuit Board (PCB) layout guidelines
The crystal should be connected on the PCB as close as possible to the oscillator input
and output pins of the chip. Take care that the load capacitors CX1, CX2, and CX3 in case
of third overtone crystal usage have a common ground plane. The external components
must also be connected to the ground plain. Loops must be made as small as possible in
order to keep the noise coupled in via the PCB as small as possible. Also parasitics
should stay as small as possible. Values of CX1 and CX2 should be chosen smaller
accordingly to the increase in parasitics of the PCB layout.
12.5 Standard I/O pad configuration
Figure 51 shows the possible pin modes for standard I/O pins with analog input function:
•Digital output driver
•Digital input: Pull-up enabled/disabled
•Digital input: Pull-down enabled/disabled
•Digital input: Repeater mode enabled/disabled
•Digital output: Pseudo open-drain mode enable/disabled
•Analog input
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Product data sheet Rev. 9.2 — 26 March 2014 100 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
12.6 Reset pad configuration
Open-drain mode available on series LPC1100L and LPC1100XL.
Fig 51. Standard I/O pad configuration
PIN
V
DD
V
DD
ESD
V
SS
ESD
strong
pull-up
strong
pull-down
V
DD
weak
pull-up
weak
pull-down
open-drain enable
output enable
repeater mode
enable
pull-up enable
pull-down enable
data output
data input
analog input
select analog input
002aah159
pin configured
as digital output
driver
pin configured
as digital input
pin configured
as analog input
Fig 52. Reset pad configuration
VSS
reset
002aaf274
VDD
VDD
VDD
Rpu ESD
ESD
20 ns RC
GLITCH FILTER PIN
Table 32
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Product data sheet Rev. 9.2 — 26 March 2014 101 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
12.7 ElectroMagnetic Compatibility (EMC)
Radiated emission measurements according to the IEC61967-2 standard using the
TEM-cell method are shown for the LPC1114FBD48/302 in Table 32.
[1] IEC levels refer to Appendix D in the IEC61967-2 Specification.
Table 32. ElectroMagnetic Compatibility (EMC) for part LPC1114FBD48/302 (TEM-cell
method)
VDD = 3.3 V; Tamb = 25
C.
Parameter Frequency band System clock = Unit
12 MHz 24 MHz 48 MHz
Input clock: IRC (12 MHz)
maximum
peak level 150 kHz to 30 MHz 757dBV
30 MHz to 150 MHz 21 10dBV
150 MHz to 1 GHz 4 8 16 dBV
IEC level[1] -ONM-
Input clock: crystal oscillator (12 MHz)
maximum
peak level 150 kHz to 30 MHz 777dBV
30 MHz to 150 MHz 218dBV
150 MHz to 1 GHz 4 7 14 dBV
IEC level[1] -ONM-
Fi ure 53 E uatiun 2
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Product data sheet Rev. 9.2 — 26 March 2014 102 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
12.8 ADC effective input impedance
A simplified diagram of the ADC input channels can be used to determine the effective
input impedance seen from an external voltage source. See Figure 53.
The effective input impedance, Rin, seen by the external voltage source, VEXT, is the
parallel impedance of ((1/fs x Cia) + Rmux + Rsw) and (1/fs x Cio), and can be calculated
using Equation 2 with
fs = sampling frequency
Cia = ADC analog input capacitance
Rmux = analog mux resistance
Rsw = switch resistance
Cio = pin capacitance
(2)
Under nominal operating condition VDD = 3.3 V and with the maximum sampling
frequency fs = 400 kHz, the parameters assume the following values:
Cia = 1 pF (max)
Rmux = 2 kΩ (max)
Rsw = 1.3 kΩ (max)
Cio = 7.1 pF (max)
The effective input impedance with these parameters is Rin = 308 kΩ.
Fig 53. ADC input channel
Cia
Rs
V
SS
VEXT
002aah615
ADC
COMPARATOR
ADC Block
Rin
Cio
Rmux Rsw
Source
<2 kΩ<1.3 kΩ
Rin 1
fsCia
------------------Rmux Rsw
++


1
fsCio
------------------



=
E©
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Product data sheet Rev. 9.2 — 26 March 2014 103 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
13. Package outline
Fig 54. Package outline SOT163-1 (SO20)
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZ
ywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
2.65 0.3
0.1 2.45
2.25 0.49
0.36 0.32
0.23 13.0
12.6 7.6
7.4 1.27 10.65
10.00 1.1
1.0 0.9
0.4 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.1
0.4
SOT163-1
10
20
wM
bp
detail X
Z
e
11
1
D
y
0.25
075E04 MS-013
pin 1 index
0.1 0.012
0.004 0.096
0.089 0.019
0.014 0.013
0.009 0.51
0.49 0.30
0.29 0.05
1.4
0.055
0.419
0.394 0.043
0.039 0.035
0.016
0.01
0.25
0.01 0.004
0.043
0.016
0.01
0 5 10 mm
scale
X
θ
A
A1
A2
HE
Lp
Q
E
c
L
vMA
(A )
3
A
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
99-12-27
03-02-19
H H HHDHLH H HH- E© W
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Product data sheet Rev. 9.2 — 26 March 2014 104 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Fig 55. Package outline SOT360-1 (TSSOP20)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 6.6
6.4 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.5
0.2 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT360-1 MO-153 99-12-27
03-02-19
wM
bp
D
Z
e
0.25
110
20 11
pin 1 index
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
A
max.
1.1
E©
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Product data sheet Rev. 9.2 — 26 March 2014 105 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Fig 56. Package outline SOT361-1 (TSSOP28)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 9.8
9.6 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.8
0.5 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT361-1 MO-153 99-12-27
03-02-19
0.25
wM
bp
Z
e
114
28 15
pin 1 index
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
D
y
0 2.5 5 mm
scale
TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm SOT361-1
A
max.
1.1
Er©
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Product data sheet Rev. 9.2 — 26 March 2014 106 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Fig 57. Package outline SOT117-1 (DIP28)
UNIT A
max. 1 2 b1
(1)
(1) (1)
cD E weM
H
L
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
DIMENSIONS (mm dimensions are derived from the original inch dimensions)
SOT117-1 99-12-27
03-02-13
A
min. A
max. bZ
max.
ME
e1
1.7
1.3 0.53
0.38 0.32
0.23 36
35 14.1
13.7 3.9
3.4 0.252.54 15.24 15.80
15.24 17.15
15.90 1.75.1 0.51 4
0.066
0.051 0.020
0.014
0.013
0.009 1.41
1.34 0.56
0.54 0.15
0.13 0.010.1 0.6 0.62
0.60 0.68
0.63 0.0670.2 0.02 0.16
051G05 MO-015 SC-510-28
MH
c
(e )
1
ME
A
L
seating plane
A1
wM
b1
e
D
A2
Z
28
1
15
14
b
E
pin 1 index
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
DIP28: plastic dual in-line package; 28 leads (600 mil) SOT117-1
,an A‘Dl 41w ALA A WAG 7 {E c E: C CC , m W n E U 7 n U , fl .‘AHUATAA ‘AT‘ AAmA rU i n— w , D E A A W 3333:: / E© 4449+?»
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Product data sheet Rev. 9.2 — 26 March 2014 107 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Fig 58. Package outline (HVQFN33 5x5)
References
Outline
version
European
projection Issue date
IEC JEDEC JEITA
MO-220
hvqfn33f_po
11-10-11
11-10-17
Unit(1)
mm
max
nom
min
0.85
0.05
0.00
0.2
5.1
4.9
3.75
3.45
5.1
4.9
3.75
3.45
0.5 3.5
A1
Dimensions (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5 x 5 x 0.85 mm
bc
0.30
0.18
D(1)
A(1) DhE(1) Ehee
1e2L
3.5
vw
0.1 0.1
y
0.05
0.5
0.3
y1
0.05
0 2.5 5 mm
scale
1/2 e
AC B
v
Cw
terminal 1
index area
A
A1
c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
916
32 25
24
17
8
1
X
D
E
C
BA
e2
terminal 1
index area
1/2 e
E© W ‘ m 7 m if, 7 : EEECECCC , WW , n i % U i n wwwwwww ‘U m i @w h m \ , , jigii / L F‘ \L
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 108 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Fig 59. Package outline (HVQFN33 7x7)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
- - -
hvqfn33_po
09-03-17
09-03-23
Unit
mm max
nom
min
1.00
0.85
0.80
0.05
0.02
0.00 0.2 7.1
7.0
6.9
4.85
4.70
4.55
7.1
7.0
6.9 0.65 4.55 0.75
0.60
0.45 0.1
A(1)
Dimensions
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;
33 terminals; body 7 x 7 x 0.85 mm
A1b
0.35
0.28
0.23
cD
(1) DhE(1) Eh
4.85
4.70
4.55
ee
1e2
4.55
Lv
0.1
w
0.05
y
0.08
y1
0 2.5 5 mm
scale
terminal 1
index area
BA
D
E
C
y
C
y1
X
detail X
A1
A
c
b
e2
e1
e
e
AC B
v
Cw
terminal 1
index area Dh
Eh
L
9 16
32
33
25
17
24
8
1
.- _ J- E©
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Product data sheet Rev. 9.2 — 26 March 2014 109 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Fig 60. Package outline SOT313-2 (LQFP48)
UNIT A
max. A1A2A3bpcE
(1) eH
ELL
pZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 1.6 0.20
0.05 1.45
1.35 0.25 0.27
0.17 0.18
0.12 7.1
6.9 0.5 9.15
8.85 0.95
0.55 7
0
o
o
0.12 0.10.21
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.75
0.45
SOT313-2 MS-026136E05 00-01-19
03-02-25
D(1) (1)(1)
7.1
6.9
HD
9.15
8.85
E
Z
0.95
0.55
D
bp
e
E
B
12
D
H
bp
E
H
vMB
D
ZD
A
ZE
e
vMA
1
48
37
36 25
24
13
θ
A1
A
Lp
detail X
L
(A )
3
A2
X
y
c
wM
wM
0 2.5 5 mm
scale
pin 1 index
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2
a: a E©M
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Product data sheet Rev. 9.2 — 26 March 2014 110 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Fig 61. Package outline SOT616-3 (HVQFN24)
0.51 0.2
A1Eh
b
UNIT ye
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 4.1
3.9
Dh
2.75
2.45
y1
4.1
3.9 2.75
2.45
e1
2.5
e2
2.5
0.30
0.18
c
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT616-3 MO-220 04-11-19
05-03-10
- - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT616-3
HVQFN24: plastic thermal enhanced very thin quad flat package; no leads;
24 terminals; body 4 x 4 x 0.85 mm
A(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
712
24 19
18
13
6
1
X
D
E
C
BA
e2
terminal 1
index area
terminal 1
index area
AC
C
B
vM
wM
1/2 e
1/2 e
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
‘ 7, / R R R ,1 i ,,,,, + ,,,,, i / R l R ‘ R ' R R S D qr r» *Dr 1 R“:' m R, o oéowoooU fi 0 O QQ'QQ O 9*; ooHoopooo D 9919092 2&4 D ,,, ,2 oooooobo E3 3 0 09,9199, 0 ,7 2 oooopo // x O O 0 0‘0 0 O 1‘ D R / ‘ 7 5 \ .‘//h n 5 E© 48—96—11»
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Product data sheet Rev. 9.2 — 26 March 2014 111 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Fig 62. Package outline TFBGA48 (SOT1155-2)
References
Outline
version
European
projection Issue date
IEC JEDEC JEITA
SOT1155-2 - - -
sot1155-2_po
13-06-17
13-06-19
Unit
mm
max
nom
min
1.10
0.95
0.85
0.30
0.25
0.20
0.35
0.30
0.25
4.6
4.5
4.4
4.6
4.5
4.4
0.5 3.5 0.15 0.08
A
Dimensions
TFBGA48: plastic thin fine-pitch ball grid array package; 48 balls; body 4.5 x 4.5 x 0.7 mm SOT1155-2
A1A2
0.80
0.70
0.65
bDEee
1
3.5
e2vw
0.05
yy
1
0.1
0 5 mm
scale
ball A1
index area
BA
D
E
A
B
C
D
E
F
H
G
24681357
b
e2
e1
e
e1/2 e
1/2 e
ball A1
index area
solder mask open area
not for solder ball
C
y
C
y1
X
detail X
AA2
A1
AC B
Ø v
CØ w
V ‘1 l 7 ? : m ‘ m \
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Product data sheet Rev. 9.2 — 26 March 2014 112 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
14. Soldering
Fig 63. Reflow soldering of the SO20 package
sot163-1_fr
occupied area
solder lands
Dimensions in mmplacement accuracy ± 0.25
1.50
0.60 (20×)
1.27 (18×)
8.00 11.00
13.40
11.40
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Product data sheet Rev. 9.2 — 26 March 2014 113 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Fig 64. Reflow soldering of the TSSOP20 package
DIMENSIONS in mm
Ay By D1 D2 Gy HyP1 C Gx
sot360-1_fr
Hx
SOT360-1
solder land
occupied area
Footprint information for reflow soldering of TSSOP20 package
AyByGy
C
Hy
Hx
Gx
P1
Generic footprint pattern
Refer to the package outline drawing for actual layout
P2
(0.125) (0.125)
D1
D2 (4x)
P2
7.200 4.500 1.350 0.400 0.600 6.900 5.300 7.4507.3000.650 0.750
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Product data sheet Rev. 9.2 — 26 March 2014 114 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Fig 65. Reflow soldering of the TSSOP28 package
DIMENSIONS in mm
Ay By D1 D2 Gy HyP1 C Gx
sot361-1_fr
Hx
SOT361-1
solder land
occupied area
Footprint information for reflow soldering of TSSOP28 package
AyByGy
C
Hy
Hx
Gx
P1
Generic footprint pattern
Refer to the package outline drawing for actual layout
P2
(0.125) (0.125)
D1
D2 (4x)
P2
7.200 4.500 1.350 0.400 0.600 9.500 5.300 7.45011.8000.650 0.750
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Product data sheet Rev. 9.2 — 26 March 2014 115 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Fig 66. Reflow soldering of the HVQFN24 package
SOT616-3Footprint information for reflow soldering of HVQFN24 package
Dimensions in mm
Ax Ay Bx By D SLx SLy SPx tot SPy tot SPx SPy Gx Gy Hx Hy
5.000 5.000 3.200 3.200
P
0.500 0.240
C
0.900 2.500 2.500 1.500 1.500 0.550 0.550 4.300 4.300 5.250 5.250
nSPx nSPy
22
sot616-3_fr
occupied area
Ax
Bx
SLx
Gx
Gy
Hy
Hx
AyBySLy
P 0.025 0.025
D
(0.105)
SPx tot
SPy tot
nSPx
nSPy
SPx
SPy
solder land plus solder paste
solder land
solder paste deposit
C
Generic footprint pattern
Refer to the package outline drawing for actual layout
Issue date 07-05-07
09-06-15
anaa package
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Product data sheet Rev. 9.2 — 26 March 2014 116 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Fig 67. Reflow soldering of the HVQFN33 package (5x5)
Footprint information for reflow soldering of HVQFN33 package
occupied area
solder paste
solder land
Dimensions in mm
P
0.5
002aag766
Issue date 11-11-15
11-11-20
Ax Ay Bx C D
5.95 5.95 4.25 0.85
By
4.25 0.27
Gx
5.25
Gy
5.25
Hy
6.2
Hx
6.2
SLx SLy nSPx nSPy
3.75 3.75 3 3
0.30
0.60
detail X
C
SLy
D
SLx
Bx
Ay
P
nSPy
nSPx
see detail X
Gx
Hx
GyHy By
Ax
V &\ Q
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Product data sheet Rev. 9.2 — 26 March 2014 117 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Fig 68. Reflow soldering of the HVQFN33 package (7x7)
Footprint information for reflow soldering of HVQFN33 package
001aao134
occupied area
solder land
solder resist
solder land plus solder paste
solder paste deposit
Dimensions in mm
Remark:
Stencil thickness: 0.125 mm
e = 0.65
evia = 4.25
OwDtot = 5.10 OA
PID = 7.25 PA+OA
OID = 8.20 OA
0.20 SR
chamfer (4×)
0.45 DM
evia = 1.05
W = 0.30 CU
evia = 4.25
evia = 2.40
LbE = 5.80 CU
LbD = 5.80 CU
PIE = 7.25 PA+OA
LaE = 7.95 CU
LaD = 7.95 CU
OIE = 8.20 OA
OwEtot = 5.10 OA
EHS = 4.85 CU
DHS = 4.85 CU
4.55 SR
4.55 SR
B-side
(A-side fully covered)
number of vias: 20
Solder resist
covered via
0.30 PH
0.60 SR cover
0.60 CU
SEhtot = 2.70 SP
SDhtot = 2.70 SP
GapE = 0.70 SP
SPE = 1.00 SP
0.45 DM
SPD = 1.00 SP
GapD = 0.70 SP
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 118 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Fig 69. Reflow soldering of the LQFP48 package
SOT313-2
DIMENSIONS in mm
occupied area
Footprint information for reflow soldering of LQFP48 package
Ax
Bx
Gx
Gy
Hy
Hx
AyBy
P1
D2 (8×)D1
(0.125)
Ax Ay Bx By D1 D2 Gx Gy Hx Hy
10.350
P2
0.560 10.350 7.350 7.350
P1
0.500 0.280
C
1.500 0.500 7.500 7.500 10.650 10.650 sot313-2_fr
solder land
C
Generic footprint pattern
Refer to the package outline drawing for actual layout
P2
0000000 00000000 00 OO %§@:
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 119 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Fig 70. Reflow soldering for the TFBGA48 package
DIMENSIONS in mm
PSLSPSRHxHy
Hx
Hy
SOT1155-2
solder land plus solder paste
occupied area
Footprint information for reflow soldering of TFBGA48 package
solder land
solder paste deposit
solder resist
P
P
SL
SP
SR
detail X
see detail X
0.50 0.225 0.275 0.325 4.75 4.75 sot1155-2_fr
http://www.nxp.com/documenIs/user manual/UM10398pdf http://www.nxp.com/documems/errata shee1/ES LPC111X.pdf
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Product data sheet Rev. 9.2 — 26 March 2014 120 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
15. Abbreviations
16. References
[1] LPC111x/LPC11Cxx User manual UM10398:
http://www.nxp.com/documents/user_manual/UM10398.pdf
[2] LPC111x Errata sheet:
http://www.nxp.com/documents/errata_sheet/ES_LPC111X.pdf
Table 33. Abbreviations
Acronym Description
ADC Analog-to-Digital Converter
AHB Advanced High-performance Bus
APB Advanced Peripheral Bus
BOD BrownOut Detection
GPIO General Purpose Input/Output
PLL Phase-Locked Loop
RC Resistor-Capacitor
SPI Serial Peripheral Interface
SSI Serial Synchronous Interface
SSP Synchronous Serial Port
TEM Transverse ElectroMagnetic
UART Universal Asynchronous Receiver/Transmitter
W Section 6.2 W
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Product data sheet Rev. 9.2 — 26 March 2014 121 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
17. Revision history
Table 34. Revision history
Document ID Release date Data sheet status Change notice Supersedes
LPC111X v.9.2 20140326 Product data sheet - LPC111X v.9.1
Modifications: •Pin description tables for RESET/PIO0_0 updated: In deep power-down mode, this pin
must be pulled HIGH externally. The RESET pin can be left unconnected or be used
as a GPIO pin if an external RESET function is not needed. See Section 6.2.
•Pin description notes relating to open-drain I2C-bus pins updated for clarity in
Section 6.2.
•Pin description of the WAKEUP pin updated for clarity. See Section 6.2.
•Parts added: LPC1114JHI33/303, LPC1111JHN33/103, LPC1112JHN33/203,
LPC1113JHN33/203, LPC1114JHN33/303, LPC1114JBD48/333, LPC1112FHI33/102,
LPC1114JBD48/303, LPC1114JBD48/323, LPC1113JBD48/303, LPC1113JHN33/303,
LPC1112JHN33/103, LPC1111JHN33/203, LPC1114JHN33/203.
LPC111X v.9.1 20131213 Product data sheet - LPC111X v.9
Modifications: •Table 17 “Static characteristics (LPC1100XL series)”:
–Added IDD max spec for Deep-sleep and Deep power-down modes @ 25 C and
105 C.
–Added Table note 11 “105 °C spec applies only to the LPC1112JHI33,
LPC1114JHN33, LPC1115JBD48, and LPC1115JET48 parts.”
–Updated Table note 12 “WAKEUP pin and RESET pin are pulled HIGH externally.”
•Table 16 “Static characteristics (LPC1100, LPC1100L series)”:
–Updated Table note 9 “WAKEUP pin and RESET pin are pulled HIGH externally.”
LPC111X v.9 20131029 Product data sheet - LPC111X v.8.2
Modifications: •Added LPC1112JHI33/203, LPC1114JHN33/333, LPC1115JBD48/303, and
LPC1115JET48/303 parts.
•Removed tclk(H) and tclk(L) from Figure 47 “SPI master timing in SPI mode” and Figure
48 “SPI slave timing in SPI mode”; spec not characterized.
•Table 22 “Power-up characteristics[1]”: Added table note “Does not apply to
LPC1100XL series”.
LPC111X v.8.2 20130805 Product data sheet - LPC111X v.8.1
Modifications: •Added LPC1115FET48/303.
LPC111X v.8.1 20130524 Product data sheet - LPC111X v.8
Modifications: •Table 4 thru Table 11: Added “5 V tolerant pad” to RESET/PIO0_0 table note.
•Added Section 9 “Thermal characteristics”.
•SRAM size corrected for part LPC1112FHN24/202 (4 kB). See Table 2.
LPC111X v.8 20130220 Product data sheet - LPC111X v.7.5
Modifications: •Table 16 “Static characteristics” added Pin capacitance section.
•Default pin state corrected for pins PIO0_4 and PIO0_5 (I; IA) in Table 11 “LPC1100XL
series: LPC1111/12/13/14 pin description table (HVQFN33 package)”.
•Table 12 “Limiting values” expanded for clarity.
•Table 19 “ Power consumption at very low frequencies using the watchdog oscillator”
added.
•Added Section 12.2 “Use of ADC input trigger signals”.
•Added Section 12.8 “ADC effective input impedance”.
LPC111X v.7.5 20121002 Product data sheet - LPC111X v.7.4
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 122 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Modifications: BOD level 0 for reset added in Table 15.
LPC111X v.7.4 20120730 Product data sheet - LPC111X v.7.3
Modifications: •Function SSEL1 added to pin PIO2_0 in Figure 6 “LPC1100XL series pin configuration
HVQFN33” and Table 11 “LPC1100XL series: LPC1111/12/13/14 pin description table
(HVQFN33 package)”.
•BOD level 0 for reset and interrupt removed.
LPC111X v.7.3 20120706 Product data sheet - LPC111X v.7.2
Modifications: •Corrected pinout for part LPC1112FHN24/202. Pin XTALOUT replaced by VDD. See
Table 6 and Figure 10.
LPC111X v.7.2 20120604 Product data sheet - LPC111X v.7.1
Modifications: •For parameters IOL, VOL, IOH, VOH, changed conditions to 1.8 V VDD < 2.5 V and 2.5
V VDD 3.6 V in Table 13).
•Capture-clear feature added to general-purpose counter/timers (see Section 7.12;
LPC1100XL series only).
•Figure 47 updated for parts with configurable open-drain mode.
•Added Section 9.5 “CoreMark data”
•Added LPC1100L series part (LPC1112FHN24/202).
•WDOSc frequency range corrected.
LPC111X v.7.1 20120401 Product data sheet - LPC111X v.7
Modifications: •Added HVQFN33 (5x5) reflow soldering information.
LPC111X v.7 20120301 Product data sheet - LPC1110_11_12_13_14 v.6
Modifications: •LPC1100XL series parts added (LPC1111FHN33/103, LPC1111FHN33/203,
LPC1112FHN33/103, LPC1112FHN33/203, LPC1112FHI33/203, LPC1113FBD48/303,
LPC1113FHN33/203, LPC1113FHN33/303, LPC1114FBD48/303,
LPC1114FHN33/203, LPC1114FHN33/303, LPC1114FHI33/303, LPC1114FBD48/323,
LPC1114FBD48/333, LPC1114FHN33/333, LPC1115FBD48/303).
LPC1110_11_12_13_14 v.6 20111102 Product data sheet - LPC1111_12_13_14 v.5
Modifications: •Parts LPC1112FHI33/202 and LPC1114FHI33/302 added.
•Parts LPC1112FDH28/102, LPC1114FDH28/102, LPC1114FN28/102,
LPC1112FDH20/102, LPC1110FD20, LPC1111FDH20/002, LPC1112FD20/102 added.
LPC1111_12_13_14 v.5 20110622 Product data sheet - LPC1111_12_13_14 v.4
Modifications: •ADC sampling frequency corrected in Table 7 (Table note 7).
•Pull-up level specified in Table 3 to Table 4 and Section 7.7.1.
•Parameter Tcy(clk) corrected on Table 17.
•WWDT for parts LPC111x/102/202/302 added in Section 2 and Section 7.15.
•Programmable open-drain mode for parts LPC111x/102/202/302 added in Section 2
and Section 7.12.
•Condition for parameter Tstg in Table 5 updated.
•Table note 4 of Table 5 updated.
•Section 13 added.
•Removed PLCC44 package information.
LPC1111_12_13_14 v.4 20110210 Product data sheet - LPC1111_12_13_14 v.3
Table 34. Revision history …continued
Document ID Release date Data sheet status Change notice Supersedes
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 123 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Modifications: •Power consumption graphs added for parts LPC111x/102/202/302 (Figure 13 to
Figure 17).
•Parameter Vhys for I2C bus pins: typical value corrected Vhys = 0.05VDD in Table 7.
•Typical value for parameter Nendu added in Table 12 “Flash characteristics”.
•I2C-bus pins configured as standard mode pins, parameter IOL changed to 3.5 mA
(minimum) for 2.0 V VDD 3.6 V.
•Section 11.6 “ElectroMagnetic Compatibility (EMC)” added.
•Power-up characterization added (Section 10.1 “Power-up ramp conditions”).
LPC1111_12_13_14 v.3 20101110 Product data sheet - LPC1111_12_13_14 v.2
Modifications: •Parts LPC111x/102/202/302 added (LPC1100L series).
•Power consumption data for parts LPC111x/102/202/302 added in Table 7.
•PLL output frequency limited to 100 MHz in Section 7.15.2.
•Description of RESET and WAKEUP functions updated in Section 6.
•WDT description updated in Section 7.14. The WDT is a 24-bit timer.
•Power profiles added to Section 2 and Section 7 for parts LPC111x/102/202/302.
LPC1111_12_13_14 v.2 20100818 Product data sheet - LPC1111_12_13_14 v.1
Modifications: •VESD limit changed to 6500 V (min) /+6500 V (max) in Table 6.
•tDS updated for SPI in master mode (Table 17).
•Deep-sleep mode functionality changed to allow BOD and watchdog oscillator as the
only analog blocks allowed to remain running in Deep-sleep mode (Section 7.15.5.3).
•VDD range changed to 3.0 V VDD 3.6 V in Table 15.
•Reset state of pins and start logic functionality added in Table 3 to Table 5.
•Section 7.16.1 added.
•Section “Memory mapping control” removed.
•VOH and IOH specifications updated for high-drive pins in Table 7.
•Section 9.4 added.
LPC1111_12_13_14 v.1 20100416 Product data sheet - -
Table 34. Revision history …continued
Document ID Release date Data sheet status Change notice Supersedes
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 124 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
18. Legal information
18.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
: hitE:I/www.nxg.com salesaddresses®nx9£0m
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Product data sheet Rev. 9.2 — 26 March 2014 125 of 127
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP Semiconductors N.V.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 126 of 127
continued >>
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
20. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3
4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 6
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6 Pinning information. . . . . . . . . . . . . . . . . . . . . 11
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 19
7 Functional description . . . . . . . . . . . . . . . . . . 45
7.1 ARM Cortex-M0 processor. . . . . . . . . . . . . . . 45
7.2 On-chip flash program memory . . . . . . . . . . . 45
7.3 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 45
7.4 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.5 Nested Vectored Interrupt Controller (NVIC) . 47
7.5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.5.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 48
7.6 IOCONFIG block . . . . . . . . . . . . . . . . . . . . . . 48
7.7 Fast general purpose parallel I/O . . . . . . . . . . 48
7.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.8 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.9 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 49
7.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.10 I2C-bus serial I/O controller . . . . . . . . . . . . . . 50
7.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.11 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.12 General purpose external event
counter/timers. . . . . . . . . . . . . . . . . . . . . . . . . 51
7.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.13 System tick timer . . . . . . . . . . . . . . . . . . . . . . 51
7.14 Watchdog timer (LPC1100 series,
LPC111x/101/201/301) . . . . . . . . . . . . . . . . . . 51
7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.15 Windowed WatchDog Timer
(LPC1100L and LPC1100XL series). . . . . . . . 52
7.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7.16 Clocking and power control . . . . . . . . . . . . . . 52
7.16.1 Crystal oscillators . . . . . . . . . . . . . . . . . . . . . . 52
7.16.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 53
7.16.1.2 System oscillator . . . . . . . . . . . . . . . . . . . . . . 53
7.16.1.3 Watchdog oscillator . . . . . . . . . . . . . . . . . . . . 54
7.16.2 System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 54
7.16.3 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 54
7.16.4 Wake-up process . . . . . . . . . . . . . . . . . . . . . . 54
7.16.5 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 54
7.16.5.1 Power profiles (LPC1100L and LPC1100XL
series only). . . . . . . . . . . . . . . . . . . . . . . . . . . 54
7.16.5.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7.16.5.3 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 55
7.16.5.4 Deep power-down mode . . . . . . . . . . . . . . . . 55
7.17 System control . . . . . . . . . . . . . . . . . . . . . . . . 55
7.17.1 Start logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7.17.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
7.17.3 Brownout detection . . . . . . . . . . . . . . . . . . . . 56
7.17.4 Code security (Code Read Protection - CRP) 56
7.17.5 APB interface . . . . . . . . . . . . . . . . . . . . . . . . . 57
7.17.6 AHBLite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
7.17.7 External interrupt inputs . . . . . . . . . . . . . . . . . 57
7.18 Emulation and debugging . . . . . . . . . . . . . . . 57
8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 58
9 Thermal characteristics . . . . . . . . . . . . . . . . . 59
10 Static characteristics . . . . . . . . . . . . . . . . . . . 61
10.1 LPC1100, LPC1100L series. . . . . . . . . . . . . . 61
10.2 LPC1100XL series . . . . . . . . . . . . . . . . . . . . . 65
10.3 ADC static characteristics . . . . . . . . . . . . . . . 69
10.4 BOD static characteristics . . . . . . . . . . . . . . . 71
10.5 Power consumption LPC1100 series
(LPC111x/101/201/301) . . . . . . . . . . . . . . . . . 72
10.6 Power consumption LPC1100L series
(LPC111x/002/102/202/302) . . . . . . . . . . . . . 75
10.7 Power consumption LPC1100XL series
(LPC111x/103/203/303/323/333) . . . . . . . . . . 78
10.8 CoreMark data . . . . . . . . . . . . . . . . . . . . . . . . 82
10.9 Peripheral power consumption . . . . . . . . . . . 84
10.10 Electrical pin characteristics. . . . . . . . . . . . . . 85
11 Dynamic characteristics. . . . . . . . . . . . . . . . . 88
11.1 Power-up ramp conditions . . . . . . . . . . . . . . . 88
11.2 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 88
11.3 External clock. . . . . . . . . . . . . . . . . . . . . . . . . 89
11.4 Internal oscillators . . . . . . . . . . . . . . . . . . . . . 90
11.5 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
11.6 I2C-bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
11.7 SPI interfaces. . . . . . . . . . . . . . . . . . . . . . . . . 94
12 Application information . . . . . . . . . . . . . . . . . 97
12.1 ADC usage notes. . . . . . . . . . . . . . . . . . . . . . 97
12.2 Use of ADC input trigger signals . . . . . . . . . . 97
12.3 XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
12.4 XTAL Printed Circuit Board (PCB) layout
guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
12.5 Standard I/O pad configuration . . . . . . . . . . . 99
12.6 Reset pad configuration . . . . . . . . . . . . . . . . 100
12.7 ElectroMagnetic Compatibility (EMC) . . . . . 101
NXP Semiconductors LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
© NXP Semiconductors N.V. 2014. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 26 March 2014
Document identifier: LPC111X
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
12.8 ADC effective input impedance . . . . . . . . . . 102
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . 103
14 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
15 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . 120
16 References . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
17 Revision history. . . . . . . . . . . . . . . . . . . . . . . 121
18 Legal information. . . . . . . . . . . . . . . . . . . . . . 124
18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . 124
18.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . 124
18.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . 124
18.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . 125
19 Contact information. . . . . . . . . . . . . . . . . . . . 125
20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

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