NCP5106A/B Datasheet by ON Semiconductor

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© Semiconductor Components Industries, LLC, 2017
February, 2017 − Rev. 9 1Publication Order Number:
NCP5106/D
NCP5106A, NCP5106B
High Voltage, High and Low
Side Driver
The NCP5106 is a high voltage gate driver IC providing two
outputs for direct drive of 2 N−channel power MOSFETs or IGBTs
arranged in a half−bridge configuration version B or any other
high−side + low−side configuration version A.
It uses the bootstrap technique to ensure a proper drive of the
high−side power switch. The driver works with 2 independent inputs.
Features
•High Voltage Range: Up to 600 V
•dV/dt Immunity ±50 V/nsec
•Negative Current Injection Characterized Over the Temperature Range
•Gate Drive Supply Range from 10 V to 20 V
•High and Low Drive Outputs
•Output Source / Sink Current Capability 250 mA / 500 mA
•3.3 V and 5 V Input Logic Compatible
•Up to VCC Swing on Input Pins
•Extended Allowable Negative Bridge Pin Voltage Swing to −10 V
for Signal Propagation
•Matched Propagation Delays Between Both Channels
•Outputs in Phase with the Inputs
•Independent Logic Inputs to Accommodate All Topologies (Version A)
•Cross Conduction Protection with 100 ns Internal Fixed Dead Time
(Version B)
•Under VCC LockOut (UVLO) for Both Channels
•Pin−to−Pin Compatible with Industry Standards
•These are Pb−Free Devices
Typical Applications
•Half−Bridge Power Converters
•Any Complementary Drive Converters (Asymmetrical Half−Bridge,
Active Clamp) (A Version Only).
•Full−Bridge Converters
SOIC−8
D SUFFIX
CASE 751
MARKING
DIAGRAMS
NCP5106 = Specific Device Code
x = A or B version
A = Assembly Location
L or WL = Wafer Lot
Y or YY = Year
W or WW = Work Week
G or G= Pb−Free Package
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1
PDIP−8
P SUFFIX
CASE 626
5106x
ALYW
G
1
8
1NCP5106x
AWL
YYWWG
PINOUT INFORMATION
8 Pin Package
1
1
IN_LO
IN_HI
VCC
GND
VBOOT
DRV_HI
BRIDGE
DRV_LO
See detailed ordering and shipping information on page 16 o
f
this data sheet.
ORDERING INFORMATION
DFN10
MN SUFFIX
CASE 506DJ
15106x
ALYWG
G
(Note: Microdot may be in either location)
10 Pin DFN Package
VBOOT
DRV_HI
BRIDGE
NC
NC
IN_LO
IN_HI
VCC
GND
DRV_LO
NCP5106A, NCP5106B
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Vcc
IN_HI
IN_LO
GND DRV_LO
Bridge
DRV_HI
VBOOT
Q1
Q2 C6
C4
C3
GND
GND
GND
NCP1395
Vcc
GND
Vbulk C1
GND
Out+
Out−
U2
R1
D3
GND
L1
C3
D2
T1
D4
Lf
Vcc
IN_HI
IN_LO
GND DRV_LO
Bridge
DRV_HI
VBOOT
U1
NCP5106
Figure 1. Typical Application Resonant Converter (LLC type)
Figure 2. Typical Application Half Bridge Converter
D1
+
+
Q1
Q2 C6
C4
C3
GND
GND
GND
MC34025
Vcc
GND
Vbulk C1
GND
Out+
Out−
U2
R1
D3
GND
L1
C3
D2
T1
D4
U1
NCP5106
D1
+
+
C5
._ 1—» {H— ._. ._ 3?;
NCP5106A, NCP5106B
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R
S Q
PULSE
TRIGGER
GND
GND GND
VCC
IN_HI
IN_LO
VBOOT
DRV_HI
BRIDGE
DRV_LO
GND
VCC
VCC UV
DETECT
DELAY
GND UV
DETECT
LEVEL
SHIFTER Q
GND
Figure 3. Detailed Block Diagram: Version A
GND
Figure 4. Detailed Block Diagram: Version B
R
S Q
PULSE
TRIGGER
GND
GND GND
VCC
IN_HI
IN_LO
VBOOT
DRV_HI
BRIDGE
DRV_LO
GND
VCC
VCC UV
DETECT
DELAY
GNDCROSS
CONDUCTION
PREVENTION
UV
DETECT
LEVEL
SHIFTER Q
PIN DESCRIPTION
Pin Name Description
IN_HI Logic Input for High Side Driver Output in Phase
IN_LO Logic Input for Low Side Driver Output in Phase
GND Ground
DRV_LO Low Side Gate Drive Output
VCC Low Side and Main Power Supply
VBOOT Bootstrap Power Supply
DRV_HI High Side Gate Drive Output
BRIDGE Bootstrap Return or High Side Floating Supply Return
NC Removed for creepage distance (DFN package only)
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MAXIMUM RATINGS
Rating Symbol Value Unit
VCC Main power supply voltage −0.3 to 20 V
VCC_transient Main transient power supply voltage:
IVCC_max = 5 mA during 10 ms 23 V
VBRIDGE VHV: High Voltage BRIDGE pin −1 to 600 V
VBRIDGE Allowable Negative Bridge Pin Voltage for IN_LO Signal Propagation to DRV_LO
(see characterization curves for detailed results) −10 V
VBOOT−VBRIDGE VHV: Floating supply voltage −0.3 to 20 V
VDRV_HI VHV: High side output voltage VBRIDGE − 0.3 to
VBOOT + 0.3 V
VDRV_LO Low side output voltage −0.3 to VCC + 0.3 V
dVBRIDGE/dt Allowable output slew rate 50 V/ns
VIN_XX Inputs IN_HI, IN_LO −1.0 to VCC + 0.3 V
ESD Capability:
− HBM model (all pins except pins 6−7−8 in 8 pins
package or 11−12−13 in 14 pins package)
− Machine model (all pins except pins 6−7−8 in 8 pins
package or 11−12−13 in 14 pins package)
2
200
kV
V
Latch up capability per JEDEC JESD78
RqJA Power dissipation and Thermal characteristics
PDIP−8: Thermal Resistance, Junction−to−Air
SO−8: Thermal Resistance, Junction−to−Air
DFN10 4x4: Thermal Resistance, Junction−to−Ambient 1 Oz Cu
DFN10 4x4: 50 mm2 Printed Circuit Copper Clad
100
178
162
°C/W
TST Storage Temperature Range −55 to +150 °C
TJ_max Maximum Operating Junction Temperature +150 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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ELECTRICAL CHARACTERISTIC (VCC = Vboot = 15 V, VGND = Vbridge, −40°C < TJ < 125°C, Outputs loaded with 1 nF)
Rating Symbol
TJ −40°C to 125°C
Units
Min Typ Max
OUTPUT SECTION
Output high short circuit pulsed current VDRV = 0 V, PW v 10 ms (Note 1) IDRVsource − 250 − mA
Output low short circuit pulsed current VDRV = VCC, PW v 10 ms (Note 1) IDRVsink − 500 − mA
Output resistor (Typical value @ 25°C) Source ROH − 30 60 W
Output resistor (Typical value @ 25°C) Sink ROL − 10 20 W
High level output voltage, VBIAS−VDRV_XX @ IDRV_XX = 20 mA VDRV_H − 0.7 1.6 V
Low level output voltage VDRV_XX @ IDRV_XX = 20 mA VDRV_L − 0.2 0.6 V
DYNAMIC OUTPUT SECTION
Turn−on propagation delay (Vbridge = 0 V) tON − 100 170 ns
Turn−off propagation delay (Vbridge = 0 V or 50 V) (Note 2) tOFF − 100 170 ns
Output voltage rise time (from 10% to 90% @ VCC = 15 V) with 1 nF load tr − 85 160 ns
Output voltage fall time (from 90% to 10% @VCC = 15 V) with 1 nF load tf − 35 75 ns
Propagation delay matching between the High side and the Low side @ 25°C (Note 3) Dt − 20 35 ns
Internal fixed dead time (only valid for B version) (Note 4) DT 65 100 190 ns
Minimum input width that changes the output tPW1 − − 50 ns
Maximum input width that does not change the output SOIC−8, PDIP−8
DFN10 tPW2 20
15 −
−−
−ns
INPUT SECTION
Low level input voltage threshold VIN − − 0.8 V
Input pull−down resistor (VIN < 0.5 V) RIN − 200 − kW
High level input voltage threshold VIN 2.3 − − V
Logic “1” input bias current @ VIN_XX = 5 V @ 25°C IIN+ − 5 25 mA
Logic “0” input bias current @ VIN_XX = 0 V @ 25°C IIN− − − 2.0 mA
SUPPLY SECTION
VCC UV Start−up voltage threshold VCC_stup 8.0 8.9 9.9 V
VCC UV Shut−down voltage threshold VCC_shtdwn 7.3 8.2 9.1 V
Hysteresis on VCC VCC_hyst 0.3 0.7 − V
Vboot Start−up voltage threshold reference to bridge pin
(Vboot_stup = Vboot − Vbridge)
Vboot_stup 8.0 8.9 9.9 V
Vboot UV Shut−down voltage threshold Vboot_shtdwn 7.3 8.2 9.1 V
Hysteresis on Vboot Vboot_hyst 0.3 0.7 − V
Leakage current on high voltage pins to GND
(VBOOT = VBRIDGE = DRV_HI = 600 V)
IHV_LEAK − 5 40 mA
Consumption in active mode (VCC = Vboot, fsw = 100 kHz and 1 nF load on both driv-
er outputs) ICC1 − 4 5 mA
Consumption in inhibition mode (VCC = Vboot) ICC2 − 250 400 mA
VCC current consumption in inhibition mode ICC3 − 200 − mA
Vboot current consumption in inhibition mode ICC4 − 50 − mA
1. Parameter guaranteed by design.
2. Turn−off propagation delay @ Vbridge = 600 V is guaranteed by design.
3. See characterization curve for Dt parameters variation on the full range temperature.
4. Version B integrates a dead time in order to prevent any cross conduction between DRV_HI and DRV_LO. See timing diagram of Figure 10.
5. Timing diagram definition see: Figure 7, Figure 8 and Figure 9.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NCP5106A, NCP5106B
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Figure 5. Input/Output Timing Diagram (A Version)
IN_HI
IN_LO
DRV_HI
DRV_LO
IN_HI
IN_LO
DRV_HI
DRV_LO
Figure 6. Input/Output Timing Diagram (B Version)
Figure 7. Propagation Delay and Rise / Fall Time Definition
IN_HI 50%
90% 90%
10% 10%
(IN_LO)
DRV_HI
(DRV_LO)
50%
toff
ton
trtf
NCP5106A, NCP5106B
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Figure 8. Matching Propagation Delay (A Version)
50%
90%
50%
ton_HI
toff_HI
10%
DRV_HI
IN_LO
ton_LO
DRV_LO
Delta_t
10% Matching Delay 1 = ton_HI − ton_LO
toff_LO
&
IN_HI
90%
Matching Delay 2 = toff_LO − toff_HI
Delta_t
50%
90%
50%
ton_HI
toff_HI
10%
DRV_HI
IN_HI
50%
10%
50%
toff_LO ton_LO
90%
DRV_LO
IN_LO
Matching Delay1=ton_HI−ton_LO
Matching Delay2=toff_HI−toff_LO
Figure 9. Matching Propagation Delay (B Version)
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IN_HI
IN_LO
DRV_HI
DRV_LO
Internal Deadtime Internal Deadtime
Figure 10. Input/Output Cross Conduction Output Protection Timing Diagram (B Version)
\\ 20
NCP5106A, NCP5106B
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CHARACTERIZATION CURVES
0
20
40
60
80
100
120
140
10 12 14 16 18 20
VCC, VOLTAGE (V)
T
ON
, PROPAGATION DELAY (ns)
Figure 11. Turn ON Propagation Delay vs.
Supply Voltage (VCC = VBOOT)
TON High Side
TON Low Side
0
20
40
60
80
100
120
140
−40 −20 0 20 40 60 80 100 12
0
TEMPERATURE (°C)
TON, PROPAGATION DELAY (ns)
Figure 12. Turn ON Propagation Delay vs.
Temperature
TON Low Side
TON High Side
0
20
40
60
80
100
120
140
10 12 14 16 18 20
VCC, VOLTAGE (V)
T
OFF
, PROPAGATION DELAY (ns)
Figure 13. Turn OFF Propagation Delay vs.
Supply Voltage (VCC = VBOOT)
TOFF High Side
TOFF Low Side
0
20
40
60
80
100
120
140
−40 −20 0 20 40 60 80 100 12
0
TEMPERATURE (°C)
TOFF
, PROPAGATION DELAY (ns)
Figure 14. Turn OFF Propagation Delay vs.
Temperature
0
20
40
60
80
100
120
140
0 1020304050
BRIDGE PIN VOLTAGE (V)
T
ON
, PROPAGATION DELAY (ns)
Figure 15. High Side Turn ON Propagation
Delay vs. VBRIDGE Voltage
0
20
40
60
80
100
120
140
160
0 102030405
0
BRIDGE PIN VOLTAGE (V)
TOFF PROPAGATION DELAY (ns)
Figure 16. High Side Turn OFF Propagation
Delay vs. VBRIDGE Voltage
TOFF High Side
TOFF Low Side
c, Low sue ngh Swde / 20 www.cmse
NCP5106A, NCP5106B
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CHARACTERIZATION CURVES
0
20
40
60
80
100
120
140
160
10 12 14 16 18 20
VCC, VOLTAGE (V)
T
ON
, RISETIME (ns)
Figure 17. Turn ON Risetime vs. Supply
Voltage (VCC = VBOOT)
tr High Side
tr Low Side
0
20
40
60
80
100
120
140
−40 −20 0 20 40 60 80 100 12
0
tr Low Side
tr High Side
TEMPERATURE (°C)
TON, RISETIME (ns)
Figure 18. Turn ON Risetime vs. Temperature
0
10
20
30
40
50
60
70
80
10 12 14 16 18 20
T
OFF
, FALLTIME (ns)
VCC, VOLTAGE (V)
Figure 19. Turn OFF Falltime vs. Supply
Voltage (VCC = VBOOT)
tf Low Side
tf High Side
0
10
20
30
40
50
70
−40 −20 0 20 40 60 80 100 12
0
tf Low Side
tf High Side
TOFF
, FALLTIME (ns)
TEMPERATURE (°C)
Figure 20. Turn OFF Falltime vs. Temperature
0
5
10
15
20
−40 −20 0 20 40 60 80 100 120
PROPAGATION DELAY MATCHING (ns)
TEMPERATURE (°C)
Figure 21. Propagation Delay Matching
Between High Side and Low Side Driver vs.
Temperature
60
0
20
100
160
200
−40 −20 0 20 40 60 80 100 12
0
DEAD TIME (ns)
TEMPERATURE (°C)
Figure 22. Dead Time vs. Temperature
40
60
80
120
140
180
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CHARACTERIZATION CURVES
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
−40 −20 0 20 40 60 80 100 120
LOW LEVEL INPUT VOLTAGE
THRESHOLD (V)
TEMPERATURE (°C)
Figure 23. Low Level Input Voltage Threshold
vs. Supply Voltage (VCC = VBOOT)
0
0.5
1
1.5
2
2.5
10 12 14 16 18 20
HIGH LEVEL INPUT VOLTAGE
THRESHOLD (V)
VCC, VOLTAGE (V)
Figure 24. Low Level Input Voltage Threshold
vs. Temperature
0.0
0.5
1.0
1.5
2.0
2.5
−40 −20 0 20 40 60 80 100 120
HIGH LEVEL INPUT VOLTAGE
THRESHOLD (V)
TEMPERATURE (°C)
Figure 25. High Level Input Voltage Threshold
vs. Supply Voltage (VCC = VBOOT)
0
0.5
1
1.5
2
2.5
3
3.5
4
10 12 14 16 18 20
LOGIC “0” INPUT CURRENT (mA)
VCC, VOLTAGE (V)
Figure 26. High Level Input Voltage Threshold
vs. Temperature
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
−40 −20 0 20 40 60 80 100 120
LOGIC “0” INPUT CURRENT (mA)
TEMPERATURE (°C)
Figure 27. Logic “0” Input Current vs. Supply
Voltage (VCC = VBOOT)Figure 28. Logic “0” Input Current vs.
Temperature
0
0.2
0.4
0.6
0.8
1
1.2
1.4
10 12 14 16 18 20
LOW LEVEL INPUT VOLTAGE THRESHOLD (V)
VCC, VOLTAGE (V)
20 Supply Voltage (Vcc = Vaom
NCP5106A, NCP5106B
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CHARACTERIZATION CURVES
0
2
4
6
8
10
−40 −20 0 20 40 60 80 100 12
0
LOGIC “1” INPUT CURRENT (mA)
TEMPERATURE (°C)
Figure 29. Logic “1” Input Current vs. Supply
Voltage (VCC = VBOOT)
0
0.2
0.4
0.6
0.8
1
10 12 14 16 18 20
LOW LEVEL OUTPUT VOLTAGE
THRESHOLD (V)
VCC, VOLTAGE (V)
Figure 30. Logic “1” Input Current vs.
Temperature
0.0
0.2
0.4
0.6
0.8
1.0
−40 −20 0 20 40 60 80 100 12
0
LOW LEVEL OUTPUT VOLTAGE (V)
TEMPERATURE (°C)
Figure 31. Low Level Output Voltage vs.
Supply Voltage (VCC = VBOOT)
0
0.4
0.8
1.2
1.6
10 12 14 16 18 20
HIGH LEVEL OUTPUT VOLTAGE
THRESHOLD (V)
VCC, VOLTAGE (V)
Figure 32. Low Level Output Voltage vs.
Temperature
0.0
0.4
0.8
1.2
1.6
−40 −20 0 20 40 60 80 100 12
0
HIGH LEVEL OUTPUT VOLTAGE (V)
TEMPERATURE (°C)
Figure 33. High Level Output Voltage vs.
Supply Voltage (V
CC
= V
BOOT
)Figure 34. High Level Output Voltage vs.
Temperature
0
1
2
3
4
5
6
7
8
10 12 14 16 18 20
LOGIC “1” INPUT CURRENT (
m
A)
VCC, VOLTAGE (V)
F‘hgh Swde l I I // In Low ‘ w l / \ ‘smk / \§§\£ / /' / VERIGDE = VEOOT = Vnnv HI (VERIDGE = Vaoo'r = Vnnv m
NCP5106A, NCP5106B
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CHARACTERIZATION CURVES
OUTPUT SOURCE CURRENT (mA)
TEMPERATURE (°C)
Figure 35. Output Source Current vs. Supply
Voltage (VCC = VBOOT)
0
50
100
150
200
250
300
350
400
−40 −20 0 20 40 60 80 100 12
0
Isrc High Side
Isrc Low Side
0
100
200
300
400
500
600
10 12 14 16 18 20
Isink High Side
Isink Low Side
OUTPUT SINK CURRENT (mA)
VCC, VOLTAGE (V)
Figure 36. Output Source Current vs.
Temperature
0
100
200
300
400
500
600
−40 −20 0 20 40 60 80 100 12
0
OUTPUT SINK CURRENT (mA)
TEMPERATURE (°C)
Figure 37. Output Sink Current vs. Supply
Voltage (VCC = VBOOT)
Isink Low Side
Isink High Side
0
0.04
0.08
0.12
0.16
0.2
0 100 200 300 400 500 600
HIGH SIDE LEAKAGE CURRENT ON
HV PINS TO GND (mA)
HV PINS VOLTAGE (V)
Figure 38. Output Sink Current vs.
Temperature
0
5
10
15
20
−40 −20 0 20 40 60 80 100 1
20
LEAKAGE CURRENT ON HIGH
VOLTAGE PINS (600 V) to GND (mA)
TEMPERATURE (°C)
Figure 39. Leakage Current on High Voltage
Pins (600 V) to Ground vs. VBRIDGE Voltage
(V
BRIGDE
= V
BOOT
= V
DRV_HI
)
Figure 40. Leakage Current on High Voltage
Pins (600 V) to Ground vs. Temperature
(VBRIDGE = V
BOOT
= V
DRv_HI
= 600 V)
0
50
100
150
200
250
300
350
400
10 12 14 16 18 20
Isrc High Side
Isrc Low Side
OUTPUT SOURCE CURRENT (mA)
VCC, VOLTAGE (V)
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CHARACTERIZATION CURVES
0
20
40
60
80
100
−40 −20 0 20 40 60 80 100 12
0
VBOOT CURRENT SUPPLY (mA)
TEMPERATURE (°C)
Figure 41. VBOOT Supply Current vs. Bootstrap
Supply Voltage
0
40
80
120
160
200
240
0 4 8 12 16 20
V
CC
SUPPLY CURRENT (
m
A)
VCC, VOLTAGE (V)
Figure 42. VBOOT Supply Current vs.
Temperature
0
100
200
300
400
−40 −20 0 20 40 60 80 100 12
0
VCC CURRENT SUPPLY (mA)
TEMPERATURE (°C)
Figure 43. VCC Supply Current vs. VCC Supply
Voltage
8.0
8.2
8.4
8.6
8.8
9.0
9.2
9.4
9.6
9.8
10.0
−40 −20 0 20 40 60 80 100 120
VCC UVLO Startup
VBOOT UVLO Startup
UVLO STARTUP VOLTAGE (V)
TEMPERATURE (°C)
Figure 44. VCC Supply Current vs. Temperature
7.0
7.2
7.4
7.6
7.8
8.0
8.2
8.4
8.6
8.8
9.0
−40 −20 0 20 40 60 80 100 12
0
UVLO SHUTDOWN VOLTAGE (V)
TEMPERATURE (°C)
Figure 45. UVLO Startup Voltage vs.
Temperature
VCC UVLO Shutdown
VBOOT UVLO Shutdown
Figure 46. UVLO Shutdown Voltage vs.
Temperature
0
20
40
60
80
100
0 4 8 12 16 20
V
BOOT
SUPPLY CURRENT (
m
A)
VBOOT
, VOLTAGE (V)
Rem : 22 R RGATE : 0 R RENE : 22 R www.cmsemi .com
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CHARACTERIZATION CURVES
0
5
10
15
20
25
30
40
0 100 200 300 400 500 600
RGATE = 0 R
CLOAD = 2.2 nF/Q = 33 nC
ICC+ IBOOT CURRENT SUPPLY (mA)
SWITCHING FREQUENCY (kHz)
Figure 47. ICC1 Consumption vs. Switching
Frequency with 15 nC Load on Each Driver @
VCC = 15 V
RGATE = 10 R
RGATE = 22 R
0
10
20
30
40
50
60
70
0 100 200 300 400 500 600
RGATE = 0 R
RGATE = 10 R
RGATE = 22 R
ICC+ IBOOT CURRENT SUPPLY (mA)
SWITCHING FREQUENCY (kHz)
Figure 48. ICC1 Consumption vs. Switching
Frequency with 33 nC Load on Each Driver @
VCC = 15 V
CLOAD = 3.3 nF/Q = 50 nC
0
20
40
60
80
100
120
0 100 200 300 400 500 600
ICC+ IBOOT CURRENT SUPPLY (mA)
SWITCHING FREQUENCY (kHz)
Figure 49. ICC1 Consumption vs. Switching
Frequency with 50 nC Load on Each Driver @
VCC = 15 V
RGATE = 0 R
RGATE = 10 R
RGATE = 22 R
CLOAD = 6.6 nF/Q = 100 nC
Figure 50. ICC1 Consumption vs. Switching
Frequency with 100 nC Load on Each Driver @
VCC = 15 V
0
5
10
15
20
25
0 100 200 300 400 500 600
RGATE = 0 R to 22 R
CLOAD = 1 nF/Q = 15 nC
ICC+ IBOOT CURRENT SUPPLY (mA)
SWITCHING FREQUENCY (kHz)
35
−35
−30
−25
−20
−15
−10
−5
0
0 100 200 300 400 500 600
Figure 51. NCP5106A, Negative Voltage Safe
Operating Area on the Bridge Pin
−40°C
25°C
125°C
NEGATIVE PULSE VOLTAGE (V)
NEGATIVE PULSE DURATION (ns)
−35
−30
−25
−20
−15
−10
−5
0
0 100 200 300 400 500 600
NEGATIVE PULSE VOLTAGE (V)
NEGATIVE PULSE DURATION (ns)
Figure 52. NCP5106B, Negative Voltage Safe
Operating Area on the Bridge Pin
−40°C
25°C
125°C
www onsem' com
NCP5106A, NCP5106B
www.onsemi.com
16
APPLICATION INFORMATION
Negative Voltage Safe Operating Area
When the driver is used in a half bridge configuration, it
is possible to see negative voltage appearing on the bridge
pin (pin 6) during the power MOSFETs transitions. When
the high−side MOSFET is switched off, the body diode of
the low−side MOSFET starts to conduct. The negative
voltage applied to the bridge pin thus corresponds to the
forward voltage of the body diode. However, as pcb copper
tracks and wire bonding introduce stray elements
(inductance and capacitor), the maximum negative voltage
of the bridge pin will combine the forward voltage and the
oscillations created by the parasitic elements. As any
CMOS device, the deep negative voltage of a selected pin
can inject carriers into the substrate, leading to an erratic
behavior of the concerned component. ON Semiconductor
provides characterization data of its half−bridge driver to
show the maximum negative voltage the driver can safely
operate with. To prevent the negative injection, it is the
designer duty to verify that the amount of negative voltage
pertinent to his/her application does not exceed the
characterization curve we provide, including some safety
margin.
In order to estimate the maximum negative voltage
accepted by the driver, this parameter has been
characterized over full the temperature range of the
component. A test fixture has been developed in which we
purposely negatively bias the bridge pin during the
freewheel period of a buck converter. When the upper gate
voltage shows signs of an erratic behavior, we consider the
limit has been reached.
Figure 51 (or 52), illustrates the negative voltage safe
operating area. Its interpretation is as follows: assume a
negative 10 V pulse featuring a 100 ns width is applied on
the bridge pin, the driver will work correctly over the whole
die temperature range. Should the pulse swing to −20 V,
keeping the same width of 100 ns, the driver will not work
properly or will be damaged for temperatures below
125°C.
Summary:
•If the negative pulse characteristic (negative voltage
level & pulse width) is above the curves the driver
runs in safe operating area.
•If the negative pulse characteristic (negative voltage
level & pulse width) is below one or all curves the
driver will NOT run in safe operating area.
Note, each curve of the Figure 51 (or 52) represents the
negative voltage and width level where the driver starts to
fail at the corresponding die temperature.
If in the application the bridge pin is too close of the safe
operating limit, it is possible to limit the negative voltage
to the bridge pin by inserting one resistor and one diode as
follows:
U1
NCP5106A
VCC
1
IN_HI
2
IN_LO
3
GND
4DRV_LO 5
BRIDGE 6
DRV_HI 7
VBOOT 8
D1
MUR160
R1
10R
D2
MUR160 C1
100n M1
M2
Vbulk
0
IN_Hi
IN_LO
0
Vcc
Figure 53. R1 and D1 Improves the Robustness of the
Driver
R1 and D1 should be placed as close as possible of the
driver. D1 should be connected directly between the bridge
pin (pin 6) and the ground pin (pin 4). By this way the
negative voltage applied to the bridge pin will be limited
by D1 and R1 and will prevent any wrong behavior.
ORDERING INFORMATION
Device Package Shipping†
NCP5106APG PDIP−8 (Pb−Free) 50 Units / Rail
NCP5106ADR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel
NCP5106BPG PDIP−8 (Pb−Free) 50 Units / Rail
NCP5106BDR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel
NCP5106AMNTWG DFN10 (Pb−Free) 4000 / Tape & Reel
NCP5106BMNTWG DFN10 (Pb−Free) 4000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Hbafij I'HH'HMH - ‘ 5 7 iii,, , T l 2. x W“ I: VAL“) LL12 fik TOP VIEW r—D j ‘ ‘ x ‘ x 7‘7‘ SEATING AIJ‘ \ ‘ \ Emu: :LJ eg—Xb SIDE VIEW
NCP5106A, NCP5106B
www.onsemi.com
17
PACKAGE DIMENSIONS
8 LEAD PDIP
CASE 626−05
ISSUE N
14
58
b2
NOTE 8
D
b
L
A1
A
eB
E
A
TOP VIEW
C
SEATING
PLANE
0.010 CA
SIDE VIEW
END VIEW
END VIEW
WITH LEADS CONSTRAINED
DIM MIN MAX
INCHES
A−−−− 0.210
A1 0.015 −−−−
b0.014 0.022
C0.008 0.014
D0.355 0.400
D1 0.005 −−−−
e0.100 BSC
E0.300 0.325
M−−−− 10
−−− 5.33
0.38 −−−
0.35 0.56
0.20 0.36
9.02 10.16
0.13 −−−
2.54 BSC
7.62 8.26
−−− 10
MIN MAX
MILLIMETERS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK-
AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE NOT
TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION E3 IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
E1 0.240 0.280 6.10 7.11
b2
eB −−−− 0.430 −−− 10.92
0.060 TYP 1.52 TYP
E1
M
8X
c
D1
B
A2 0.115 0.195 2.92 4.95
L0.115 0.150 2.92 3.81
°°
H
NOTE 5
e
e/2 A2
NOTE 3
MBMNOTE 6
M
NCP5106A, NCP5106B
www.onsemi.com
18
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
SEATING
PLANE
1
4
58
N
J
X 45_
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
BS
D
H
C
0.10 (0.004)
DIM
AMIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010) ZSXS
M
____
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
REflE‘ W", El m\ E #fii ,i m“ fig SIDE VIEW BOT-[OM VIEW Eh R 5 EoR DEVICE oRN CONTAINING w oRTIoN DETAIL A ALTERNAIE CoNsTRuCTIoN A72 AND DETAIL E ALr TERNATE CONSTRUCHON 5,2 ARE NoT APPLICAELE \‘ZZZJJ may be Accessad :II www mm cumsIle gar RaIenI, Mamng gm
NCP5106A, NCP5106B
www.onsemi.com
19
PACKAGE DIMENSIONS
DFN10 4x4, 0.8P
CASE 506DJ
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS
MEASURED BETWEEN 0.25 AND 0.30 MM FROM THE
TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED PAD AS
WELL AS THE TERMINALS.
5. FOR DEVICE OPN CONTAINING W OPTION, DETAIL A
ALTERNATE CONSTRUCTION A−2 AND DETAIL B AL-
TERNATE CONSTRUCTION B−2 ARE NOT APPLICABLE.
A
D
E
B
C0.10
PIN ONE
REFERENCE
TOP VIEW
SIDE VIEW
BOTTOM VIEW
A
D2
E2
C
C0.10
C0.10
C0.08
A1 SEATING
PLANE
e
NOTE 3
b
10X
0.10 C
0.05 C
ABB
DIM MIN MAX
MILLIMETERS
A0.80 1.00
A1 0.00 0.05
b0.25 0.35
D4.00 BSC
D2 2.90 3.10
E4.00 BSC
E2 1.85 2.05
e0.80 BSC
E3
L0.35 0.45
1
6
K
A3 0.20 REF
MOUNTING FOOTPRINT
NOTE 4
A3
DETAIL B
DETAIL A
L1
DETAIL A
L
ALTERNATE TERMINAL
CONSTRUCTIONS
L
L1 0.00 0.15
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTIONS
A1 A3
4.30
0.80
0.60
10X
DIMENSIONS: MILLIMETERS
0.42
3.20
PITCH
2.15
10X
1
PACKAGE
OUTLINE
RECOMMENDED
10X L
10
5
0.375 BSC
10X
2X
2X
K0.90 −−−
ALTERNATE A−1 ALTERNATE A−2
ALTERNATE B−1 ALTERNATE B−2
0.10 C ABB
0.10 C ABB
E3
0.75
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