MC79M00 Series Datasheet by ON Semiconductor

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July, 2013 − Rev. 15

1Publication Order Number:

MC79M00/D

MC79M00 Series

500 mA Negative Voltage

Regulators

The MC79M00 series of fixed output negative voltage regulators

are intended as complements to the popular MC78M00 series devices.

Available in fixed output voltage options of −5.0 V, −8.0 V, −12 V

and −15 V, these regulators employ current limiting, thermal

shutdown, and safe−area compensation, making them remarkably

rugged under most operating conditions. With adequate heatsinking

they can deliver output currents in excess of 0.5 A.

Features

•No External Components Required

•Internal Thermal Overload Protection

•Internal Short Circuit Current Limiting

•Output Transistor Safe−Area Compensation

•Also Available in Surface Mount DPAK (DT) Package

•Pb−Free Packages are Available

DEVICE TYPE/NOMINAL OUTPUT VOLTAGE

Device Nominal Output Voltage

MC79M05

MC79M08

MC79M12

MC79M15

−5.0 V

−8.0 V

−12 V

−15 V

Figure 1. Representative Schematic Diagram

GND

2.4 k

3.6 k

1.2 k

1.1 k

2.0 k

12 k

1.0 k

4.9 k

2.0 k

14.7 k

11.5 k5472.0 k

4.0 k

0.3

10 k

20 k 20 k

20 pF

10 pF

240

750

100

2.0 k

This device contains 31 active transistors.

DPAK−3

DT SUFFIX

CASE 369C

Pin 1. Ground

2. Input

3. Output

TO−220−3

T SUFFIX

CASE 221AB

http://onsemi.com

THREE−TERMINAL

NEGATIVE FIXED

VOLTAGE REGULATORS

See detailed ordering and shipping information in the package

dimensions section on page 6 of this data sheet.

ORDERING INFORMATION

MARKING

DIAGRAMS

79MxxyT

AWLYWWG

xx = 05, 08, 12, or 15

y = B or C

A = Assembly Location

WL, L = Wafer Lot

Y = Year

WW = Work Week

G = Pb−Free Device

STANDARD APPLICATION

MC79MXX

Input

Cin*

0.33 mF

Output

CO**

1.0 mF

A common ground is required between the input

and the output voltages. The input voltage must

remain typically 1.1 V more negative even during

the high point of the input ripple voltage.

XX These two digits of the type number indicate

nominal voltage.

in is required if regulator is located an

appreciable distance from power supply filter.

** CO improve stability and transient response.

9MxxBG

ALYWW

79MxxG

ALYWW

MC79M00 Series

http://onsemi.com

MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)

Rating Symbol Value Unit

Input Voltage VI−35 Vdc

Power Dissipation

Case 221A (TO−220−3)

TA = 25°C PDInternally Limited W

Thermal Resistance, Junction−to−Ambient qJA 65 °C/W

Thermal Resistance, Junction−to−Case qJC 5.0 °C/W

Case 369C (DPAK−3)

TA = 25°C PDInternally Limited W

Thermal Resistance, Junction−to−Ambient qJA 92 °C/W

Thermal Resistance, Junction−to−Case qJC 6.0 °C/W

Storage Junction Temperature Tstg −65 to +150 °C

Operating Junction Temperature Range TJ−40 to +150 °C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

*This device series contains ESD protection and exceeds the following tests:

Human Body Model 2000 V per MIL_STD_883, Method 3015

Machine Model Method 200 V

MC79M05B, C

ELECTRICAL CHARACTERISTICS (VI = −10 V, IO = 350 mA, Tlow to Thigh (Note 2), unless otherwise noted.)

Characteristic Symbol Min Typ Max Unit

Output Voltage (TJ = 25°C) VO−4.8 −5.0 −5.2 Vdc

Line Regulation, TJ = 25°C (Note 1)

−7.0 Vdc ≥ VI ≥ −25 Vdc

−8.0 Vdc ≥ VI ≥ −18 Vdc

Regline

−

7.0

2.0

Load Regulation, TJ = 25°C (Note 1)

5.0 mA ≤ IO ≤ 500 mA

Regload

−30 100

Output Voltage

−7.0 Vdc ≥ VI ≥ −25 Vdc, 5.0 mA ≤ IO ≤ 350 mA

−4.75 − −5.25

Vdc

Input Bias Current (TJ = 25°C) IIB −4.3 8.0 mA

Input Bias Current Change

−8.0 Vdc ≥ VI ≥ −25 Vdc, IO = 350 mA

5.0 mA ≤ IO ≤ 350 mA, VI = −10 V

DIIB

−

0.4

Output Noise Voltage, TA = 25°C, 10 Hz ≤ f ≤ 100 kHz Vn−40 −mV

Ripple Rejection (f = 120 Hz) RR 54 66 −dB

Dropout Voltage

IO = 500 mA, TJ = 25°C

VI−VO

−1.1 −

Vdc

Average Temperature Coefficient of Output Voltage

IO = 5.0 mA, 0°C ≤ TJ ≤ 125°C

DVO/DT

−0.2 −

mV/°C

1. Load and line regulation are specified at constant temperature. Change in VO due to heating effects must be taken into account separately.

Pulse testing with low duty cycle is used.

2. B = Tlow to Thigh, −40°C < TJ < 125°C C = Tlow to Thigh, 0°C < TJ < 125°C.

MC79M00 Series

http://onsemi.com

MC79M08B, C

ELECTRICAL CHARACTERISTICS (VI = −10 V, IO = 350 mA, Tlow to Thigh (Note 4), unless otherwise noted.)

Characteristic Symbol Min Typ Max Unit

Output Voltage (TJ = 25°C) VO−7.7 −8.0 −8.3 Vdc

Line Regulation, TJ = 25°C (Note 3)

−10.5 Vdc ≥ VI ≥ −25 Vdc

−11 Vdc ≥ VI ≥ −21 Vdc

Regline

−

5.0

3.0

Load Regulation, TJ = 25°C (Note 3)

5.0 mA ≤ IO ≤ 500 mA

Regload

−30 100

Output Voltage

−10.5 Vdc ≥ VI ≥ −25 Vdc, 5.0 mA ≤ IO ≤ 350 mA

−7.6 −8.0 −8.4

Vdc

Input Bias Current (TJ = 25°C) IIB − − 8.0 mA

Input Bias Current Change

−10.5 Vdc ≥ VI ≥ −25 Vdc, IO = 350 mA

5.0 mA ≤ IO ≤ 350 mA, VI = −10 V

DIIB

−

0.4

Output Noise Voltage, TA = 25°C, 10 Hz ≤ f ≤ 100 kHz Vn−60 −mV

Ripple Rejection (f = 120 Hz) RR 54 63 −dB

Dropout Voltage

IO = 500 mA, TJ = 25°C

VI−VO

−1.1 −

Vdc

Average Temperature Coefficient of Output Voltage

IO = 5.0 mA, 0°C ≤ TJ ≤ 125°C

DVO/DT

−0.4 −

mV/°C

3. Load and line regulation are specified at constant temperature. Change in VO due to heating effects must be taken into account separately.

Pulse testing with low duty cycle is used.

4. B = Tlow to Thigh, −40°C < TJ < 125°C

C = Tlow to Thigh, 0°C < TJ < 125°C

MC79M12B, C

ELECTRICAL CHARACTERISTICS (VI = −19 V, IO = 350 mA, Tlow to Thigh (Note 6), unless otherwise noted.)

Characteristic Symbol Min Typ Max Unit

Output Voltage (TJ = 25°C) VO−11.5 −12 −12.5 Vdc

Line Regulation, TJ = 25°C (Note 5)

−14.5 Vdc ≥ VI ≥ −30 Vdc

−15 Vdc ≥ VI ≥ −25 Vdc

Regline

−

5.0

3.0

Load Regulation, TJ = 25°C (Note 5)

5.0 mA ≤ IO ≤ 500 mA

Regload

−30 240

Output Voltage

−14.5 Vdc ≥ VI ≥ −30 Vdc, 5.0 mA ≤ IO ≤ 350 mA

−11.4 − −12.6

Vdc

Input Bias Current (TJ = 25°C) IIB −4.4 8.0 mA

Input Bias Current Change

−14.5 Vdc ≥ VI ≥ −30 Vdc, IO = 350 mA

5.0 mA ≤ IO ≤ 350 mA, VI = −19 V

DIIB

−

0.4

Output Noise Voltage, TA = 25°C, 10 Hz ≤ f ≤ 100 kHz Vn−75 −mV

Ripple Rejection (f = 120 Hz) RR 54 60 −dB

Dropout Voltage

IO = 500 mA, TJ = 25°C

VI−VO

−1.1 −

Vdc

Average Temperature Coefficient of Output Voltage

IO = 5.0 mA, 0°C ≤ TJ ≤ 125°C

DVO/DT

− −0.8 −

mV/°C

5. Load and line regulation are specified at constant temperature. Change in VO due to heating effects must be taken into account separately.

Pulse testing with low duty cycle is used.

6. B = Tlow to Thigh, −40°C < TJ < 125°C

C = Tlow to Thigh, 0°C < TJ < 125°C

MC79M00 Series

http://onsemi.com

MC79M15B, C

ELECTRICAL CHARACTERISTICS (VI = −23 V, IO = 350 mA, Tlow to Thigh (Note 8), unless otherwise noted.)

Characteristic Symbol Min Typ Max Unit

Output Voltage (TJ = 25°C) VO−14.4 −15 −15.6 Vdc

Line Regulation, TJ = 25°C (Note 7)

−17.5 Vdc ≥ VI ≥ −30 Vdc

−18 Vdc ≥ VI ≥ −28 Vdc

Regline

−

5.0

3.0

Load Regulation, TJ = 25°C (Note 7)

5.0 mA ≤ IO ≤ 500 mA

Regload

−30 240

Output Voltage

−17.5 Vdc ≥ VI ≥ −30 Vdc, 5.0 mA ≤ IO ≤ 350 mA

−14.25 − −15.75

Vdc

Input Bias Current (TJ = 25°C) IIB −4.4 8.0 mA

Input Bias Current Change

−17.5 Vdc ≥ VI ≥ −30 Vdc, IO = 350 mA

5.0 mA ≤ IO ≤ 350 mA, VI = −23 V

DIIB

−

0.4

Output Noise Voltage, TA = 25°C, 10 Hz ≤ f ≤ 100 kHz Vn−90 −mV

Ripple Rejection (f = 120 Hz) RR 54 60 −dB

Dropout Voltage

IO = 500 mA, TJ = 25°C

VI−VO

−1.1 −

Vdc

Average Temperature Coefficient of Output Voltage

IO = 5.0 mA, 0°C ≤ TJ ≤ 125°C

DVO/DT

− −1.0 −

mV/°C

7. Load and line regulation are specified at constant temperature. Change in VO due to heating effects must be taken into account separately.

Pulse testing with low duty cycle is used.

8. B = Tlow to Thigh, −40°C < TJ < 125°C

C = Tlow to Thigh, 0°C < TJ < 125°C

R , THERMAL RESISTANCE

JAθ

JUNCTION‐TO‐AIR ( C/W)°

PD, MAXIMUM POWER DISSIPATION (W)

Figure 1. DPAK−3 Thermal Resistance and Maximum

Power Dissipation versus P.C.B. Copper Length

100

010203025155.0

L, LENGTH OF COPPER (mm)

Minimum

Size Pad L

Free Air

Mounted

Vertically

RqJA

2.0 oz. Copper

0.4

0.8

1.2

1.6

2.0

2.4

PD(max) for TA = 50°C

MC79M00 Series

http://onsemi.com

Protection Diodes

When external capacitors are used with MC79M00 series

regulator it is sometimes necessary to add protection diodes

to prevent the capacitors from discharging through low

current points into the regulator or from output polarity

reversals. Generally, no protection diode is required for

values of output capacitance less then 10mF. Figure 2 shows

the MC79M15 with the recommended protection diodes.

•Opposite Polarity Protection

Diode D1 protects the regulator from output polarity

reversals during startup, power off and short-circuit

operation.

•Reverse-bias Protection

Diode D2 prevents output capacitor from discharging thru

the MC79M15 during an input short circuit or fast switch off

of power supply.

Figure 2. Protection Diodes

Gnd Gnd

-20 V

Input

-15 V

Output

MC79M15

1.0 mF 1.0 mFMBRS140

or Equiv

MBRS140

or Equiv

MC79MOSBDT MC79MOSBDTRK MC79MOSBT MC79M05CDT MC79M05CDTRK MC79M05CT MC79MOBBDT MC79MOBBDTRK MC79MOBBT MC79MOBCDT MC79MOBCDTRK MC79MOBCT MC79M1 ZBDT MC79M128DTRK MC79M1 ZBT MC79M1 2CDT MC79M12CDTRK MC79M1 2ST DPAK 75 Umls / Hall DPAK DPAK 2500 Unlls / Reel DPAK 70—220 50 Umls / Hall TO-220 DPAK 75 Umls / Hall DPAK DPAK 2500 Unlls / Reel DPAK 70—220 50 Umls / Hall TO-220 DPAK 75 Umls / Hall DPAK 2500 Unlls / Reel DPAK 70—220 50 Umls / Hall TO-220 DPAK 75 Umls / Hall DPAK DPAK 2500 Unlls / Reel DPAK 70—220 50 Umls / Hall TO-220 DPAK 75 Umls / Hall DPAK DPAK 2500 Unlls / Reel DPAK 70—220 50 Umls / Hall TO-220 DPAK 75 Umls / Hall DPAK DPAK 2500 Unlls / Reel DPAK 70—220 50 Umls / Hall To -220

MC79M00 Series

http://onsemi.com

ORDERING INFORMATION

Device Output Voltage

Tolerance

Operating

Temperature Range Package Shipping†

MC79M05BDT

4.0%

TJ = −40°C to +125°C

DPAK 75 Units / Rail

MC79M05BDTG DPAK

(Pb−Free) 75 Units / Rail

MC79M05BDTRK DPAK 2500 Units / Reel

MC79M05BDTRKG DPAK

(Pb−Free) 2500 Units / Reel

MC79M05BT TO−220 50 Units / Rail

MC79M05BTG TO−220

(Pb−Free) 50 Units / Rail

MC79M05CDT

TJ = 0°C to +125°C

DPAK 75 Units / Rail

MC79M05CDTG DPAK

(Pb−Free) 75 Units / Rail

MC79M05CDTRK DPAK 2500 Units / Reel

MC79M05CDTRKG DPAK

(Pb−Free) 2500 Units / Reel

MC79M05CT TO−220 50 Units / Rail

MC79M05CTG TO−220

(Pb−Free) 50 Units / Rail

MC79M08BDT

TJ = −40°C to +125°C

DPAK 75 Units / Rail

MC79M08BDTRK DPAK 2500 Units / Reel

MC79M08BDTRKG DPAK

(Pb−Free) 2500 Units / Reel

MC79M08BT TO−220 50 Units / Rail

MC79M08BTG TO−220

(Pb−Free) 50 Units / Rail

MC79M08CDT

TJ = 0°C to +125°C

DPAK 75 Units / Rail

MC79M08CDTG DPAK

(Pb−Free) 75 Units / Rail

MC79M08CDTRK DPAK 2500 Units / Reel

MC79M08CDTRKG DPAK

(Pb−Free) 2500 Units / Reel

MC79M08CT TO−220 50 Units / Rail

MC79M08CTG TO−220

(Pb−Free) 50 Units / Rail

MC79M12BDT

TJ = −40°C to +125°C

DPAK 75 Units / Rail

MC79M12BDTG DPAK

(Pb−Free) 75 Units / Rail

MC79M12BDTRK DPAK 2500 Units / Reel

MC79M12BDTRKG DPAK

(Pb−Free) 2500 Units / Reel

MC79M12BT TO−220 50 Units / Rail

MC79M12BTG TO−220

(Pb−Free) 50 Units / Rail

MC79M12CDT

TJ = 0°C to +125°C

DPAK 75 Units / Rail

MC79M12CDTG DPAK

(Pb−Free) 75 Units / Rail

MC79M12CDTRK DPAK 2500 Units / Reel

MC79M12CDTRKG DPAK

(Pb−Free) 2500 Units / Reel

MC79M12CT TO−220 50 Units / Rail

MC79M12CTG TO−220

(Pb−Free) 50 Units / Rail

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

MC79M00 Series

http://onsemi.com

ORDERING INFORMATION

Device Output Voltage

Tolerance

Operating

Temperature Range Package Shipping[

MC79M15BDT

4.0%

TJ = −40°C to +125°C

DPAK 75 Units / Rail

MC79M15BDTG DPAK

(Pb−Free) 75 Units / Rail

MC79M15BDTRK DPAK 2500 Units / Reel

MC79M15BDTRKG DPAK

(Pb−Free) 2500 Units / Reel

MC79M15BT TO−220 50 Units / Rail

MC79M15BTG TO−220

(Pb−Free) 50 Units / Rail

MC79M15CDT

TJ = 0°C to +125°C

DPAK 75 Units / Rail

MC79M15CDTG DPAK

(Pb−Free) 75 Units / Rail

MC79M15CDTRK DPAK 2500 Units / Reel

MC79M15CDTRKG DPAK

(Pb−Free) 2500 Units / Reel

MC79M15CT TO−220 50 Units / Rail

MC79M15CTG TO−220

(Pb−Free) 50 Units / Rail

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

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TO−220, SINGLE GAUGE

CASE 221AB−01

ISSUE A

DATE 16 NOV 2010

SCALE 1:1

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCHES.

3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND

LEAD IRREGULARITIES ARE ALLOWED.

4. PRODUCT SHIPPED PRIOR TO 2008 HAD DIMENSIONS

S = 0.045 - 0.055 INCHES (1.143 - 1.397 MM)

STYLE 1:

PIN 1. BASE

2. COLLECTOR

3. EMITTER

4. COLLECTOR

STYLE 2:

PIN 1. BASE

2. EMITTER

3. COLLECTOR

4. EMITTER

STYLE 3:

PIN 1. CATHODE

2. ANODE

3. GATE

4. ANODE

STYLE 4:

PIN 1. MAIN TERMINAL 1

2. MAIN TERMINAL 2

3. GATE

4. MAIN TERMINAL 2

STYLE 7:

PIN 1. CATHODE

2. ANODE

3. CATHODE

4. ANODE

STYLE 10:

PIN 1. GATE

2. SOURCE

3. DRAIN

4. SOURCE

STYLE 5:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

STYLE 8:

PIN 1. CATHODE

2. ANODE

3. EXTERNAL TRIP/DELAY

4. ANODE

STYLE 6:

PIN 1. ANODE

2. CATHODE

3. ANODE

4. CATHODE

STYLE 9:

PIN 1. GATE

2. COLLECTOR

3. EMITTER

4. COLLECTOR

STYLE 11:

PIN 1. DRAIN

2. SOURCE

3. GATE

4. SOURCE

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.570 0.620 14.48 15.75

B0.380 0.405 9.66 10.28

C0.160 0.190 4.07 4.82

D0.025 0.035 0.64 0.88

F0.142 0.147 3.61 3.73

G0.095 0.105 2.42 2.66

H0.110 0.155 2.80 3.93

J0.018 0.025 0.46 0.64

K0.500 0.562 12.70 14.27

L0.045 0.060 1.15 1.52

N0.190 0.210 4.83 5.33

Q0.100 0.120 2.54 3.04

R0.080 0.110 2.04 2.79

S0.020 0.024 0.508 0.61

T0.235 0.255 5.97 6.47

U0.000 0.050 0.00 1.27

V0.045 --- 1.15 ---

Z--- 0.080 --- 2.04

123

SEATING

PLANE

−T−

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

98AON23085D

DOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 1

TO−220, SINGLE GAUGE

4 12% 3 SCALE l:l FE! «5*» j; ILA c2 \ w T l 'T L4 \ \ A, iﬂe L? 4P CTVLET SIVLE 2 STVLE 3 sT PTNT EASE PTNT GATE PTNT ANODE P 2 COLLECTOR 2 DRAIN 2 CATHODE 3 EMTTTER 3 SouRCE 3 ANODE 6 COLLECTOR 4 DRAIN 6 CATHODE STVLE s SIVLE 7 STVLE a STVLE 9 mm MT1 PTNT GATE le NC mm AN 2 MT2 2 COLLECTOR 2 CAIHODE 2 C 3 GATE 3 EMTTTER 3 ANODE a R 6 MT2 4 COLLECTOR 4 CAIHODE a C SOLDERING F 620 WZEEF +8 11:2|:|j_f 3L \ L4 ’FOT addmonal Tnlarmamn On our delal‘s p‘ease dawnload me ON Mounhng Techmques Recerence Le A L A 0N Semiwndudw"

DPAK (SINGLE GAUGE)

CASE 369C

ISSUE F DATE 21 JUL 2015

SCALE 1:1

STYLE 1:

PIN 1. BASE

2. COLLECTOR

3. EMITTER

4. COLLECTOR

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

STYLE 3:

PIN 1. ANODE

2. CATHODE

3. ANODE

4. CATHODE

STYLE 4:

PIN 1. CATHODE

2. ANODE

3. GATE

4. ANODE

STYLE 5:

PIN 1. GATE

2. ANODE

3. CATHODE

4. ANODE

STYLE 6:

PIN 1. MT1

2. MT2

3. GATE

4. MT2

STYLE 7:

PIN 1. GATE

2. COLLECTOR

3. EMITTER

4. COLLECTOR

123

STYLE 8:

PIN 1. N/C

2. CATHODE

3. ANODE

4. CATHODE

STYLE 9:

PIN 1. ANODE

2. CATHODE

3. RESISTOR ADJUST

4. CATHODE

STYLE 10:

PIN 1. CATHODE

2. ANODE

3. CATHODE

4. ANODE

L4b2

0.005 (0.13) C

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

D0.235 0.245 5.97 6.22

E0.250 0.265 6.35 6.73

A0.086 0.094 2.18 2.38

b0.025 0.035 0.63 0.89

c2 0.018 0.024 0.46 0.61

b2 0.028 0.045 0.72 1.14

c0.018 0.024 0.46 0.61

e0.090 BSC 2.29 BSC

b3 0.180 0.215 4.57 5.46

L4 −−− 0.040 −−− 1.01

L0.055 0.070 1.40 1.78

L3 0.035 0.050 0.89 1.27

Z0.155 −−− 3.93 −−−

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. CONTROLLING DIMENSION: INCHES.

3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-

MENSIONS b3, L3 and Z.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLD

FLASH, PROTRUSIONS, OR BURRS. MOLD

FLASH, PROTRUSIONS, OR GATE BURRS SHALL

NOT EXCEED 0.006 INCHES PER SIDE.

5. DIMENSIONS D AND E ARE DETERMINED AT THE

OUTERMOST EXTREMES OF THE PLASTIC BODY.

6. DATUMS A AND B ARE DETERMINED AT DATUM

PLANE H.

7. OPTIONAL MOLD FEATURE.

12 3

XXXXXX = Device Code

A = Assembly Location

L = Wafer Lot

Y = Year

WW = Work Week

G = Pb−Free Package

AYWW

XXX

XXXXXG

XXXXXXG

ALYWW

DiscreteIC

5.80

0.228

2.58

0.102

1.60

0.063

6.20

0.244

3.00

0.118

6.17

0.243

ǒmm

inchesǓ

SCALE 3:1

GENERIC

MARKING DIAGRAM*

*This information is generic. Please refer

to device data sheet for actual part

marking.

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

H0.370 0.410 9.40 10.41

A1 0.000 0.005 0.00 0.13

L1 0.114 REF 2.90 REF

L2 0.020 BSC 0.51 BSC

DETAIL A

SEATING

PLANE

L2 GAUGE

PLANE

DETAIL A

ROTATED 90 CW5

eBOTTOM VIEW

BOTTOM VIEW

SIDE VIEW

TOP VIEW

ALTERNATE

CONSTRUCTIONS

NOTE 7

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

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October, 2002 − Rev. 0 Case Outline Number:

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DOCUMENT NUMBER:

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NEW STANDARD:

DESCRIPTION:

98AON10527D

ON SEMICONDUCTOR STANDARD

REF TO JEDEC TO−252

DPAK SINGLE GAUGE SURFACE MOUNT

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ISSUE REVISION DATE

ORELEASED FOR PRODUCTION. REQ. BY L. GAN 24 SEP 2001

AADDED STYLE 8. REQ. BY S. ALLEN. 06 AUG 2008

BADDED STYLE 9. REQ. BY D. WARNER. 16 JAN 2009

CADDED STYLE 10. REQ. BY S. ALLEN. 09 JUN 2009

DRELABELED DRAWING TO JEDEC STANDARDS. ADDED SIDE VIEW DETAIL A.

CORRECTED MARKING INFORMATION. REQ. BY D. TRUHITTE. 29 JUN 2010

EADDED ALTERNATE CONSTRUCTION BOTTOM VIEW. MODIFIED DIMENSIONS

b2 AND L1. CORRECTED MARKING DIAGRAM FOR DISCRETE. REQ. BY I. CAM-

BALIZA.

06 FEB 2014

FADDED SECOND ALTERNATE CONSTRUCTION BOTTOM VIEW. REQ. BY K.

MUSTAFA. 21 JUL 2015

July, 2015 − Rev. F Case Outline Number

369C

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