I These Devices are Pb—Free and are Roi-[S Compliant
A‘ 2—M w
A2
A3
Data A4
inputs
Outpui 05‘
Enabies 052
V2
V3
V
5
V5
V6
V7
V5
PIN 20 :vcc
PIN 10 : GND
Figure 1. Logic Diagram
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© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 9 1Publication Order Number:
MC74HC541A/D
MC74HC541A
Octal 3-State Noninverting
Buffer/Line Driver/Line
Receiver
High−Performance Silicon−Gate CMOS
The MC74HC541A is identical in pinout to the LS541. The device
inputs are compatible with Standard CMOS outputs. External pull−up
resistors make them compatible with LSTTL outputs.
The HC541A is an octal noninverting buffer/line driver/line
receiver designed to be used with 3−state memory address drivers,
clock drivers, and other bus−oriented systems. This device features
inputs and outputs on opposite sides of the package and two ANDed
active−low output enables.
The HC541A is similar in function to the HC540A, which has
inverting outputs.
Features
•Output Drive Capability: 15 LSTTL Loads
•Outputs Directly Interface to CMOS, NMOS and TTL
•Operating Voltage Range: 2.0 to 6.0 V
•Low Input Current: 1 mA
•High Noise Immunity Characteristic of CMOS Devices
•In Compliance With the JEDEC Standard No. 7 A Requirements
•Chip Complexity: 134 FETs or 33.5 Equivalent Gates
•NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•These Devices are Pb−Free and are RoHS Compliant
18 Y1
2
A1
17 Y2
3
A2
16 Y3
4
A3
15 Y4
5
A4
14 Y5
6
A5
13 Y6
7
A6
12 Y7
8
A7
11 Y8
9
A8
OE1
OE2
1
19
Output
Enables
Data
Inputs
Noninverting
Outputs
PIN 20 = VCC
PIN 10 = GND
Figure 1. Logic Diagram
http://onsemi.com
1
20
MARKING DIAGRAMS
SOIC−20
HC541A
AWLYYWWG
HC
541A
ALYWG
G
TSSOP−20
20
1
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G= Pb−Free Package
(Note: Microdot may be in either location)
L
L
H
X
L
L
X
H
L
H
X
X
Inputs Output Y
OE1 OE2 A
L
H
Z
Z
X = Don’t Care
Z = High Impedance
FUNCTION TABLE
SOIC−20
DW SUFFIX
CASE 751D
TSSOP−20
DT SUFFIX
CASE 948E
PIN ASSIGNMENT
1920 18 17 16 15 14
21 34567
VCC
13
8
12
9
11
10
OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
OE1 A1 A2 A3 A4 A5 A6 A7 A8 GND
MC74HC541A
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2
MAXIMUM RATINGS
Symbol Parameter Value Unit
VCC DC Supply Voltage −0.5 to +7.0 V
VIDC Input Voltage −0.5 ≤ VI ≤ VCC + 0.5 V
VODC Output Voltage (Note 1) −0.5 ≤ VO ≤ VCC + 0.5 V
IIK DC Input Diode Current ±20 mA
IOK DC Output Diode Current ±35 mA
IODC Output Sink Current ±35 mA
ICC DC Supply Current per Supply Pin ±75 mA
IGND DC Ground Current per Ground Pin ±75 mA
TSTG Storage Temperature Range −65 to +150 _C
TLLead Temperature, 1 mm from Case for 10 Seconds 260 _C
TJJunction Temperature under Bias +150 _C
qJA Thermal Resistance SOIC
TSSOP 96
128
_C/W
PDPower Dissipation in Still Air at 85_C SOIC
TSSOP 500
450 mW
MSL Moisture Sensitivity Level 1
FRFlammability Rating Oxygen Index: 30% − 35% UL 94 V−0 @ 0.125 in
VESD ESD Withstand Voltage Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
> 4000
> 300
> 1000
V
ILatchup Latchup Performance Above VCC and Below GND at 85_C (Note 5) ±300 mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. IO absolute maximum rating must be observed.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V
VIN,
VOUT
DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
TAOperating Temperature Range, All Package Types −55 +125 _C
tr, tfInput Rise/Fall Time VCC = 2.0 V
(Figure 2) VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level.
MC74HC541A
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3
DC CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol Parameter Condition
VCC
V−55 to
25_C≤85_C≤125_CUnit
VIH Minimum High−Level Input Voltage VOUT = 0.1 V
|IOUT| ≤ 20 mA2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
V
VIL Maximum Low−Level Input Voltage VOUT = VCC − 0.1 V
|IOUT| ≤ 20 mA2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
V
VOH Minimum High−Level Output Voltage VIN = VIL
|IOUT| ≤ 20 mA2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
VIN = VIL |IOUT| ≤ 3.6 mA
|IOUT| ≤ 6.0 mA
|IOUT| ≤ 7.8 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
VOL Maximum Low−Level Output Voltage VIN = VIH
|IOUT| ≤ 20 mA2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
VIN = VIH |IOUT| ≤ 3.6 mA
|IOUT| ≤ 6.0 mA
|IOUT| ≤ 7.8 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
IIN Maximum Input Leakage Current VIN = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA
IOZ Maximum 3−State Leakage Current Output in High Impedance State
VIN = VIL or VIH
VOUT = VCC or GND
6.0 ±0.5 ±5.0 ±10.0 mA
ICC Maximum Quiescent Supply
Current (per Package) VIN = VCC or GND
IOUT = 0 mA6.0 4 40 160 mA
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol Parameter
VCC
V−55 to
25_C≤85_C≤125_CUnit
tPLH,
tPHL
Maximum Propagation Delay, Input A to Output Y
(Figures 2 and 4) 2.0
3.0
4.5
6.0
80
30
18
15
100
40
23
20
120
55
28
25
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to Output Y
(Figures 3 and 5) 2.0
3.0
4.5
6.0
110
45
25
21
140
60
31
26
165
75
38
31
ns
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to Output Y
(Figures 3 and 5) 2.0
3.0
4.5
6.0
110
45
25
21
140
60
31
26
165
75
38
31
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 2 and 4) 2.0
3.0
4.5
6.0
60
22
12
10
75
28
15
13
90
34
18
15
ns
CIN Maximum Input Capacitance 10 10 10 pF
COUT Maximum 3−State Output Capacitance (High Impedance State Output) 15 15 15 pF
Typical @ 25°C, VCC = 5.0 V, VEE = 0 V
CPD Power Dissipation Capacitance (Per Buffer) (Note 7) 35 pF
7. Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC.
MC74HC541A
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4
Figure 2. Switching Waveform
VCC
GND
INPUT A
OUTPUT Y
tPLH
OE1 or OE2 50%
VCC
GND
OUTPUT Y
tPZL
OUTPUT Y
tPZH
HIGH
IMPEDANCE
VOL
VOH
HIGH
IMPEDANCE
10%
90%
tPLZ
tPHZ
50%
50%
tPHL
90%
50%
10%
tr
tTLH
tf
tTHL
Figure 3. Switching Waveform
90%
50%
10%
50%
CL*
*Includes all probe and jig capacitance
TEST
POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 4. Test Circuit
Figure 5. Test Circuit
CL*
*Includes all probe and jig capacitance
TEST
POINT
DEVICE
UNDER
TEST
OUTPUT 1 kWCONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ and tPZH.
|||||||||
MC74HC541A
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5
PIN DESCRIPTIONS
INPUTS
A1, A2, A3, A4, A5, A6, A7, A8 (PINS 2, 3, 4, 5, 6, 7, 8, 9)
Data input pins. Data on these pins appear in non−inverted
form on the corresponding Y outputs, when the outputs are
enabled.
CONTROLS
OE1, OE2 (PINS 1, 19)
Output enables (active−low). When a low voltage is
applied to both of these pins, the outputs are enabled and the
device functions as an non−inverting buffer. When a high
voltage is applied to either input, the outputs assume the high
impedance state.
OUTPUTS
Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 18, 17, 16, 15, 14,
13, 12, 11)
Device outputs. Depending upon the state of the output
enable pins, these outputs are either non−inverting outputs
or high−impedance outputs.
VCC
To 7 Other Buffers
Figure 6. Logic Detail
One of Eight
Buffers
INPUT A
OE1
OE2
OUTPUT Y
ORDERING INFORMATION
Device Package Shipping†
MC74HC541ADWG SOIC−20 WIDE
(Pb−Free) 38 Units / Rail
MC74HC541ADWR2G SOIC−20 WIDE
(Pb−Free) 1000 Tape & Reel
NLV74HC541ADWR2G* SOIC−20 WIDE
(Pb−Free) 1000 Tape & Reel
MC74HC541ADTG TSSOP−20
(Pb−Free) 75 Units / Rail
MC74HC541ADTR2G TSSOP−20
(Pb−Free) 2500 Tape & Reel
NLV74HC541ADTR2G* TSSOP−20
(Pb−Free) 2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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SHALL NoT EXCEED u 25 In mm RER SIDE
5 DIMENSION K DOES NOT INCLUDE
DAMRAR RROTRusION ALLOWARLE
DAMRAR RROTRusION SHALL RE 0 03
\El unaI TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION
5 TERMINAL NuMaERs ARE SHOWN FOR
REEERENcE ONLv
7 DIMENSION A AND a ARE TO BE
DETERMINED AT DATUM RLANE ,w,
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MC74HC541A
http://onsemi.com
6
PACKAGE DIMENSIONS
TSSOP−20
DT SUFFIX
CASE 948E−02
ISSUE C
DIM
A
MIN MAX MIN MAX
INCHES
6.60 0.260
MILLIMETERS
B4.30 4.50 0.169 0.177
C1.20 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.27 0.37 0.011 0.015
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
____
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
110
1120
PIN 1
IDENT
A
B
−T−
0.100 (0.004)
C
DGH
SECTION N−N
K
K1
JJ1
N
N
M
F
−W−
SEATING
PLANE
−V−
−U−
S
U
M
0.10 (0.004) V S
T
20X REFK
L
L/2
2X
S
U0.15 (0.006) T
DETAIL E
0.25 (0.010)
DETAIL E 6.40 0.252
--- ---
S
U0.15 (0.006) T
7.06
16X
0.36 16X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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MC74HC541A
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7
PACKAGE DIMENSIONS
SOIC−20
DW SUFFIX
CASE 751D−05
ISSUE G
20
1
11
10
B20X
H10X
C
L
18X A1
A
SEATING
PLANE
q
hX 45_
E
D
M
0.25 M
B
M
0.25 S
AS
B
T
eT
B
A
DIM MIN MAX
MILLIMETERS
A2.35 2.65
A1 0.10 0.25
B0.35 0.49
C0.23 0.32
D12.65 12.95
E7.40 7.60
e1.27 BSC
H10.05 10.55
h0.25 0.75
L0.50 0.90
q0 7
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
__
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SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
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or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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P
UBLICATION ORDERING INFORMATION
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
MC74HC541A/D
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