http://www.semicenductors.ghi‘ipscom/buses/iZc/
Technical Reference Note iMP USB-to-I2C DLL User's Manual Page 2 of 7
Prepared by R. Chua
I²C PROTOCOL
GENERAL CHARACTERISTICS
The I²C protocol allows data to be transferred between devices using two open-drain (or open-collector)
bi-directional lines. One line is the serial clock (SCL) and the other is the serial data (SDA). The bus
master generates the Start conditions, the clock signals on SCL, as well as the Stop condition. An
acknowledge (ACK) is transmitted by the receiving device on the bus after each byte is sent.
BIT TRANSFER
Data on SDA must be stable while SCL is high. The state of SDA when SCL is high determines the logic
level of the transmitted data bit.
START AND STOP CONDITIONS
Within the procedure of the I²C bus, unique situations arise which are defined as START and STOP
conditions. A HIGH to LOW transition on the SDA line while SCL is HIGH is one such unique case. This
situation indicates a START condition. A LOW to HIGH transition on the SDA line while SCL is HIGH
defines a STOP condition. The master always generates START and STOP conditions. The bus is
considered to be busy after the START condition. The bus is considered to be free again a certain time
after the STOP condition.
I²C ADDRESS
The first seven bits of an I²C transmission, after a Start condition, make up the slave address. The eighth
bit (or the least significant bit) is the R/W bit that determines the direction of the message.
A '0' in the least significant position of the first byte means that the master will WRITE information
to the selected slave. A '1' in this position means that the master will READ information from the slave.
When an I²C address is sent, each device in a system compares the first seven bits after the START
condition with its own address. If they match, the device considers itself addressed by the master as a
slave-receiver or slave-transmitter, depending on the R/W bit.
SUBADDRESS
When an I²C device contains more than one register, the various registers are generally accessed using a
subaddress that is sent following the device address (see the I2CWriteArray and I2CReadArray sections
below). The subaddress acts like a pointer to the register that needs to be accessed.
DATA TRANSFER
Every byte on the SDA line must be 8-bits long. The number of bytes that can be transmitted per transfer
is unrestricted. Each byte must also be followed by an acknowledge bit. Data is transferred with the
most significant bit first. If a receiver can’t receive another complete byte of data until it has performed
some other function, it can hold the clock line SCL low to force the transmitter into a wait state.
ACKNOWLEDGE
The Acknowledge related clock pulse is generated by the master. The transmitter releases the SDA line
during the acknowledge clock pulse. The receiver must pull down the SDA line during the acknowledge
clock pulse so that it remains stable low during the high period of the clock pulse.
The master-receiver signals the end of a read by not acknowledging the last byte it requires.
I²C BUS DOCUMENTATION
The complete I²C Bus specification can be found at http://www.semiconductors.philips.com/buses/i2c/.